1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK1 3 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK2 5 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK1-IRBUILDER 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK2-IRBUILDER 9 10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -fopenmp-version=45 -o - | FileCheck %s --check-prefixes=CHECK3 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -fopenmp-version=45 -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK4 13 14 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -fopenmp-version=45 -o - | FileCheck %s --check-prefixes=CHECK3-IRBUILDER 15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -fopenmp-version=45 -o %t %s 16 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-enable-irbuilder -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK4-IRBUILDER 17 18 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 19 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 21 // expected-no-diagnostics 22 #ifndef HEADER 23 #define HEADER 24 25 void static_not_chunked(float *a, float *b, float *c, float *d) { 26 #pragma omp for schedule(static) ordered 27 28 // Loop header 29 30 for (int i = 32000000; i > 33; i += -7) { 31 // Start of body: calculate i from IV: 32 33 // ... start of ordered region ... 34 // ... loop body ... 35 // End of body: store into a[i]: 36 // ... end of ordered region ... 37 #pragma omp ordered 38 a[i] = b[i] * c[i] * d[i]; 39 } 40 } 41 42 void dynamic1(float *a, float *b, float *c, float *d) { 43 #pragma omp for schedule(dynamic) ordered 44 45 // Loop header 46 47 for (unsigned long long i = 131071; i < 2147483647; i += 127) { 48 // Start of body: calculate i from IV: 49 50 // ... start of ordered region ... 51 // ... loop body ... 52 // End of body: store into a[i]: 53 // ... end of ordered region ... 54 #pragma omp ordered threads 55 a[i] = b[i] * c[i] * d[i]; 56 57 // ... end iteration for ordered loop ... 58 } 59 } 60 61 void test_auto(float *a, float *b, float *c, float *d) { 62 unsigned int x = 0; 63 unsigned int y = 0; 64 #pragma omp for schedule(auto) collapse(2) ordered 65 66 // Loop header 67 68 // FIXME: When the iteration count of some nested loop is not a known constant, 69 // we should pre-calculate it, like we do for the total number of iterations! 70 for (char i = static_cast<char>(y); i <= '9'; ++i) 71 for (x = 11; x > 0; --x) { 72 // Start of body: indices are calculated from IV: 73 74 // ... start of ordered region ... 75 // ... loop body ... 76 // End of body: store into a[i]: 77 // ... end of ordered region ... 78 #pragma omp ordered 79 a[i] = b[i] * c[i] * d[i]; 80 81 // ... end iteration for ordered loop ... 82 } 83 } 84 85 void runtime(float *a, float *b, float *c, float *d) { 86 int x = 0; 87 #pragma omp for collapse(2) schedule(runtime) ordered 88 89 // Loop header 90 91 for (unsigned char i = '0' ; i <= '9'; ++i) 92 for (x = -10; x < 10; ++x) { 93 // Start of body: indices are calculated from IV: 94 95 // ... start of ordered region ... 96 // ... loop body ... 97 // End of body: store into a[i]: 98 // ... end of ordered region ... 99 #pragma omp ordered threads 100 a[i] = b[i] * c[i] * d[i]; 101 102 // ... end iteration for ordered loop ... 103 } 104 } 105 106 float f[10]; 107 void foo_simd(int low, int up) { 108 #pragma omp simd 109 for (int i = low; i < up; ++i) { 110 f[i] = 0.0; 111 #pragma omp ordered simd 112 f[i] = 1.0; 113 } 114 #pragma omp for simd ordered 115 for (int i = low; i < up; ++i) { 116 f[i] = 0.0; 117 #pragma omp ordered simd 118 f[i] = 1.0; 119 } 120 } 121 122 123 #endif // HEADER 124 125 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 126 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 127 // CHECK1-NEXT: entry: 128 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 129 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 130 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 131 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 132 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 133 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 134 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 135 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 136 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 137 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 138 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 139 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 140 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 141 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 142 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 143 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 144 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 145 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 146 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 147 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 148 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 149 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 150 // CHECK1: omp.dispatch.cond: 151 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 152 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 153 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 154 // CHECK1: omp.dispatch.body: 155 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 156 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 157 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 158 // CHECK1: omp.inner.for.cond: 159 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 160 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 161 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 162 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 163 // CHECK1: omp.inner.for.body: 164 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 165 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7 166 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 167 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4 168 // CHECK1-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 169 // CHECK1-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 170 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 171 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 172 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM]] 173 // CHECK1-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 174 // CHECK1-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 175 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 176 // CHECK1-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64 177 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM1]] 178 // CHECK1-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 179 // CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 180 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 181 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 182 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64 183 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM4]] 184 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX5]], align 4 185 // CHECK1-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]] 186 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 187 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 188 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 189 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM7]] 190 // CHECK1-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 191 // CHECK1-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 192 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 193 // CHECK1: omp.body.continue: 194 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 195 // CHECK1: omp.inner.for.inc: 196 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 197 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], 1 198 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 199 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 200 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 201 // CHECK1: omp.inner.for.end: 202 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 203 // CHECK1: omp.dispatch.inc: 204 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 205 // CHECK1: omp.dispatch.end: 206 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP0]]) 207 // CHECK1-NEXT: ret void 208 // 209 // 210 // CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 211 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 212 // CHECK1-NEXT: entry: 213 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 214 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 215 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 216 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 217 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 218 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 219 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 220 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 221 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 222 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 223 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 224 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 225 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 226 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 227 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 228 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 229 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 230 // CHECK1-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 231 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 232 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 233 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1) 234 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 235 // CHECK1: omp.dispatch.cond: 236 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 237 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 238 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 239 // CHECK1: omp.dispatch.body: 240 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 241 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[DOTOMP_IV]], align 8 242 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 243 // CHECK1: omp.inner.for.cond: 244 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 245 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 246 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP4]], 1 247 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]] 248 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 249 // CHECK1: omp.inner.for.body: 250 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 251 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP5]], 127 252 // CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 253 // CHECK1-NEXT: store i64 [[ADD1]], i64* [[I]], align 8 254 // CHECK1-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 255 // CHECK1-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 256 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[I]], align 8 257 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[TMP7]] 258 // CHECK1-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 259 // CHECK1-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 260 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[I]], align 8 261 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[TMP10]] 262 // CHECK1-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 263 // CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 264 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 265 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[I]], align 8 266 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[TMP13]] 267 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX4]], align 4 268 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]] 269 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 270 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[I]], align 8 271 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[TMP16]] 272 // CHECK1-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 273 // CHECK1-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 274 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 275 // CHECK1: omp.body.continue: 276 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 277 // CHECK1: omp.inner.for.inc: 278 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 279 // CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP17]], 1 280 // CHECK1-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 281 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 282 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 283 // CHECK1: omp.inner.for.end: 284 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 285 // CHECK1: omp.dispatch.inc: 286 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 287 // CHECK1: omp.dispatch.end: 288 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 289 // CHECK1-NEXT: ret void 290 // 291 // 292 // CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 293 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 294 // CHECK1-NEXT: entry: 295 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 296 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 297 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 298 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 299 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 300 // CHECK1-NEXT: [[Y:%.*]] = alloca i32, align 4 301 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 302 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 303 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 304 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 305 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 306 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 307 // CHECK1-NEXT: [[X6:%.*]] = alloca i32, align 4 308 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 309 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 310 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 311 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 312 // CHECK1-NEXT: [[I8:%.*]] = alloca i8, align 1 313 // CHECK1-NEXT: [[X9:%.*]] = alloca i32, align 4 314 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 315 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 316 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 317 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 318 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 319 // CHECK1-NEXT: store i32 0, i32* [[X]], align 4 320 // CHECK1-NEXT: store i32 0, i32* [[Y]], align 4 321 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[Y]], align 4 322 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[TMP1]] to i8 323 // CHECK1-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 324 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 325 // CHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 326 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 327 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 328 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 329 // CHECK1-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 330 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 331 // CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 332 // CHECK1-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 333 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 334 // CHECK1-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 335 // CHECK1-NEXT: store i32 11, i32* [[X6]], align 4 336 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 337 // CHECK1-NEXT: [[CONV7:%.*]] = sext i8 [[TMP4]] to i32 338 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 339 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 340 // CHECK1: omp.precond.then: 341 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 342 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 343 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_UB]], align 8 344 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 345 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 346 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 347 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741894, i64 0, i64 [[TMP6]], i64 1, i64 1) 348 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 349 // CHECK1: omp.dispatch.cond: 350 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 351 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 352 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 353 // CHECK1: omp.dispatch.body: 354 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 355 // CHECK1-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 356 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 357 // CHECK1: omp.inner.for.cond: 358 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 359 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 360 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]] 361 // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 362 // CHECK1: omp.inner.for.body: 363 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 364 // CHECK1-NEXT: [[CONV11:%.*]] = sext i8 [[TMP11]] to i64 365 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 366 // CHECK1-NEXT: [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11 367 // CHECK1-NEXT: [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1 368 // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]] 369 // CHECK1-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8 370 // CHECK1-NEXT: store i8 [[CONV15]], i8* [[I8]], align 1 371 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 372 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 373 // CHECK1-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11 374 // CHECK1-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11 375 // CHECK1-NEXT: [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]] 376 // CHECK1-NEXT: [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1 377 // CHECK1-NEXT: [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]] 378 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32 379 // CHECK1-NEXT: store i32 [[CONV21]], i32* [[X9]], align 4 380 // CHECK1-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 381 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[B_ADDR]], align 8 382 // CHECK1-NEXT: [[TMP16:%.*]] = load i8, i8* [[I8]], align 1 383 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64 384 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM]] 385 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4 386 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[C_ADDR]], align 8 387 // CHECK1-NEXT: [[TMP19:%.*]] = load i8, i8* [[I8]], align 1 388 // CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64 389 // CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM22]] 390 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX23]], align 4 391 // CHECK1-NEXT: [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]] 392 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[D_ADDR]], align 8 393 // CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[I8]], align 1 394 // CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64 395 // CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM25]] 396 // CHECK1-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX26]], align 4 397 // CHECK1-NEXT: [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]] 398 // CHECK1-NEXT: [[TMP24:%.*]] = load float*, float** [[A_ADDR]], align 8 399 // CHECK1-NEXT: [[TMP25:%.*]] = load i8, i8* [[I8]], align 1 400 // CHECK1-NEXT: [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64 401 // CHECK1-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM28]] 402 // CHECK1-NEXT: store float [[MUL27]], float* [[ARRAYIDX29]], align 4 403 // CHECK1-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 404 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 405 // CHECK1: omp.body.continue: 406 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 407 // CHECK1: omp.inner.for.inc: 408 // CHECK1-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 409 // CHECK1-NEXT: [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1 410 // CHECK1-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 411 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 412 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 413 // CHECK1: omp.inner.for.end: 414 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 415 // CHECK1: omp.dispatch.inc: 416 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 417 // CHECK1: omp.dispatch.end: 418 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 419 // CHECK1: omp.precond.end: 420 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 421 // CHECK1-NEXT: ret void 422 // 423 // 424 // CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 425 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 426 // CHECK1-NEXT: entry: 427 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 428 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 429 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 430 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 431 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 432 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 433 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 434 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 435 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 436 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 437 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 438 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 439 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 440 // CHECK1-NEXT: [[X2:%.*]] = alloca i32, align 4 441 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 442 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 443 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 444 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 445 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 446 // CHECK1-NEXT: store i32 0, i32* [[X]], align 4 447 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 448 // CHECK1-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 449 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 450 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 451 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741893, i32 0, i32 199, i32 1, i32 1) 452 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 453 // CHECK1: omp.dispatch.cond: 454 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 455 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 456 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 457 // CHECK1: omp.dispatch.body: 458 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 459 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 460 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 461 // CHECK1: omp.inner.for.cond: 462 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 463 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 464 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 465 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 466 // CHECK1: omp.inner.for.body: 467 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 468 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 20 469 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 470 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 471 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 472 // CHECK1-NEXT: store i8 [[CONV]], i8* [[I]], align 1 473 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 474 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 475 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20 476 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20 477 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]] 478 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 479 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]] 480 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[X2]], align 4 481 // CHECK1-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 482 // CHECK1-NEXT: [[TMP8:%.*]] = load float*, float** [[B_ADDR]], align 8 483 // CHECK1-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 484 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64 485 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 486 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 487 // CHECK1-NEXT: [[TMP11:%.*]] = load float*, float** [[C_ADDR]], align 8 488 // CHECK1-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 489 // CHECK1-NEXT: [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64 490 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM7]] 491 // CHECK1-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX8]], align 4 492 // CHECK1-NEXT: [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]] 493 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[D_ADDR]], align 8 494 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 495 // CHECK1-NEXT: [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64 496 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM10]] 497 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX11]], align 4 498 // CHECK1-NEXT: [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]] 499 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[A_ADDR]], align 8 500 // CHECK1-NEXT: [[TMP18:%.*]] = load i8, i8* [[I]], align 1 501 // CHECK1-NEXT: [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64 502 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM13]] 503 // CHECK1-NEXT: store float [[MUL12]], float* [[ARRAYIDX14]], align 4 504 // CHECK1-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 505 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 506 // CHECK1: omp.body.continue: 507 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 508 // CHECK1: omp.inner.for.inc: 509 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 510 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1 511 // CHECK1-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4 512 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 513 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 514 // CHECK1: omp.inner.for.end: 515 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 516 // CHECK1: omp.dispatch.inc: 517 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 518 // CHECK1: omp.dispatch.end: 519 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 520 // CHECK1-NEXT: ret void 521 // 522 // 523 // CHECK1-LABEL: define {{[^@]+}}@_Z8foo_simdii 524 // CHECK1-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { 525 // CHECK1-NEXT: entry: 526 // CHECK1-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 527 // CHECK1-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 528 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 529 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 530 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 531 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 532 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 533 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 534 // CHECK1-NEXT: [[I5:%.*]] = alloca i32, align 4 535 // CHECK1-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 536 // CHECK1-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 537 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 538 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 539 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 540 // CHECK1-NEXT: [[I26:%.*]] = alloca i32, align 4 541 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 542 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 543 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 544 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 545 // CHECK1-NEXT: [[I28:%.*]] = alloca i32, align 4 546 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 547 // CHECK1-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 548 // CHECK1-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 549 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 550 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 551 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[UP_ADDR]], align 4 552 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 553 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 554 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 555 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 556 // CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 557 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 558 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 559 // CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 560 // CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 561 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 562 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 563 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 564 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 565 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 566 // CHECK1-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 567 // CHECK1: simd.if.then: 568 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 569 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 570 // CHECK1: omp.inner.for.cond: 571 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 572 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 573 // CHECK1-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 574 // CHECK1-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]] 575 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 576 // CHECK1: omp.inner.for.body: 577 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3 578 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 579 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1 580 // CHECK1-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]] 581 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3 582 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !3 583 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 584 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 585 // CHECK1-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 586 // CHECK1-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3 587 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 588 // CHECK1: omp.body.continue: 589 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 590 // CHECK1: omp.inner.for.inc: 591 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 592 // CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1 593 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 594 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 595 // CHECK1: omp.inner.for.end: 596 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 597 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 598 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 599 // CHECK1-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]] 600 // CHECK1-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 601 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 602 // CHECK1-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 603 // CHECK1-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 604 // CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]] 605 // CHECK1-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 606 // CHECK1-NEXT: br label [[SIMD_IF_END]] 607 // CHECK1: simd.if.end: 608 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 609 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_18]], align 4 610 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 611 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_19]], align 4 612 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 613 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 614 // CHECK1-NEXT: [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]] 615 // CHECK1-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 616 // CHECK1-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 617 // CHECK1-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 618 // CHECK1-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 619 // CHECK1-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 620 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 621 // CHECK1-NEXT: store i32 [[TMP21]], i32* [[I26]], align 4 622 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 623 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 624 // CHECK1-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] 625 // CHECK1-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 626 // CHECK1: omp.precond.then: 627 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 628 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 629 // CHECK1-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_UB]], align 4 630 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 631 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 632 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 633 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1) 634 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 635 // CHECK1: omp.dispatch.cond: 636 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 637 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0 638 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 639 // CHECK1: omp.dispatch.body: 640 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 641 // CHECK1-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4 642 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 643 // CHECK1: omp.inner.for.cond29: 644 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 645 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 646 // CHECK1-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1 647 // CHECK1-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]] 648 // CHECK1-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]] 649 // CHECK1: omp.inner.for.body32: 650 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7 651 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 652 // CHECK1-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1 653 // CHECK1-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]] 654 // CHECK1-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4, !llvm.access.group !7 655 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[I28]], align 4, !llvm.access.group !7 656 // CHECK1-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 657 // CHECK1-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM35]] 658 // CHECK1-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4, !llvm.access.group !7 659 // CHECK1-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7 660 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] 661 // CHECK1: omp.body.continue37: 662 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]] 663 // CHECK1: omp.inner.for.inc38: 664 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 665 // CHECK1-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1 666 // CHECK1-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 667 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group !7 668 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]] 669 // CHECK1: omp.inner.for.end40: 670 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 671 // CHECK1: omp.dispatch.inc: 672 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 673 // CHECK1: omp.dispatch.end: 674 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 675 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 676 // CHECK1-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 677 // CHECK1: .omp.final.then: 678 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 679 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 680 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 681 // CHECK1-NEXT: [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]] 682 // CHECK1-NEXT: [[SUB42:%.*]] = sub i32 [[SUB41]], 1 683 // CHECK1-NEXT: [[ADD43:%.*]] = add i32 [[SUB42]], 1 684 // CHECK1-NEXT: [[DIV44:%.*]] = udiv i32 [[ADD43]], 1 685 // CHECK1-NEXT: [[MUL45:%.*]] = mul i32 [[DIV44]], 1 686 // CHECK1-NEXT: [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]] 687 // CHECK1-NEXT: store i32 [[ADD46]], i32* [[I28]], align 4 688 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 689 // CHECK1: .omp.final.done: 690 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 691 // CHECK1: omp.precond.end: 692 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 693 // CHECK1-NEXT: ret void 694 // 695 // 696 // CHECK1-LABEL: define {{[^@]+}}@__captured_stmt 697 // CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 698 // CHECK1-NEXT: entry: 699 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 700 // CHECK1-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 701 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 702 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 703 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 704 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 705 // CHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 706 // CHECK1-NEXT: ret void 707 // 708 // 709 // CHECK1-LABEL: define {{[^@]+}}@__captured_stmt.1 710 // CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 711 // CHECK1-NEXT: entry: 712 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 713 // CHECK1-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 714 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 715 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 716 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 717 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 718 // CHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 719 // CHECK1-NEXT: ret void 720 // 721 // 722 // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 723 // CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 724 // CHECK2-NEXT: entry: 725 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 726 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 727 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 728 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 729 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 730 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 731 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 732 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 733 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 734 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 735 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 736 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 737 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 738 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 739 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 740 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 741 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 742 // CHECK2-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 743 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 744 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 745 // CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 746 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 747 // CHECK2: omp.dispatch.cond: 748 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 749 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 750 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 751 // CHECK2: omp.dispatch.body: 752 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 753 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 754 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 755 // CHECK2: omp.inner.for.cond: 756 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 757 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 758 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 759 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 760 // CHECK2: omp.inner.for.body: 761 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 762 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7 763 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 764 // CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4 765 // CHECK2-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 766 // CHECK2-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 767 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 768 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 769 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM]] 770 // CHECK2-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 771 // CHECK2-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 772 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 773 // CHECK2-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64 774 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM1]] 775 // CHECK2-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 776 // CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 777 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 778 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 779 // CHECK2-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64 780 // CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM4]] 781 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX5]], align 4 782 // CHECK2-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]] 783 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 784 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 785 // CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 786 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM7]] 787 // CHECK2-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 788 // CHECK2-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 789 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 790 // CHECK2: omp.body.continue: 791 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 792 // CHECK2: omp.inner.for.inc: 793 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 794 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], 1 795 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 796 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 797 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 798 // CHECK2: omp.inner.for.end: 799 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 800 // CHECK2: omp.dispatch.inc: 801 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 802 // CHECK2: omp.dispatch.end: 803 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP0]]) 804 // CHECK2-NEXT: ret void 805 // 806 // 807 // CHECK2-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 808 // CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 809 // CHECK2-NEXT: entry: 810 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 811 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 812 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 813 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 814 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 815 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 816 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 817 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 818 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 819 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 820 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 821 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 822 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 823 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 824 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 825 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 826 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 827 // CHECK2-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 828 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 829 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 830 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1) 831 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 832 // CHECK2: omp.dispatch.cond: 833 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 834 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 835 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 836 // CHECK2: omp.dispatch.body: 837 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 838 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[DOTOMP_IV]], align 8 839 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 840 // CHECK2: omp.inner.for.cond: 841 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 842 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 843 // CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP4]], 1 844 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]] 845 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 846 // CHECK2: omp.inner.for.body: 847 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 848 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP5]], 127 849 // CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 850 // CHECK2-NEXT: store i64 [[ADD1]], i64* [[I]], align 8 851 // CHECK2-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 852 // CHECK2-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 853 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[I]], align 8 854 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[TMP7]] 855 // CHECK2-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 856 // CHECK2-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 857 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[I]], align 8 858 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[TMP10]] 859 // CHECK2-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 860 // CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 861 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 862 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[I]], align 8 863 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[TMP13]] 864 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX4]], align 4 865 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]] 866 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 867 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[I]], align 8 868 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[TMP16]] 869 // CHECK2-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 870 // CHECK2-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 871 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 872 // CHECK2: omp.body.continue: 873 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 874 // CHECK2: omp.inner.for.inc: 875 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 876 // CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP17]], 1 877 // CHECK2-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 878 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 879 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 880 // CHECK2: omp.inner.for.end: 881 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 882 // CHECK2: omp.dispatch.inc: 883 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 884 // CHECK2: omp.dispatch.end: 885 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 886 // CHECK2-NEXT: ret void 887 // 888 // 889 // CHECK2-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 890 // CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 891 // CHECK2-NEXT: entry: 892 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 893 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 894 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 895 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 896 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 897 // CHECK2-NEXT: [[Y:%.*]] = alloca i32, align 4 898 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 899 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 900 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 901 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 902 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 903 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1 904 // CHECK2-NEXT: [[X6:%.*]] = alloca i32, align 4 905 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 906 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 907 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 908 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 909 // CHECK2-NEXT: [[I8:%.*]] = alloca i8, align 1 910 // CHECK2-NEXT: [[X9:%.*]] = alloca i32, align 4 911 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 912 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 913 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 914 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 915 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 916 // CHECK2-NEXT: store i32 0, i32* [[X]], align 4 917 // CHECK2-NEXT: store i32 0, i32* [[Y]], align 4 918 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[Y]], align 4 919 // CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[TMP1]] to i8 920 // CHECK2-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 921 // CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 922 // CHECK2-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 923 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 924 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 925 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 926 // CHECK2-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 927 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 928 // CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 929 // CHECK2-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 930 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 931 // CHECK2-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 932 // CHECK2-NEXT: store i32 11, i32* [[X6]], align 4 933 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 934 // CHECK2-NEXT: [[CONV7:%.*]] = sext i8 [[TMP4]] to i32 935 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 936 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 937 // CHECK2: omp.precond.then: 938 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 939 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 940 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_UB]], align 8 941 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 942 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 943 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 944 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741894, i64 0, i64 [[TMP6]], i64 1, i64 1) 945 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 946 // CHECK2: omp.dispatch.cond: 947 // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 948 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 949 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 950 // CHECK2: omp.dispatch.body: 951 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 952 // CHECK2-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 953 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 954 // CHECK2: omp.inner.for.cond: 955 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 956 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 957 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]] 958 // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 959 // CHECK2: omp.inner.for.body: 960 // CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 961 // CHECK2-NEXT: [[CONV11:%.*]] = sext i8 [[TMP11]] to i64 962 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 963 // CHECK2-NEXT: [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11 964 // CHECK2-NEXT: [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1 965 // CHECK2-NEXT: [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]] 966 // CHECK2-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8 967 // CHECK2-NEXT: store i8 [[CONV15]], i8* [[I8]], align 1 968 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 969 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 970 // CHECK2-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11 971 // CHECK2-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11 972 // CHECK2-NEXT: [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]] 973 // CHECK2-NEXT: [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1 974 // CHECK2-NEXT: [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]] 975 // CHECK2-NEXT: [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32 976 // CHECK2-NEXT: store i32 [[CONV21]], i32* [[X9]], align 4 977 // CHECK2-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 978 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[B_ADDR]], align 8 979 // CHECK2-NEXT: [[TMP16:%.*]] = load i8, i8* [[I8]], align 1 980 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64 981 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM]] 982 // CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4 983 // CHECK2-NEXT: [[TMP18:%.*]] = load float*, float** [[C_ADDR]], align 8 984 // CHECK2-NEXT: [[TMP19:%.*]] = load i8, i8* [[I8]], align 1 985 // CHECK2-NEXT: [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64 986 // CHECK2-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM22]] 987 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX23]], align 4 988 // CHECK2-NEXT: [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]] 989 // CHECK2-NEXT: [[TMP21:%.*]] = load float*, float** [[D_ADDR]], align 8 990 // CHECK2-NEXT: [[TMP22:%.*]] = load i8, i8* [[I8]], align 1 991 // CHECK2-NEXT: [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64 992 // CHECK2-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM25]] 993 // CHECK2-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX26]], align 4 994 // CHECK2-NEXT: [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]] 995 // CHECK2-NEXT: [[TMP24:%.*]] = load float*, float** [[A_ADDR]], align 8 996 // CHECK2-NEXT: [[TMP25:%.*]] = load i8, i8* [[I8]], align 1 997 // CHECK2-NEXT: [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64 998 // CHECK2-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM28]] 999 // CHECK2-NEXT: store float [[MUL27]], float* [[ARRAYIDX29]], align 4 1000 // CHECK2-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1001 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1002 // CHECK2: omp.body.continue: 1003 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1004 // CHECK2: omp.inner.for.inc: 1005 // CHECK2-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1006 // CHECK2-NEXT: [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1 1007 // CHECK2-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 1008 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1009 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1010 // CHECK2: omp.inner.for.end: 1011 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1012 // CHECK2: omp.dispatch.inc: 1013 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1014 // CHECK2: omp.dispatch.end: 1015 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 1016 // CHECK2: omp.precond.end: 1017 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1018 // CHECK2-NEXT: ret void 1019 // 1020 // 1021 // CHECK2-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 1022 // CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1023 // CHECK2-NEXT: entry: 1024 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1025 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1026 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1027 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1028 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 1029 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1030 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 1031 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1032 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1033 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1034 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1035 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1036 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1 1037 // CHECK2-NEXT: [[X2:%.*]] = alloca i32, align 4 1038 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1039 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1040 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1041 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1042 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1043 // CHECK2-NEXT: store i32 0, i32* [[X]], align 4 1044 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1045 // CHECK2-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 1046 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1047 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1048 // CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741893, i32 0, i32 199, i32 1, i32 1) 1049 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1050 // CHECK2: omp.dispatch.cond: 1051 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1052 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 1053 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1054 // CHECK2: omp.dispatch.body: 1055 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1056 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 1057 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1058 // CHECK2: omp.inner.for.cond: 1059 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1060 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1061 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 1062 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1063 // CHECK2: omp.inner.for.body: 1064 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1065 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 20 1066 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1067 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 1068 // CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 1069 // CHECK2-NEXT: store i8 [[CONV]], i8* [[I]], align 1 1070 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1071 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1072 // CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20 1073 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20 1074 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]] 1075 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1076 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]] 1077 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[X2]], align 4 1078 // CHECK2-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1079 // CHECK2-NEXT: [[TMP8:%.*]] = load float*, float** [[B_ADDR]], align 8 1080 // CHECK2-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 1081 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64 1082 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 1083 // CHECK2-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 1084 // CHECK2-NEXT: [[TMP11:%.*]] = load float*, float** [[C_ADDR]], align 8 1085 // CHECK2-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 1086 // CHECK2-NEXT: [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64 1087 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM7]] 1088 // CHECK2-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX8]], align 4 1089 // CHECK2-NEXT: [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]] 1090 // CHECK2-NEXT: [[TMP14:%.*]] = load float*, float** [[D_ADDR]], align 8 1091 // CHECK2-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 1092 // CHECK2-NEXT: [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64 1093 // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM10]] 1094 // CHECK2-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX11]], align 4 1095 // CHECK2-NEXT: [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]] 1096 // CHECK2-NEXT: [[TMP17:%.*]] = load float*, float** [[A_ADDR]], align 8 1097 // CHECK2-NEXT: [[TMP18:%.*]] = load i8, i8* [[I]], align 1 1098 // CHECK2-NEXT: [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64 1099 // CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM13]] 1100 // CHECK2-NEXT: store float [[MUL12]], float* [[ARRAYIDX14]], align 4 1101 // CHECK2-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1102 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1103 // CHECK2: omp.body.continue: 1104 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1105 // CHECK2: omp.inner.for.inc: 1106 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1107 // CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1 1108 // CHECK2-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4 1109 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1110 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1111 // CHECK2: omp.inner.for.end: 1112 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1113 // CHECK2: omp.dispatch.inc: 1114 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1115 // CHECK2: omp.dispatch.end: 1116 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1117 // CHECK2-NEXT: ret void 1118 // 1119 // 1120 // CHECK2-LABEL: define {{[^@]+}}@_Z8foo_simdii 1121 // CHECK2-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { 1122 // CHECK2-NEXT: entry: 1123 // CHECK2-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 1124 // CHECK2-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 1125 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1126 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1127 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1128 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1129 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1130 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1131 // CHECK2-NEXT: [[I5:%.*]] = alloca i32, align 4 1132 // CHECK2-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 1133 // CHECK2-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 1134 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 1135 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 1136 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 1137 // CHECK2-NEXT: [[I26:%.*]] = alloca i32, align 4 1138 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1139 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1140 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1141 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1142 // CHECK2-NEXT: [[I28:%.*]] = alloca i32, align 4 1143 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1144 // CHECK2-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 1145 // CHECK2-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 1146 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 1147 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 1148 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[UP_ADDR]], align 4 1149 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1150 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1151 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1152 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 1153 // CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 1154 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 1155 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1156 // CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 1157 // CHECK2-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1158 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1159 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 1160 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1161 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1162 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 1163 // CHECK2-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 1164 // CHECK2: simd.if.then: 1165 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 1166 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1167 // CHECK2: omp.inner.for.cond: 1168 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1169 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 1170 // CHECK2-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 1171 // CHECK2-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]] 1172 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1173 // CHECK2: omp.inner.for.body: 1174 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3 1175 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1176 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1 1177 // CHECK2-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]] 1178 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3 1179 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !3 1180 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 1181 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1182 // CHECK2-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 1183 // CHECK2-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3 1184 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1185 // CHECK2: omp.body.continue: 1186 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1187 // CHECK2: omp.inner.for.inc: 1188 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1189 // CHECK2-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1 1190 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1191 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1192 // CHECK2: omp.inner.for.end: 1193 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1194 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1195 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1196 // CHECK2-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]] 1197 // CHECK2-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 1198 // CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 1199 // CHECK2-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 1200 // CHECK2-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 1201 // CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]] 1202 // CHECK2-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 1203 // CHECK2-NEXT: br label [[SIMD_IF_END]] 1204 // CHECK2: simd.if.end: 1205 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 1206 // CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_18]], align 4 1207 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 1208 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_19]], align 4 1209 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1210 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1211 // CHECK2-NEXT: [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]] 1212 // CHECK2-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 1213 // CHECK2-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 1214 // CHECK2-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 1215 // CHECK2-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 1216 // CHECK2-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 1217 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1218 // CHECK2-NEXT: store i32 [[TMP21]], i32* [[I26]], align 4 1219 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1220 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1221 // CHECK2-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] 1222 // CHECK2-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1223 // CHECK2: omp.precond.then: 1224 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1225 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 1226 // CHECK2-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_UB]], align 4 1227 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1228 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1229 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 1230 // CHECK2-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1) 1231 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1232 // CHECK2: omp.dispatch.cond: 1233 // CHECK2-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1234 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0 1235 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1236 // CHECK2: omp.dispatch.body: 1237 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1238 // CHECK2-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4 1239 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 1240 // CHECK2: omp.inner.for.cond29: 1241 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1242 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 1243 // CHECK2-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1 1244 // CHECK2-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]] 1245 // CHECK2-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]] 1246 // CHECK2: omp.inner.for.body32: 1247 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7 1248 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1249 // CHECK2-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1 1250 // CHECK2-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]] 1251 // CHECK2-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4, !llvm.access.group !7 1252 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[I28]], align 4, !llvm.access.group !7 1253 // CHECK2-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 1254 // CHECK2-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM35]] 1255 // CHECK2-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4, !llvm.access.group !7 1256 // CHECK2-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7 1257 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] 1258 // CHECK2: omp.body.continue37: 1259 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]] 1260 // CHECK2: omp.inner.for.inc38: 1261 // CHECK2-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1262 // CHECK2-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1 1263 // CHECK2-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1264 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group !7 1265 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]] 1266 // CHECK2: omp.inner.for.end40: 1267 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1268 // CHECK2: omp.dispatch.inc: 1269 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1270 // CHECK2: omp.dispatch.end: 1271 // CHECK2-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1272 // CHECK2-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1273 // CHECK2-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1274 // CHECK2: .omp.final.then: 1275 // CHECK2-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1276 // CHECK2-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1277 // CHECK2-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1278 // CHECK2-NEXT: [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]] 1279 // CHECK2-NEXT: [[SUB42:%.*]] = sub i32 [[SUB41]], 1 1280 // CHECK2-NEXT: [[ADD43:%.*]] = add i32 [[SUB42]], 1 1281 // CHECK2-NEXT: [[DIV44:%.*]] = udiv i32 [[ADD43]], 1 1282 // CHECK2-NEXT: [[MUL45:%.*]] = mul i32 [[DIV44]], 1 1283 // CHECK2-NEXT: [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]] 1284 // CHECK2-NEXT: store i32 [[ADD46]], i32* [[I28]], align 4 1285 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] 1286 // CHECK2: .omp.final.done: 1287 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 1288 // CHECK2: omp.precond.end: 1289 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1290 // CHECK2-NEXT: ret void 1291 // 1292 // 1293 // CHECK2-LABEL: define {{[^@]+}}@__captured_stmt 1294 // CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 1295 // CHECK2-NEXT: entry: 1296 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 1297 // CHECK2-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 1298 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 1299 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1300 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 1301 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1302 // CHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 1303 // CHECK2-NEXT: ret void 1304 // 1305 // 1306 // CHECK2-LABEL: define {{[^@]+}}@__captured_stmt.1 1307 // CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 1308 // CHECK2-NEXT: entry: 1309 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 1310 // CHECK2-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 1311 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 1312 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1313 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 1314 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1315 // CHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 1316 // CHECK2-NEXT: ret void 1317 // 1318 // 1319 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1320 // CHECK1-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 1321 // CHECK1-IRBUILDER-NEXT: entry: 1322 // CHECK1-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1323 // CHECK1-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1324 // CHECK1-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1325 // CHECK1-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1326 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1327 // CHECK1-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i32, align 4 1328 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1329 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1330 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1331 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1332 // CHECK1-IRBUILDER-NEXT: [[I:%.*]] = alloca i32, align 4 1333 // CHECK1-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1334 // CHECK1-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1335 // CHECK1-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1336 // CHECK1-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1337 // CHECK1-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1338 // CHECK1-IRBUILDER-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1339 // CHECK1-IRBUILDER-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1340 // CHECK1-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1341 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 1342 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 1343 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1344 // CHECK1-IRBUILDER: omp.dispatch.cond: 1345 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 1346 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1347 // CHECK1-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 1348 // CHECK1-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1349 // CHECK1-IRBUILDER: omp.dispatch.body: 1350 // CHECK1-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1351 // CHECK1-IRBUILDER-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1352 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1353 // CHECK1-IRBUILDER: omp.inner.for.cond: 1354 // CHECK1-IRBUILDER-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1355 // CHECK1-IRBUILDER-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1356 // CHECK1-IRBUILDER-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1357 // CHECK1-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1358 // CHECK1-IRBUILDER: omp.inner.for.body: 1359 // CHECK1-IRBUILDER-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1360 // CHECK1-IRBUILDER-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 1361 // CHECK1-IRBUILDER-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1362 // CHECK1-IRBUILDER-NEXT: store i32 [[SUB]], i32* [[I]], align 4 1363 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1364 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) 1365 // CHECK1-IRBUILDER-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8 1366 // CHECK1-IRBUILDER-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 1367 // CHECK1-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 1368 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]] 1369 // CHECK1-IRBUILDER-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4 1370 // CHECK1-IRBUILDER-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8 1371 // CHECK1-IRBUILDER-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1372 // CHECK1-IRBUILDER-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 1373 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM3]] 1374 // CHECK1-IRBUILDER-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX4]], align 4 1375 // CHECK1-IRBUILDER-NEXT: [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]] 1376 // CHECK1-IRBUILDER-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8 1377 // CHECK1-IRBUILDER-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 1378 // CHECK1-IRBUILDER-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP12]] to i64 1379 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM6]] 1380 // CHECK1-IRBUILDER-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX7]], align 4 1381 // CHECK1-IRBUILDER-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP13]] 1382 // CHECK1-IRBUILDER-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8 1383 // CHECK1-IRBUILDER-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 1384 // CHECK1-IRBUILDER-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64 1385 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM9]] 1386 // CHECK1-IRBUILDER-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 1387 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 1388 // CHECK1-IRBUILDER: omp.inner.for.body.ordered.after: 1389 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) 1390 // CHECK1-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1391 // CHECK1-IRBUILDER: omp.body.continue: 1392 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1393 // CHECK1-IRBUILDER: omp.inner.for.inc: 1394 // CHECK1-IRBUILDER-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1395 // CHECK1-IRBUILDER-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 1396 // CHECK1-IRBUILDER-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1397 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 1398 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) 1399 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 1400 // CHECK1-IRBUILDER: omp.inner.for.end: 1401 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1402 // CHECK1-IRBUILDER: omp.dispatch.inc: 1403 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 1404 // CHECK1-IRBUILDER: omp.dispatch.end: 1405 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1406 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM12]]) 1407 // CHECK1-IRBUILDER-NEXT: ret void 1408 // 1409 // 1410 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 1411 // CHECK1-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1412 // CHECK1-IRBUILDER-NEXT: entry: 1413 // CHECK1-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1414 // CHECK1-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1415 // CHECK1-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1416 // CHECK1-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1417 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1418 // CHECK1-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i64, align 8 1419 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1420 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1421 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1422 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1423 // CHECK1-IRBUILDER-NEXT: [[I:%.*]] = alloca i64, align 8 1424 // CHECK1-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1425 // CHECK1-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1426 // CHECK1-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1427 // CHECK1-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1428 // CHECK1-IRBUILDER-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1429 // CHECK1-IRBUILDER-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 1430 // CHECK1-IRBUILDER-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1431 // CHECK1-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1432 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6:[0-9]+]]) 1433 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1) 1434 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1435 // CHECK1-IRBUILDER: omp.dispatch.cond: 1436 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 1437 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1438 // CHECK1-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 1439 // CHECK1-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1440 // CHECK1-IRBUILDER: omp.dispatch.body: 1441 // CHECK1-IRBUILDER-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1442 // CHECK1-IRBUILDER-NEXT: store i64 [[TMP1]], i64* [[DOTOMP_IV]], align 8 1443 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1444 // CHECK1-IRBUILDER: omp.inner.for.cond: 1445 // CHECK1-IRBUILDER-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1446 // CHECK1-IRBUILDER-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1447 // CHECK1-IRBUILDER-NEXT: [[ADD:%.*]] = add i64 [[TMP3]], 1 1448 // CHECK1-IRBUILDER-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP2]], [[ADD]] 1449 // CHECK1-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1450 // CHECK1-IRBUILDER: omp.inner.for.body: 1451 // CHECK1-IRBUILDER-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1452 // CHECK1-IRBUILDER-NEXT: [[MUL:%.*]] = mul i64 [[TMP4]], 127 1453 // CHECK1-IRBUILDER-NEXT: [[ADD2:%.*]] = add i64 131071, [[MUL]] 1454 // CHECK1-IRBUILDER-NEXT: store i64 [[ADD2]], i64* [[I]], align 8 1455 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1456 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) 1457 // CHECK1-IRBUILDER-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8 1458 // CHECK1-IRBUILDER-NEXT: [[TMP6:%.*]] = load i64, i64* [[I]], align 8 1459 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[TMP6]] 1460 // CHECK1-IRBUILDER-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4 1461 // CHECK1-IRBUILDER-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8 1462 // CHECK1-IRBUILDER-NEXT: [[TMP9:%.*]] = load i64, i64* [[I]], align 8 1463 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[TMP9]] 1464 // CHECK1-IRBUILDER-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX4]], align 4 1465 // CHECK1-IRBUILDER-NEXT: [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]] 1466 // CHECK1-IRBUILDER-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8 1467 // CHECK1-IRBUILDER-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 1468 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 1469 // CHECK1-IRBUILDER-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX6]], align 4 1470 // CHECK1-IRBUILDER-NEXT: [[MUL7:%.*]] = fmul float [[MUL5]], [[TMP13]] 1471 // CHECK1-IRBUILDER-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8 1472 // CHECK1-IRBUILDER-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8 1473 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 1474 // CHECK1-IRBUILDER-NEXT: store float [[MUL7]], float* [[ARRAYIDX8]], align 4 1475 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 1476 // CHECK1-IRBUILDER: omp.inner.for.body.ordered.after: 1477 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) 1478 // CHECK1-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1479 // CHECK1-IRBUILDER: omp.body.continue: 1480 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1481 // CHECK1-IRBUILDER: omp.inner.for.inc: 1482 // CHECK1-IRBUILDER-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1483 // CHECK1-IRBUILDER-NEXT: [[ADD9:%.*]] = add i64 [[TMP16]], 1 1484 // CHECK1-IRBUILDER-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8 1485 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 1486 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]]) 1487 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 1488 // CHECK1-IRBUILDER: omp.inner.for.end: 1489 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1490 // CHECK1-IRBUILDER: omp.dispatch.inc: 1491 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 1492 // CHECK1-IRBUILDER: omp.dispatch.end: 1493 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1494 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) 1495 // CHECK1-IRBUILDER-NEXT: ret void 1496 // 1497 // 1498 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 1499 // CHECK1-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1500 // CHECK1-IRBUILDER-NEXT: entry: 1501 // CHECK1-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1502 // CHECK1-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1503 // CHECK1-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1504 // CHECK1-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1505 // CHECK1-IRBUILDER-NEXT: [[X:%.*]] = alloca i32, align 4 1506 // CHECK1-IRBUILDER-NEXT: [[Y:%.*]] = alloca i32, align 4 1507 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1508 // CHECK1-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i8, align 1 1509 // CHECK1-IRBUILDER-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1510 // CHECK1-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1511 // CHECK1-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 1512 // CHECK1-IRBUILDER-NEXT: [[I:%.*]] = alloca i8, align 1 1513 // CHECK1-IRBUILDER-NEXT: [[X6:%.*]] = alloca i32, align 4 1514 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1515 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1516 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1517 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1518 // CHECK1-IRBUILDER-NEXT: [[I8:%.*]] = alloca i8, align 1 1519 // CHECK1-IRBUILDER-NEXT: [[X9:%.*]] = alloca i32, align 4 1520 // CHECK1-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1521 // CHECK1-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1522 // CHECK1-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1523 // CHECK1-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1524 // CHECK1-IRBUILDER-NEXT: store i32 0, i32* [[X]], align 4 1525 // CHECK1-IRBUILDER-NEXT: store i32 0, i32* [[Y]], align 4 1526 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 1527 // CHECK1-IRBUILDER-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 1528 // CHECK1-IRBUILDER-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 1529 // CHECK1-IRBUILDER-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1530 // CHECK1-IRBUILDER-NEXT: [[CONV3:%.*]] = sext i8 [[TMP1]] to i32 1531 // CHECK1-IRBUILDER-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 1532 // CHECK1-IRBUILDER-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 1533 // CHECK1-IRBUILDER-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1534 // CHECK1-IRBUILDER-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 1535 // CHECK1-IRBUILDER-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 1536 // CHECK1-IRBUILDER-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 1537 // CHECK1-IRBUILDER-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 1538 // CHECK1-IRBUILDER-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1539 // CHECK1-IRBUILDER-NEXT: store i8 [[TMP2]], i8* [[I]], align 1 1540 // CHECK1-IRBUILDER-NEXT: store i32 11, i32* [[X6]], align 4 1541 // CHECK1-IRBUILDER-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1542 // CHECK1-IRBUILDER-NEXT: [[CONV7:%.*]] = sext i8 [[TMP3]] to i32 1543 // CHECK1-IRBUILDER-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 1544 // CHECK1-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1545 // CHECK1-IRBUILDER: omp.precond.then: 1546 // CHECK1-IRBUILDER-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1547 // CHECK1-IRBUILDER-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1548 // CHECK1-IRBUILDER-NEXT: store i64 [[TMP4]], i64* [[DOTOMP_UB]], align 8 1549 // CHECK1-IRBUILDER-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1550 // CHECK1-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1551 // CHECK1-IRBUILDER-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1552 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8:[0-9]+]]) 1553 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741894, i64 0, i64 [[TMP5]], i64 1, i64 1) 1554 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1555 // CHECK1-IRBUILDER: omp.dispatch.cond: 1556 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 1557 // CHECK1-IRBUILDER-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1558 // CHECK1-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 1559 // CHECK1-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1560 // CHECK1-IRBUILDER: omp.dispatch.body: 1561 // CHECK1-IRBUILDER-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1562 // CHECK1-IRBUILDER-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 1563 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1564 // CHECK1-IRBUILDER: omp.inner.for.cond: 1565 // CHECK1-IRBUILDER-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1566 // CHECK1-IRBUILDER-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1567 // CHECK1-IRBUILDER-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP8]], [[TMP9]] 1568 // CHECK1-IRBUILDER-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1569 // CHECK1-IRBUILDER: omp.inner.for.body: 1570 // CHECK1-IRBUILDER-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1571 // CHECK1-IRBUILDER-NEXT: [[CONV12:%.*]] = sext i8 [[TMP10]] to i64 1572 // CHECK1-IRBUILDER-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1573 // CHECK1-IRBUILDER-NEXT: [[DIV13:%.*]] = sdiv i64 [[TMP11]], 11 1574 // CHECK1-IRBUILDER-NEXT: [[MUL14:%.*]] = mul nsw i64 [[DIV13]], 1 1575 // CHECK1-IRBUILDER-NEXT: [[ADD15:%.*]] = add nsw i64 [[CONV12]], [[MUL14]] 1576 // CHECK1-IRBUILDER-NEXT: [[CONV16:%.*]] = trunc i64 [[ADD15]] to i8 1577 // CHECK1-IRBUILDER-NEXT: store i8 [[CONV16]], i8* [[I8]], align 1 1578 // CHECK1-IRBUILDER-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1579 // CHECK1-IRBUILDER-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1580 // CHECK1-IRBUILDER-NEXT: [[DIV17:%.*]] = sdiv i64 [[TMP13]], 11 1581 // CHECK1-IRBUILDER-NEXT: [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 11 1582 // CHECK1-IRBUILDER-NEXT: [[SUB19:%.*]] = sub nsw i64 [[TMP12]], [[MUL18]] 1583 // CHECK1-IRBUILDER-NEXT: [[MUL20:%.*]] = mul nsw i64 [[SUB19]], 1 1584 // CHECK1-IRBUILDER-NEXT: [[SUB21:%.*]] = sub nsw i64 11, [[MUL20]] 1585 // CHECK1-IRBUILDER-NEXT: [[CONV22:%.*]] = trunc i64 [[SUB21]] to i32 1586 // CHECK1-IRBUILDER-NEXT: store i32 [[CONV22]], i32* [[X9]], align 4 1587 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1588 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]]) 1589 // CHECK1-IRBUILDER-NEXT: [[TMP14:%.*]] = load float*, float** [[B_ADDR]], align 8 1590 // CHECK1-IRBUILDER-NEXT: [[TMP15:%.*]] = load i8, i8* [[I8]], align 1 1591 // CHECK1-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP15]] to i64 1592 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 1593 // CHECK1-IRBUILDER-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4 1594 // CHECK1-IRBUILDER-NEXT: [[TMP17:%.*]] = load float*, float** [[C_ADDR]], align 8 1595 // CHECK1-IRBUILDER-NEXT: [[TMP18:%.*]] = load i8, i8* [[I8]], align 1 1596 // CHECK1-IRBUILDER-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP18]] to i64 1597 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM24]] 1598 // CHECK1-IRBUILDER-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX25]], align 4 1599 // CHECK1-IRBUILDER-NEXT: [[MUL26:%.*]] = fmul float [[TMP16]], [[TMP19]] 1600 // CHECK1-IRBUILDER-NEXT: [[TMP20:%.*]] = load float*, float** [[D_ADDR]], align 8 1601 // CHECK1-IRBUILDER-NEXT: [[TMP21:%.*]] = load i8, i8* [[I8]], align 1 1602 // CHECK1-IRBUILDER-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP21]] to i64 1603 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM27]] 1604 // CHECK1-IRBUILDER-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX28]], align 4 1605 // CHECK1-IRBUILDER-NEXT: [[MUL29:%.*]] = fmul float [[MUL26]], [[TMP22]] 1606 // CHECK1-IRBUILDER-NEXT: [[TMP23:%.*]] = load float*, float** [[A_ADDR]], align 8 1607 // CHECK1-IRBUILDER-NEXT: [[TMP24:%.*]] = load i8, i8* [[I8]], align 1 1608 // CHECK1-IRBUILDER-NEXT: [[IDXPROM30:%.*]] = sext i8 [[TMP24]] to i64 1609 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM30]] 1610 // CHECK1-IRBUILDER-NEXT: store float [[MUL29]], float* [[ARRAYIDX31]], align 4 1611 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 1612 // CHECK1-IRBUILDER: omp.inner.for.body.ordered.after: 1613 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]]) 1614 // CHECK1-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1615 // CHECK1-IRBUILDER: omp.body.continue: 1616 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1617 // CHECK1-IRBUILDER: omp.inner.for.inc: 1618 // CHECK1-IRBUILDER-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1619 // CHECK1-IRBUILDER-NEXT: [[ADD32:%.*]] = add nsw i64 [[TMP25]], 1 1620 // CHECK1-IRBUILDER-NEXT: store i64 [[ADD32]], i64* [[DOTOMP_IV]], align 8 1621 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM33:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 1622 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM33]]) 1623 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 1624 // CHECK1-IRBUILDER: omp.inner.for.end: 1625 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1626 // CHECK1-IRBUILDER: omp.dispatch.inc: 1627 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 1628 // CHECK1-IRBUILDER: omp.dispatch.end: 1629 // CHECK1-IRBUILDER-NEXT: br label [[OMP_PRECOND_END]] 1630 // CHECK1-IRBUILDER: omp.precond.end: 1631 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM34:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1632 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM34]]) 1633 // CHECK1-IRBUILDER-NEXT: ret void 1634 // 1635 // 1636 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 1637 // CHECK1-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1638 // CHECK1-IRBUILDER-NEXT: entry: 1639 // CHECK1-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1640 // CHECK1-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1641 // CHECK1-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1642 // CHECK1-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1643 // CHECK1-IRBUILDER-NEXT: [[X:%.*]] = alloca i32, align 4 1644 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1645 // CHECK1-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i8, align 1 1646 // CHECK1-IRBUILDER-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1647 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1648 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1649 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1650 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1651 // CHECK1-IRBUILDER-NEXT: [[I:%.*]] = alloca i8, align 1 1652 // CHECK1-IRBUILDER-NEXT: [[X2:%.*]] = alloca i32, align 4 1653 // CHECK1-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1654 // CHECK1-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1655 // CHECK1-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1656 // CHECK1-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1657 // CHECK1-IRBUILDER-NEXT: store i32 0, i32* [[X]], align 4 1658 // CHECK1-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1659 // CHECK1-IRBUILDER-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 1660 // CHECK1-IRBUILDER-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1661 // CHECK1-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1662 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10:[0-9]+]]) 1663 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741893, i32 0, i32 199, i32 1, i32 1) 1664 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1665 // CHECK1-IRBUILDER: omp.dispatch.cond: 1666 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 1667 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1668 // CHECK1-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 1669 // CHECK1-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1670 // CHECK1-IRBUILDER: omp.dispatch.body: 1671 // CHECK1-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1672 // CHECK1-IRBUILDER-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1673 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1674 // CHECK1-IRBUILDER: omp.inner.for.cond: 1675 // CHECK1-IRBUILDER-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1676 // CHECK1-IRBUILDER-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1677 // CHECK1-IRBUILDER-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1678 // CHECK1-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1679 // CHECK1-IRBUILDER: omp.inner.for.body: 1680 // CHECK1-IRBUILDER-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1681 // CHECK1-IRBUILDER-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 20 1682 // CHECK1-IRBUILDER-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1683 // CHECK1-IRBUILDER-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 1684 // CHECK1-IRBUILDER-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 1685 // CHECK1-IRBUILDER-NEXT: store i8 [[CONV]], i8* [[I]], align 1 1686 // CHECK1-IRBUILDER-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1687 // CHECK1-IRBUILDER-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1688 // CHECK1-IRBUILDER-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP6]], 20 1689 // CHECK1-IRBUILDER-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 20 1690 // CHECK1-IRBUILDER-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], [[MUL5]] 1691 // CHECK1-IRBUILDER-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 1692 // CHECK1-IRBUILDER-NEXT: [[ADD7:%.*]] = add nsw i32 -10, [[MUL6]] 1693 // CHECK1-IRBUILDER-NEXT: store i32 [[ADD7]], i32* [[X2]], align 4 1694 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM8:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1695 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]]) 1696 // CHECK1-IRBUILDER-NEXT: [[TMP7:%.*]] = load float*, float** [[B_ADDR]], align 8 1697 // CHECK1-IRBUILDER-NEXT: [[TMP8:%.*]] = load i8, i8* [[I]], align 1 1698 // CHECK1-IRBUILDER-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP8]] to i64 1699 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM]] 1700 // CHECK1-IRBUILDER-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 1701 // CHECK1-IRBUILDER-NEXT: [[TMP10:%.*]] = load float*, float** [[C_ADDR]], align 8 1702 // CHECK1-IRBUILDER-NEXT: [[TMP11:%.*]] = load i8, i8* [[I]], align 1 1703 // CHECK1-IRBUILDER-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP11]] to i64 1704 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM9]] 1705 // CHECK1-IRBUILDER-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX10]], align 4 1706 // CHECK1-IRBUILDER-NEXT: [[MUL11:%.*]] = fmul float [[TMP9]], [[TMP12]] 1707 // CHECK1-IRBUILDER-NEXT: [[TMP13:%.*]] = load float*, float** [[D_ADDR]], align 8 1708 // CHECK1-IRBUILDER-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 1709 // CHECK1-IRBUILDER-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP14]] to i64 1710 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM12]] 1711 // CHECK1-IRBUILDER-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX13]], align 4 1712 // CHECK1-IRBUILDER-NEXT: [[MUL14:%.*]] = fmul float [[MUL11]], [[TMP15]] 1713 // CHECK1-IRBUILDER-NEXT: [[TMP16:%.*]] = load float*, float** [[A_ADDR]], align 8 1714 // CHECK1-IRBUILDER-NEXT: [[TMP17:%.*]] = load i8, i8* [[I]], align 1 1715 // CHECK1-IRBUILDER-NEXT: [[IDXPROM15:%.*]] = zext i8 [[TMP17]] to i64 1716 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM15]] 1717 // CHECK1-IRBUILDER-NEXT: store float [[MUL14]], float* [[ARRAYIDX16]], align 4 1718 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 1719 // CHECK1-IRBUILDER: omp.inner.for.body.ordered.after: 1720 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]]) 1721 // CHECK1-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1722 // CHECK1-IRBUILDER: omp.body.continue: 1723 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1724 // CHECK1-IRBUILDER: omp.inner.for.inc: 1725 // CHECK1-IRBUILDER-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1726 // CHECK1-IRBUILDER-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP18]], 1 1727 // CHECK1-IRBUILDER-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4 1728 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 1729 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM18]]) 1730 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 1731 // CHECK1-IRBUILDER: omp.inner.for.end: 1732 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1733 // CHECK1-IRBUILDER: omp.dispatch.inc: 1734 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 1735 // CHECK1-IRBUILDER: omp.dispatch.end: 1736 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM19:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1737 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM19]]) 1738 // CHECK1-IRBUILDER-NEXT: ret void 1739 // 1740 // 1741 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z8foo_simdii 1742 // CHECK1-IRBUILDER-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { 1743 // CHECK1-IRBUILDER-NEXT: entry: 1744 // CHECK1-IRBUILDER-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 1745 // CHECK1-IRBUILDER-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 1746 // CHECK1-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i32, align 4 1747 // CHECK1-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1748 // CHECK1-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1749 // CHECK1-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1750 // CHECK1-IRBUILDER-NEXT: [[I:%.*]] = alloca i32, align 4 1751 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1752 // CHECK1-IRBUILDER-NEXT: [[I5:%.*]] = alloca i32, align 4 1753 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 1754 // CHECK1-IRBUILDER-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 1755 // CHECK1-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 1756 // CHECK1-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 1757 // CHECK1-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 1758 // CHECK1-IRBUILDER-NEXT: [[I26:%.*]] = alloca i32, align 4 1759 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1760 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1761 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1762 // CHECK1-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1763 // CHECK1-IRBUILDER-NEXT: [[I28:%.*]] = alloca i32, align 4 1764 // CHECK1-IRBUILDER-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 1765 // CHECK1-IRBUILDER-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 1766 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 1767 // CHECK1-IRBUILDER-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 1768 // CHECK1-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[UP_ADDR]], align 4 1769 // CHECK1-IRBUILDER-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1770 // CHECK1-IRBUILDER-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1771 // CHECK1-IRBUILDER-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1772 // CHECK1-IRBUILDER-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 1773 // CHECK1-IRBUILDER-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 1774 // CHECK1-IRBUILDER-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 1775 // CHECK1-IRBUILDER-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1776 // CHECK1-IRBUILDER-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 1777 // CHECK1-IRBUILDER-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1778 // CHECK1-IRBUILDER-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1779 // CHECK1-IRBUILDER-NEXT: store i32 [[TMP4]], i32* [[I]], align 4 1780 // CHECK1-IRBUILDER-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1781 // CHECK1-IRBUILDER-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1782 // CHECK1-IRBUILDER-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] 1783 // CHECK1-IRBUILDER-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 1784 // CHECK1-IRBUILDER: simd.if.then: 1785 // CHECK1-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 1786 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1787 // CHECK1-IRBUILDER: omp.inner.for.cond: 1788 // CHECK1-IRBUILDER-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1789 // CHECK1-IRBUILDER-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 1790 // CHECK1-IRBUILDER-NEXT: [[ADD6:%.*]] = add i32 [[TMP8]], 1 1791 // CHECK1-IRBUILDER-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]] 1792 // CHECK1-IRBUILDER-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1793 // CHECK1-IRBUILDER: omp.inner.for.body: 1794 // CHECK1-IRBUILDER-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3 1795 // CHECK1-IRBUILDER-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1796 // CHECK1-IRBUILDER-NEXT: [[MUL:%.*]] = mul i32 [[TMP10]], 1 1797 // CHECK1-IRBUILDER-NEXT: [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]] 1798 // CHECK1-IRBUILDER-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3 1799 // CHECK1-IRBUILDER-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !3 1800 // CHECK1-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 1801 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1802 // CHECK1-IRBUILDER-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 1803 // CHECK1-IRBUILDER-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3 1804 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 1805 // CHECK1-IRBUILDER: omp.inner.for.body.ordered.after: 1806 // CHECK1-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1807 // CHECK1-IRBUILDER: omp.body.continue: 1808 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1809 // CHECK1-IRBUILDER: omp.inner.for.inc: 1810 // CHECK1-IRBUILDER-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1811 // CHECK1-IRBUILDER-NEXT: [[ADD9:%.*]] = add i32 [[TMP12]], 1 1812 // CHECK1-IRBUILDER-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1813 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1814 // CHECK1-IRBUILDER: omp.inner.for.end: 1815 // CHECK1-IRBUILDER-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1816 // CHECK1-IRBUILDER-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1817 // CHECK1-IRBUILDER-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1818 // CHECK1-IRBUILDER-NEXT: [[SUB10:%.*]] = sub i32 [[TMP14]], [[TMP15]] 1819 // CHECK1-IRBUILDER-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 1820 // CHECK1-IRBUILDER-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 1821 // CHECK1-IRBUILDER-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 1822 // CHECK1-IRBUILDER-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 1823 // CHECK1-IRBUILDER-NEXT: [[ADD15:%.*]] = add i32 [[TMP13]], [[MUL14]] 1824 // CHECK1-IRBUILDER-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 1825 // CHECK1-IRBUILDER-NEXT: br label [[SIMD_IF_END]] 1826 // CHECK1-IRBUILDER: simd.if.end: 1827 // CHECK1-IRBUILDER-NEXT: [[TMP16:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 1828 // CHECK1-IRBUILDER-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_18]], align 4 1829 // CHECK1-IRBUILDER-NEXT: [[TMP17:%.*]] = load i32, i32* [[UP_ADDR]], align 4 1830 // CHECK1-IRBUILDER-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_19]], align 4 1831 // CHECK1-IRBUILDER-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1832 // CHECK1-IRBUILDER-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1833 // CHECK1-IRBUILDER-NEXT: [[SUB21:%.*]] = sub i32 [[TMP18]], [[TMP19]] 1834 // CHECK1-IRBUILDER-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 1835 // CHECK1-IRBUILDER-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 1836 // CHECK1-IRBUILDER-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 1837 // CHECK1-IRBUILDER-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 1838 // CHECK1-IRBUILDER-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 1839 // CHECK1-IRBUILDER-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1840 // CHECK1-IRBUILDER-NEXT: store i32 [[TMP20]], i32* [[I26]], align 4 1841 // CHECK1-IRBUILDER-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1842 // CHECK1-IRBUILDER-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1843 // CHECK1-IRBUILDER-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] 1844 // CHECK1-IRBUILDER-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1845 // CHECK1-IRBUILDER: omp.precond.then: 1846 // CHECK1-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1847 // CHECK1-IRBUILDER-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 1848 // CHECK1-IRBUILDER-NEXT: store i32 [[TMP23]], i32* [[DOTOMP_UB]], align 4 1849 // CHECK1-IRBUILDER-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1850 // CHECK1-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1851 // CHECK1-IRBUILDER-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 1852 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12:[0-9]+]]) 1853 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 [[TMP24]], i32 1, i32 1) 1854 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1855 // CHECK1-IRBUILDER: omp.dispatch.cond: 1856 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM29:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 1857 // CHECK1-IRBUILDER-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM29]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1858 // CHECK1-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP25]], 0 1859 // CHECK1-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1860 // CHECK1-IRBUILDER: omp.dispatch.body: 1861 // CHECK1-IRBUILDER-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1862 // CHECK1-IRBUILDER-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_IV16]], align 4 1863 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] 1864 // CHECK1-IRBUILDER: omp.inner.for.cond30: 1865 // CHECK1-IRBUILDER-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1866 // CHECK1-IRBUILDER-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 1867 // CHECK1-IRBUILDER-NEXT: [[ADD31:%.*]] = add i32 [[TMP28]], 1 1868 // CHECK1-IRBUILDER-NEXT: [[CMP32:%.*]] = icmp ult i32 [[TMP27]], [[ADD31]] 1869 // CHECK1-IRBUILDER-NEXT: br i1 [[CMP32]], label [[OMP_INNER_FOR_BODY33:%.*]], label [[OMP_INNER_FOR_END42:%.*]] 1870 // CHECK1-IRBUILDER: omp.inner.for.body33: 1871 // CHECK1-IRBUILDER-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7 1872 // CHECK1-IRBUILDER-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1873 // CHECK1-IRBUILDER-NEXT: [[MUL34:%.*]] = mul i32 [[TMP30]], 1 1874 // CHECK1-IRBUILDER-NEXT: [[ADD35:%.*]] = add i32 [[TMP29]], [[MUL34]] 1875 // CHECK1-IRBUILDER-NEXT: store i32 [[ADD35]], i32* [[I28]], align 4, !llvm.access.group !7 1876 // CHECK1-IRBUILDER-NEXT: [[TMP31:%.*]] = load i32, i32* [[I28]], align 4, !llvm.access.group !7 1877 // CHECK1-IRBUILDER-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 1878 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM36]] 1879 // CHECK1-IRBUILDER-NEXT: store float 0.000000e+00, float* [[ARRAYIDX37]], align 4, !llvm.access.group !7 1880 // CHECK1-IRBUILDER-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7 1881 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY33_ORDERED_AFTER:%.*]] 1882 // CHECK1-IRBUILDER: omp.inner.for.body33.ordered.after: 1883 // CHECK1-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE38:%.*]] 1884 // CHECK1-IRBUILDER: omp.body.continue38: 1885 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC39:%.*]] 1886 // CHECK1-IRBUILDER: omp.inner.for.inc39: 1887 // CHECK1-IRBUILDER-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1888 // CHECK1-IRBUILDER-NEXT: [[ADD40:%.*]] = add i32 [[TMP32]], 1 1889 // CHECK1-IRBUILDER-NEXT: store i32 [[ADD40]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1890 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 1891 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]]), !llvm.access.group !7 1892 // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]] 1893 // CHECK1-IRBUILDER: omp.inner.for.end42: 1894 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1895 // CHECK1-IRBUILDER: omp.dispatch.inc: 1896 // CHECK1-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 1897 // CHECK1-IRBUILDER: omp.dispatch.end: 1898 // CHECK1-IRBUILDER-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1899 // CHECK1-IRBUILDER-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 1900 // CHECK1-IRBUILDER-NEXT: br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1901 // CHECK1-IRBUILDER: .omp.final.then: 1902 // CHECK1-IRBUILDER-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1903 // CHECK1-IRBUILDER-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1904 // CHECK1-IRBUILDER-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1905 // CHECK1-IRBUILDER-NEXT: [[SUB43:%.*]] = sub i32 [[TMP36]], [[TMP37]] 1906 // CHECK1-IRBUILDER-NEXT: [[SUB44:%.*]] = sub i32 [[SUB43]], 1 1907 // CHECK1-IRBUILDER-NEXT: [[ADD45:%.*]] = add i32 [[SUB44]], 1 1908 // CHECK1-IRBUILDER-NEXT: [[DIV46:%.*]] = udiv i32 [[ADD45]], 1 1909 // CHECK1-IRBUILDER-NEXT: [[MUL47:%.*]] = mul i32 [[DIV46]], 1 1910 // CHECK1-IRBUILDER-NEXT: [[ADD48:%.*]] = add i32 [[TMP35]], [[MUL47]] 1911 // CHECK1-IRBUILDER-NEXT: store i32 [[ADD48]], i32* [[I28]], align 4 1912 // CHECK1-IRBUILDER-NEXT: br label [[DOTOMP_FINAL_DONE]] 1913 // CHECK1-IRBUILDER: .omp.final.done: 1914 // CHECK1-IRBUILDER-NEXT: br label [[OMP_PRECOND_END]] 1915 // CHECK1-IRBUILDER: omp.precond.end: 1916 // CHECK1-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM49:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1917 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM49]]) 1918 // CHECK1-IRBUILDER-NEXT: ret void 1919 // 1920 // 1921 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt 1922 // CHECK1-IRBUILDER-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 1923 // CHECK1-IRBUILDER-NEXT: entry: 1924 // CHECK1-IRBUILDER-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 1925 // CHECK1-IRBUILDER-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 1926 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 1927 // CHECK1-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1928 // CHECK1-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 1929 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1930 // CHECK1-IRBUILDER-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 1931 // CHECK1-IRBUILDER-NEXT: ret void 1932 // 1933 // 1934 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt.1 1935 // CHECK1-IRBUILDER-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 1936 // CHECK1-IRBUILDER-NEXT: entry: 1937 // CHECK1-IRBUILDER-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 1938 // CHECK1-IRBUILDER-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 1939 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 1940 // CHECK1-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1941 // CHECK1-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 1942 // CHECK1-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1943 // CHECK1-IRBUILDER-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 1944 // CHECK1-IRBUILDER-NEXT: ret void 1945 // 1946 // 1947 // CHECK2-IRBUILDER-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1948 // CHECK2-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 1949 // CHECK2-IRBUILDER-NEXT: entry: 1950 // CHECK2-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1951 // CHECK2-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1952 // CHECK2-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1953 // CHECK2-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1954 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1955 // CHECK2-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i32, align 4 1956 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1957 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1958 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1959 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1960 // CHECK2-IRBUILDER-NEXT: [[I:%.*]] = alloca i32, align 4 1961 // CHECK2-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1962 // CHECK2-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1963 // CHECK2-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1964 // CHECK2-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1965 // CHECK2-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1966 // CHECK2-IRBUILDER-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1967 // CHECK2-IRBUILDER-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1968 // CHECK2-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1969 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 1970 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 1971 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1972 // CHECK2-IRBUILDER: omp.dispatch.cond: 1973 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 1974 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1975 // CHECK2-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 1976 // CHECK2-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1977 // CHECK2-IRBUILDER: omp.dispatch.body: 1978 // CHECK2-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1979 // CHECK2-IRBUILDER-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1980 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1981 // CHECK2-IRBUILDER: omp.inner.for.cond: 1982 // CHECK2-IRBUILDER-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1983 // CHECK2-IRBUILDER-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1984 // CHECK2-IRBUILDER-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1985 // CHECK2-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1986 // CHECK2-IRBUILDER: omp.inner.for.body: 1987 // CHECK2-IRBUILDER-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1988 // CHECK2-IRBUILDER-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 1989 // CHECK2-IRBUILDER-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1990 // CHECK2-IRBUILDER-NEXT: store i32 [[SUB]], i32* [[I]], align 4 1991 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1992 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) 1993 // CHECK2-IRBUILDER-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8 1994 // CHECK2-IRBUILDER-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 1995 // CHECK2-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 1996 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]] 1997 // CHECK2-IRBUILDER-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4 1998 // CHECK2-IRBUILDER-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8 1999 // CHECK2-IRBUILDER-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 2000 // CHECK2-IRBUILDER-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 2001 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM3]] 2002 // CHECK2-IRBUILDER-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2003 // CHECK2-IRBUILDER-NEXT: [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]] 2004 // CHECK2-IRBUILDER-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8 2005 // CHECK2-IRBUILDER-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 2006 // CHECK2-IRBUILDER-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP12]] to i64 2007 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM6]] 2008 // CHECK2-IRBUILDER-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX7]], align 4 2009 // CHECK2-IRBUILDER-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP13]] 2010 // CHECK2-IRBUILDER-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8 2011 // CHECK2-IRBUILDER-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 2012 // CHECK2-IRBUILDER-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64 2013 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM9]] 2014 // CHECK2-IRBUILDER-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 2015 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 2016 // CHECK2-IRBUILDER: omp.inner.for.body.ordered.after: 2017 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) 2018 // CHECK2-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2019 // CHECK2-IRBUILDER: omp.body.continue: 2020 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2021 // CHECK2-IRBUILDER: omp.inner.for.inc: 2022 // CHECK2-IRBUILDER-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2023 // CHECK2-IRBUILDER-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 2024 // CHECK2-IRBUILDER-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2025 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 2026 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) 2027 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 2028 // CHECK2-IRBUILDER: omp.inner.for.end: 2029 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2030 // CHECK2-IRBUILDER: omp.dispatch.inc: 2031 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 2032 // CHECK2-IRBUILDER: omp.dispatch.end: 2033 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2034 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM12]]) 2035 // CHECK2-IRBUILDER-NEXT: ret void 2036 // 2037 // 2038 // CHECK2-IRBUILDER-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 2039 // CHECK2-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2040 // CHECK2-IRBUILDER-NEXT: entry: 2041 // CHECK2-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2042 // CHECK2-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2043 // CHECK2-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2044 // CHECK2-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2045 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2046 // CHECK2-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i64, align 8 2047 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2048 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2049 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2050 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2051 // CHECK2-IRBUILDER-NEXT: [[I:%.*]] = alloca i64, align 8 2052 // CHECK2-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2053 // CHECK2-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2054 // CHECK2-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2055 // CHECK2-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2056 // CHECK2-IRBUILDER-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2057 // CHECK2-IRBUILDER-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 2058 // CHECK2-IRBUILDER-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2059 // CHECK2-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2060 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6:[0-9]+]]) 2061 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1) 2062 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2063 // CHECK2-IRBUILDER: omp.dispatch.cond: 2064 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 2065 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 2066 // CHECK2-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 2067 // CHECK2-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2068 // CHECK2-IRBUILDER: omp.dispatch.body: 2069 // CHECK2-IRBUILDER-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2070 // CHECK2-IRBUILDER-NEXT: store i64 [[TMP1]], i64* [[DOTOMP_IV]], align 8 2071 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2072 // CHECK2-IRBUILDER: omp.inner.for.cond: 2073 // CHECK2-IRBUILDER-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2074 // CHECK2-IRBUILDER-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2075 // CHECK2-IRBUILDER-NEXT: [[ADD:%.*]] = add i64 [[TMP3]], 1 2076 // CHECK2-IRBUILDER-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP2]], [[ADD]] 2077 // CHECK2-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2078 // CHECK2-IRBUILDER: omp.inner.for.body: 2079 // CHECK2-IRBUILDER-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2080 // CHECK2-IRBUILDER-NEXT: [[MUL:%.*]] = mul i64 [[TMP4]], 127 2081 // CHECK2-IRBUILDER-NEXT: [[ADD2:%.*]] = add i64 131071, [[MUL]] 2082 // CHECK2-IRBUILDER-NEXT: store i64 [[ADD2]], i64* [[I]], align 8 2083 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2084 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) 2085 // CHECK2-IRBUILDER-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8 2086 // CHECK2-IRBUILDER-NEXT: [[TMP6:%.*]] = load i64, i64* [[I]], align 8 2087 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[TMP6]] 2088 // CHECK2-IRBUILDER-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4 2089 // CHECK2-IRBUILDER-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8 2090 // CHECK2-IRBUILDER-NEXT: [[TMP9:%.*]] = load i64, i64* [[I]], align 8 2091 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[TMP9]] 2092 // CHECK2-IRBUILDER-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2093 // CHECK2-IRBUILDER-NEXT: [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]] 2094 // CHECK2-IRBUILDER-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8 2095 // CHECK2-IRBUILDER-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 2096 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 2097 // CHECK2-IRBUILDER-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX6]], align 4 2098 // CHECK2-IRBUILDER-NEXT: [[MUL7:%.*]] = fmul float [[MUL5]], [[TMP13]] 2099 // CHECK2-IRBUILDER-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8 2100 // CHECK2-IRBUILDER-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8 2101 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 2102 // CHECK2-IRBUILDER-NEXT: store float [[MUL7]], float* [[ARRAYIDX8]], align 4 2103 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 2104 // CHECK2-IRBUILDER: omp.inner.for.body.ordered.after: 2105 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) 2106 // CHECK2-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2107 // CHECK2-IRBUILDER: omp.body.continue: 2108 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2109 // CHECK2-IRBUILDER: omp.inner.for.inc: 2110 // CHECK2-IRBUILDER-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2111 // CHECK2-IRBUILDER-NEXT: [[ADD9:%.*]] = add i64 [[TMP16]], 1 2112 // CHECK2-IRBUILDER-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8 2113 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 2114 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]]) 2115 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 2116 // CHECK2-IRBUILDER: omp.inner.for.end: 2117 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2118 // CHECK2-IRBUILDER: omp.dispatch.inc: 2119 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 2120 // CHECK2-IRBUILDER: omp.dispatch.end: 2121 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2122 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) 2123 // CHECK2-IRBUILDER-NEXT: ret void 2124 // 2125 // 2126 // CHECK2-IRBUILDER-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 2127 // CHECK2-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2128 // CHECK2-IRBUILDER-NEXT: entry: 2129 // CHECK2-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2130 // CHECK2-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2131 // CHECK2-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2132 // CHECK2-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2133 // CHECK2-IRBUILDER-NEXT: [[X:%.*]] = alloca i32, align 4 2134 // CHECK2-IRBUILDER-NEXT: [[Y:%.*]] = alloca i32, align 4 2135 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2136 // CHECK2-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i8, align 1 2137 // CHECK2-IRBUILDER-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2138 // CHECK2-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2139 // CHECK2-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 2140 // CHECK2-IRBUILDER-NEXT: [[I:%.*]] = alloca i8, align 1 2141 // CHECK2-IRBUILDER-NEXT: [[X6:%.*]] = alloca i32, align 4 2142 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2143 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2144 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2145 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2146 // CHECK2-IRBUILDER-NEXT: [[I8:%.*]] = alloca i8, align 1 2147 // CHECK2-IRBUILDER-NEXT: [[X9:%.*]] = alloca i32, align 4 2148 // CHECK2-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2149 // CHECK2-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2150 // CHECK2-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2151 // CHECK2-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2152 // CHECK2-IRBUILDER-NEXT: store i32 0, i32* [[X]], align 4 2153 // CHECK2-IRBUILDER-NEXT: store i32 0, i32* [[Y]], align 4 2154 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 2155 // CHECK2-IRBUILDER-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 2156 // CHECK2-IRBUILDER-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 2157 // CHECK2-IRBUILDER-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2158 // CHECK2-IRBUILDER-NEXT: [[CONV3:%.*]] = sext i8 [[TMP1]] to i32 2159 // CHECK2-IRBUILDER-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 2160 // CHECK2-IRBUILDER-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 2161 // CHECK2-IRBUILDER-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2162 // CHECK2-IRBUILDER-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 2163 // CHECK2-IRBUILDER-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 2164 // CHECK2-IRBUILDER-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 2165 // CHECK2-IRBUILDER-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 2166 // CHECK2-IRBUILDER-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2167 // CHECK2-IRBUILDER-NEXT: store i8 [[TMP2]], i8* [[I]], align 1 2168 // CHECK2-IRBUILDER-NEXT: store i32 11, i32* [[X6]], align 4 2169 // CHECK2-IRBUILDER-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2170 // CHECK2-IRBUILDER-NEXT: [[CONV7:%.*]] = sext i8 [[TMP3]] to i32 2171 // CHECK2-IRBUILDER-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 2172 // CHECK2-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2173 // CHECK2-IRBUILDER: omp.precond.then: 2174 // CHECK2-IRBUILDER-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2175 // CHECK2-IRBUILDER-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2176 // CHECK2-IRBUILDER-NEXT: store i64 [[TMP4]], i64* [[DOTOMP_UB]], align 8 2177 // CHECK2-IRBUILDER-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2178 // CHECK2-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2179 // CHECK2-IRBUILDER-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2180 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8:[0-9]+]]) 2181 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741894, i64 0, i64 [[TMP5]], i64 1, i64 1) 2182 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2183 // CHECK2-IRBUILDER: omp.dispatch.cond: 2184 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 2185 // CHECK2-IRBUILDER-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 2186 // CHECK2-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 2187 // CHECK2-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2188 // CHECK2-IRBUILDER: omp.dispatch.body: 2189 // CHECK2-IRBUILDER-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2190 // CHECK2-IRBUILDER-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 2191 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2192 // CHECK2-IRBUILDER: omp.inner.for.cond: 2193 // CHECK2-IRBUILDER-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2194 // CHECK2-IRBUILDER-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2195 // CHECK2-IRBUILDER-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP8]], [[TMP9]] 2196 // CHECK2-IRBUILDER-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2197 // CHECK2-IRBUILDER: omp.inner.for.body: 2198 // CHECK2-IRBUILDER-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2199 // CHECK2-IRBUILDER-NEXT: [[CONV12:%.*]] = sext i8 [[TMP10]] to i64 2200 // CHECK2-IRBUILDER-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2201 // CHECK2-IRBUILDER-NEXT: [[DIV13:%.*]] = sdiv i64 [[TMP11]], 11 2202 // CHECK2-IRBUILDER-NEXT: [[MUL14:%.*]] = mul nsw i64 [[DIV13]], 1 2203 // CHECK2-IRBUILDER-NEXT: [[ADD15:%.*]] = add nsw i64 [[CONV12]], [[MUL14]] 2204 // CHECK2-IRBUILDER-NEXT: [[CONV16:%.*]] = trunc i64 [[ADD15]] to i8 2205 // CHECK2-IRBUILDER-NEXT: store i8 [[CONV16]], i8* [[I8]], align 1 2206 // CHECK2-IRBUILDER-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2207 // CHECK2-IRBUILDER-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2208 // CHECK2-IRBUILDER-NEXT: [[DIV17:%.*]] = sdiv i64 [[TMP13]], 11 2209 // CHECK2-IRBUILDER-NEXT: [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 11 2210 // CHECK2-IRBUILDER-NEXT: [[SUB19:%.*]] = sub nsw i64 [[TMP12]], [[MUL18]] 2211 // CHECK2-IRBUILDER-NEXT: [[MUL20:%.*]] = mul nsw i64 [[SUB19]], 1 2212 // CHECK2-IRBUILDER-NEXT: [[SUB21:%.*]] = sub nsw i64 11, [[MUL20]] 2213 // CHECK2-IRBUILDER-NEXT: [[CONV22:%.*]] = trunc i64 [[SUB21]] to i32 2214 // CHECK2-IRBUILDER-NEXT: store i32 [[CONV22]], i32* [[X9]], align 4 2215 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2216 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]]) 2217 // CHECK2-IRBUILDER-NEXT: [[TMP14:%.*]] = load float*, float** [[B_ADDR]], align 8 2218 // CHECK2-IRBUILDER-NEXT: [[TMP15:%.*]] = load i8, i8* [[I8]], align 1 2219 // CHECK2-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP15]] to i64 2220 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 2221 // CHECK2-IRBUILDER-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4 2222 // CHECK2-IRBUILDER-NEXT: [[TMP17:%.*]] = load float*, float** [[C_ADDR]], align 8 2223 // CHECK2-IRBUILDER-NEXT: [[TMP18:%.*]] = load i8, i8* [[I8]], align 1 2224 // CHECK2-IRBUILDER-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP18]] to i64 2225 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM24]] 2226 // CHECK2-IRBUILDER-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX25]], align 4 2227 // CHECK2-IRBUILDER-NEXT: [[MUL26:%.*]] = fmul float [[TMP16]], [[TMP19]] 2228 // CHECK2-IRBUILDER-NEXT: [[TMP20:%.*]] = load float*, float** [[D_ADDR]], align 8 2229 // CHECK2-IRBUILDER-NEXT: [[TMP21:%.*]] = load i8, i8* [[I8]], align 1 2230 // CHECK2-IRBUILDER-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP21]] to i64 2231 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM27]] 2232 // CHECK2-IRBUILDER-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX28]], align 4 2233 // CHECK2-IRBUILDER-NEXT: [[MUL29:%.*]] = fmul float [[MUL26]], [[TMP22]] 2234 // CHECK2-IRBUILDER-NEXT: [[TMP23:%.*]] = load float*, float** [[A_ADDR]], align 8 2235 // CHECK2-IRBUILDER-NEXT: [[TMP24:%.*]] = load i8, i8* [[I8]], align 1 2236 // CHECK2-IRBUILDER-NEXT: [[IDXPROM30:%.*]] = sext i8 [[TMP24]] to i64 2237 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM30]] 2238 // CHECK2-IRBUILDER-NEXT: store float [[MUL29]], float* [[ARRAYIDX31]], align 4 2239 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 2240 // CHECK2-IRBUILDER: omp.inner.for.body.ordered.after: 2241 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]]) 2242 // CHECK2-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2243 // CHECK2-IRBUILDER: omp.body.continue: 2244 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2245 // CHECK2-IRBUILDER: omp.inner.for.inc: 2246 // CHECK2-IRBUILDER-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2247 // CHECK2-IRBUILDER-NEXT: [[ADD32:%.*]] = add nsw i64 [[TMP25]], 1 2248 // CHECK2-IRBUILDER-NEXT: store i64 [[ADD32]], i64* [[DOTOMP_IV]], align 8 2249 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM33:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 2250 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM33]]) 2251 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 2252 // CHECK2-IRBUILDER: omp.inner.for.end: 2253 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2254 // CHECK2-IRBUILDER: omp.dispatch.inc: 2255 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 2256 // CHECK2-IRBUILDER: omp.dispatch.end: 2257 // CHECK2-IRBUILDER-NEXT: br label [[OMP_PRECOND_END]] 2258 // CHECK2-IRBUILDER: omp.precond.end: 2259 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM34:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2260 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM34]]) 2261 // CHECK2-IRBUILDER-NEXT: ret void 2262 // 2263 // 2264 // CHECK2-IRBUILDER-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 2265 // CHECK2-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2266 // CHECK2-IRBUILDER-NEXT: entry: 2267 // CHECK2-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2268 // CHECK2-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2269 // CHECK2-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2270 // CHECK2-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2271 // CHECK2-IRBUILDER-NEXT: [[X:%.*]] = alloca i32, align 4 2272 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2273 // CHECK2-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i8, align 1 2274 // CHECK2-IRBUILDER-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2275 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2276 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2277 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2278 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2279 // CHECK2-IRBUILDER-NEXT: [[I:%.*]] = alloca i8, align 1 2280 // CHECK2-IRBUILDER-NEXT: [[X2:%.*]] = alloca i32, align 4 2281 // CHECK2-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2282 // CHECK2-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2283 // CHECK2-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2284 // CHECK2-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2285 // CHECK2-IRBUILDER-NEXT: store i32 0, i32* [[X]], align 4 2286 // CHECK2-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2287 // CHECK2-IRBUILDER-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 2288 // CHECK2-IRBUILDER-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2289 // CHECK2-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2290 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10:[0-9]+]]) 2291 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741893, i32 0, i32 199, i32 1, i32 1) 2292 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2293 // CHECK2-IRBUILDER: omp.dispatch.cond: 2294 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 2295 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2296 // CHECK2-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 2297 // CHECK2-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2298 // CHECK2-IRBUILDER: omp.dispatch.body: 2299 // CHECK2-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2300 // CHECK2-IRBUILDER-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 2301 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2302 // CHECK2-IRBUILDER: omp.inner.for.cond: 2303 // CHECK2-IRBUILDER-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2304 // CHECK2-IRBUILDER-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2305 // CHECK2-IRBUILDER-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 2306 // CHECK2-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2307 // CHECK2-IRBUILDER: omp.inner.for.body: 2308 // CHECK2-IRBUILDER-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2309 // CHECK2-IRBUILDER-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 20 2310 // CHECK2-IRBUILDER-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2311 // CHECK2-IRBUILDER-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 2312 // CHECK2-IRBUILDER-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 2313 // CHECK2-IRBUILDER-NEXT: store i8 [[CONV]], i8* [[I]], align 1 2314 // CHECK2-IRBUILDER-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2315 // CHECK2-IRBUILDER-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2316 // CHECK2-IRBUILDER-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP6]], 20 2317 // CHECK2-IRBUILDER-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 20 2318 // CHECK2-IRBUILDER-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], [[MUL5]] 2319 // CHECK2-IRBUILDER-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 2320 // CHECK2-IRBUILDER-NEXT: [[ADD7:%.*]] = add nsw i32 -10, [[MUL6]] 2321 // CHECK2-IRBUILDER-NEXT: store i32 [[ADD7]], i32* [[X2]], align 4 2322 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM8:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2323 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]]) 2324 // CHECK2-IRBUILDER-NEXT: [[TMP7:%.*]] = load float*, float** [[B_ADDR]], align 8 2325 // CHECK2-IRBUILDER-NEXT: [[TMP8:%.*]] = load i8, i8* [[I]], align 1 2326 // CHECK2-IRBUILDER-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP8]] to i64 2327 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM]] 2328 // CHECK2-IRBUILDER-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 2329 // CHECK2-IRBUILDER-NEXT: [[TMP10:%.*]] = load float*, float** [[C_ADDR]], align 8 2330 // CHECK2-IRBUILDER-NEXT: [[TMP11:%.*]] = load i8, i8* [[I]], align 1 2331 // CHECK2-IRBUILDER-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP11]] to i64 2332 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM9]] 2333 // CHECK2-IRBUILDER-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX10]], align 4 2334 // CHECK2-IRBUILDER-NEXT: [[MUL11:%.*]] = fmul float [[TMP9]], [[TMP12]] 2335 // CHECK2-IRBUILDER-NEXT: [[TMP13:%.*]] = load float*, float** [[D_ADDR]], align 8 2336 // CHECK2-IRBUILDER-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 2337 // CHECK2-IRBUILDER-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP14]] to i64 2338 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM12]] 2339 // CHECK2-IRBUILDER-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX13]], align 4 2340 // CHECK2-IRBUILDER-NEXT: [[MUL14:%.*]] = fmul float [[MUL11]], [[TMP15]] 2341 // CHECK2-IRBUILDER-NEXT: [[TMP16:%.*]] = load float*, float** [[A_ADDR]], align 8 2342 // CHECK2-IRBUILDER-NEXT: [[TMP17:%.*]] = load i8, i8* [[I]], align 1 2343 // CHECK2-IRBUILDER-NEXT: [[IDXPROM15:%.*]] = zext i8 [[TMP17]] to i64 2344 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM15]] 2345 // CHECK2-IRBUILDER-NEXT: store float [[MUL14]], float* [[ARRAYIDX16]], align 4 2346 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 2347 // CHECK2-IRBUILDER: omp.inner.for.body.ordered.after: 2348 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]]) 2349 // CHECK2-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2350 // CHECK2-IRBUILDER: omp.body.continue: 2351 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2352 // CHECK2-IRBUILDER: omp.inner.for.inc: 2353 // CHECK2-IRBUILDER-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2354 // CHECK2-IRBUILDER-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP18]], 1 2355 // CHECK2-IRBUILDER-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4 2356 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 2357 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM18]]) 2358 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 2359 // CHECK2-IRBUILDER: omp.inner.for.end: 2360 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2361 // CHECK2-IRBUILDER: omp.dispatch.inc: 2362 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 2363 // CHECK2-IRBUILDER: omp.dispatch.end: 2364 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM19:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2365 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM19]]) 2366 // CHECK2-IRBUILDER-NEXT: ret void 2367 // 2368 // 2369 // CHECK2-IRBUILDER-LABEL: define {{[^@]+}}@_Z8foo_simdii 2370 // CHECK2-IRBUILDER-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { 2371 // CHECK2-IRBUILDER-NEXT: entry: 2372 // CHECK2-IRBUILDER-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 2373 // CHECK2-IRBUILDER-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 2374 // CHECK2-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i32, align 4 2375 // CHECK2-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2376 // CHECK2-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2377 // CHECK2-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2378 // CHECK2-IRBUILDER-NEXT: [[I:%.*]] = alloca i32, align 4 2379 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2380 // CHECK2-IRBUILDER-NEXT: [[I5:%.*]] = alloca i32, align 4 2381 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 2382 // CHECK2-IRBUILDER-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 2383 // CHECK2-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 2384 // CHECK2-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 2385 // CHECK2-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 2386 // CHECK2-IRBUILDER-NEXT: [[I26:%.*]] = alloca i32, align 4 2387 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2388 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2389 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2390 // CHECK2-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2391 // CHECK2-IRBUILDER-NEXT: [[I28:%.*]] = alloca i32, align 4 2392 // CHECK2-IRBUILDER-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 2393 // CHECK2-IRBUILDER-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 2394 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 2395 // CHECK2-IRBUILDER-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 2396 // CHECK2-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[UP_ADDR]], align 4 2397 // CHECK2-IRBUILDER-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2398 // CHECK2-IRBUILDER-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2399 // CHECK2-IRBUILDER-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2400 // CHECK2-IRBUILDER-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 2401 // CHECK2-IRBUILDER-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 2402 // CHECK2-IRBUILDER-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 2403 // CHECK2-IRBUILDER-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2404 // CHECK2-IRBUILDER-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 2405 // CHECK2-IRBUILDER-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2406 // CHECK2-IRBUILDER-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2407 // CHECK2-IRBUILDER-NEXT: store i32 [[TMP4]], i32* [[I]], align 4 2408 // CHECK2-IRBUILDER-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2409 // CHECK2-IRBUILDER-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2410 // CHECK2-IRBUILDER-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] 2411 // CHECK2-IRBUILDER-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 2412 // CHECK2-IRBUILDER: simd.if.then: 2413 // CHECK2-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 2414 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2415 // CHECK2-IRBUILDER: omp.inner.for.cond: 2416 // CHECK2-IRBUILDER-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2417 // CHECK2-IRBUILDER-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 2418 // CHECK2-IRBUILDER-NEXT: [[ADD6:%.*]] = add i32 [[TMP8]], 1 2419 // CHECK2-IRBUILDER-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]] 2420 // CHECK2-IRBUILDER-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2421 // CHECK2-IRBUILDER: omp.inner.for.body: 2422 // CHECK2-IRBUILDER-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3 2423 // CHECK2-IRBUILDER-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2424 // CHECK2-IRBUILDER-NEXT: [[MUL:%.*]] = mul i32 [[TMP10]], 1 2425 // CHECK2-IRBUILDER-NEXT: [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]] 2426 // CHECK2-IRBUILDER-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3 2427 // CHECK2-IRBUILDER-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !3 2428 // CHECK2-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 2429 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 2430 // CHECK2-IRBUILDER-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 2431 // CHECK2-IRBUILDER-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3 2432 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 2433 // CHECK2-IRBUILDER: omp.inner.for.body.ordered.after: 2434 // CHECK2-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2435 // CHECK2-IRBUILDER: omp.body.continue: 2436 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2437 // CHECK2-IRBUILDER: omp.inner.for.inc: 2438 // CHECK2-IRBUILDER-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2439 // CHECK2-IRBUILDER-NEXT: [[ADD9:%.*]] = add i32 [[TMP12]], 1 2440 // CHECK2-IRBUILDER-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2441 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2442 // CHECK2-IRBUILDER: omp.inner.for.end: 2443 // CHECK2-IRBUILDER-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2444 // CHECK2-IRBUILDER-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2445 // CHECK2-IRBUILDER-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2446 // CHECK2-IRBUILDER-NEXT: [[SUB10:%.*]] = sub i32 [[TMP14]], [[TMP15]] 2447 // CHECK2-IRBUILDER-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 2448 // CHECK2-IRBUILDER-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 2449 // CHECK2-IRBUILDER-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 2450 // CHECK2-IRBUILDER-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 2451 // CHECK2-IRBUILDER-NEXT: [[ADD15:%.*]] = add i32 [[TMP13]], [[MUL14]] 2452 // CHECK2-IRBUILDER-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 2453 // CHECK2-IRBUILDER-NEXT: br label [[SIMD_IF_END]] 2454 // CHECK2-IRBUILDER: simd.if.end: 2455 // CHECK2-IRBUILDER-NEXT: [[TMP16:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 2456 // CHECK2-IRBUILDER-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_18]], align 4 2457 // CHECK2-IRBUILDER-NEXT: [[TMP17:%.*]] = load i32, i32* [[UP_ADDR]], align 4 2458 // CHECK2-IRBUILDER-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_19]], align 4 2459 // CHECK2-IRBUILDER-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2460 // CHECK2-IRBUILDER-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2461 // CHECK2-IRBUILDER-NEXT: [[SUB21:%.*]] = sub i32 [[TMP18]], [[TMP19]] 2462 // CHECK2-IRBUILDER-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 2463 // CHECK2-IRBUILDER-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 2464 // CHECK2-IRBUILDER-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 2465 // CHECK2-IRBUILDER-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 2466 // CHECK2-IRBUILDER-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 2467 // CHECK2-IRBUILDER-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2468 // CHECK2-IRBUILDER-NEXT: store i32 [[TMP20]], i32* [[I26]], align 4 2469 // CHECK2-IRBUILDER-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2470 // CHECK2-IRBUILDER-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2471 // CHECK2-IRBUILDER-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] 2472 // CHECK2-IRBUILDER-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2473 // CHECK2-IRBUILDER: omp.precond.then: 2474 // CHECK2-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2475 // CHECK2-IRBUILDER-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 2476 // CHECK2-IRBUILDER-NEXT: store i32 [[TMP23]], i32* [[DOTOMP_UB]], align 4 2477 // CHECK2-IRBUILDER-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2478 // CHECK2-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2479 // CHECK2-IRBUILDER-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 2480 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12:[0-9]+]]) 2481 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 [[TMP24]], i32 1, i32 1) 2482 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2483 // CHECK2-IRBUILDER: omp.dispatch.cond: 2484 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM29:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 2485 // CHECK2-IRBUILDER-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM29]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2486 // CHECK2-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP25]], 0 2487 // CHECK2-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2488 // CHECK2-IRBUILDER: omp.dispatch.body: 2489 // CHECK2-IRBUILDER-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2490 // CHECK2-IRBUILDER-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_IV16]], align 4 2491 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] 2492 // CHECK2-IRBUILDER: omp.inner.for.cond30: 2493 // CHECK2-IRBUILDER-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 2494 // CHECK2-IRBUILDER-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 2495 // CHECK2-IRBUILDER-NEXT: [[ADD31:%.*]] = add i32 [[TMP28]], 1 2496 // CHECK2-IRBUILDER-NEXT: [[CMP32:%.*]] = icmp ult i32 [[TMP27]], [[ADD31]] 2497 // CHECK2-IRBUILDER-NEXT: br i1 [[CMP32]], label [[OMP_INNER_FOR_BODY33:%.*]], label [[OMP_INNER_FOR_END42:%.*]] 2498 // CHECK2-IRBUILDER: omp.inner.for.body33: 2499 // CHECK2-IRBUILDER-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7 2500 // CHECK2-IRBUILDER-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 2501 // CHECK2-IRBUILDER-NEXT: [[MUL34:%.*]] = mul i32 [[TMP30]], 1 2502 // CHECK2-IRBUILDER-NEXT: [[ADD35:%.*]] = add i32 [[TMP29]], [[MUL34]] 2503 // CHECK2-IRBUILDER-NEXT: store i32 [[ADD35]], i32* [[I28]], align 4, !llvm.access.group !7 2504 // CHECK2-IRBUILDER-NEXT: [[TMP31:%.*]] = load i32, i32* [[I28]], align 4, !llvm.access.group !7 2505 // CHECK2-IRBUILDER-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 2506 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM36]] 2507 // CHECK2-IRBUILDER-NEXT: store float 0.000000e+00, float* [[ARRAYIDX37]], align 4, !llvm.access.group !7 2508 // CHECK2-IRBUILDER-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7 2509 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY33_ORDERED_AFTER:%.*]] 2510 // CHECK2-IRBUILDER: omp.inner.for.body33.ordered.after: 2511 // CHECK2-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE38:%.*]] 2512 // CHECK2-IRBUILDER: omp.body.continue38: 2513 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC39:%.*]] 2514 // CHECK2-IRBUILDER: omp.inner.for.inc39: 2515 // CHECK2-IRBUILDER-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 2516 // CHECK2-IRBUILDER-NEXT: [[ADD40:%.*]] = add i32 [[TMP32]], 1 2517 // CHECK2-IRBUILDER-NEXT: store i32 [[ADD40]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 2518 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 2519 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]]), !llvm.access.group !7 2520 // CHECK2-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]] 2521 // CHECK2-IRBUILDER: omp.inner.for.end42: 2522 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2523 // CHECK2-IRBUILDER: omp.dispatch.inc: 2524 // CHECK2-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 2525 // CHECK2-IRBUILDER: omp.dispatch.end: 2526 // CHECK2-IRBUILDER-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2527 // CHECK2-IRBUILDER-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 2528 // CHECK2-IRBUILDER-NEXT: br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2529 // CHECK2-IRBUILDER: .omp.final.then: 2530 // CHECK2-IRBUILDER-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2531 // CHECK2-IRBUILDER-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2532 // CHECK2-IRBUILDER-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2533 // CHECK2-IRBUILDER-NEXT: [[SUB43:%.*]] = sub i32 [[TMP36]], [[TMP37]] 2534 // CHECK2-IRBUILDER-NEXT: [[SUB44:%.*]] = sub i32 [[SUB43]], 1 2535 // CHECK2-IRBUILDER-NEXT: [[ADD45:%.*]] = add i32 [[SUB44]], 1 2536 // CHECK2-IRBUILDER-NEXT: [[DIV46:%.*]] = udiv i32 [[ADD45]], 1 2537 // CHECK2-IRBUILDER-NEXT: [[MUL47:%.*]] = mul i32 [[DIV46]], 1 2538 // CHECK2-IRBUILDER-NEXT: [[ADD48:%.*]] = add i32 [[TMP35]], [[MUL47]] 2539 // CHECK2-IRBUILDER-NEXT: store i32 [[ADD48]], i32* [[I28]], align 4 2540 // CHECK2-IRBUILDER-NEXT: br label [[DOTOMP_FINAL_DONE]] 2541 // CHECK2-IRBUILDER: .omp.final.done: 2542 // CHECK2-IRBUILDER-NEXT: br label [[OMP_PRECOND_END]] 2543 // CHECK2-IRBUILDER: omp.precond.end: 2544 // CHECK2-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM49:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2545 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM49]]) 2546 // CHECK2-IRBUILDER-NEXT: ret void 2547 // 2548 // 2549 // CHECK2-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt 2550 // CHECK2-IRBUILDER-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 2551 // CHECK2-IRBUILDER-NEXT: entry: 2552 // CHECK2-IRBUILDER-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 2553 // CHECK2-IRBUILDER-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 2554 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 2555 // CHECK2-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2556 // CHECK2-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 2557 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 2558 // CHECK2-IRBUILDER-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 2559 // CHECK2-IRBUILDER-NEXT: ret void 2560 // 2561 // 2562 // CHECK2-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt.1 2563 // CHECK2-IRBUILDER-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 2564 // CHECK2-IRBUILDER-NEXT: entry: 2565 // CHECK2-IRBUILDER-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 2566 // CHECK2-IRBUILDER-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 2567 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 2568 // CHECK2-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2569 // CHECK2-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 2570 // CHECK2-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 2571 // CHECK2-IRBUILDER-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 2572 // CHECK2-IRBUILDER-NEXT: ret void 2573 // 2574 // 2575 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 2576 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 2577 // CHECK3-NEXT: entry: 2578 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2579 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2580 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2581 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2582 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2583 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2584 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2585 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2586 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2587 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2588 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2589 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 2590 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2591 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2592 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2593 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2594 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2595 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2596 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2597 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2598 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 2599 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2600 // CHECK3: omp.dispatch.cond: 2601 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2602 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 2603 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2604 // CHECK3: omp.dispatch.body: 2605 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2606 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 2607 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2608 // CHECK3: omp.inner.for.cond: 2609 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2610 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2611 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 2612 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2613 // CHECK3: omp.inner.for.body: 2614 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2615 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7 2616 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 2617 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4 2618 // CHECK3-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2619 // CHECK3-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 2620 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 2621 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 2622 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM]] 2623 // CHECK3-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 2624 // CHECK3-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 2625 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 2626 // CHECK3-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64 2627 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM1]] 2628 // CHECK3-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2629 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 2630 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 2631 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2632 // CHECK3-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64 2633 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM4]] 2634 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX5]], align 4 2635 // CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]] 2636 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 2637 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2638 // CHECK3-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 2639 // CHECK3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM7]] 2640 // CHECK3-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 2641 // CHECK3-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2642 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2643 // CHECK3: omp.body.continue: 2644 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2645 // CHECK3: omp.inner.for.inc: 2646 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2647 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], 1 2648 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2649 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2650 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2651 // CHECK3: omp.inner.for.end: 2652 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2653 // CHECK3: omp.dispatch.inc: 2654 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2655 // CHECK3: omp.dispatch.end: 2656 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP0]]) 2657 // CHECK3-NEXT: ret void 2658 // 2659 // 2660 // CHECK3-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 2661 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2662 // CHECK3-NEXT: entry: 2663 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2664 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2665 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2666 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2667 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2668 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 8 2669 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2670 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2671 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2672 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2673 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 2674 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2675 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2676 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2677 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2678 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2679 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2680 // CHECK3-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 2681 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2682 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2683 // CHECK3-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 67, i64 0, i64 16908287, i64 1, i64 1) 2684 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2685 // CHECK3: omp.dispatch.cond: 2686 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 2687 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 2688 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2689 // CHECK3: omp.dispatch.body: 2690 // CHECK3-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2691 // CHECK3-NEXT: store i64 [[TMP2]], i64* [[DOTOMP_IV]], align 8 2692 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2693 // CHECK3: omp.inner.for.cond: 2694 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2695 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2696 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[TMP4]], 1 2697 // CHECK3-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]] 2698 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2699 // CHECK3: omp.inner.for.body: 2700 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2701 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP5]], 127 2702 // CHECK3-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 2703 // CHECK3-NEXT: store i64 [[ADD1]], i64* [[I]], align 8 2704 // CHECK3-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2705 // CHECK3-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 2706 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[I]], align 8 2707 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[TMP7]] 2708 // CHECK3-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 2709 // CHECK3-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 2710 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[I]], align 8 2711 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[TMP10]] 2712 // CHECK3-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2713 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 2714 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 2715 // CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[I]], align 8 2716 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[TMP13]] 2717 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2718 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]] 2719 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 2720 // CHECK3-NEXT: [[TMP16:%.*]] = load i64, i64* [[I]], align 8 2721 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[TMP16]] 2722 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 2723 // CHECK3-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2724 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2725 // CHECK3: omp.body.continue: 2726 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2727 // CHECK3: omp.inner.for.inc: 2728 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2729 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP17]], 1 2730 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 2731 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2732 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2733 // CHECK3: omp.inner.for.end: 2734 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2735 // CHECK3: omp.dispatch.inc: 2736 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2737 // CHECK3: omp.dispatch.end: 2738 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 2739 // CHECK3-NEXT: ret void 2740 // 2741 // 2742 // CHECK3-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 2743 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2744 // CHECK3-NEXT: entry: 2745 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2746 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2747 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2748 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2749 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 2750 // CHECK3-NEXT: [[Y:%.*]] = alloca i32, align 4 2751 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2752 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 2753 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2754 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2755 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 2756 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 2757 // CHECK3-NEXT: [[X6:%.*]] = alloca i32, align 4 2758 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2759 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2760 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2761 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2762 // CHECK3-NEXT: [[I8:%.*]] = alloca i8, align 1 2763 // CHECK3-NEXT: [[X9:%.*]] = alloca i32, align 4 2764 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2765 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2766 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2767 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2768 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2769 // CHECK3-NEXT: store i32 0, i32* [[X]], align 4 2770 // CHECK3-NEXT: store i32 0, i32* [[Y]], align 4 2771 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[Y]], align 4 2772 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[TMP1]] to i8 2773 // CHECK3-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 2774 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2775 // CHECK3-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 2776 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 2777 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 2778 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2779 // CHECK3-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 2780 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 2781 // CHECK3-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 2782 // CHECK3-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 2783 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2784 // CHECK3-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 2785 // CHECK3-NEXT: store i32 11, i32* [[X6]], align 4 2786 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2787 // CHECK3-NEXT: [[CONV7:%.*]] = sext i8 [[TMP4]] to i32 2788 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 2789 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2790 // CHECK3: omp.precond.then: 2791 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2792 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2793 // CHECK3-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_UB]], align 8 2794 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2795 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2796 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2797 // CHECK3-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 70, i64 0, i64 [[TMP6]], i64 1, i64 1) 2798 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2799 // CHECK3: omp.dispatch.cond: 2800 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 2801 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 2802 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2803 // CHECK3: omp.dispatch.body: 2804 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2805 // CHECK3-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 2806 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2807 // CHECK3: omp.inner.for.cond: 2808 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2809 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2810 // CHECK3-NEXT: [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]] 2811 // CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2812 // CHECK3: omp.inner.for.body: 2813 // CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2814 // CHECK3-NEXT: [[CONV11:%.*]] = sext i8 [[TMP11]] to i64 2815 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2816 // CHECK3-NEXT: [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11 2817 // CHECK3-NEXT: [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1 2818 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]] 2819 // CHECK3-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8 2820 // CHECK3-NEXT: store i8 [[CONV15]], i8* [[I8]], align 1 2821 // CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2822 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2823 // CHECK3-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11 2824 // CHECK3-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11 2825 // CHECK3-NEXT: [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]] 2826 // CHECK3-NEXT: [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1 2827 // CHECK3-NEXT: [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]] 2828 // CHECK3-NEXT: [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32 2829 // CHECK3-NEXT: store i32 [[CONV21]], i32* [[X9]], align 4 2830 // CHECK3-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2831 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[B_ADDR]], align 8 2832 // CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[I8]], align 1 2833 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64 2834 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM]] 2835 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4 2836 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[C_ADDR]], align 8 2837 // CHECK3-NEXT: [[TMP19:%.*]] = load i8, i8* [[I8]], align 1 2838 // CHECK3-NEXT: [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64 2839 // CHECK3-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM22]] 2840 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX23]], align 4 2841 // CHECK3-NEXT: [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]] 2842 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[D_ADDR]], align 8 2843 // CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[I8]], align 1 2844 // CHECK3-NEXT: [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64 2845 // CHECK3-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM25]] 2846 // CHECK3-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX26]], align 4 2847 // CHECK3-NEXT: [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]] 2848 // CHECK3-NEXT: [[TMP24:%.*]] = load float*, float** [[A_ADDR]], align 8 2849 // CHECK3-NEXT: [[TMP25:%.*]] = load i8, i8* [[I8]], align 1 2850 // CHECK3-NEXT: [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64 2851 // CHECK3-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM28]] 2852 // CHECK3-NEXT: store float [[MUL27]], float* [[ARRAYIDX29]], align 4 2853 // CHECK3-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2854 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2855 // CHECK3: omp.body.continue: 2856 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2857 // CHECK3: omp.inner.for.inc: 2858 // CHECK3-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2859 // CHECK3-NEXT: [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1 2860 // CHECK3-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 2861 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2862 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2863 // CHECK3: omp.inner.for.end: 2864 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2865 // CHECK3: omp.dispatch.inc: 2866 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2867 // CHECK3: omp.dispatch.end: 2868 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 2869 // CHECK3: omp.precond.end: 2870 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 2871 // CHECK3-NEXT: ret void 2872 // 2873 // 2874 // CHECK3-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 2875 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2876 // CHECK3-NEXT: entry: 2877 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2878 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2879 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2880 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2881 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 2882 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2883 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 2884 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2885 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2886 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2887 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2888 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2889 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 2890 // CHECK3-NEXT: [[X2:%.*]] = alloca i32, align 4 2891 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2892 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2893 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2894 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2895 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2896 // CHECK3-NEXT: store i32 0, i32* [[X]], align 4 2897 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2898 // CHECK3-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 2899 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2900 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2901 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 69, i32 0, i32 199, i32 1, i32 1) 2902 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2903 // CHECK3: omp.dispatch.cond: 2904 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2905 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 2906 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2907 // CHECK3: omp.dispatch.body: 2908 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2909 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 2910 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2911 // CHECK3: omp.inner.for.cond: 2912 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2913 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2914 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 2915 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2916 // CHECK3: omp.inner.for.body: 2917 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2918 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 20 2919 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2920 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 2921 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 2922 // CHECK3-NEXT: store i8 [[CONV]], i8* [[I]], align 1 2923 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2924 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2925 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20 2926 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20 2927 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]] 2928 // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 2929 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]] 2930 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[X2]], align 4 2931 // CHECK3-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2932 // CHECK3-NEXT: [[TMP8:%.*]] = load float*, float** [[B_ADDR]], align 8 2933 // CHECK3-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 2934 // CHECK3-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64 2935 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 2936 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 2937 // CHECK3-NEXT: [[TMP11:%.*]] = load float*, float** [[C_ADDR]], align 8 2938 // CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 2939 // CHECK3-NEXT: [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64 2940 // CHECK3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM7]] 2941 // CHECK3-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX8]], align 4 2942 // CHECK3-NEXT: [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]] 2943 // CHECK3-NEXT: [[TMP14:%.*]] = load float*, float** [[D_ADDR]], align 8 2944 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 2945 // CHECK3-NEXT: [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64 2946 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM10]] 2947 // CHECK3-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX11]], align 4 2948 // CHECK3-NEXT: [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]] 2949 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[A_ADDR]], align 8 2950 // CHECK3-NEXT: [[TMP18:%.*]] = load i8, i8* [[I]], align 1 2951 // CHECK3-NEXT: [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64 2952 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM13]] 2953 // CHECK3-NEXT: store float [[MUL12]], float* [[ARRAYIDX14]], align 4 2954 // CHECK3-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2955 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2956 // CHECK3: omp.body.continue: 2957 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2958 // CHECK3: omp.inner.for.inc: 2959 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2960 // CHECK3-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1 2961 // CHECK3-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4 2962 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2963 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2964 // CHECK3: omp.inner.for.end: 2965 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2966 // CHECK3: omp.dispatch.inc: 2967 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2968 // CHECK3: omp.dispatch.end: 2969 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 2970 // CHECK3-NEXT: ret void 2971 // 2972 // 2973 // CHECK3-LABEL: define {{[^@]+}}@_Z8foo_simdii 2974 // CHECK3-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { 2975 // CHECK3-NEXT: entry: 2976 // CHECK3-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 2977 // CHECK3-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 2978 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2979 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2980 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2981 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2982 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2983 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2984 // CHECK3-NEXT: [[I5:%.*]] = alloca i32, align 4 2985 // CHECK3-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 2986 // CHECK3-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 2987 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 2988 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 2989 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 2990 // CHECK3-NEXT: [[I26:%.*]] = alloca i32, align 4 2991 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2992 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2993 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2994 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2995 // CHECK3-NEXT: [[I28:%.*]] = alloca i32, align 4 2996 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2997 // CHECK3-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 2998 // CHECK3-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 2999 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 3000 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 3001 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[UP_ADDR]], align 4 3002 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3003 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3004 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3005 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 3006 // CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 3007 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 3008 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3009 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 3010 // CHECK3-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3011 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3012 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 3013 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3014 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3015 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 3016 // CHECK3-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 3017 // CHECK3: simd.if.then: 3018 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 3019 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3020 // CHECK3: omp.inner.for.cond: 3021 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 3022 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3023 // CHECK3-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 3024 // CHECK3-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]] 3025 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3026 // CHECK3: omp.inner.for.body: 3027 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3 3028 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 3029 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1 3030 // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]] 3031 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3 3032 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !3 3033 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 3034 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 3035 // CHECK3-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 3036 // CHECK3-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3 3037 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3038 // CHECK3: omp.body.continue: 3039 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3040 // CHECK3: omp.inner.for.inc: 3041 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 3042 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1 3043 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 3044 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3045 // CHECK3: omp.inner.for.end: 3046 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3047 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3048 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3049 // CHECK3-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]] 3050 // CHECK3-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 3051 // CHECK3-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 3052 // CHECK3-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 3053 // CHECK3-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 3054 // CHECK3-NEXT: [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]] 3055 // CHECK3-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 3056 // CHECK3-NEXT: br label [[SIMD_IF_END]] 3057 // CHECK3: simd.if.end: 3058 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 3059 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_18]], align 4 3060 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 3061 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_19]], align 4 3062 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3063 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 3064 // CHECK3-NEXT: [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]] 3065 // CHECK3-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 3066 // CHECK3-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 3067 // CHECK3-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 3068 // CHECK3-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 3069 // CHECK3-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 3070 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 3071 // CHECK3-NEXT: store i32 [[TMP21]], i32* [[I26]], align 4 3072 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 3073 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3074 // CHECK3-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] 3075 // CHECK3-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3076 // CHECK3: omp.precond.then: 3077 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3078 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 3079 // CHECK3-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_UB]], align 4 3080 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3081 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3082 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 3083 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1) 3084 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3085 // CHECK3: omp.dispatch.cond: 3086 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 3087 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0 3088 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3089 // CHECK3: omp.dispatch.body: 3090 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3091 // CHECK3-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4 3092 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 3093 // CHECK3: omp.inner.for.cond29: 3094 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 3095 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 3096 // CHECK3-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1 3097 // CHECK3-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]] 3098 // CHECK3-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]] 3099 // CHECK3: omp.inner.for.body32: 3100 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7 3101 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 3102 // CHECK3-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1 3103 // CHECK3-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]] 3104 // CHECK3-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4, !llvm.access.group !7 3105 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[I28]], align 4, !llvm.access.group !7 3106 // CHECK3-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 3107 // CHECK3-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM35]] 3108 // CHECK3-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4, !llvm.access.group !7 3109 // CHECK3-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7 3110 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] 3111 // CHECK3: omp.body.continue37: 3112 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]] 3113 // CHECK3: omp.inner.for.inc38: 3114 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 3115 // CHECK3-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1 3116 // CHECK3-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 3117 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group !7 3118 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]] 3119 // CHECK3: omp.inner.for.end40: 3120 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3121 // CHECK3: omp.dispatch.inc: 3122 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 3123 // CHECK3: omp.dispatch.end: 3124 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3125 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 3126 // CHECK3-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3127 // CHECK3: .omp.final.then: 3128 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 3129 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3130 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 3131 // CHECK3-NEXT: [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]] 3132 // CHECK3-NEXT: [[SUB42:%.*]] = sub i32 [[SUB41]], 1 3133 // CHECK3-NEXT: [[ADD43:%.*]] = add i32 [[SUB42]], 1 3134 // CHECK3-NEXT: [[DIV44:%.*]] = udiv i32 [[ADD43]], 1 3135 // CHECK3-NEXT: [[MUL45:%.*]] = mul i32 [[DIV44]], 1 3136 // CHECK3-NEXT: [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]] 3137 // CHECK3-NEXT: store i32 [[ADD46]], i32* [[I28]], align 4 3138 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3139 // CHECK3: .omp.final.done: 3140 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 3141 // CHECK3: omp.precond.end: 3142 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 3143 // CHECK3-NEXT: ret void 3144 // 3145 // 3146 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt 3147 // CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 3148 // CHECK3-NEXT: entry: 3149 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 3150 // CHECK3-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 3151 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 3152 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3153 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 3154 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 3155 // CHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 3156 // CHECK3-NEXT: ret void 3157 // 3158 // 3159 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.1 3160 // CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 3161 // CHECK3-NEXT: entry: 3162 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 3163 // CHECK3-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 3164 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 3165 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3166 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 3167 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 3168 // CHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 3169 // CHECK3-NEXT: ret void 3170 // 3171 // 3172 // CHECK4-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 3173 // CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 3174 // CHECK4-NEXT: entry: 3175 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3176 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3177 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3178 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3179 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3180 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 3181 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3182 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3183 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3184 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3185 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 3186 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 3187 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3188 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3189 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3190 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3191 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3192 // CHECK4-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 3193 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3194 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3195 // CHECK4-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 3196 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3197 // CHECK4: omp.dispatch.cond: 3198 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 3199 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 3200 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3201 // CHECK4: omp.dispatch.body: 3202 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3203 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 3204 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3205 // CHECK4: omp.inner.for.cond: 3206 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3207 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3208 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 3209 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3210 // CHECK4: omp.inner.for.body: 3211 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3212 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7 3213 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 3214 // CHECK4-NEXT: store i32 [[SUB]], i32* [[I]], align 4 3215 // CHECK4-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 3216 // CHECK4-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 3217 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 3218 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 3219 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM]] 3220 // CHECK4-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 3221 // CHECK4-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 3222 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 3223 // CHECK4-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64 3224 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM1]] 3225 // CHECK4-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 3226 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 3227 // CHECK4-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 3228 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 3229 // CHECK4-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64 3230 // CHECK4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM4]] 3231 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX5]], align 4 3232 // CHECK4-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]] 3233 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 3234 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 3235 // CHECK4-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 3236 // CHECK4-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM7]] 3237 // CHECK4-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 3238 // CHECK4-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 3239 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3240 // CHECK4: omp.body.continue: 3241 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3242 // CHECK4: omp.inner.for.inc: 3243 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3244 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], 1 3245 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 3246 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 3247 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 3248 // CHECK4: omp.inner.for.end: 3249 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3250 // CHECK4: omp.dispatch.inc: 3251 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 3252 // CHECK4: omp.dispatch.end: 3253 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP0]]) 3254 // CHECK4-NEXT: ret void 3255 // 3256 // 3257 // CHECK4-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 3258 // CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 3259 // CHECK4-NEXT: entry: 3260 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3261 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3262 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3263 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3264 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3265 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 8 3266 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3267 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3268 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3269 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3270 // CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 3271 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3272 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3273 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3274 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3275 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3276 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3277 // CHECK4-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 3278 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3279 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3280 // CHECK4-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 67, i64 0, i64 16908287, i64 1, i64 1) 3281 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3282 // CHECK4: omp.dispatch.cond: 3283 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 3284 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 3285 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3286 // CHECK4: omp.dispatch.body: 3287 // CHECK4-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3288 // CHECK4-NEXT: store i64 [[TMP2]], i64* [[DOTOMP_IV]], align 8 3289 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3290 // CHECK4: omp.inner.for.cond: 3291 // CHECK4-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3292 // CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3293 // CHECK4-NEXT: [[ADD:%.*]] = add i64 [[TMP4]], 1 3294 // CHECK4-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]] 3295 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3296 // CHECK4: omp.inner.for.body: 3297 // CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3298 // CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP5]], 127 3299 // CHECK4-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 3300 // CHECK4-NEXT: store i64 [[ADD1]], i64* [[I]], align 8 3301 // CHECK4-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 3302 // CHECK4-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 3303 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[I]], align 8 3304 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[TMP7]] 3305 // CHECK4-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 3306 // CHECK4-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 3307 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[I]], align 8 3308 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[TMP10]] 3309 // CHECK4-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 3310 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 3311 // CHECK4-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 3312 // CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[I]], align 8 3313 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[TMP13]] 3314 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX4]], align 4 3315 // CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]] 3316 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 3317 // CHECK4-NEXT: [[TMP16:%.*]] = load i64, i64* [[I]], align 8 3318 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[TMP16]] 3319 // CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 3320 // CHECK4-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 3321 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3322 // CHECK4: omp.body.continue: 3323 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3324 // CHECK4: omp.inner.for.inc: 3325 // CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3326 // CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP17]], 1 3327 // CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 3328 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 3329 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 3330 // CHECK4: omp.inner.for.end: 3331 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3332 // CHECK4: omp.dispatch.inc: 3333 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 3334 // CHECK4: omp.dispatch.end: 3335 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 3336 // CHECK4-NEXT: ret void 3337 // 3338 // 3339 // CHECK4-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 3340 // CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 3341 // CHECK4-NEXT: entry: 3342 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3343 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3344 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3345 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3346 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 3347 // CHECK4-NEXT: [[Y:%.*]] = alloca i32, align 4 3348 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3349 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 3350 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3351 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3352 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 3353 // CHECK4-NEXT: [[I:%.*]] = alloca i8, align 1 3354 // CHECK4-NEXT: [[X6:%.*]] = alloca i32, align 4 3355 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3356 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3357 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3358 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3359 // CHECK4-NEXT: [[I8:%.*]] = alloca i8, align 1 3360 // CHECK4-NEXT: [[X9:%.*]] = alloca i32, align 4 3361 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3362 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3363 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3364 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3365 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3366 // CHECK4-NEXT: store i32 0, i32* [[X]], align 4 3367 // CHECK4-NEXT: store i32 0, i32* [[Y]], align 4 3368 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[Y]], align 4 3369 // CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[TMP1]] to i8 3370 // CHECK4-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 3371 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3372 // CHECK4-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 3373 // CHECK4-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 3374 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 3375 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3376 // CHECK4-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 3377 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 3378 // CHECK4-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 3379 // CHECK4-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 3380 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3381 // CHECK4-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 3382 // CHECK4-NEXT: store i32 11, i32* [[X6]], align 4 3383 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3384 // CHECK4-NEXT: [[CONV7:%.*]] = sext i8 [[TMP4]] to i32 3385 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 3386 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3387 // CHECK4: omp.precond.then: 3388 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3389 // CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3390 // CHECK4-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_UB]], align 8 3391 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3392 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3393 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3394 // CHECK4-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 70, i64 0, i64 [[TMP6]], i64 1, i64 1) 3395 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3396 // CHECK4: omp.dispatch.cond: 3397 // CHECK4-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 3398 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 3399 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3400 // CHECK4: omp.dispatch.body: 3401 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3402 // CHECK4-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 3403 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3404 // CHECK4: omp.inner.for.cond: 3405 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3406 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3407 // CHECK4-NEXT: [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]] 3408 // CHECK4-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3409 // CHECK4: omp.inner.for.body: 3410 // CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3411 // CHECK4-NEXT: [[CONV11:%.*]] = sext i8 [[TMP11]] to i64 3412 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3413 // CHECK4-NEXT: [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11 3414 // CHECK4-NEXT: [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1 3415 // CHECK4-NEXT: [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]] 3416 // CHECK4-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8 3417 // CHECK4-NEXT: store i8 [[CONV15]], i8* [[I8]], align 1 3418 // CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3419 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3420 // CHECK4-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11 3421 // CHECK4-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11 3422 // CHECK4-NEXT: [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]] 3423 // CHECK4-NEXT: [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1 3424 // CHECK4-NEXT: [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]] 3425 // CHECK4-NEXT: [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32 3426 // CHECK4-NEXT: store i32 [[CONV21]], i32* [[X9]], align 4 3427 // CHECK4-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 3428 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[B_ADDR]], align 8 3429 // CHECK4-NEXT: [[TMP16:%.*]] = load i8, i8* [[I8]], align 1 3430 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64 3431 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM]] 3432 // CHECK4-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4 3433 // CHECK4-NEXT: [[TMP18:%.*]] = load float*, float** [[C_ADDR]], align 8 3434 // CHECK4-NEXT: [[TMP19:%.*]] = load i8, i8* [[I8]], align 1 3435 // CHECK4-NEXT: [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64 3436 // CHECK4-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM22]] 3437 // CHECK4-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX23]], align 4 3438 // CHECK4-NEXT: [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]] 3439 // CHECK4-NEXT: [[TMP21:%.*]] = load float*, float** [[D_ADDR]], align 8 3440 // CHECK4-NEXT: [[TMP22:%.*]] = load i8, i8* [[I8]], align 1 3441 // CHECK4-NEXT: [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64 3442 // CHECK4-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM25]] 3443 // CHECK4-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX26]], align 4 3444 // CHECK4-NEXT: [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]] 3445 // CHECK4-NEXT: [[TMP24:%.*]] = load float*, float** [[A_ADDR]], align 8 3446 // CHECK4-NEXT: [[TMP25:%.*]] = load i8, i8* [[I8]], align 1 3447 // CHECK4-NEXT: [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64 3448 // CHECK4-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM28]] 3449 // CHECK4-NEXT: store float [[MUL27]], float* [[ARRAYIDX29]], align 4 3450 // CHECK4-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 3451 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3452 // CHECK4: omp.body.continue: 3453 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3454 // CHECK4: omp.inner.for.inc: 3455 // CHECK4-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3456 // CHECK4-NEXT: [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1 3457 // CHECK4-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 3458 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 3459 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 3460 // CHECK4: omp.inner.for.end: 3461 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3462 // CHECK4: omp.dispatch.inc: 3463 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 3464 // CHECK4: omp.dispatch.end: 3465 // CHECK4-NEXT: br label [[OMP_PRECOND_END]] 3466 // CHECK4: omp.precond.end: 3467 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 3468 // CHECK4-NEXT: ret void 3469 // 3470 // 3471 // CHECK4-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 3472 // CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 3473 // CHECK4-NEXT: entry: 3474 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3475 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3476 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3477 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3478 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 3479 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3480 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 3481 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3482 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3483 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3484 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3485 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3486 // CHECK4-NEXT: [[I:%.*]] = alloca i8, align 1 3487 // CHECK4-NEXT: [[X2:%.*]] = alloca i32, align 4 3488 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3489 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3490 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3491 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3492 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3493 // CHECK4-NEXT: store i32 0, i32* [[X]], align 4 3494 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3495 // CHECK4-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 3496 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3497 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3498 // CHECK4-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 69, i32 0, i32 199, i32 1, i32 1) 3499 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3500 // CHECK4: omp.dispatch.cond: 3501 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 3502 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 3503 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3504 // CHECK4: omp.dispatch.body: 3505 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3506 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 3507 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3508 // CHECK4: omp.inner.for.cond: 3509 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3510 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3511 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 3512 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3513 // CHECK4: omp.inner.for.body: 3514 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3515 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 20 3516 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 3517 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 3518 // CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 3519 // CHECK4-NEXT: store i8 [[CONV]], i8* [[I]], align 1 3520 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3521 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3522 // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20 3523 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20 3524 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]] 3525 // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 3526 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]] 3527 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[X2]], align 4 3528 // CHECK4-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 3529 // CHECK4-NEXT: [[TMP8:%.*]] = load float*, float** [[B_ADDR]], align 8 3530 // CHECK4-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 3531 // CHECK4-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64 3532 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 3533 // CHECK4-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 3534 // CHECK4-NEXT: [[TMP11:%.*]] = load float*, float** [[C_ADDR]], align 8 3535 // CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 3536 // CHECK4-NEXT: [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64 3537 // CHECK4-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM7]] 3538 // CHECK4-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX8]], align 4 3539 // CHECK4-NEXT: [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]] 3540 // CHECK4-NEXT: [[TMP14:%.*]] = load float*, float** [[D_ADDR]], align 8 3541 // CHECK4-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 3542 // CHECK4-NEXT: [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64 3543 // CHECK4-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM10]] 3544 // CHECK4-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX11]], align 4 3545 // CHECK4-NEXT: [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]] 3546 // CHECK4-NEXT: [[TMP17:%.*]] = load float*, float** [[A_ADDR]], align 8 3547 // CHECK4-NEXT: [[TMP18:%.*]] = load i8, i8* [[I]], align 1 3548 // CHECK4-NEXT: [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64 3549 // CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM13]] 3550 // CHECK4-NEXT: store float [[MUL12]], float* [[ARRAYIDX14]], align 4 3551 // CHECK4-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 3552 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3553 // CHECK4: omp.body.continue: 3554 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3555 // CHECK4: omp.inner.for.inc: 3556 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3557 // CHECK4-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1 3558 // CHECK4-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4 3559 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 3560 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 3561 // CHECK4: omp.inner.for.end: 3562 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3563 // CHECK4: omp.dispatch.inc: 3564 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 3565 // CHECK4: omp.dispatch.end: 3566 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 3567 // CHECK4-NEXT: ret void 3568 // 3569 // 3570 // CHECK4-LABEL: define {{[^@]+}}@_Z8foo_simdii 3571 // CHECK4-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { 3572 // CHECK4-NEXT: entry: 3573 // CHECK4-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 3574 // CHECK4-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 3575 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 3576 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3577 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3578 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3579 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 3580 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3581 // CHECK4-NEXT: [[I5:%.*]] = alloca i32, align 4 3582 // CHECK4-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 3583 // CHECK4-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 3584 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 3585 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 3586 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 3587 // CHECK4-NEXT: [[I26:%.*]] = alloca i32, align 4 3588 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3589 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3590 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3591 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3592 // CHECK4-NEXT: [[I28:%.*]] = alloca i32, align 4 3593 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3594 // CHECK4-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 3595 // CHECK4-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 3596 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 3597 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 3598 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[UP_ADDR]], align 4 3599 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3600 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3601 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3602 // CHECK4-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 3603 // CHECK4-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 3604 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 3605 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3606 // CHECK4-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 3607 // CHECK4-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3608 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3609 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 3610 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3611 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3612 // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 3613 // CHECK4-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 3614 // CHECK4: simd.if.then: 3615 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 3616 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3617 // CHECK4: omp.inner.for.cond: 3618 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 3619 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3620 // CHECK4-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 3621 // CHECK4-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]] 3622 // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3623 // CHECK4: omp.inner.for.body: 3624 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3 3625 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 3626 // CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1 3627 // CHECK4-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]] 3628 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3 3629 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !3 3630 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 3631 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 3632 // CHECK4-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 3633 // CHECK4-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3 3634 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3635 // CHECK4: omp.body.continue: 3636 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3637 // CHECK4: omp.inner.for.inc: 3638 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 3639 // CHECK4-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1 3640 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 3641 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3642 // CHECK4: omp.inner.for.end: 3643 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3644 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3645 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3646 // CHECK4-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]] 3647 // CHECK4-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 3648 // CHECK4-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 3649 // CHECK4-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 3650 // CHECK4-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 3651 // CHECK4-NEXT: [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]] 3652 // CHECK4-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 3653 // CHECK4-NEXT: br label [[SIMD_IF_END]] 3654 // CHECK4: simd.if.end: 3655 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 3656 // CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_18]], align 4 3657 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 3658 // CHECK4-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_19]], align 4 3659 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3660 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 3661 // CHECK4-NEXT: [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]] 3662 // CHECK4-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 3663 // CHECK4-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 3664 // CHECK4-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 3665 // CHECK4-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 3666 // CHECK4-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 3667 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 3668 // CHECK4-NEXT: store i32 [[TMP21]], i32* [[I26]], align 4 3669 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 3670 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3671 // CHECK4-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] 3672 // CHECK4-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3673 // CHECK4: omp.precond.then: 3674 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3675 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 3676 // CHECK4-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_UB]], align 4 3677 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3678 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3679 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 3680 // CHECK4-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1) 3681 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3682 // CHECK4: omp.dispatch.cond: 3683 // CHECK4-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 3684 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0 3685 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3686 // CHECK4: omp.dispatch.body: 3687 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3688 // CHECK4-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4 3689 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 3690 // CHECK4: omp.inner.for.cond29: 3691 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 3692 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 3693 // CHECK4-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1 3694 // CHECK4-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]] 3695 // CHECK4-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]] 3696 // CHECK4: omp.inner.for.body32: 3697 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7 3698 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 3699 // CHECK4-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1 3700 // CHECK4-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]] 3701 // CHECK4-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4, !llvm.access.group !7 3702 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[I28]], align 4, !llvm.access.group !7 3703 // CHECK4-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 3704 // CHECK4-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM35]] 3705 // CHECK4-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4, !llvm.access.group !7 3706 // CHECK4-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7 3707 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] 3708 // CHECK4: omp.body.continue37: 3709 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]] 3710 // CHECK4: omp.inner.for.inc38: 3711 // CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 3712 // CHECK4-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1 3713 // CHECK4-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 3714 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group !7 3715 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]] 3716 // CHECK4: omp.inner.for.end40: 3717 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3718 // CHECK4: omp.dispatch.inc: 3719 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 3720 // CHECK4: omp.dispatch.end: 3721 // CHECK4-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3722 // CHECK4-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 3723 // CHECK4-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3724 // CHECK4: .omp.final.then: 3725 // CHECK4-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 3726 // CHECK4-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3727 // CHECK4-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 3728 // CHECK4-NEXT: [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]] 3729 // CHECK4-NEXT: [[SUB42:%.*]] = sub i32 [[SUB41]], 1 3730 // CHECK4-NEXT: [[ADD43:%.*]] = add i32 [[SUB42]], 1 3731 // CHECK4-NEXT: [[DIV44:%.*]] = udiv i32 [[ADD43]], 1 3732 // CHECK4-NEXT: [[MUL45:%.*]] = mul i32 [[DIV44]], 1 3733 // CHECK4-NEXT: [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]] 3734 // CHECK4-NEXT: store i32 [[ADD46]], i32* [[I28]], align 4 3735 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] 3736 // CHECK4: .omp.final.done: 3737 // CHECK4-NEXT: br label [[OMP_PRECOND_END]] 3738 // CHECK4: omp.precond.end: 3739 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 3740 // CHECK4-NEXT: ret void 3741 // 3742 // 3743 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt 3744 // CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 3745 // CHECK4-NEXT: entry: 3746 // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 3747 // CHECK4-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 3748 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 3749 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3750 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 3751 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 3752 // CHECK4-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 3753 // CHECK4-NEXT: ret void 3754 // 3755 // 3756 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt.1 3757 // CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 3758 // CHECK4-NEXT: entry: 3759 // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 3760 // CHECK4-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 3761 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 3762 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3763 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 3764 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 3765 // CHECK4-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 3766 // CHECK4-NEXT: ret void 3767 // 3768 // 3769 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 3770 // CHECK3-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 3771 // CHECK3-IRBUILDER-NEXT: entry: 3772 // CHECK3-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3773 // CHECK3-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3774 // CHECK3-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3775 // CHECK3-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3776 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3777 // CHECK3-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i32, align 4 3778 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3779 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3780 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3781 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3782 // CHECK3-IRBUILDER-NEXT: [[I:%.*]] = alloca i32, align 4 3783 // CHECK3-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3784 // CHECK3-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3785 // CHECK3-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3786 // CHECK3-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3787 // CHECK3-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3788 // CHECK3-IRBUILDER-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 3789 // CHECK3-IRBUILDER-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3790 // CHECK3-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3791 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 3792 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 3793 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3794 // CHECK3-IRBUILDER: omp.dispatch.cond: 3795 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 3796 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 3797 // CHECK3-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 3798 // CHECK3-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3799 // CHECK3-IRBUILDER: omp.dispatch.body: 3800 // CHECK3-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3801 // CHECK3-IRBUILDER-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 3802 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3803 // CHECK3-IRBUILDER: omp.inner.for.cond: 3804 // CHECK3-IRBUILDER-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3805 // CHECK3-IRBUILDER-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3806 // CHECK3-IRBUILDER-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 3807 // CHECK3-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3808 // CHECK3-IRBUILDER: omp.inner.for.body: 3809 // CHECK3-IRBUILDER-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3810 // CHECK3-IRBUILDER-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 3811 // CHECK3-IRBUILDER-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 3812 // CHECK3-IRBUILDER-NEXT: store i32 [[SUB]], i32* [[I]], align 4 3813 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3814 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) 3815 // CHECK3-IRBUILDER-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8 3816 // CHECK3-IRBUILDER-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 3817 // CHECK3-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 3818 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]] 3819 // CHECK3-IRBUILDER-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4 3820 // CHECK3-IRBUILDER-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8 3821 // CHECK3-IRBUILDER-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 3822 // CHECK3-IRBUILDER-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 3823 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM3]] 3824 // CHECK3-IRBUILDER-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX4]], align 4 3825 // CHECK3-IRBUILDER-NEXT: [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]] 3826 // CHECK3-IRBUILDER-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8 3827 // CHECK3-IRBUILDER-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 3828 // CHECK3-IRBUILDER-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP12]] to i64 3829 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM6]] 3830 // CHECK3-IRBUILDER-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX7]], align 4 3831 // CHECK3-IRBUILDER-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP13]] 3832 // CHECK3-IRBUILDER-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8 3833 // CHECK3-IRBUILDER-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 3834 // CHECK3-IRBUILDER-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64 3835 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM9]] 3836 // CHECK3-IRBUILDER-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 3837 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 3838 // CHECK3-IRBUILDER: omp.inner.for.body.ordered.after: 3839 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) 3840 // CHECK3-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3841 // CHECK3-IRBUILDER: omp.body.continue: 3842 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3843 // CHECK3-IRBUILDER: omp.inner.for.inc: 3844 // CHECK3-IRBUILDER-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3845 // CHECK3-IRBUILDER-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 3846 // CHECK3-IRBUILDER-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 3847 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 3848 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) 3849 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 3850 // CHECK3-IRBUILDER: omp.inner.for.end: 3851 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3852 // CHECK3-IRBUILDER: omp.dispatch.inc: 3853 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 3854 // CHECK3-IRBUILDER: omp.dispatch.end: 3855 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3856 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM12]]) 3857 // CHECK3-IRBUILDER-NEXT: ret void 3858 // 3859 // 3860 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 3861 // CHECK3-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 3862 // CHECK3-IRBUILDER-NEXT: entry: 3863 // CHECK3-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3864 // CHECK3-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3865 // CHECK3-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3866 // CHECK3-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3867 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3868 // CHECK3-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i64, align 8 3869 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3870 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3871 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3872 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3873 // CHECK3-IRBUILDER-NEXT: [[I:%.*]] = alloca i64, align 8 3874 // CHECK3-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3875 // CHECK3-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3876 // CHECK3-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3877 // CHECK3-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3878 // CHECK3-IRBUILDER-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3879 // CHECK3-IRBUILDER-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 3880 // CHECK3-IRBUILDER-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3881 // CHECK3-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3882 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6:[0-9]+]]) 3883 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 67, i64 0, i64 16908287, i64 1, i64 1) 3884 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3885 // CHECK3-IRBUILDER: omp.dispatch.cond: 3886 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 3887 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 3888 // CHECK3-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 3889 // CHECK3-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3890 // CHECK3-IRBUILDER: omp.dispatch.body: 3891 // CHECK3-IRBUILDER-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3892 // CHECK3-IRBUILDER-NEXT: store i64 [[TMP1]], i64* [[DOTOMP_IV]], align 8 3893 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3894 // CHECK3-IRBUILDER: omp.inner.for.cond: 3895 // CHECK3-IRBUILDER-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3896 // CHECK3-IRBUILDER-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3897 // CHECK3-IRBUILDER-NEXT: [[ADD:%.*]] = add i64 [[TMP3]], 1 3898 // CHECK3-IRBUILDER-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP2]], [[ADD]] 3899 // CHECK3-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3900 // CHECK3-IRBUILDER: omp.inner.for.body: 3901 // CHECK3-IRBUILDER-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3902 // CHECK3-IRBUILDER-NEXT: [[MUL:%.*]] = mul i64 [[TMP4]], 127 3903 // CHECK3-IRBUILDER-NEXT: [[ADD2:%.*]] = add i64 131071, [[MUL]] 3904 // CHECK3-IRBUILDER-NEXT: store i64 [[ADD2]], i64* [[I]], align 8 3905 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3906 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) 3907 // CHECK3-IRBUILDER-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8 3908 // CHECK3-IRBUILDER-NEXT: [[TMP6:%.*]] = load i64, i64* [[I]], align 8 3909 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[TMP6]] 3910 // CHECK3-IRBUILDER-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4 3911 // CHECK3-IRBUILDER-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8 3912 // CHECK3-IRBUILDER-NEXT: [[TMP9:%.*]] = load i64, i64* [[I]], align 8 3913 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[TMP9]] 3914 // CHECK3-IRBUILDER-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX4]], align 4 3915 // CHECK3-IRBUILDER-NEXT: [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]] 3916 // CHECK3-IRBUILDER-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8 3917 // CHECK3-IRBUILDER-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 3918 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 3919 // CHECK3-IRBUILDER-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX6]], align 4 3920 // CHECK3-IRBUILDER-NEXT: [[MUL7:%.*]] = fmul float [[MUL5]], [[TMP13]] 3921 // CHECK3-IRBUILDER-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8 3922 // CHECK3-IRBUILDER-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8 3923 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 3924 // CHECK3-IRBUILDER-NEXT: store float [[MUL7]], float* [[ARRAYIDX8]], align 4 3925 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 3926 // CHECK3-IRBUILDER: omp.inner.for.body.ordered.after: 3927 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) 3928 // CHECK3-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3929 // CHECK3-IRBUILDER: omp.body.continue: 3930 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3931 // CHECK3-IRBUILDER: omp.inner.for.inc: 3932 // CHECK3-IRBUILDER-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3933 // CHECK3-IRBUILDER-NEXT: [[ADD9:%.*]] = add i64 [[TMP16]], 1 3934 // CHECK3-IRBUILDER-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8 3935 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 3936 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]]) 3937 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 3938 // CHECK3-IRBUILDER: omp.inner.for.end: 3939 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3940 // CHECK3-IRBUILDER: omp.dispatch.inc: 3941 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 3942 // CHECK3-IRBUILDER: omp.dispatch.end: 3943 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3944 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) 3945 // CHECK3-IRBUILDER-NEXT: ret void 3946 // 3947 // 3948 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 3949 // CHECK3-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 3950 // CHECK3-IRBUILDER-NEXT: entry: 3951 // CHECK3-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3952 // CHECK3-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3953 // CHECK3-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3954 // CHECK3-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3955 // CHECK3-IRBUILDER-NEXT: [[X:%.*]] = alloca i32, align 4 3956 // CHECK3-IRBUILDER-NEXT: [[Y:%.*]] = alloca i32, align 4 3957 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3958 // CHECK3-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i8, align 1 3959 // CHECK3-IRBUILDER-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3960 // CHECK3-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3961 // CHECK3-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 3962 // CHECK3-IRBUILDER-NEXT: [[I:%.*]] = alloca i8, align 1 3963 // CHECK3-IRBUILDER-NEXT: [[X6:%.*]] = alloca i32, align 4 3964 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3965 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3966 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3967 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3968 // CHECK3-IRBUILDER-NEXT: [[I8:%.*]] = alloca i8, align 1 3969 // CHECK3-IRBUILDER-NEXT: [[X9:%.*]] = alloca i32, align 4 3970 // CHECK3-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3971 // CHECK3-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3972 // CHECK3-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3973 // CHECK3-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3974 // CHECK3-IRBUILDER-NEXT: store i32 0, i32* [[X]], align 4 3975 // CHECK3-IRBUILDER-NEXT: store i32 0, i32* [[Y]], align 4 3976 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 3977 // CHECK3-IRBUILDER-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 3978 // CHECK3-IRBUILDER-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 3979 // CHECK3-IRBUILDER-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3980 // CHECK3-IRBUILDER-NEXT: [[CONV3:%.*]] = sext i8 [[TMP1]] to i32 3981 // CHECK3-IRBUILDER-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 3982 // CHECK3-IRBUILDER-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 3983 // CHECK3-IRBUILDER-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3984 // CHECK3-IRBUILDER-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 3985 // CHECK3-IRBUILDER-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 3986 // CHECK3-IRBUILDER-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 3987 // CHECK3-IRBUILDER-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 3988 // CHECK3-IRBUILDER-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3989 // CHECK3-IRBUILDER-NEXT: store i8 [[TMP2]], i8* [[I]], align 1 3990 // CHECK3-IRBUILDER-NEXT: store i32 11, i32* [[X6]], align 4 3991 // CHECK3-IRBUILDER-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3992 // CHECK3-IRBUILDER-NEXT: [[CONV7:%.*]] = sext i8 [[TMP3]] to i32 3993 // CHECK3-IRBUILDER-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 3994 // CHECK3-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3995 // CHECK3-IRBUILDER: omp.precond.then: 3996 // CHECK3-IRBUILDER-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3997 // CHECK3-IRBUILDER-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3998 // CHECK3-IRBUILDER-NEXT: store i64 [[TMP4]], i64* [[DOTOMP_UB]], align 8 3999 // CHECK3-IRBUILDER-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4000 // CHECK3-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4001 // CHECK3-IRBUILDER-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 4002 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8:[0-9]+]]) 4003 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 70, i64 0, i64 [[TMP5]], i64 1, i64 1) 4004 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4005 // CHECK3-IRBUILDER: omp.dispatch.cond: 4006 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 4007 // CHECK3-IRBUILDER-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 4008 // CHECK3-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 4009 // CHECK3-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4010 // CHECK3-IRBUILDER: omp.dispatch.body: 4011 // CHECK3-IRBUILDER-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4012 // CHECK3-IRBUILDER-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 4013 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4014 // CHECK3-IRBUILDER: omp.inner.for.cond: 4015 // CHECK3-IRBUILDER-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4016 // CHECK3-IRBUILDER-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4017 // CHECK3-IRBUILDER-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP8]], [[TMP9]] 4018 // CHECK3-IRBUILDER-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4019 // CHECK3-IRBUILDER: omp.inner.for.body: 4020 // CHECK3-IRBUILDER-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4021 // CHECK3-IRBUILDER-NEXT: [[CONV12:%.*]] = sext i8 [[TMP10]] to i64 4022 // CHECK3-IRBUILDER-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4023 // CHECK3-IRBUILDER-NEXT: [[DIV13:%.*]] = sdiv i64 [[TMP11]], 11 4024 // CHECK3-IRBUILDER-NEXT: [[MUL14:%.*]] = mul nsw i64 [[DIV13]], 1 4025 // CHECK3-IRBUILDER-NEXT: [[ADD15:%.*]] = add nsw i64 [[CONV12]], [[MUL14]] 4026 // CHECK3-IRBUILDER-NEXT: [[CONV16:%.*]] = trunc i64 [[ADD15]] to i8 4027 // CHECK3-IRBUILDER-NEXT: store i8 [[CONV16]], i8* [[I8]], align 1 4028 // CHECK3-IRBUILDER-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4029 // CHECK3-IRBUILDER-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4030 // CHECK3-IRBUILDER-NEXT: [[DIV17:%.*]] = sdiv i64 [[TMP13]], 11 4031 // CHECK3-IRBUILDER-NEXT: [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 11 4032 // CHECK3-IRBUILDER-NEXT: [[SUB19:%.*]] = sub nsw i64 [[TMP12]], [[MUL18]] 4033 // CHECK3-IRBUILDER-NEXT: [[MUL20:%.*]] = mul nsw i64 [[SUB19]], 1 4034 // CHECK3-IRBUILDER-NEXT: [[SUB21:%.*]] = sub nsw i64 11, [[MUL20]] 4035 // CHECK3-IRBUILDER-NEXT: [[CONV22:%.*]] = trunc i64 [[SUB21]] to i32 4036 // CHECK3-IRBUILDER-NEXT: store i32 [[CONV22]], i32* [[X9]], align 4 4037 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4038 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]]) 4039 // CHECK3-IRBUILDER-NEXT: [[TMP14:%.*]] = load float*, float** [[B_ADDR]], align 8 4040 // CHECK3-IRBUILDER-NEXT: [[TMP15:%.*]] = load i8, i8* [[I8]], align 1 4041 // CHECK3-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP15]] to i64 4042 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 4043 // CHECK3-IRBUILDER-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4 4044 // CHECK3-IRBUILDER-NEXT: [[TMP17:%.*]] = load float*, float** [[C_ADDR]], align 8 4045 // CHECK3-IRBUILDER-NEXT: [[TMP18:%.*]] = load i8, i8* [[I8]], align 1 4046 // CHECK3-IRBUILDER-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP18]] to i64 4047 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM24]] 4048 // CHECK3-IRBUILDER-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX25]], align 4 4049 // CHECK3-IRBUILDER-NEXT: [[MUL26:%.*]] = fmul float [[TMP16]], [[TMP19]] 4050 // CHECK3-IRBUILDER-NEXT: [[TMP20:%.*]] = load float*, float** [[D_ADDR]], align 8 4051 // CHECK3-IRBUILDER-NEXT: [[TMP21:%.*]] = load i8, i8* [[I8]], align 1 4052 // CHECK3-IRBUILDER-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP21]] to i64 4053 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM27]] 4054 // CHECK3-IRBUILDER-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX28]], align 4 4055 // CHECK3-IRBUILDER-NEXT: [[MUL29:%.*]] = fmul float [[MUL26]], [[TMP22]] 4056 // CHECK3-IRBUILDER-NEXT: [[TMP23:%.*]] = load float*, float** [[A_ADDR]], align 8 4057 // CHECK3-IRBUILDER-NEXT: [[TMP24:%.*]] = load i8, i8* [[I8]], align 1 4058 // CHECK3-IRBUILDER-NEXT: [[IDXPROM30:%.*]] = sext i8 [[TMP24]] to i64 4059 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM30]] 4060 // CHECK3-IRBUILDER-NEXT: store float [[MUL29]], float* [[ARRAYIDX31]], align 4 4061 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 4062 // CHECK3-IRBUILDER: omp.inner.for.body.ordered.after: 4063 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]]) 4064 // CHECK3-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4065 // CHECK3-IRBUILDER: omp.body.continue: 4066 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4067 // CHECK3-IRBUILDER: omp.inner.for.inc: 4068 // CHECK3-IRBUILDER-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4069 // CHECK3-IRBUILDER-NEXT: [[ADD32:%.*]] = add nsw i64 [[TMP25]], 1 4070 // CHECK3-IRBUILDER-NEXT: store i64 [[ADD32]], i64* [[DOTOMP_IV]], align 8 4071 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM33:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 4072 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM33]]) 4073 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 4074 // CHECK3-IRBUILDER: omp.inner.for.end: 4075 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4076 // CHECK3-IRBUILDER: omp.dispatch.inc: 4077 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 4078 // CHECK3-IRBUILDER: omp.dispatch.end: 4079 // CHECK3-IRBUILDER-NEXT: br label [[OMP_PRECOND_END]] 4080 // CHECK3-IRBUILDER: omp.precond.end: 4081 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM34:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4082 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM34]]) 4083 // CHECK3-IRBUILDER-NEXT: ret void 4084 // 4085 // 4086 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 4087 // CHECK3-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4088 // CHECK3-IRBUILDER-NEXT: entry: 4089 // CHECK3-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4090 // CHECK3-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4091 // CHECK3-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4092 // CHECK3-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4093 // CHECK3-IRBUILDER-NEXT: [[X:%.*]] = alloca i32, align 4 4094 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4095 // CHECK3-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i8, align 1 4096 // CHECK3-IRBUILDER-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4097 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4098 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4099 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4100 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4101 // CHECK3-IRBUILDER-NEXT: [[I:%.*]] = alloca i8, align 1 4102 // CHECK3-IRBUILDER-NEXT: [[X2:%.*]] = alloca i32, align 4 4103 // CHECK3-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4104 // CHECK3-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4105 // CHECK3-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4106 // CHECK3-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4107 // CHECK3-IRBUILDER-NEXT: store i32 0, i32* [[X]], align 4 4108 // CHECK3-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4109 // CHECK3-IRBUILDER-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 4110 // CHECK3-IRBUILDER-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4111 // CHECK3-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4112 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10:[0-9]+]]) 4113 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 69, i32 0, i32 199, i32 1, i32 1) 4114 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4115 // CHECK3-IRBUILDER: omp.dispatch.cond: 4116 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 4117 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 4118 // CHECK3-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 4119 // CHECK3-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4120 // CHECK3-IRBUILDER: omp.dispatch.body: 4121 // CHECK3-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4122 // CHECK3-IRBUILDER-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 4123 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4124 // CHECK3-IRBUILDER: omp.inner.for.cond: 4125 // CHECK3-IRBUILDER-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4126 // CHECK3-IRBUILDER-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4127 // CHECK3-IRBUILDER-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 4128 // CHECK3-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4129 // CHECK3-IRBUILDER: omp.inner.for.body: 4130 // CHECK3-IRBUILDER-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4131 // CHECK3-IRBUILDER-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 20 4132 // CHECK3-IRBUILDER-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 4133 // CHECK3-IRBUILDER-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 4134 // CHECK3-IRBUILDER-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 4135 // CHECK3-IRBUILDER-NEXT: store i8 [[CONV]], i8* [[I]], align 1 4136 // CHECK3-IRBUILDER-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4137 // CHECK3-IRBUILDER-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4138 // CHECK3-IRBUILDER-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP6]], 20 4139 // CHECK3-IRBUILDER-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 20 4140 // CHECK3-IRBUILDER-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], [[MUL5]] 4141 // CHECK3-IRBUILDER-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 4142 // CHECK3-IRBUILDER-NEXT: [[ADD7:%.*]] = add nsw i32 -10, [[MUL6]] 4143 // CHECK3-IRBUILDER-NEXT: store i32 [[ADD7]], i32* [[X2]], align 4 4144 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM8:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4145 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]]) 4146 // CHECK3-IRBUILDER-NEXT: [[TMP7:%.*]] = load float*, float** [[B_ADDR]], align 8 4147 // CHECK3-IRBUILDER-NEXT: [[TMP8:%.*]] = load i8, i8* [[I]], align 1 4148 // CHECK3-IRBUILDER-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP8]] to i64 4149 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM]] 4150 // CHECK3-IRBUILDER-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 4151 // CHECK3-IRBUILDER-NEXT: [[TMP10:%.*]] = load float*, float** [[C_ADDR]], align 8 4152 // CHECK3-IRBUILDER-NEXT: [[TMP11:%.*]] = load i8, i8* [[I]], align 1 4153 // CHECK3-IRBUILDER-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP11]] to i64 4154 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM9]] 4155 // CHECK3-IRBUILDER-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX10]], align 4 4156 // CHECK3-IRBUILDER-NEXT: [[MUL11:%.*]] = fmul float [[TMP9]], [[TMP12]] 4157 // CHECK3-IRBUILDER-NEXT: [[TMP13:%.*]] = load float*, float** [[D_ADDR]], align 8 4158 // CHECK3-IRBUILDER-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 4159 // CHECK3-IRBUILDER-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP14]] to i64 4160 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM12]] 4161 // CHECK3-IRBUILDER-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX13]], align 4 4162 // CHECK3-IRBUILDER-NEXT: [[MUL14:%.*]] = fmul float [[MUL11]], [[TMP15]] 4163 // CHECK3-IRBUILDER-NEXT: [[TMP16:%.*]] = load float*, float** [[A_ADDR]], align 8 4164 // CHECK3-IRBUILDER-NEXT: [[TMP17:%.*]] = load i8, i8* [[I]], align 1 4165 // CHECK3-IRBUILDER-NEXT: [[IDXPROM15:%.*]] = zext i8 [[TMP17]] to i64 4166 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM15]] 4167 // CHECK3-IRBUILDER-NEXT: store float [[MUL14]], float* [[ARRAYIDX16]], align 4 4168 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 4169 // CHECK3-IRBUILDER: omp.inner.for.body.ordered.after: 4170 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]]) 4171 // CHECK3-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4172 // CHECK3-IRBUILDER: omp.body.continue: 4173 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4174 // CHECK3-IRBUILDER: omp.inner.for.inc: 4175 // CHECK3-IRBUILDER-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4176 // CHECK3-IRBUILDER-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP18]], 1 4177 // CHECK3-IRBUILDER-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4 4178 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 4179 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM18]]) 4180 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 4181 // CHECK3-IRBUILDER: omp.inner.for.end: 4182 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4183 // CHECK3-IRBUILDER: omp.dispatch.inc: 4184 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 4185 // CHECK3-IRBUILDER: omp.dispatch.end: 4186 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM19:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4187 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM19]]) 4188 // CHECK3-IRBUILDER-NEXT: ret void 4189 // 4190 // 4191 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z8foo_simdii 4192 // CHECK3-IRBUILDER-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { 4193 // CHECK3-IRBUILDER-NEXT: entry: 4194 // CHECK3-IRBUILDER-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 4195 // CHECK3-IRBUILDER-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 4196 // CHECK3-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i32, align 4 4197 // CHECK3-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4198 // CHECK3-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4199 // CHECK3-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 4200 // CHECK3-IRBUILDER-NEXT: [[I:%.*]] = alloca i32, align 4 4201 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4202 // CHECK3-IRBUILDER-NEXT: [[I5:%.*]] = alloca i32, align 4 4203 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 4204 // CHECK3-IRBUILDER-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 4205 // CHECK3-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 4206 // CHECK3-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 4207 // CHECK3-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 4208 // CHECK3-IRBUILDER-NEXT: [[I26:%.*]] = alloca i32, align 4 4209 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4210 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4211 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4212 // CHECK3-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4213 // CHECK3-IRBUILDER-NEXT: [[I28:%.*]] = alloca i32, align 4 4214 // CHECK3-IRBUILDER-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 4215 // CHECK3-IRBUILDER-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 4216 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 4217 // CHECK3-IRBUILDER-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 4218 // CHECK3-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[UP_ADDR]], align 4 4219 // CHECK3-IRBUILDER-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4220 // CHECK3-IRBUILDER-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4221 // CHECK3-IRBUILDER-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4222 // CHECK3-IRBUILDER-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 4223 // CHECK3-IRBUILDER-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 4224 // CHECK3-IRBUILDER-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 4225 // CHECK3-IRBUILDER-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4226 // CHECK3-IRBUILDER-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 4227 // CHECK3-IRBUILDER-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 4228 // CHECK3-IRBUILDER-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4229 // CHECK3-IRBUILDER-NEXT: store i32 [[TMP4]], i32* [[I]], align 4 4230 // CHECK3-IRBUILDER-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4231 // CHECK3-IRBUILDER-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4232 // CHECK3-IRBUILDER-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] 4233 // CHECK3-IRBUILDER-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 4234 // CHECK3-IRBUILDER: simd.if.then: 4235 // CHECK3-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 4236 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4237 // CHECK3-IRBUILDER: omp.inner.for.cond: 4238 // CHECK3-IRBUILDER-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4239 // CHECK3-IRBUILDER-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 4240 // CHECK3-IRBUILDER-NEXT: [[ADD6:%.*]] = add i32 [[TMP8]], 1 4241 // CHECK3-IRBUILDER-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]] 4242 // CHECK3-IRBUILDER-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4243 // CHECK3-IRBUILDER: omp.inner.for.body: 4244 // CHECK3-IRBUILDER-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3 4245 // CHECK3-IRBUILDER-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4246 // CHECK3-IRBUILDER-NEXT: [[MUL:%.*]] = mul i32 [[TMP10]], 1 4247 // CHECK3-IRBUILDER-NEXT: [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]] 4248 // CHECK3-IRBUILDER-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3 4249 // CHECK3-IRBUILDER-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !3 4250 // CHECK3-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 4251 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 4252 // CHECK3-IRBUILDER-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 4253 // CHECK3-IRBUILDER-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3 4254 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 4255 // CHECK3-IRBUILDER: omp.inner.for.body.ordered.after: 4256 // CHECK3-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4257 // CHECK3-IRBUILDER: omp.body.continue: 4258 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4259 // CHECK3-IRBUILDER: omp.inner.for.inc: 4260 // CHECK3-IRBUILDER-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4261 // CHECK3-IRBUILDER-NEXT: [[ADD9:%.*]] = add i32 [[TMP12]], 1 4262 // CHECK3-IRBUILDER-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4263 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 4264 // CHECK3-IRBUILDER: omp.inner.for.end: 4265 // CHECK3-IRBUILDER-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4266 // CHECK3-IRBUILDER-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4267 // CHECK3-IRBUILDER-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4268 // CHECK3-IRBUILDER-NEXT: [[SUB10:%.*]] = sub i32 [[TMP14]], [[TMP15]] 4269 // CHECK3-IRBUILDER-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 4270 // CHECK3-IRBUILDER-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 4271 // CHECK3-IRBUILDER-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 4272 // CHECK3-IRBUILDER-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 4273 // CHECK3-IRBUILDER-NEXT: [[ADD15:%.*]] = add i32 [[TMP13]], [[MUL14]] 4274 // CHECK3-IRBUILDER-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 4275 // CHECK3-IRBUILDER-NEXT: br label [[SIMD_IF_END]] 4276 // CHECK3-IRBUILDER: simd.if.end: 4277 // CHECK3-IRBUILDER-NEXT: [[TMP16:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 4278 // CHECK3-IRBUILDER-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_18]], align 4 4279 // CHECK3-IRBUILDER-NEXT: [[TMP17:%.*]] = load i32, i32* [[UP_ADDR]], align 4 4280 // CHECK3-IRBUILDER-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_19]], align 4 4281 // CHECK3-IRBUILDER-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 4282 // CHECK3-IRBUILDER-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 4283 // CHECK3-IRBUILDER-NEXT: [[SUB21:%.*]] = sub i32 [[TMP18]], [[TMP19]] 4284 // CHECK3-IRBUILDER-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 4285 // CHECK3-IRBUILDER-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 4286 // CHECK3-IRBUILDER-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 4287 // CHECK3-IRBUILDER-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 4288 // CHECK3-IRBUILDER-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 4289 // CHECK3-IRBUILDER-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 4290 // CHECK3-IRBUILDER-NEXT: store i32 [[TMP20]], i32* [[I26]], align 4 4291 // CHECK3-IRBUILDER-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 4292 // CHECK3-IRBUILDER-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 4293 // CHECK3-IRBUILDER-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] 4294 // CHECK3-IRBUILDER-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 4295 // CHECK3-IRBUILDER: omp.precond.then: 4296 // CHECK3-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4297 // CHECK3-IRBUILDER-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 4298 // CHECK3-IRBUILDER-NEXT: store i32 [[TMP23]], i32* [[DOTOMP_UB]], align 4 4299 // CHECK3-IRBUILDER-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4300 // CHECK3-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4301 // CHECK3-IRBUILDER-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 4302 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12:[0-9]+]]) 4303 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 [[TMP24]], i32 1, i32 1) 4304 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4305 // CHECK3-IRBUILDER: omp.dispatch.cond: 4306 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM29:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 4307 // CHECK3-IRBUILDER-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM29]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 4308 // CHECK3-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP25]], 0 4309 // CHECK3-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4310 // CHECK3-IRBUILDER: omp.dispatch.body: 4311 // CHECK3-IRBUILDER-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4312 // CHECK3-IRBUILDER-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_IV16]], align 4 4313 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] 4314 // CHECK3-IRBUILDER: omp.inner.for.cond30: 4315 // CHECK3-IRBUILDER-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 4316 // CHECK3-IRBUILDER-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 4317 // CHECK3-IRBUILDER-NEXT: [[ADD31:%.*]] = add i32 [[TMP28]], 1 4318 // CHECK3-IRBUILDER-NEXT: [[CMP32:%.*]] = icmp ult i32 [[TMP27]], [[ADD31]] 4319 // CHECK3-IRBUILDER-NEXT: br i1 [[CMP32]], label [[OMP_INNER_FOR_BODY33:%.*]], label [[OMP_INNER_FOR_END42:%.*]] 4320 // CHECK3-IRBUILDER: omp.inner.for.body33: 4321 // CHECK3-IRBUILDER-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7 4322 // CHECK3-IRBUILDER-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 4323 // CHECK3-IRBUILDER-NEXT: [[MUL34:%.*]] = mul i32 [[TMP30]], 1 4324 // CHECK3-IRBUILDER-NEXT: [[ADD35:%.*]] = add i32 [[TMP29]], [[MUL34]] 4325 // CHECK3-IRBUILDER-NEXT: store i32 [[ADD35]], i32* [[I28]], align 4, !llvm.access.group !7 4326 // CHECK3-IRBUILDER-NEXT: [[TMP31:%.*]] = load i32, i32* [[I28]], align 4, !llvm.access.group !7 4327 // CHECK3-IRBUILDER-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 4328 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM36]] 4329 // CHECK3-IRBUILDER-NEXT: store float 0.000000e+00, float* [[ARRAYIDX37]], align 4, !llvm.access.group !7 4330 // CHECK3-IRBUILDER-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7 4331 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY33_ORDERED_AFTER:%.*]] 4332 // CHECK3-IRBUILDER: omp.inner.for.body33.ordered.after: 4333 // CHECK3-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE38:%.*]] 4334 // CHECK3-IRBUILDER: omp.body.continue38: 4335 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC39:%.*]] 4336 // CHECK3-IRBUILDER: omp.inner.for.inc39: 4337 // CHECK3-IRBUILDER-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 4338 // CHECK3-IRBUILDER-NEXT: [[ADD40:%.*]] = add i32 [[TMP32]], 1 4339 // CHECK3-IRBUILDER-NEXT: store i32 [[ADD40]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 4340 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 4341 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]]), !llvm.access.group !7 4342 // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]] 4343 // CHECK3-IRBUILDER: omp.inner.for.end42: 4344 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4345 // CHECK3-IRBUILDER: omp.dispatch.inc: 4346 // CHECK3-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 4347 // CHECK3-IRBUILDER: omp.dispatch.end: 4348 // CHECK3-IRBUILDER-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4349 // CHECK3-IRBUILDER-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 4350 // CHECK3-IRBUILDER-NEXT: br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4351 // CHECK3-IRBUILDER: .omp.final.then: 4352 // CHECK3-IRBUILDER-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 4353 // CHECK3-IRBUILDER-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 4354 // CHECK3-IRBUILDER-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 4355 // CHECK3-IRBUILDER-NEXT: [[SUB43:%.*]] = sub i32 [[TMP36]], [[TMP37]] 4356 // CHECK3-IRBUILDER-NEXT: [[SUB44:%.*]] = sub i32 [[SUB43]], 1 4357 // CHECK3-IRBUILDER-NEXT: [[ADD45:%.*]] = add i32 [[SUB44]], 1 4358 // CHECK3-IRBUILDER-NEXT: [[DIV46:%.*]] = udiv i32 [[ADD45]], 1 4359 // CHECK3-IRBUILDER-NEXT: [[MUL47:%.*]] = mul i32 [[DIV46]], 1 4360 // CHECK3-IRBUILDER-NEXT: [[ADD48:%.*]] = add i32 [[TMP35]], [[MUL47]] 4361 // CHECK3-IRBUILDER-NEXT: store i32 [[ADD48]], i32* [[I28]], align 4 4362 // CHECK3-IRBUILDER-NEXT: br label [[DOTOMP_FINAL_DONE]] 4363 // CHECK3-IRBUILDER: .omp.final.done: 4364 // CHECK3-IRBUILDER-NEXT: br label [[OMP_PRECOND_END]] 4365 // CHECK3-IRBUILDER: omp.precond.end: 4366 // CHECK3-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM49:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4367 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM49]]) 4368 // CHECK3-IRBUILDER-NEXT: ret void 4369 // 4370 // 4371 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt 4372 // CHECK3-IRBUILDER-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 4373 // CHECK3-IRBUILDER-NEXT: entry: 4374 // CHECK3-IRBUILDER-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 4375 // CHECK3-IRBUILDER-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 4376 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 4377 // CHECK3-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4378 // CHECK3-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 4379 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 4380 // CHECK3-IRBUILDER-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 4381 // CHECK3-IRBUILDER-NEXT: ret void 4382 // 4383 // 4384 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt.1 4385 // CHECK3-IRBUILDER-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 4386 // CHECK3-IRBUILDER-NEXT: entry: 4387 // CHECK3-IRBUILDER-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 4388 // CHECK3-IRBUILDER-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 4389 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 4390 // CHECK3-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4391 // CHECK3-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 4392 // CHECK3-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 4393 // CHECK3-IRBUILDER-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 4394 // CHECK3-IRBUILDER-NEXT: ret void 4395 // 4396 // 4397 // CHECK4-IRBUILDER-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 4398 // CHECK4-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 4399 // CHECK4-IRBUILDER-NEXT: entry: 4400 // CHECK4-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4401 // CHECK4-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4402 // CHECK4-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4403 // CHECK4-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4404 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4405 // CHECK4-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i32, align 4 4406 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4407 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4408 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4409 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4410 // CHECK4-IRBUILDER-NEXT: [[I:%.*]] = alloca i32, align 4 4411 // CHECK4-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4412 // CHECK4-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4413 // CHECK4-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4414 // CHECK4-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4415 // CHECK4-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4416 // CHECK4-IRBUILDER-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 4417 // CHECK4-IRBUILDER-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4418 // CHECK4-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4419 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 4420 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 4421 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4422 // CHECK4-IRBUILDER: omp.dispatch.cond: 4423 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 4424 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 4425 // CHECK4-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 4426 // CHECK4-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4427 // CHECK4-IRBUILDER: omp.dispatch.body: 4428 // CHECK4-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4429 // CHECK4-IRBUILDER-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 4430 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4431 // CHECK4-IRBUILDER: omp.inner.for.cond: 4432 // CHECK4-IRBUILDER-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4433 // CHECK4-IRBUILDER-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4434 // CHECK4-IRBUILDER-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 4435 // CHECK4-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4436 // CHECK4-IRBUILDER: omp.inner.for.body: 4437 // CHECK4-IRBUILDER-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4438 // CHECK4-IRBUILDER-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 4439 // CHECK4-IRBUILDER-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 4440 // CHECK4-IRBUILDER-NEXT: store i32 [[SUB]], i32* [[I]], align 4 4441 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4442 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) 4443 // CHECK4-IRBUILDER-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8 4444 // CHECK4-IRBUILDER-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 4445 // CHECK4-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 4446 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]] 4447 // CHECK4-IRBUILDER-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4 4448 // CHECK4-IRBUILDER-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8 4449 // CHECK4-IRBUILDER-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 4450 // CHECK4-IRBUILDER-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 4451 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM3]] 4452 // CHECK4-IRBUILDER-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX4]], align 4 4453 // CHECK4-IRBUILDER-NEXT: [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]] 4454 // CHECK4-IRBUILDER-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8 4455 // CHECK4-IRBUILDER-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 4456 // CHECK4-IRBUILDER-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP12]] to i64 4457 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM6]] 4458 // CHECK4-IRBUILDER-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX7]], align 4 4459 // CHECK4-IRBUILDER-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP13]] 4460 // CHECK4-IRBUILDER-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8 4461 // CHECK4-IRBUILDER-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 4462 // CHECK4-IRBUILDER-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64 4463 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM9]] 4464 // CHECK4-IRBUILDER-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 4465 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 4466 // CHECK4-IRBUILDER: omp.inner.for.body.ordered.after: 4467 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) 4468 // CHECK4-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4469 // CHECK4-IRBUILDER: omp.body.continue: 4470 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4471 // CHECK4-IRBUILDER: omp.inner.for.inc: 4472 // CHECK4-IRBUILDER-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4473 // CHECK4-IRBUILDER-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 4474 // CHECK4-IRBUILDER-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 4475 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 4476 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) 4477 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 4478 // CHECK4-IRBUILDER: omp.inner.for.end: 4479 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4480 // CHECK4-IRBUILDER: omp.dispatch.inc: 4481 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 4482 // CHECK4-IRBUILDER: omp.dispatch.end: 4483 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4484 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM12]]) 4485 // CHECK4-IRBUILDER-NEXT: ret void 4486 // 4487 // 4488 // CHECK4-IRBUILDER-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 4489 // CHECK4-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4490 // CHECK4-IRBUILDER-NEXT: entry: 4491 // CHECK4-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4492 // CHECK4-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4493 // CHECK4-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4494 // CHECK4-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4495 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4496 // CHECK4-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i64, align 8 4497 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4498 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4499 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4500 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4501 // CHECK4-IRBUILDER-NEXT: [[I:%.*]] = alloca i64, align 8 4502 // CHECK4-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4503 // CHECK4-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4504 // CHECK4-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4505 // CHECK4-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4506 // CHECK4-IRBUILDER-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4507 // CHECK4-IRBUILDER-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 4508 // CHECK4-IRBUILDER-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4509 // CHECK4-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4510 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6:[0-9]+]]) 4511 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 67, i64 0, i64 16908287, i64 1, i64 1) 4512 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4513 // CHECK4-IRBUILDER: omp.dispatch.cond: 4514 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 4515 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 4516 // CHECK4-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 4517 // CHECK4-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4518 // CHECK4-IRBUILDER: omp.dispatch.body: 4519 // CHECK4-IRBUILDER-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4520 // CHECK4-IRBUILDER-NEXT: store i64 [[TMP1]], i64* [[DOTOMP_IV]], align 8 4521 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4522 // CHECK4-IRBUILDER: omp.inner.for.cond: 4523 // CHECK4-IRBUILDER-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4524 // CHECK4-IRBUILDER-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4525 // CHECK4-IRBUILDER-NEXT: [[ADD:%.*]] = add i64 [[TMP3]], 1 4526 // CHECK4-IRBUILDER-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP2]], [[ADD]] 4527 // CHECK4-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4528 // CHECK4-IRBUILDER: omp.inner.for.body: 4529 // CHECK4-IRBUILDER-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4530 // CHECK4-IRBUILDER-NEXT: [[MUL:%.*]] = mul i64 [[TMP4]], 127 4531 // CHECK4-IRBUILDER-NEXT: [[ADD2:%.*]] = add i64 131071, [[MUL]] 4532 // CHECK4-IRBUILDER-NEXT: store i64 [[ADD2]], i64* [[I]], align 8 4533 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4534 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) 4535 // CHECK4-IRBUILDER-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8 4536 // CHECK4-IRBUILDER-NEXT: [[TMP6:%.*]] = load i64, i64* [[I]], align 8 4537 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[TMP6]] 4538 // CHECK4-IRBUILDER-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4 4539 // CHECK4-IRBUILDER-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8 4540 // CHECK4-IRBUILDER-NEXT: [[TMP9:%.*]] = load i64, i64* [[I]], align 8 4541 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[TMP9]] 4542 // CHECK4-IRBUILDER-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX4]], align 4 4543 // CHECK4-IRBUILDER-NEXT: [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]] 4544 // CHECK4-IRBUILDER-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8 4545 // CHECK4-IRBUILDER-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 4546 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 4547 // CHECK4-IRBUILDER-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX6]], align 4 4548 // CHECK4-IRBUILDER-NEXT: [[MUL7:%.*]] = fmul float [[MUL5]], [[TMP13]] 4549 // CHECK4-IRBUILDER-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8 4550 // CHECK4-IRBUILDER-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8 4551 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 4552 // CHECK4-IRBUILDER-NEXT: store float [[MUL7]], float* [[ARRAYIDX8]], align 4 4553 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 4554 // CHECK4-IRBUILDER: omp.inner.for.body.ordered.after: 4555 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) 4556 // CHECK4-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4557 // CHECK4-IRBUILDER: omp.body.continue: 4558 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4559 // CHECK4-IRBUILDER: omp.inner.for.inc: 4560 // CHECK4-IRBUILDER-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4561 // CHECK4-IRBUILDER-NEXT: [[ADD9:%.*]] = add i64 [[TMP16]], 1 4562 // CHECK4-IRBUILDER-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8 4563 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 4564 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]]) 4565 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 4566 // CHECK4-IRBUILDER: omp.inner.for.end: 4567 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4568 // CHECK4-IRBUILDER: omp.dispatch.inc: 4569 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 4570 // CHECK4-IRBUILDER: omp.dispatch.end: 4571 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4572 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM11]]) 4573 // CHECK4-IRBUILDER-NEXT: ret void 4574 // 4575 // 4576 // CHECK4-IRBUILDER-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 4577 // CHECK4-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4578 // CHECK4-IRBUILDER-NEXT: entry: 4579 // CHECK4-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4580 // CHECK4-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4581 // CHECK4-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4582 // CHECK4-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4583 // CHECK4-IRBUILDER-NEXT: [[X:%.*]] = alloca i32, align 4 4584 // CHECK4-IRBUILDER-NEXT: [[Y:%.*]] = alloca i32, align 4 4585 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4586 // CHECK4-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i8, align 1 4587 // CHECK4-IRBUILDER-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4588 // CHECK4-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4589 // CHECK4-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 4590 // CHECK4-IRBUILDER-NEXT: [[I:%.*]] = alloca i8, align 1 4591 // CHECK4-IRBUILDER-NEXT: [[X6:%.*]] = alloca i32, align 4 4592 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4593 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4594 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4595 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4596 // CHECK4-IRBUILDER-NEXT: [[I8:%.*]] = alloca i8, align 1 4597 // CHECK4-IRBUILDER-NEXT: [[X9:%.*]] = alloca i32, align 4 4598 // CHECK4-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4599 // CHECK4-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4600 // CHECK4-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4601 // CHECK4-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4602 // CHECK4-IRBUILDER-NEXT: store i32 0, i32* [[X]], align 4 4603 // CHECK4-IRBUILDER-NEXT: store i32 0, i32* [[Y]], align 4 4604 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 4605 // CHECK4-IRBUILDER-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 4606 // CHECK4-IRBUILDER-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 4607 // CHECK4-IRBUILDER-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4608 // CHECK4-IRBUILDER-NEXT: [[CONV3:%.*]] = sext i8 [[TMP1]] to i32 4609 // CHECK4-IRBUILDER-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 4610 // CHECK4-IRBUILDER-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 4611 // CHECK4-IRBUILDER-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4612 // CHECK4-IRBUILDER-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 4613 // CHECK4-IRBUILDER-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 4614 // CHECK4-IRBUILDER-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 4615 // CHECK4-IRBUILDER-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 4616 // CHECK4-IRBUILDER-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4617 // CHECK4-IRBUILDER-NEXT: store i8 [[TMP2]], i8* [[I]], align 1 4618 // CHECK4-IRBUILDER-NEXT: store i32 11, i32* [[X6]], align 4 4619 // CHECK4-IRBUILDER-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4620 // CHECK4-IRBUILDER-NEXT: [[CONV7:%.*]] = sext i8 [[TMP3]] to i32 4621 // CHECK4-IRBUILDER-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 4622 // CHECK4-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 4623 // CHECK4-IRBUILDER: omp.precond.then: 4624 // CHECK4-IRBUILDER-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4625 // CHECK4-IRBUILDER-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 4626 // CHECK4-IRBUILDER-NEXT: store i64 [[TMP4]], i64* [[DOTOMP_UB]], align 8 4627 // CHECK4-IRBUILDER-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4628 // CHECK4-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4629 // CHECK4-IRBUILDER-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 4630 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8:[0-9]+]]) 4631 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 70, i64 0, i64 [[TMP5]], i64 1, i64 1) 4632 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4633 // CHECK4-IRBUILDER: omp.dispatch.cond: 4634 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 4635 // CHECK4-IRBUILDER-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 4636 // CHECK4-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 4637 // CHECK4-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4638 // CHECK4-IRBUILDER: omp.dispatch.body: 4639 // CHECK4-IRBUILDER-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4640 // CHECK4-IRBUILDER-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 4641 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4642 // CHECK4-IRBUILDER: omp.inner.for.cond: 4643 // CHECK4-IRBUILDER-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4644 // CHECK4-IRBUILDER-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4645 // CHECK4-IRBUILDER-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP8]], [[TMP9]] 4646 // CHECK4-IRBUILDER-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4647 // CHECK4-IRBUILDER: omp.inner.for.body: 4648 // CHECK4-IRBUILDER-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4649 // CHECK4-IRBUILDER-NEXT: [[CONV12:%.*]] = sext i8 [[TMP10]] to i64 4650 // CHECK4-IRBUILDER-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4651 // CHECK4-IRBUILDER-NEXT: [[DIV13:%.*]] = sdiv i64 [[TMP11]], 11 4652 // CHECK4-IRBUILDER-NEXT: [[MUL14:%.*]] = mul nsw i64 [[DIV13]], 1 4653 // CHECK4-IRBUILDER-NEXT: [[ADD15:%.*]] = add nsw i64 [[CONV12]], [[MUL14]] 4654 // CHECK4-IRBUILDER-NEXT: [[CONV16:%.*]] = trunc i64 [[ADD15]] to i8 4655 // CHECK4-IRBUILDER-NEXT: store i8 [[CONV16]], i8* [[I8]], align 1 4656 // CHECK4-IRBUILDER-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4657 // CHECK4-IRBUILDER-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4658 // CHECK4-IRBUILDER-NEXT: [[DIV17:%.*]] = sdiv i64 [[TMP13]], 11 4659 // CHECK4-IRBUILDER-NEXT: [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 11 4660 // CHECK4-IRBUILDER-NEXT: [[SUB19:%.*]] = sub nsw i64 [[TMP12]], [[MUL18]] 4661 // CHECK4-IRBUILDER-NEXT: [[MUL20:%.*]] = mul nsw i64 [[SUB19]], 1 4662 // CHECK4-IRBUILDER-NEXT: [[SUB21:%.*]] = sub nsw i64 11, [[MUL20]] 4663 // CHECK4-IRBUILDER-NEXT: [[CONV22:%.*]] = trunc i64 [[SUB21]] to i32 4664 // CHECK4-IRBUILDER-NEXT: store i32 [[CONV22]], i32* [[X9]], align 4 4665 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4666 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]]) 4667 // CHECK4-IRBUILDER-NEXT: [[TMP14:%.*]] = load float*, float** [[B_ADDR]], align 8 4668 // CHECK4-IRBUILDER-NEXT: [[TMP15:%.*]] = load i8, i8* [[I8]], align 1 4669 // CHECK4-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP15]] to i64 4670 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 4671 // CHECK4-IRBUILDER-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4 4672 // CHECK4-IRBUILDER-NEXT: [[TMP17:%.*]] = load float*, float** [[C_ADDR]], align 8 4673 // CHECK4-IRBUILDER-NEXT: [[TMP18:%.*]] = load i8, i8* [[I8]], align 1 4674 // CHECK4-IRBUILDER-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP18]] to i64 4675 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM24]] 4676 // CHECK4-IRBUILDER-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX25]], align 4 4677 // CHECK4-IRBUILDER-NEXT: [[MUL26:%.*]] = fmul float [[TMP16]], [[TMP19]] 4678 // CHECK4-IRBUILDER-NEXT: [[TMP20:%.*]] = load float*, float** [[D_ADDR]], align 8 4679 // CHECK4-IRBUILDER-NEXT: [[TMP21:%.*]] = load i8, i8* [[I8]], align 1 4680 // CHECK4-IRBUILDER-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP21]] to i64 4681 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM27]] 4682 // CHECK4-IRBUILDER-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX28]], align 4 4683 // CHECK4-IRBUILDER-NEXT: [[MUL29:%.*]] = fmul float [[MUL26]], [[TMP22]] 4684 // CHECK4-IRBUILDER-NEXT: [[TMP23:%.*]] = load float*, float** [[A_ADDR]], align 8 4685 // CHECK4-IRBUILDER-NEXT: [[TMP24:%.*]] = load i8, i8* [[I8]], align 1 4686 // CHECK4-IRBUILDER-NEXT: [[IDXPROM30:%.*]] = sext i8 [[TMP24]] to i64 4687 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM30]] 4688 // CHECK4-IRBUILDER-NEXT: store float [[MUL29]], float* [[ARRAYIDX31]], align 4 4689 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 4690 // CHECK4-IRBUILDER: omp.inner.for.body.ordered.after: 4691 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]]) 4692 // CHECK4-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4693 // CHECK4-IRBUILDER: omp.body.continue: 4694 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4695 // CHECK4-IRBUILDER: omp.inner.for.inc: 4696 // CHECK4-IRBUILDER-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4697 // CHECK4-IRBUILDER-NEXT: [[ADD32:%.*]] = add nsw i64 [[TMP25]], 1 4698 // CHECK4-IRBUILDER-NEXT: store i64 [[ADD32]], i64* [[DOTOMP_IV]], align 8 4699 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM33:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 4700 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM33]]) 4701 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 4702 // CHECK4-IRBUILDER: omp.inner.for.end: 4703 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4704 // CHECK4-IRBUILDER: omp.dispatch.inc: 4705 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 4706 // CHECK4-IRBUILDER: omp.dispatch.end: 4707 // CHECK4-IRBUILDER-NEXT: br label [[OMP_PRECOND_END]] 4708 // CHECK4-IRBUILDER: omp.precond.end: 4709 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM34:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4710 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM34]]) 4711 // CHECK4-IRBUILDER-NEXT: ret void 4712 // 4713 // 4714 // CHECK4-IRBUILDER-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 4715 // CHECK4-IRBUILDER-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4716 // CHECK4-IRBUILDER-NEXT: entry: 4717 // CHECK4-IRBUILDER-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4718 // CHECK4-IRBUILDER-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4719 // CHECK4-IRBUILDER-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4720 // CHECK4-IRBUILDER-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4721 // CHECK4-IRBUILDER-NEXT: [[X:%.*]] = alloca i32, align 4 4722 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4723 // CHECK4-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i8, align 1 4724 // CHECK4-IRBUILDER-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4725 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4726 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4727 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4728 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4729 // CHECK4-IRBUILDER-NEXT: [[I:%.*]] = alloca i8, align 1 4730 // CHECK4-IRBUILDER-NEXT: [[X2:%.*]] = alloca i32, align 4 4731 // CHECK4-IRBUILDER-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4732 // CHECK4-IRBUILDER-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4733 // CHECK4-IRBUILDER-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4734 // CHECK4-IRBUILDER-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4735 // CHECK4-IRBUILDER-NEXT: store i32 0, i32* [[X]], align 4 4736 // CHECK4-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4737 // CHECK4-IRBUILDER-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 4738 // CHECK4-IRBUILDER-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4739 // CHECK4-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4740 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10:[0-9]+]]) 4741 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 69, i32 0, i32 199, i32 1, i32 1) 4742 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4743 // CHECK4-IRBUILDER: omp.dispatch.cond: 4744 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 4745 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 4746 // CHECK4-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 4747 // CHECK4-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4748 // CHECK4-IRBUILDER: omp.dispatch.body: 4749 // CHECK4-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4750 // CHECK4-IRBUILDER-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 4751 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4752 // CHECK4-IRBUILDER: omp.inner.for.cond: 4753 // CHECK4-IRBUILDER-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4754 // CHECK4-IRBUILDER-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4755 // CHECK4-IRBUILDER-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 4756 // CHECK4-IRBUILDER-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4757 // CHECK4-IRBUILDER: omp.inner.for.body: 4758 // CHECK4-IRBUILDER-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4759 // CHECK4-IRBUILDER-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 20 4760 // CHECK4-IRBUILDER-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 4761 // CHECK4-IRBUILDER-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 4762 // CHECK4-IRBUILDER-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 4763 // CHECK4-IRBUILDER-NEXT: store i8 [[CONV]], i8* [[I]], align 1 4764 // CHECK4-IRBUILDER-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4765 // CHECK4-IRBUILDER-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4766 // CHECK4-IRBUILDER-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP6]], 20 4767 // CHECK4-IRBUILDER-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 20 4768 // CHECK4-IRBUILDER-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], [[MUL5]] 4769 // CHECK4-IRBUILDER-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 4770 // CHECK4-IRBUILDER-NEXT: [[ADD7:%.*]] = add nsw i32 -10, [[MUL6]] 4771 // CHECK4-IRBUILDER-NEXT: store i32 [[ADD7]], i32* [[X2]], align 4 4772 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM8:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4773 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]]) 4774 // CHECK4-IRBUILDER-NEXT: [[TMP7:%.*]] = load float*, float** [[B_ADDR]], align 8 4775 // CHECK4-IRBUILDER-NEXT: [[TMP8:%.*]] = load i8, i8* [[I]], align 1 4776 // CHECK4-IRBUILDER-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP8]] to i64 4777 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM]] 4778 // CHECK4-IRBUILDER-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 4779 // CHECK4-IRBUILDER-NEXT: [[TMP10:%.*]] = load float*, float** [[C_ADDR]], align 8 4780 // CHECK4-IRBUILDER-NEXT: [[TMP11:%.*]] = load i8, i8* [[I]], align 1 4781 // CHECK4-IRBUILDER-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP11]] to i64 4782 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM9]] 4783 // CHECK4-IRBUILDER-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX10]], align 4 4784 // CHECK4-IRBUILDER-NEXT: [[MUL11:%.*]] = fmul float [[TMP9]], [[TMP12]] 4785 // CHECK4-IRBUILDER-NEXT: [[TMP13:%.*]] = load float*, float** [[D_ADDR]], align 8 4786 // CHECK4-IRBUILDER-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 4787 // CHECK4-IRBUILDER-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP14]] to i64 4788 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM12]] 4789 // CHECK4-IRBUILDER-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX13]], align 4 4790 // CHECK4-IRBUILDER-NEXT: [[MUL14:%.*]] = fmul float [[MUL11]], [[TMP15]] 4791 // CHECK4-IRBUILDER-NEXT: [[TMP16:%.*]] = load float*, float** [[A_ADDR]], align 8 4792 // CHECK4-IRBUILDER-NEXT: [[TMP17:%.*]] = load i8, i8* [[I]], align 1 4793 // CHECK4-IRBUILDER-NEXT: [[IDXPROM15:%.*]] = zext i8 [[TMP17]] to i64 4794 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM15]] 4795 // CHECK4-IRBUILDER-NEXT: store float [[MUL14]], float* [[ARRAYIDX16]], align 4 4796 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 4797 // CHECK4-IRBUILDER: omp.inner.for.body.ordered.after: 4798 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]]) 4799 // CHECK4-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4800 // CHECK4-IRBUILDER: omp.body.continue: 4801 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4802 // CHECK4-IRBUILDER: omp.inner.for.inc: 4803 // CHECK4-IRBUILDER-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4804 // CHECK4-IRBUILDER-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP18]], 1 4805 // CHECK4-IRBUILDER-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4 4806 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 4807 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM18]]) 4808 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]] 4809 // CHECK4-IRBUILDER: omp.inner.for.end: 4810 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4811 // CHECK4-IRBUILDER: omp.dispatch.inc: 4812 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 4813 // CHECK4-IRBUILDER: omp.dispatch.end: 4814 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM19:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4815 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM19]]) 4816 // CHECK4-IRBUILDER-NEXT: ret void 4817 // 4818 // 4819 // CHECK4-IRBUILDER-LABEL: define {{[^@]+}}@_Z8foo_simdii 4820 // CHECK4-IRBUILDER-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { 4821 // CHECK4-IRBUILDER-NEXT: entry: 4822 // CHECK4-IRBUILDER-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 4823 // CHECK4-IRBUILDER-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 4824 // CHECK4-IRBUILDER-NEXT: [[TMP:%.*]] = alloca i32, align 4 4825 // CHECK4-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4826 // CHECK4-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4827 // CHECK4-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 4828 // CHECK4-IRBUILDER-NEXT: [[I:%.*]] = alloca i32, align 4 4829 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4830 // CHECK4-IRBUILDER-NEXT: [[I5:%.*]] = alloca i32, align 4 4831 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 4832 // CHECK4-IRBUILDER-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 4833 // CHECK4-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 4834 // CHECK4-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 4835 // CHECK4-IRBUILDER-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 4836 // CHECK4-IRBUILDER-NEXT: [[I26:%.*]] = alloca i32, align 4 4837 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4838 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4839 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4840 // CHECK4-IRBUILDER-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4841 // CHECK4-IRBUILDER-NEXT: [[I28:%.*]] = alloca i32, align 4 4842 // CHECK4-IRBUILDER-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 4843 // CHECK4-IRBUILDER-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 4844 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 4845 // CHECK4-IRBUILDER-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 4846 // CHECK4-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[UP_ADDR]], align 4 4847 // CHECK4-IRBUILDER-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4848 // CHECK4-IRBUILDER-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4849 // CHECK4-IRBUILDER-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4850 // CHECK4-IRBUILDER-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 4851 // CHECK4-IRBUILDER-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 4852 // CHECK4-IRBUILDER-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 4853 // CHECK4-IRBUILDER-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4854 // CHECK4-IRBUILDER-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 4855 // CHECK4-IRBUILDER-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 4856 // CHECK4-IRBUILDER-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4857 // CHECK4-IRBUILDER-NEXT: store i32 [[TMP4]], i32* [[I]], align 4 4858 // CHECK4-IRBUILDER-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4859 // CHECK4-IRBUILDER-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4860 // CHECK4-IRBUILDER-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] 4861 // CHECK4-IRBUILDER-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 4862 // CHECK4-IRBUILDER: simd.if.then: 4863 // CHECK4-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 4864 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4865 // CHECK4-IRBUILDER: omp.inner.for.cond: 4866 // CHECK4-IRBUILDER-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4867 // CHECK4-IRBUILDER-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 4868 // CHECK4-IRBUILDER-NEXT: [[ADD6:%.*]] = add i32 [[TMP8]], 1 4869 // CHECK4-IRBUILDER-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]] 4870 // CHECK4-IRBUILDER-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4871 // CHECK4-IRBUILDER: omp.inner.for.body: 4872 // CHECK4-IRBUILDER-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3 4873 // CHECK4-IRBUILDER-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4874 // CHECK4-IRBUILDER-NEXT: [[MUL:%.*]] = mul i32 [[TMP10]], 1 4875 // CHECK4-IRBUILDER-NEXT: [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]] 4876 // CHECK4-IRBUILDER-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3 4877 // CHECK4-IRBUILDER-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !3 4878 // CHECK4-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 4879 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 4880 // CHECK4-IRBUILDER-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 4881 // CHECK4-IRBUILDER-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3 4882 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] 4883 // CHECK4-IRBUILDER: omp.inner.for.body.ordered.after: 4884 // CHECK4-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4885 // CHECK4-IRBUILDER: omp.body.continue: 4886 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4887 // CHECK4-IRBUILDER: omp.inner.for.inc: 4888 // CHECK4-IRBUILDER-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4889 // CHECK4-IRBUILDER-NEXT: [[ADD9:%.*]] = add i32 [[TMP12]], 1 4890 // CHECK4-IRBUILDER-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4891 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 4892 // CHECK4-IRBUILDER: omp.inner.for.end: 4893 // CHECK4-IRBUILDER-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4894 // CHECK4-IRBUILDER-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4895 // CHECK4-IRBUILDER-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4896 // CHECK4-IRBUILDER-NEXT: [[SUB10:%.*]] = sub i32 [[TMP14]], [[TMP15]] 4897 // CHECK4-IRBUILDER-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 4898 // CHECK4-IRBUILDER-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 4899 // CHECK4-IRBUILDER-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 4900 // CHECK4-IRBUILDER-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 4901 // CHECK4-IRBUILDER-NEXT: [[ADD15:%.*]] = add i32 [[TMP13]], [[MUL14]] 4902 // CHECK4-IRBUILDER-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 4903 // CHECK4-IRBUILDER-NEXT: br label [[SIMD_IF_END]] 4904 // CHECK4-IRBUILDER: simd.if.end: 4905 // CHECK4-IRBUILDER-NEXT: [[TMP16:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 4906 // CHECK4-IRBUILDER-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_18]], align 4 4907 // CHECK4-IRBUILDER-NEXT: [[TMP17:%.*]] = load i32, i32* [[UP_ADDR]], align 4 4908 // CHECK4-IRBUILDER-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_19]], align 4 4909 // CHECK4-IRBUILDER-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 4910 // CHECK4-IRBUILDER-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 4911 // CHECK4-IRBUILDER-NEXT: [[SUB21:%.*]] = sub i32 [[TMP18]], [[TMP19]] 4912 // CHECK4-IRBUILDER-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 4913 // CHECK4-IRBUILDER-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 4914 // CHECK4-IRBUILDER-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 4915 // CHECK4-IRBUILDER-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 4916 // CHECK4-IRBUILDER-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 4917 // CHECK4-IRBUILDER-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 4918 // CHECK4-IRBUILDER-NEXT: store i32 [[TMP20]], i32* [[I26]], align 4 4919 // CHECK4-IRBUILDER-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 4920 // CHECK4-IRBUILDER-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 4921 // CHECK4-IRBUILDER-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] 4922 // CHECK4-IRBUILDER-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 4923 // CHECK4-IRBUILDER: omp.precond.then: 4924 // CHECK4-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4925 // CHECK4-IRBUILDER-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 4926 // CHECK4-IRBUILDER-NEXT: store i32 [[TMP23]], i32* [[DOTOMP_UB]], align 4 4927 // CHECK4-IRBUILDER-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4928 // CHECK4-IRBUILDER-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4929 // CHECK4-IRBUILDER-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 4930 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12:[0-9]+]]) 4931 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 [[TMP24]], i32 1, i32 1) 4932 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4933 // CHECK4-IRBUILDER: omp.dispatch.cond: 4934 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM29:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 4935 // CHECK4-IRBUILDER-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM29]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 4936 // CHECK4-IRBUILDER-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP25]], 0 4937 // CHECK4-IRBUILDER-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4938 // CHECK4-IRBUILDER: omp.dispatch.body: 4939 // CHECK4-IRBUILDER-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4940 // CHECK4-IRBUILDER-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_IV16]], align 4 4941 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] 4942 // CHECK4-IRBUILDER: omp.inner.for.cond30: 4943 // CHECK4-IRBUILDER-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 4944 // CHECK4-IRBUILDER-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 4945 // CHECK4-IRBUILDER-NEXT: [[ADD31:%.*]] = add i32 [[TMP28]], 1 4946 // CHECK4-IRBUILDER-NEXT: [[CMP32:%.*]] = icmp ult i32 [[TMP27]], [[ADD31]] 4947 // CHECK4-IRBUILDER-NEXT: br i1 [[CMP32]], label [[OMP_INNER_FOR_BODY33:%.*]], label [[OMP_INNER_FOR_END42:%.*]] 4948 // CHECK4-IRBUILDER: omp.inner.for.body33: 4949 // CHECK4-IRBUILDER-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7 4950 // CHECK4-IRBUILDER-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 4951 // CHECK4-IRBUILDER-NEXT: [[MUL34:%.*]] = mul i32 [[TMP30]], 1 4952 // CHECK4-IRBUILDER-NEXT: [[ADD35:%.*]] = add i32 [[TMP29]], [[MUL34]] 4953 // CHECK4-IRBUILDER-NEXT: store i32 [[ADD35]], i32* [[I28]], align 4, !llvm.access.group !7 4954 // CHECK4-IRBUILDER-NEXT: [[TMP31:%.*]] = load i32, i32* [[I28]], align 4, !llvm.access.group !7 4955 // CHECK4-IRBUILDER-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 4956 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM36]] 4957 // CHECK4-IRBUILDER-NEXT: store float 0.000000e+00, float* [[ARRAYIDX37]], align 4, !llvm.access.group !7 4958 // CHECK4-IRBUILDER-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7 4959 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY33_ORDERED_AFTER:%.*]] 4960 // CHECK4-IRBUILDER: omp.inner.for.body33.ordered.after: 4961 // CHECK4-IRBUILDER-NEXT: br label [[OMP_BODY_CONTINUE38:%.*]] 4962 // CHECK4-IRBUILDER: omp.body.continue38: 4963 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_INC39:%.*]] 4964 // CHECK4-IRBUILDER: omp.inner.for.inc39: 4965 // CHECK4-IRBUILDER-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 4966 // CHECK4-IRBUILDER-NEXT: [[ADD40:%.*]] = add i32 [[TMP32]], 1 4967 // CHECK4-IRBUILDER-NEXT: store i32 [[ADD40]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 4968 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 4969 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]]), !llvm.access.group !7 4970 // CHECK4-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]] 4971 // CHECK4-IRBUILDER: omp.inner.for.end42: 4972 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4973 // CHECK4-IRBUILDER: omp.dispatch.inc: 4974 // CHECK4-IRBUILDER-NEXT: br label [[OMP_DISPATCH_COND]] 4975 // CHECK4-IRBUILDER: omp.dispatch.end: 4976 // CHECK4-IRBUILDER-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4977 // CHECK4-IRBUILDER-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 4978 // CHECK4-IRBUILDER-NEXT: br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4979 // CHECK4-IRBUILDER: .omp.final.then: 4980 // CHECK4-IRBUILDER-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 4981 // CHECK4-IRBUILDER-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 4982 // CHECK4-IRBUILDER-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 4983 // CHECK4-IRBUILDER-NEXT: [[SUB43:%.*]] = sub i32 [[TMP36]], [[TMP37]] 4984 // CHECK4-IRBUILDER-NEXT: [[SUB44:%.*]] = sub i32 [[SUB43]], 1 4985 // CHECK4-IRBUILDER-NEXT: [[ADD45:%.*]] = add i32 [[SUB44]], 1 4986 // CHECK4-IRBUILDER-NEXT: [[DIV46:%.*]] = udiv i32 [[ADD45]], 1 4987 // CHECK4-IRBUILDER-NEXT: [[MUL47:%.*]] = mul i32 [[DIV46]], 1 4988 // CHECK4-IRBUILDER-NEXT: [[ADD48:%.*]] = add i32 [[TMP35]], [[MUL47]] 4989 // CHECK4-IRBUILDER-NEXT: store i32 [[ADD48]], i32* [[I28]], align 4 4990 // CHECK4-IRBUILDER-NEXT: br label [[DOTOMP_FINAL_DONE]] 4991 // CHECK4-IRBUILDER: .omp.final.done: 4992 // CHECK4-IRBUILDER-NEXT: br label [[OMP_PRECOND_END]] 4993 // CHECK4-IRBUILDER: omp.precond.end: 4994 // CHECK4-IRBUILDER-NEXT: [[OMP_GLOBAL_THREAD_NUM49:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4995 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM49]]) 4996 // CHECK4-IRBUILDER-NEXT: ret void 4997 // 4998 // 4999 // CHECK4-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt 5000 // CHECK4-IRBUILDER-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 5001 // CHECK4-IRBUILDER-NEXT: entry: 5002 // CHECK4-IRBUILDER-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 5003 // CHECK4-IRBUILDER-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 5004 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 5005 // CHECK4-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5006 // CHECK4-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 5007 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 5008 // CHECK4-IRBUILDER-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 5009 // CHECK4-IRBUILDER-NEXT: ret void 5010 // 5011 // 5012 // CHECK4-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt.1 5013 // CHECK4-IRBUILDER-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 5014 // CHECK4-IRBUILDER-NEXT: entry: 5015 // CHECK4-IRBUILDER-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 5016 // CHECK4-IRBUILDER-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 5017 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 5018 // CHECK4-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5019 // CHECK4-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 5020 // CHECK4-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 5021 // CHECK4-IRBUILDER-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 5022 // CHECK4-IRBUILDER-NEXT: ret void 5023 // 5024 // 5025 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 5026 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 5027 // CHECK5-NEXT: entry: 5028 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5029 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5030 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5031 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5032 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 5033 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5034 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5035 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5036 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5037 // CHECK5-NEXT: store i32 32000000, i32* [[I]], align 4 5038 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 5039 // CHECK5: for.cond: 5040 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 5041 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 5042 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 5043 // CHECK5: for.body: 5044 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 5045 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 5046 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 5047 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 5048 // CHECK5-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 5049 // CHECK5-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 5050 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 5051 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 5052 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 5053 // CHECK5-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 5054 // CHECK5-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 5055 // CHECK5-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 5056 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 5057 // CHECK5-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 5058 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 5059 // CHECK5-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 5060 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 5061 // CHECK5-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 5062 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 5063 // CHECK5-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 5064 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 5065 // CHECK5-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 5066 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 5067 // CHECK5: for.inc: 5068 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 5069 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 5070 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 5071 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 5072 // CHECK5: for.end: 5073 // CHECK5-NEXT: ret void 5074 // 5075 // 5076 // CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 5077 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 5078 // CHECK5-NEXT: entry: 5079 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5080 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5081 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5082 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5083 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 5084 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5085 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5086 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5087 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5088 // CHECK5-NEXT: store i64 131071, i64* [[I]], align 8 5089 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 5090 // CHECK5: for.cond: 5091 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 5092 // CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 5093 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 5094 // CHECK5: for.body: 5095 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 5096 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 5097 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] 5098 // CHECK5-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 5099 // CHECK5-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 5100 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 5101 // CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] 5102 // CHECK5-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 5103 // CHECK5-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 5104 // CHECK5-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 5105 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 5106 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] 5107 // CHECK5-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 5108 // CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 5109 // CHECK5-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 5110 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 5111 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] 5112 // CHECK5-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 5113 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 5114 // CHECK5: for.inc: 5115 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 5116 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 5117 // CHECK5-NEXT: store i64 [[ADD]], i64* [[I]], align 8 5118 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 5119 // CHECK5: for.end: 5120 // CHECK5-NEXT: ret void 5121 // 5122 // 5123 // CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 5124 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 5125 // CHECK5-NEXT: entry: 5126 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5127 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5128 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5129 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5130 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 5131 // CHECK5-NEXT: [[Y:%.*]] = alloca i32, align 4 5132 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 5133 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5134 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5135 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5136 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5137 // CHECK5-NEXT: store i32 0, i32* [[X]], align 4 5138 // CHECK5-NEXT: store i32 0, i32* [[Y]], align 4 5139 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 5140 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 5141 // CHECK5-NEXT: store i8 [[CONV]], i8* [[I]], align 1 5142 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 5143 // CHECK5: for.cond: 5144 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 5145 // CHECK5-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32 5146 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57 5147 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 5148 // CHECK5: for.body: 5149 // CHECK5-NEXT: store i32 11, i32* [[X]], align 4 5150 // CHECK5-NEXT: br label [[FOR_COND2:%.*]] 5151 // CHECK5: for.cond2: 5152 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4 5153 // CHECK5-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0 5154 // CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] 5155 // CHECK5: for.body4: 5156 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8 5157 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1 5158 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64 5159 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]] 5160 // CHECK5-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4 5161 // CHECK5-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8 5162 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1 5163 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64 5164 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]] 5165 // CHECK5-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4 5166 // CHECK5-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]] 5167 // CHECK5-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8 5168 // CHECK5-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1 5169 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64 5170 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]] 5171 // CHECK5-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 5172 // CHECK5-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]] 5173 // CHECK5-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8 5174 // CHECK5-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1 5175 // CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64 5176 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]] 5177 // CHECK5-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4 5178 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 5179 // CHECK5: for.inc: 5180 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4 5181 // CHECK5-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1 5182 // CHECK5-NEXT: store i32 [[DEC]], i32* [[X]], align 4 5183 // CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] 5184 // CHECK5: for.end: 5185 // CHECK5-NEXT: br label [[FOR_INC12:%.*]] 5186 // CHECK5: for.inc12: 5187 // CHECK5-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 5188 // CHECK5-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1 5189 // CHECK5-NEXT: store i8 [[INC]], i8* [[I]], align 1 5190 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 5191 // CHECK5: for.end13: 5192 // CHECK5-NEXT: ret void 5193 // 5194 // 5195 // CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 5196 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 5197 // CHECK5-NEXT: entry: 5198 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5199 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5200 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5201 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5202 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 5203 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 5204 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5205 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5206 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5207 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5208 // CHECK5-NEXT: store i32 0, i32* [[X]], align 4 5209 // CHECK5-NEXT: store i8 48, i8* [[I]], align 1 5210 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 5211 // CHECK5: for.cond: 5212 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 5213 // CHECK5-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 5214 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57 5215 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 5216 // CHECK5: for.body: 5217 // CHECK5-NEXT: store i32 -10, i32* [[X]], align 4 5218 // CHECK5-NEXT: br label [[FOR_COND1:%.*]] 5219 // CHECK5: for.cond1: 5220 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 5221 // CHECK5-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10 5222 // CHECK5-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 5223 // CHECK5: for.body3: 5224 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8 5225 // CHECK5-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1 5226 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64 5227 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]] 5228 // CHECK5-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4 5229 // CHECK5-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8 5230 // CHECK5-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 5231 // CHECK5-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64 5232 // CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]] 5233 // CHECK5-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4 5234 // CHECK5-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]] 5235 // CHECK5-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8 5236 // CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 5237 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64 5238 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]] 5239 // CHECK5-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 5240 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]] 5241 // CHECK5-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8 5242 // CHECK5-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 5243 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64 5244 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]] 5245 // CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 5246 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 5247 // CHECK5: for.inc: 5248 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4 5249 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 5250 // CHECK5-NEXT: store i32 [[INC]], i32* [[X]], align 4 5251 // CHECK5-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP7:![0-9]+]] 5252 // CHECK5: for.end: 5253 // CHECK5-NEXT: br label [[FOR_INC11:%.*]] 5254 // CHECK5: for.inc11: 5255 // CHECK5-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 5256 // CHECK5-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1 5257 // CHECK5-NEXT: store i8 [[INC12]], i8* [[I]], align 1 5258 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 5259 // CHECK5: for.end13: 5260 // CHECK5-NEXT: ret void 5261 // 5262 // 5263 // CHECK5-LABEL: define {{[^@]+}}@_Z8foo_simdii 5264 // CHECK5-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { 5265 // CHECK5-NEXT: entry: 5266 // CHECK5-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 5267 // CHECK5-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 5268 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 5269 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5270 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5271 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 5272 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 5273 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5274 // CHECK5-NEXT: [[I5:%.*]] = alloca i32, align 4 5275 // CHECK5-NEXT: [[_TMP18:%.*]] = alloca i32, align 4 5276 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 5277 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 5278 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 5279 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5280 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5281 // CHECK5-NEXT: [[I27:%.*]] = alloca i32, align 4 5282 // CHECK5-NEXT: [[DOTOMP_IV30:%.*]] = alloca i32, align 4 5283 // CHECK5-NEXT: [[I31:%.*]] = alloca i32, align 4 5284 // CHECK5-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 5285 // CHECK5-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 5286 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 5287 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 5288 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[UP_ADDR]], align 4 5289 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 5290 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 5291 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5292 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 5293 // CHECK5-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 5294 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 5295 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 5296 // CHECK5-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 5297 // CHECK5-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 5298 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5299 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[I]], align 4 5300 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5301 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 5302 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] 5303 // CHECK5-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 5304 // CHECK5: simd.if.then: 5305 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 5306 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5307 // CHECK5: omp.inner.for.cond: 5308 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 5309 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !9 5310 // CHECK5-NEXT: [[ADD6:%.*]] = add i32 [[TMP8]], 1 5311 // CHECK5-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]] 5312 // CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5313 // CHECK5: omp.inner.for.body: 5314 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !9 5315 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 5316 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP10]], 1 5317 // CHECK5-NEXT: [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]] 5318 // CHECK5-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !9 5319 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !9 5320 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 5321 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 5322 // CHECK5-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 5323 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !9 5324 // CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 5325 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM9]] 5326 // CHECK5-NEXT: store float 1.000000e+00, float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 5327 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5328 // CHECK5: omp.body.continue: 5329 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5330 // CHECK5: omp.inner.for.inc: 5331 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 5332 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP13]], 1 5333 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 5334 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 5335 // CHECK5: omp.inner.for.end: 5336 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5337 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 5338 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5339 // CHECK5-NEXT: [[SUB12:%.*]] = sub i32 [[TMP15]], [[TMP16]] 5340 // CHECK5-NEXT: [[SUB13:%.*]] = sub i32 [[SUB12]], 1 5341 // CHECK5-NEXT: [[ADD14:%.*]] = add i32 [[SUB13]], 1 5342 // CHECK5-NEXT: [[DIV15:%.*]] = udiv i32 [[ADD14]], 1 5343 // CHECK5-NEXT: [[MUL16:%.*]] = mul i32 [[DIV15]], 1 5344 // CHECK5-NEXT: [[ADD17:%.*]] = add i32 [[TMP14]], [[MUL16]] 5345 // CHECK5-NEXT: store i32 [[ADD17]], i32* [[I5]], align 4 5346 // CHECK5-NEXT: br label [[SIMD_IF_END]] 5347 // CHECK5: simd.if.end: 5348 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 5349 // CHECK5-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_19]], align 4 5350 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 5351 // CHECK5-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_20]], align 4 5352 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 5353 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 5354 // CHECK5-NEXT: [[SUB22:%.*]] = sub i32 [[TMP19]], [[TMP20]] 5355 // CHECK5-NEXT: [[SUB23:%.*]] = sub i32 [[SUB22]], 1 5356 // CHECK5-NEXT: [[ADD24:%.*]] = add i32 [[SUB23]], 1 5357 // CHECK5-NEXT: [[DIV25:%.*]] = udiv i32 [[ADD24]], 1 5358 // CHECK5-NEXT: [[SUB26:%.*]] = sub i32 [[DIV25]], 1 5359 // CHECK5-NEXT: store i32 [[SUB26]], i32* [[DOTCAPTURE_EXPR_21]], align 4 5360 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5361 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 5362 // CHECK5-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_UB]], align 4 5363 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 5364 // CHECK5-NEXT: store i32 [[TMP22]], i32* [[I27]], align 4 5365 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 5366 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 5367 // CHECK5-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP23]], [[TMP24]] 5368 // CHECK5-NEXT: br i1 [[CMP28]], label [[SIMD_IF_THEN29:%.*]], label [[SIMD_IF_END52:%.*]] 5369 // CHECK5: simd.if.then29: 5370 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5371 // CHECK5-NEXT: store i32 [[TMP25]], i32* [[DOTOMP_IV30]], align 4 5372 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND32:%.*]] 5373 // CHECK5: omp.inner.for.cond32: 5374 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 5375 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 5376 // CHECK5-NEXT: [[ADD33:%.*]] = add i32 [[TMP27]], 1 5377 // CHECK5-NEXT: [[CMP34:%.*]] = icmp ult i32 [[TMP26]], [[ADD33]] 5378 // CHECK5-NEXT: br i1 [[CMP34]], label [[OMP_INNER_FOR_BODY35:%.*]], label [[OMP_INNER_FOR_END45:%.*]] 5379 // CHECK5: omp.inner.for.body35: 5380 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4, !llvm.access.group !13 5381 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 5382 // CHECK5-NEXT: [[MUL36:%.*]] = mul i32 [[TMP29]], 1 5383 // CHECK5-NEXT: [[ADD37:%.*]] = add i32 [[TMP28]], [[MUL36]] 5384 // CHECK5-NEXT: store i32 [[ADD37]], i32* [[I31]], align 4, !llvm.access.group !13 5385 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4, !llvm.access.group !13 5386 // CHECK5-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP30]] to i64 5387 // CHECK5-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM38]] 5388 // CHECK5-NEXT: store float 0.000000e+00, float* [[ARRAYIDX39]], align 4, !llvm.access.group !13 5389 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[I31]], align 4, !llvm.access.group !13 5390 // CHECK5-NEXT: [[IDXPROM40:%.*]] = sext i32 [[TMP31]] to i64 5391 // CHECK5-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM40]] 5392 // CHECK5-NEXT: store float 1.000000e+00, float* [[ARRAYIDX41]], align 4, !llvm.access.group !13 5393 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE42:%.*]] 5394 // CHECK5: omp.body.continue42: 5395 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC43:%.*]] 5396 // CHECK5: omp.inner.for.inc43: 5397 // CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 5398 // CHECK5-NEXT: [[ADD44:%.*]] = add i32 [[TMP32]], 1 5399 // CHECK5-NEXT: store i32 [[ADD44]], i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 5400 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND32]], !llvm.loop [[LOOP14:![0-9]+]] 5401 // CHECK5: omp.inner.for.end45: 5402 // CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 5403 // CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 5404 // CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 5405 // CHECK5-NEXT: [[SUB46:%.*]] = sub i32 [[TMP34]], [[TMP35]] 5406 // CHECK5-NEXT: [[SUB47:%.*]] = sub i32 [[SUB46]], 1 5407 // CHECK5-NEXT: [[ADD48:%.*]] = add i32 [[SUB47]], 1 5408 // CHECK5-NEXT: [[DIV49:%.*]] = udiv i32 [[ADD48]], 1 5409 // CHECK5-NEXT: [[MUL50:%.*]] = mul i32 [[DIV49]], 1 5410 // CHECK5-NEXT: [[ADD51:%.*]] = add i32 [[TMP33]], [[MUL50]] 5411 // CHECK5-NEXT: store i32 [[ADD51]], i32* [[I31]], align 4 5412 // CHECK5-NEXT: br label [[SIMD_IF_END52]] 5413 // CHECK5: simd.if.end52: 5414 // CHECK5-NEXT: ret void 5415 // 5416 // 5417 // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 5418 // CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 5419 // CHECK6-NEXT: entry: 5420 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5421 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5422 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5423 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5424 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 5425 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5426 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5427 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5428 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5429 // CHECK6-NEXT: store i32 32000000, i32* [[I]], align 4 5430 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 5431 // CHECK6: for.cond: 5432 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 5433 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 5434 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 5435 // CHECK6: for.body: 5436 // CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 5437 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 5438 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 5439 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 5440 // CHECK6-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 5441 // CHECK6-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 5442 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 5443 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 5444 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 5445 // CHECK6-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 5446 // CHECK6-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 5447 // CHECK6-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 5448 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 5449 // CHECK6-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 5450 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 5451 // CHECK6-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 5452 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 5453 // CHECK6-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 5454 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 5455 // CHECK6-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 5456 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 5457 // CHECK6-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 5458 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 5459 // CHECK6: for.inc: 5460 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 5461 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 5462 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 5463 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 5464 // CHECK6: for.end: 5465 // CHECK6-NEXT: ret void 5466 // 5467 // 5468 // CHECK6-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 5469 // CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 5470 // CHECK6-NEXT: entry: 5471 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5472 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5473 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5474 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5475 // CHECK6-NEXT: [[I:%.*]] = alloca i64, align 8 5476 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5477 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5478 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5479 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5480 // CHECK6-NEXT: store i64 131071, i64* [[I]], align 8 5481 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 5482 // CHECK6: for.cond: 5483 // CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 5484 // CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 5485 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 5486 // CHECK6: for.body: 5487 // CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 5488 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 5489 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] 5490 // CHECK6-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 5491 // CHECK6-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 5492 // CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 5493 // CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] 5494 // CHECK6-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 5495 // CHECK6-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 5496 // CHECK6-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 5497 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 5498 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] 5499 // CHECK6-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 5500 // CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 5501 // CHECK6-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 5502 // CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 5503 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] 5504 // CHECK6-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 5505 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 5506 // CHECK6: for.inc: 5507 // CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 5508 // CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 5509 // CHECK6-NEXT: store i64 [[ADD]], i64* [[I]], align 8 5510 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 5511 // CHECK6: for.end: 5512 // CHECK6-NEXT: ret void 5513 // 5514 // 5515 // CHECK6-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 5516 // CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 5517 // CHECK6-NEXT: entry: 5518 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5519 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5520 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5521 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5522 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 5523 // CHECK6-NEXT: [[Y:%.*]] = alloca i32, align 4 5524 // CHECK6-NEXT: [[I:%.*]] = alloca i8, align 1 5525 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5526 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5527 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5528 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5529 // CHECK6-NEXT: store i32 0, i32* [[X]], align 4 5530 // CHECK6-NEXT: store i32 0, i32* [[Y]], align 4 5531 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 5532 // CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 5533 // CHECK6-NEXT: store i8 [[CONV]], i8* [[I]], align 1 5534 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 5535 // CHECK6: for.cond: 5536 // CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 5537 // CHECK6-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32 5538 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57 5539 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 5540 // CHECK6: for.body: 5541 // CHECK6-NEXT: store i32 11, i32* [[X]], align 4 5542 // CHECK6-NEXT: br label [[FOR_COND2:%.*]] 5543 // CHECK6: for.cond2: 5544 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4 5545 // CHECK6-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0 5546 // CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] 5547 // CHECK6: for.body4: 5548 // CHECK6-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8 5549 // CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1 5550 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64 5551 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]] 5552 // CHECK6-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4 5553 // CHECK6-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8 5554 // CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1 5555 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64 5556 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]] 5557 // CHECK6-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4 5558 // CHECK6-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]] 5559 // CHECK6-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8 5560 // CHECK6-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1 5561 // CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64 5562 // CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]] 5563 // CHECK6-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 5564 // CHECK6-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]] 5565 // CHECK6-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8 5566 // CHECK6-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1 5567 // CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64 5568 // CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]] 5569 // CHECK6-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4 5570 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 5571 // CHECK6: for.inc: 5572 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4 5573 // CHECK6-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1 5574 // CHECK6-NEXT: store i32 [[DEC]], i32* [[X]], align 4 5575 // CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] 5576 // CHECK6: for.end: 5577 // CHECK6-NEXT: br label [[FOR_INC12:%.*]] 5578 // CHECK6: for.inc12: 5579 // CHECK6-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 5580 // CHECK6-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1 5581 // CHECK6-NEXT: store i8 [[INC]], i8* [[I]], align 1 5582 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 5583 // CHECK6: for.end13: 5584 // CHECK6-NEXT: ret void 5585 // 5586 // 5587 // CHECK6-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 5588 // CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 5589 // CHECK6-NEXT: entry: 5590 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5591 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5592 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5593 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5594 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 5595 // CHECK6-NEXT: [[I:%.*]] = alloca i8, align 1 5596 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5597 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5598 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5599 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5600 // CHECK6-NEXT: store i32 0, i32* [[X]], align 4 5601 // CHECK6-NEXT: store i8 48, i8* [[I]], align 1 5602 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 5603 // CHECK6: for.cond: 5604 // CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 5605 // CHECK6-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 5606 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57 5607 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 5608 // CHECK6: for.body: 5609 // CHECK6-NEXT: store i32 -10, i32* [[X]], align 4 5610 // CHECK6-NEXT: br label [[FOR_COND1:%.*]] 5611 // CHECK6: for.cond1: 5612 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 5613 // CHECK6-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10 5614 // CHECK6-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 5615 // CHECK6: for.body3: 5616 // CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8 5617 // CHECK6-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1 5618 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64 5619 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]] 5620 // CHECK6-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4 5621 // CHECK6-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8 5622 // CHECK6-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 5623 // CHECK6-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64 5624 // CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]] 5625 // CHECK6-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4 5626 // CHECK6-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]] 5627 // CHECK6-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8 5628 // CHECK6-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 5629 // CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64 5630 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]] 5631 // CHECK6-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 5632 // CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]] 5633 // CHECK6-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8 5634 // CHECK6-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 5635 // CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64 5636 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]] 5637 // CHECK6-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 5638 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 5639 // CHECK6: for.inc: 5640 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4 5641 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 5642 // CHECK6-NEXT: store i32 [[INC]], i32* [[X]], align 4 5643 // CHECK6-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP7:![0-9]+]] 5644 // CHECK6: for.end: 5645 // CHECK6-NEXT: br label [[FOR_INC11:%.*]] 5646 // CHECK6: for.inc11: 5647 // CHECK6-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 5648 // CHECK6-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1 5649 // CHECK6-NEXT: store i8 [[INC12]], i8* [[I]], align 1 5650 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 5651 // CHECK6: for.end13: 5652 // CHECK6-NEXT: ret void 5653 // 5654 // 5655 // CHECK6-LABEL: define {{[^@]+}}@_Z8foo_simdii 5656 // CHECK6-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { 5657 // CHECK6-NEXT: entry: 5658 // CHECK6-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 5659 // CHECK6-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 5660 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 5661 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5662 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5663 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 5664 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 5665 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5666 // CHECK6-NEXT: [[I5:%.*]] = alloca i32, align 4 5667 // CHECK6-NEXT: [[_TMP18:%.*]] = alloca i32, align 4 5668 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 5669 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 5670 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 5671 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5672 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5673 // CHECK6-NEXT: [[I27:%.*]] = alloca i32, align 4 5674 // CHECK6-NEXT: [[DOTOMP_IV30:%.*]] = alloca i32, align 4 5675 // CHECK6-NEXT: [[I31:%.*]] = alloca i32, align 4 5676 // CHECK6-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 5677 // CHECK6-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 5678 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 5679 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 5680 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[UP_ADDR]], align 4 5681 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 5682 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 5683 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5684 // CHECK6-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 5685 // CHECK6-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 5686 // CHECK6-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 5687 // CHECK6-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 5688 // CHECK6-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 5689 // CHECK6-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 5690 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5691 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[I]], align 4 5692 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5693 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 5694 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] 5695 // CHECK6-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 5696 // CHECK6: simd.if.then: 5697 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 5698 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5699 // CHECK6: omp.inner.for.cond: 5700 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 5701 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !9 5702 // CHECK6-NEXT: [[ADD6:%.*]] = add i32 [[TMP8]], 1 5703 // CHECK6-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]] 5704 // CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5705 // CHECK6: omp.inner.for.body: 5706 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !9 5707 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 5708 // CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP10]], 1 5709 // CHECK6-NEXT: [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]] 5710 // CHECK6-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !9 5711 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !9 5712 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 5713 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 5714 // CHECK6-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 5715 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !9 5716 // CHECK6-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 5717 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM9]] 5718 // CHECK6-NEXT: store float 1.000000e+00, float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 5719 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5720 // CHECK6: omp.body.continue: 5721 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5722 // CHECK6: omp.inner.for.inc: 5723 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 5724 // CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP13]], 1 5725 // CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 5726 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 5727 // CHECK6: omp.inner.for.end: 5728 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5729 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 5730 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5731 // CHECK6-NEXT: [[SUB12:%.*]] = sub i32 [[TMP15]], [[TMP16]] 5732 // CHECK6-NEXT: [[SUB13:%.*]] = sub i32 [[SUB12]], 1 5733 // CHECK6-NEXT: [[ADD14:%.*]] = add i32 [[SUB13]], 1 5734 // CHECK6-NEXT: [[DIV15:%.*]] = udiv i32 [[ADD14]], 1 5735 // CHECK6-NEXT: [[MUL16:%.*]] = mul i32 [[DIV15]], 1 5736 // CHECK6-NEXT: [[ADD17:%.*]] = add i32 [[TMP14]], [[MUL16]] 5737 // CHECK6-NEXT: store i32 [[ADD17]], i32* [[I5]], align 4 5738 // CHECK6-NEXT: br label [[SIMD_IF_END]] 5739 // CHECK6: simd.if.end: 5740 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 5741 // CHECK6-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_19]], align 4 5742 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 5743 // CHECK6-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_20]], align 4 5744 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 5745 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 5746 // CHECK6-NEXT: [[SUB22:%.*]] = sub i32 [[TMP19]], [[TMP20]] 5747 // CHECK6-NEXT: [[SUB23:%.*]] = sub i32 [[SUB22]], 1 5748 // CHECK6-NEXT: [[ADD24:%.*]] = add i32 [[SUB23]], 1 5749 // CHECK6-NEXT: [[DIV25:%.*]] = udiv i32 [[ADD24]], 1 5750 // CHECK6-NEXT: [[SUB26:%.*]] = sub i32 [[DIV25]], 1 5751 // CHECK6-NEXT: store i32 [[SUB26]], i32* [[DOTCAPTURE_EXPR_21]], align 4 5752 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5753 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 5754 // CHECK6-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_UB]], align 4 5755 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 5756 // CHECK6-NEXT: store i32 [[TMP22]], i32* [[I27]], align 4 5757 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 5758 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 5759 // CHECK6-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP23]], [[TMP24]] 5760 // CHECK6-NEXT: br i1 [[CMP28]], label [[SIMD_IF_THEN29:%.*]], label [[SIMD_IF_END52:%.*]] 5761 // CHECK6: simd.if.then29: 5762 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5763 // CHECK6-NEXT: store i32 [[TMP25]], i32* [[DOTOMP_IV30]], align 4 5764 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND32:%.*]] 5765 // CHECK6: omp.inner.for.cond32: 5766 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 5767 // CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 5768 // CHECK6-NEXT: [[ADD33:%.*]] = add i32 [[TMP27]], 1 5769 // CHECK6-NEXT: [[CMP34:%.*]] = icmp ult i32 [[TMP26]], [[ADD33]] 5770 // CHECK6-NEXT: br i1 [[CMP34]], label [[OMP_INNER_FOR_BODY35:%.*]], label [[OMP_INNER_FOR_END45:%.*]] 5771 // CHECK6: omp.inner.for.body35: 5772 // CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4, !llvm.access.group !13 5773 // CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 5774 // CHECK6-NEXT: [[MUL36:%.*]] = mul i32 [[TMP29]], 1 5775 // CHECK6-NEXT: [[ADD37:%.*]] = add i32 [[TMP28]], [[MUL36]] 5776 // CHECK6-NEXT: store i32 [[ADD37]], i32* [[I31]], align 4, !llvm.access.group !13 5777 // CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4, !llvm.access.group !13 5778 // CHECK6-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP30]] to i64 5779 // CHECK6-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM38]] 5780 // CHECK6-NEXT: store float 0.000000e+00, float* [[ARRAYIDX39]], align 4, !llvm.access.group !13 5781 // CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[I31]], align 4, !llvm.access.group !13 5782 // CHECK6-NEXT: [[IDXPROM40:%.*]] = sext i32 [[TMP31]] to i64 5783 // CHECK6-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM40]] 5784 // CHECK6-NEXT: store float 1.000000e+00, float* [[ARRAYIDX41]], align 4, !llvm.access.group !13 5785 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE42:%.*]] 5786 // CHECK6: omp.body.continue42: 5787 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC43:%.*]] 5788 // CHECK6: omp.inner.for.inc43: 5789 // CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 5790 // CHECK6-NEXT: [[ADD44:%.*]] = add i32 [[TMP32]], 1 5791 // CHECK6-NEXT: store i32 [[ADD44]], i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 5792 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND32]], !llvm.loop [[LOOP14:![0-9]+]] 5793 // CHECK6: omp.inner.for.end45: 5794 // CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 5795 // CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 5796 // CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 5797 // CHECK6-NEXT: [[SUB46:%.*]] = sub i32 [[TMP34]], [[TMP35]] 5798 // CHECK6-NEXT: [[SUB47:%.*]] = sub i32 [[SUB46]], 1 5799 // CHECK6-NEXT: [[ADD48:%.*]] = add i32 [[SUB47]], 1 5800 // CHECK6-NEXT: [[DIV49:%.*]] = udiv i32 [[ADD48]], 1 5801 // CHECK6-NEXT: [[MUL50:%.*]] = mul i32 [[DIV49]], 1 5802 // CHECK6-NEXT: [[ADD51:%.*]] = add i32 [[TMP33]], [[MUL50]] 5803 // CHECK6-NEXT: store i32 [[ADD51]], i32* [[I31]], align 4 5804 // CHECK6-NEXT: br label [[SIMD_IF_END52]] 5805 // CHECK6: simd.if.end52: 5806 // CHECK6-NEXT: ret void 5807 // 5808