1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-function-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" 2 // Test target codegen - host bc file has to be created first. 3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 4 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK1 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -fopenmp-cuda-parallel-target-regions | FileCheck %s --check-prefix CHECK2 6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 7 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK3 8 // RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK4 9 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -fopenmp-cuda-parallel-target-regions | FileCheck %s --check-prefix CHECK5 10 // RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -fopenmp-cuda-parallel-target-regions | FileCheck %s --check-prefix CHECK6 11 // expected-no-diagnostics 12 #ifndef HEADER 13 #define HEADER 14 15 template<typename tx> 16 tx ftemplate(int n) { 17 int i; 18 19 #pragma omp target teams distribute 20 for (i = 0; i < 10; ++i) 21 { 22 #pragma omp parallel 23 ++i; 24 } 25 26 return i; 27 } 28 29 int bar(int n){ 30 int a = 0; 31 32 a += ftemplate<char>(n); 33 34 return a; 35 } 36 37 #endif 38 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker 39 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 40 // CHECK1-NEXT: entry: 41 // CHECK1-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 42 // CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 43 // CHECK1-NEXT: store i8* null, i8** [[WORK_FN]], align 8 44 // CHECK1-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 45 // CHECK1-NEXT: br label [[DOTAWAIT_WORK:%.*]] 46 // CHECK1: .await.work: 47 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 48 // CHECK1-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 49 // CHECK1-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 50 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 51 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 52 // CHECK1-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 53 // CHECK1-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 54 // CHECK1: .select.workers: 55 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 56 // CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 57 // CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 58 // CHECK1: .execute.parallel: 59 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 60 // CHECK1-NEXT: [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 8 61 // CHECK1-NEXT: [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*) 62 // CHECK1-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]] 63 // CHECK1: .execute.fn: 64 // CHECK1-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR3:[0-9]+]] 65 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 66 // CHECK1: .check.next: 67 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 68 // CHECK1-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]]) 69 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL]] 70 // CHECK1: .terminate.parallel: 71 // CHECK1-NEXT: call void @__kmpc_kernel_end_parallel() 72 // CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]] 73 // CHECK1: .barrier.parallel: 74 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 75 // CHECK1-NEXT: br label [[DOTAWAIT_WORK]] 76 // CHECK1: .exit: 77 // CHECK1-NEXT: ret void 78 // 79 // 80 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19 81 // CHECK1-SAME: () #[[ATTR1:[0-9]+]] { 82 // CHECK1-NEXT: entry: 83 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 84 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 85 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 86 // CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 87 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 88 // CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 89 // CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 90 // CHECK1-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 91 // CHECK1-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 92 // CHECK1: .worker: 93 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker() #[[ATTR3]] 94 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 95 // CHECK1: .mastercheck: 96 // CHECK1-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 97 // CHECK1-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 98 // CHECK1-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 99 // CHECK1-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 100 // CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 101 // CHECK1-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 102 // CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 103 // CHECK1-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 104 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 105 // CHECK1: .master: 106 // CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 107 // CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 108 // CHECK1-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 109 // CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 110 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack() 111 // CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 112 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4 113 // CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]] 114 // CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 115 // CHECK1: .termination.notifier: 116 // CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1) 117 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 118 // CHECK1-NEXT: br label [[DOTEXIT]] 119 // CHECK1: .exit: 120 // CHECK1-NEXT: ret void 121 // 122 // 123 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ 124 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 125 // CHECK1-NEXT: entry: 126 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 127 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 128 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 129 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 130 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 131 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 132 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 133 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 134 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 135 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 136 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 137 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* @"_openmp_static_kernel$is_shared", align 2 138 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* @"_openmp_static_kernel$size", align 8 139 // CHECK1-NEXT: call void @__kmpc_get_team_static_memory(i16 0, i8* addrspacecast (i8 addrspace(3)* getelementptr inbounds (%"union._shared_openmp_static_memory_type_$_", %"union._shared_openmp_static_memory_type_$_" addrspace(3)* @"_openmp_shared_static_glob_rd_$_", i32 0, i32 0, i32 0) to i8*), i64 [[TMP1]], i16 [[TMP0]], i8** addrspacecast (i8* addrspace(3)* @"_openmp_kernel_static_glob_rd$ptr" to i8**)) 140 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8* addrspace(3)* @"_openmp_kernel_static_glob_rd$ptr", align 8 141 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 0 142 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8* [[TMP3]] to %struct._globalized_locals_ty* 143 // CHECK1-NEXT: [[I:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[TMP4]], i32 0, i32 0 144 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 145 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 146 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 147 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 148 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 149 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 150 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 151 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 152 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 9 153 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 154 // CHECK1: cond.true: 155 // CHECK1-NEXT: br label [[COND_END:%.*]] 156 // CHECK1: cond.false: 157 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 158 // CHECK1-NEXT: br label [[COND_END]] 159 // CHECK1: cond.end: 160 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 161 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 162 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 163 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 164 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 165 // CHECK1: omp.inner.for.cond: 166 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 167 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 168 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 169 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 170 // CHECK1: omp.inner.for.body: 171 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 172 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 173 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 174 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 175 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 176 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i32* [[I]] to i8* 177 // CHECK1-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 178 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 179 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP15]], i64 1) 180 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 181 // CHECK1: omp.body.continue: 182 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 183 // CHECK1: omp.inner.for.inc: 184 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 185 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], 1 186 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 187 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 188 // CHECK1: omp.inner.for.end: 189 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 190 // CHECK1: omp.loop.exit: 191 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) 192 // CHECK1-NEXT: [[TMP17:%.*]] = load i16, i16* @"_openmp_static_kernel$is_shared", align 2 193 // CHECK1-NEXT: call void @__kmpc_restore_team_static_memory(i16 0, i16 [[TMP17]]) 194 // CHECK1-NEXT: ret void 195 // 196 // 197 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 198 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { 199 // CHECK1-NEXT: entry: 200 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 201 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 202 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 203 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 204 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 205 // CHECK1-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 206 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 207 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 208 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 209 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 210 // CHECK1-NEXT: ret void 211 // 212 // 213 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 214 // CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { 215 // CHECK1-NEXT: entry: 216 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 217 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 218 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 219 // CHECK1-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8 220 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 221 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 222 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 223 // CHECK1-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 224 // CHECK1-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8 225 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0 226 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 227 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 8 228 // CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]] 229 // CHECK1-NEXT: ret void 230 // 231 // 232 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker 233 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 234 // CHECK2-NEXT: entry: 235 // CHECK2-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 236 // CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 237 // CHECK2-NEXT: store i8* null, i8** [[WORK_FN]], align 8 238 // CHECK2-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 239 // CHECK2-NEXT: br label [[DOTAWAIT_WORK:%.*]] 240 // CHECK2: .await.work: 241 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 242 // CHECK2-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 243 // CHECK2-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 244 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 245 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 246 // CHECK2-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 247 // CHECK2-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 248 // CHECK2: .select.workers: 249 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 250 // CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 251 // CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 252 // CHECK2: .execute.parallel: 253 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 254 // CHECK2-NEXT: [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 8 255 // CHECK2-NEXT: [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*) 256 // CHECK2-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]] 257 // CHECK2: .execute.fn: 258 // CHECK2-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR3:[0-9]+]] 259 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 260 // CHECK2: .check.next: 261 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 262 // CHECK2-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]]) 263 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL]] 264 // CHECK2: .terminate.parallel: 265 // CHECK2-NEXT: call void @__kmpc_kernel_end_parallel() 266 // CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]] 267 // CHECK2: .barrier.parallel: 268 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 269 // CHECK2-NEXT: br label [[DOTAWAIT_WORK]] 270 // CHECK2: .exit: 271 // CHECK2-NEXT: ret void 272 // 273 // 274 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19 275 // CHECK2-SAME: () #[[ATTR1:[0-9]+]] { 276 // CHECK2-NEXT: entry: 277 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 278 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 279 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 280 // CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 281 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 282 // CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 283 // CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 284 // CHECK2-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 285 // CHECK2-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 286 // CHECK2: .worker: 287 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker() #[[ATTR3]] 288 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 289 // CHECK2: .mastercheck: 290 // CHECK2-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 291 // CHECK2-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 292 // CHECK2-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 293 // CHECK2-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 294 // CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 295 // CHECK2-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 296 // CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 297 // CHECK2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 298 // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 299 // CHECK2: .master: 300 // CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 301 // CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 302 // CHECK2-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 303 // CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 304 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack() 305 // CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 306 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4 307 // CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]] 308 // CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 309 // CHECK2: .termination.notifier: 310 // CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1) 311 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 312 // CHECK2-NEXT: br label [[DOTEXIT]] 313 // CHECK2: .exit: 314 // CHECK2-NEXT: ret void 315 // 316 // 317 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ 318 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 319 // CHECK2-NEXT: entry: 320 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 321 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 322 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 323 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 324 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 325 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 326 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 327 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 328 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 329 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 330 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 331 // CHECK2-NEXT: [[TMP0:%.*]] = call i8* @__kmpc_data_sharing_push_stack(i64 4, i16 1) 332 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to %struct._globalized_locals_ty* 333 // CHECK2-NEXT: [[I:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[TMP1]], i32 0, i32 0 334 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 335 // CHECK2-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 336 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 337 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 338 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 339 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 340 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 341 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 342 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 343 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 344 // CHECK2: cond.true: 345 // CHECK2-NEXT: br label [[COND_END:%.*]] 346 // CHECK2: cond.false: 347 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 348 // CHECK2-NEXT: br label [[COND_END]] 349 // CHECK2: cond.end: 350 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 351 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 352 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 353 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 354 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 355 // CHECK2: omp.inner.for.cond: 356 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 357 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 358 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 359 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 360 // CHECK2: omp.inner.for.body: 361 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 362 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 363 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 364 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 365 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 366 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i32* [[I]] to i8* 367 // CHECK2-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 8 368 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 369 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP12]], i64 1) 370 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 371 // CHECK2: omp.body.continue: 372 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 373 // CHECK2: omp.inner.for.inc: 374 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 375 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1 376 // CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 377 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 378 // CHECK2: omp.inner.for.end: 379 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 380 // CHECK2: omp.loop.exit: 381 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 382 // CHECK2-NEXT: call void @__kmpc_data_sharing_pop_stack(i8* [[TMP0]]) 383 // CHECK2-NEXT: ret void 384 // 385 // 386 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 387 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { 388 // CHECK2-NEXT: entry: 389 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 390 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 391 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 392 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 393 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 394 // CHECK2-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 395 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 396 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 397 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 398 // CHECK2-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 399 // CHECK2-NEXT: ret void 400 // 401 // 402 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 403 // CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { 404 // CHECK2-NEXT: entry: 405 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 406 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 407 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 408 // CHECK2-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8 409 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 410 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 411 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 412 // CHECK2-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 413 // CHECK2-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8 414 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0 415 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 416 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 8 417 // CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]] 418 // CHECK2-NEXT: ret void 419 // 420 // 421 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker 422 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 423 // CHECK3-NEXT: entry: 424 // CHECK3-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 425 // CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 426 // CHECK3-NEXT: store i8* null, i8** [[WORK_FN]], align 4 427 // CHECK3-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 428 // CHECK3-NEXT: br label [[DOTAWAIT_WORK:%.*]] 429 // CHECK3: .await.work: 430 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 431 // CHECK3-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 432 // CHECK3-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 433 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 434 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 435 // CHECK3-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 436 // CHECK3-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 437 // CHECK3: .select.workers: 438 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 439 // CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 440 // CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 441 // CHECK3: .execute.parallel: 442 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 443 // CHECK3-NEXT: [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 4 444 // CHECK3-NEXT: [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*) 445 // CHECK3-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]] 446 // CHECK3: .execute.fn: 447 // CHECK3-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR3:[0-9]+]] 448 // CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 449 // CHECK3: .check.next: 450 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 451 // CHECK3-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]]) 452 // CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL]] 453 // CHECK3: .terminate.parallel: 454 // CHECK3-NEXT: call void @__kmpc_kernel_end_parallel() 455 // CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]] 456 // CHECK3: .barrier.parallel: 457 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 458 // CHECK3-NEXT: br label [[DOTAWAIT_WORK]] 459 // CHECK3: .exit: 460 // CHECK3-NEXT: ret void 461 // 462 // 463 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19 464 // CHECK3-SAME: () #[[ATTR1:[0-9]+]] { 465 // CHECK3-NEXT: entry: 466 // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 467 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 468 // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 469 // CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 470 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 471 // CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 472 // CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 473 // CHECK3-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 474 // CHECK3-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 475 // CHECK3: .worker: 476 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker() #[[ATTR3]] 477 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 478 // CHECK3: .mastercheck: 479 // CHECK3-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 480 // CHECK3-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 481 // CHECK3-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 482 // CHECK3-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 483 // CHECK3-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 484 // CHECK3-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 485 // CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 486 // CHECK3-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 487 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 488 // CHECK3: .master: 489 // CHECK3-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 490 // CHECK3-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 491 // CHECK3-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 492 // CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 493 // CHECK3-NEXT: call void @__kmpc_data_sharing_init_stack() 494 // CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 495 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4 496 // CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]] 497 // CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 498 // CHECK3: .termination.notifier: 499 // CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1) 500 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 501 // CHECK3-NEXT: br label [[DOTEXIT]] 502 // CHECK3: .exit: 503 // CHECK3-NEXT: ret void 504 // 505 // 506 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ 507 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 508 // CHECK3-NEXT: entry: 509 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 510 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 511 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 512 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 513 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 514 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 515 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 516 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 517 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 518 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 519 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 520 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* @"_openmp_static_kernel$is_shared", align 2 521 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* @"_openmp_static_kernel$size", align 4 522 // CHECK3-NEXT: call void @__kmpc_get_team_static_memory(i16 0, i8* addrspacecast (i8 addrspace(3)* getelementptr inbounds (%"union._shared_openmp_static_memory_type_$_", %"union._shared_openmp_static_memory_type_$_" addrspace(3)* @"_openmp_shared_static_glob_rd_$_", i32 0, i32 0, i32 0) to i8*), i32 [[TMP1]], i16 [[TMP0]], i8** addrspacecast (i8* addrspace(3)* @"_openmp_kernel_static_glob_rd$ptr" to i8**)) 523 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8* addrspace(3)* @"_openmp_kernel_static_glob_rd$ptr", align 4 524 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i32 0 525 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8* [[TMP3]] to %struct._globalized_locals_ty* 526 // CHECK3-NEXT: [[I:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[TMP4]], i32 0, i32 0 527 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 528 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 529 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 530 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 531 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 532 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 533 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 534 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 535 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 9 536 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 537 // CHECK3: cond.true: 538 // CHECK3-NEXT: br label [[COND_END:%.*]] 539 // CHECK3: cond.false: 540 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 541 // CHECK3-NEXT: br label [[COND_END]] 542 // CHECK3: cond.end: 543 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 544 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 545 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 546 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 547 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 548 // CHECK3: omp.inner.for.cond: 549 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 550 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 551 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 552 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 553 // CHECK3: omp.inner.for.body: 554 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 555 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 556 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 557 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 558 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 559 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i32* [[I]] to i8* 560 // CHECK3-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 4 561 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 562 // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP15]], i32 1) 563 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 564 // CHECK3: omp.body.continue: 565 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 566 // CHECK3: omp.inner.for.inc: 567 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 568 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], 1 569 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 570 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 571 // CHECK3: omp.inner.for.end: 572 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 573 // CHECK3: omp.loop.exit: 574 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) 575 // CHECK3-NEXT: [[TMP17:%.*]] = load i16, i16* @"_openmp_static_kernel$is_shared", align 2 576 // CHECK3-NEXT: call void @__kmpc_restore_team_static_memory(i16 0, i16 [[TMP17]]) 577 // CHECK3-NEXT: ret void 578 // 579 // 580 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 581 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { 582 // CHECK3-NEXT: entry: 583 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 584 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 585 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 4 586 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 587 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 588 // CHECK3-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 4 589 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 4 590 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 591 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 592 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 593 // CHECK3-NEXT: ret void 594 // 595 // 596 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 597 // CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { 598 // CHECK3-NEXT: entry: 599 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 600 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 601 // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 602 // CHECK3-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 603 // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 604 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 605 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 606 // CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 607 // CHECK3-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4 608 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0 609 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 610 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4 611 // CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]] 612 // CHECK3-NEXT: ret void 613 // 614 // 615 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker 616 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 617 // CHECK4-NEXT: entry: 618 // CHECK4-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 619 // CHECK4-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 620 // CHECK4-NEXT: store i8* null, i8** [[WORK_FN]], align 4 621 // CHECK4-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 622 // CHECK4-NEXT: br label [[DOTAWAIT_WORK:%.*]] 623 // CHECK4: .await.work: 624 // CHECK4-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 625 // CHECK4-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 626 // CHECK4-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 627 // CHECK4-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 628 // CHECK4-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 629 // CHECK4-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 630 // CHECK4-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 631 // CHECK4: .select.workers: 632 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 633 // CHECK4-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 634 // CHECK4-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 635 // CHECK4: .execute.parallel: 636 // CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 637 // CHECK4-NEXT: [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 4 638 // CHECK4-NEXT: [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*) 639 // CHECK4-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]] 640 // CHECK4: .execute.fn: 641 // CHECK4-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR3:[0-9]+]] 642 // CHECK4-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 643 // CHECK4: .check.next: 644 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 645 // CHECK4-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]]) 646 // CHECK4-NEXT: br label [[DOTTERMINATE_PARALLEL]] 647 // CHECK4: .terminate.parallel: 648 // CHECK4-NEXT: call void @__kmpc_kernel_end_parallel() 649 // CHECK4-NEXT: br label [[DOTBARRIER_PARALLEL]] 650 // CHECK4: .barrier.parallel: 651 // CHECK4-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 652 // CHECK4-NEXT: br label [[DOTAWAIT_WORK]] 653 // CHECK4: .exit: 654 // CHECK4-NEXT: ret void 655 // 656 // 657 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19 658 // CHECK4-SAME: () #[[ATTR1:[0-9]+]] { 659 // CHECK4-NEXT: entry: 660 // CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 661 // CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 662 // CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 663 // CHECK4-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 664 // CHECK4-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 665 // CHECK4-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 666 // CHECK4-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 667 // CHECK4-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 668 // CHECK4-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 669 // CHECK4: .worker: 670 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker() #[[ATTR3]] 671 // CHECK4-NEXT: br label [[DOTEXIT:%.*]] 672 // CHECK4: .mastercheck: 673 // CHECK4-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 674 // CHECK4-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 675 // CHECK4-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 676 // CHECK4-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 677 // CHECK4-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 678 // CHECK4-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 679 // CHECK4-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 680 // CHECK4-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 681 // CHECK4-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 682 // CHECK4: .master: 683 // CHECK4-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 684 // CHECK4-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 685 // CHECK4-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 686 // CHECK4-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 687 // CHECK4-NEXT: call void @__kmpc_data_sharing_init_stack() 688 // CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 689 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4 690 // CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]] 691 // CHECK4-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 692 // CHECK4: .termination.notifier: 693 // CHECK4-NEXT: call void @__kmpc_kernel_deinit(i16 1) 694 // CHECK4-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 695 // CHECK4-NEXT: br label [[DOTEXIT]] 696 // CHECK4: .exit: 697 // CHECK4-NEXT: ret void 698 // 699 // 700 // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ 701 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 702 // CHECK4-NEXT: entry: 703 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 704 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 705 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 706 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 707 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 708 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 709 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 710 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 711 // CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 712 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 713 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 714 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* @"_openmp_static_kernel$is_shared", align 2 715 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* @"_openmp_static_kernel$size", align 4 716 // CHECK4-NEXT: call void @__kmpc_get_team_static_memory(i16 0, i8* addrspacecast (i8 addrspace(3)* getelementptr inbounds (%"union._shared_openmp_static_memory_type_$_", %"union._shared_openmp_static_memory_type_$_" addrspace(3)* @"_openmp_shared_static_glob_rd_$_", i32 0, i32 0, i32 0) to i8*), i32 [[TMP1]], i16 [[TMP0]], i8** addrspacecast (i8* addrspace(3)* @"_openmp_kernel_static_glob_rd$ptr" to i8**)) 717 // CHECK4-NEXT: [[TMP2:%.*]] = load i8*, i8* addrspace(3)* @"_openmp_kernel_static_glob_rd$ptr", align 4 718 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i32 0 719 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast i8* [[TMP3]] to %struct._globalized_locals_ty* 720 // CHECK4-NEXT: [[I:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[TMP4]], i32 0, i32 0 721 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 722 // CHECK4-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 723 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 724 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 725 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 726 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 727 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 728 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 729 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 9 730 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 731 // CHECK4: cond.true: 732 // CHECK4-NEXT: br label [[COND_END:%.*]] 733 // CHECK4: cond.false: 734 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 735 // CHECK4-NEXT: br label [[COND_END]] 736 // CHECK4: cond.end: 737 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 738 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 739 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 740 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 741 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 742 // CHECK4: omp.inner.for.cond: 743 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 744 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 745 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 746 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 747 // CHECK4: omp.inner.for.body: 748 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 749 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 750 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 751 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 752 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 753 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i32* [[I]] to i8* 754 // CHECK4-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 4 755 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 756 // CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP15]], i32 1) 757 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 758 // CHECK4: omp.body.continue: 759 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 760 // CHECK4: omp.inner.for.inc: 761 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 762 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], 1 763 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 764 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 765 // CHECK4: omp.inner.for.end: 766 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 767 // CHECK4: omp.loop.exit: 768 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) 769 // CHECK4-NEXT: [[TMP17:%.*]] = load i16, i16* @"_openmp_static_kernel$is_shared", align 2 770 // CHECK4-NEXT: call void @__kmpc_restore_team_static_memory(i16 0, i16 [[TMP17]]) 771 // CHECK4-NEXT: ret void 772 // 773 // 774 // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 775 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { 776 // CHECK4-NEXT: entry: 777 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 778 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 779 // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 4 780 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 781 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 782 // CHECK4-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 4 783 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 4 784 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 785 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 786 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 787 // CHECK4-NEXT: ret void 788 // 789 // 790 // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 791 // CHECK4-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { 792 // CHECK4-NEXT: entry: 793 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 794 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 795 // CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 796 // CHECK4-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 797 // CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 798 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 799 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 800 // CHECK4-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 801 // CHECK4-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4 802 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0 803 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 804 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4 805 // CHECK4-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]] 806 // CHECK4-NEXT: ret void 807 // 808 // 809 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker 810 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 811 // CHECK5-NEXT: entry: 812 // CHECK5-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 813 // CHECK5-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 814 // CHECK5-NEXT: store i8* null, i8** [[WORK_FN]], align 4 815 // CHECK5-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 816 // CHECK5-NEXT: br label [[DOTAWAIT_WORK:%.*]] 817 // CHECK5: .await.work: 818 // CHECK5-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 819 // CHECK5-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 820 // CHECK5-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 821 // CHECK5-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 822 // CHECK5-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 823 // CHECK5-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 824 // CHECK5-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 825 // CHECK5: .select.workers: 826 // CHECK5-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 827 // CHECK5-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 828 // CHECK5-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 829 // CHECK5: .execute.parallel: 830 // CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 831 // CHECK5-NEXT: [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 4 832 // CHECK5-NEXT: [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*) 833 // CHECK5-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]] 834 // CHECK5: .execute.fn: 835 // CHECK5-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR3:[0-9]+]] 836 // CHECK5-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 837 // CHECK5: .check.next: 838 // CHECK5-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 839 // CHECK5-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]]) 840 // CHECK5-NEXT: br label [[DOTTERMINATE_PARALLEL]] 841 // CHECK5: .terminate.parallel: 842 // CHECK5-NEXT: call void @__kmpc_kernel_end_parallel() 843 // CHECK5-NEXT: br label [[DOTBARRIER_PARALLEL]] 844 // CHECK5: .barrier.parallel: 845 // CHECK5-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 846 // CHECK5-NEXT: br label [[DOTAWAIT_WORK]] 847 // CHECK5: .exit: 848 // CHECK5-NEXT: ret void 849 // 850 // 851 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19 852 // CHECK5-SAME: () #[[ATTR1:[0-9]+]] { 853 // CHECK5-NEXT: entry: 854 // CHECK5-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 855 // CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 856 // CHECK5-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 857 // CHECK5-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 858 // CHECK5-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 859 // CHECK5-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 860 // CHECK5-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 861 // CHECK5-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 862 // CHECK5-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 863 // CHECK5: .worker: 864 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker() #[[ATTR3]] 865 // CHECK5-NEXT: br label [[DOTEXIT:%.*]] 866 // CHECK5: .mastercheck: 867 // CHECK5-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 868 // CHECK5-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 869 // CHECK5-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 870 // CHECK5-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 871 // CHECK5-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 872 // CHECK5-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 873 // CHECK5-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 874 // CHECK5-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 875 // CHECK5-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 876 // CHECK5: .master: 877 // CHECK5-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 878 // CHECK5-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 879 // CHECK5-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 880 // CHECK5-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 881 // CHECK5-NEXT: call void @__kmpc_data_sharing_init_stack() 882 // CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 883 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4 884 // CHECK5-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]] 885 // CHECK5-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 886 // CHECK5: .termination.notifier: 887 // CHECK5-NEXT: call void @__kmpc_kernel_deinit(i16 1) 888 // CHECK5-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 889 // CHECK5-NEXT: br label [[DOTEXIT]] 890 // CHECK5: .exit: 891 // CHECK5-NEXT: ret void 892 // 893 // 894 // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__ 895 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 896 // CHECK5-NEXT: entry: 897 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 898 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 899 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 900 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 901 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 902 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 903 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 904 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 905 // CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 906 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 907 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 908 // CHECK5-NEXT: [[TMP0:%.*]] = call i8* @__kmpc_data_sharing_push_stack(i32 4, i16 1) 909 // CHECK5-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to %struct._globalized_locals_ty* 910 // CHECK5-NEXT: [[I:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[TMP1]], i32 0, i32 0 911 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 912 // CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 913 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 914 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 915 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 916 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 917 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 918 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 919 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 920 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 921 // CHECK5: cond.true: 922 // CHECK5-NEXT: br label [[COND_END:%.*]] 923 // CHECK5: cond.false: 924 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 925 // CHECK5-NEXT: br label [[COND_END]] 926 // CHECK5: cond.end: 927 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 928 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 929 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 930 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 931 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 932 // CHECK5: omp.inner.for.cond: 933 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 934 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 935 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 936 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 937 // CHECK5: omp.inner.for.body: 938 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 939 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 940 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 941 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 942 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 943 // CHECK5-NEXT: [[TMP11:%.*]] = bitcast i32* [[I]] to i8* 944 // CHECK5-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4 945 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 946 // CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP12]], i32 1) 947 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 948 // CHECK5: omp.body.continue: 949 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 950 // CHECK5: omp.inner.for.inc: 951 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 952 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1 953 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 954 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 955 // CHECK5: omp.inner.for.end: 956 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 957 // CHECK5: omp.loop.exit: 958 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 959 // CHECK5-NEXT: call void @__kmpc_data_sharing_pop_stack(i8* [[TMP0]]) 960 // CHECK5-NEXT: ret void 961 // 962 // 963 // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1 964 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { 965 // CHECK5-NEXT: entry: 966 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 967 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 968 // CHECK5-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 4 969 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 970 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 971 // CHECK5-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 4 972 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 4 973 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 974 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 975 // CHECK5-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 976 // CHECK5-NEXT: ret void 977 // 978 // 979 // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 980 // CHECK5-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { 981 // CHECK5-NEXT: entry: 982 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 983 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 984 // CHECK5-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 985 // CHECK5-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 986 // CHECK5-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 987 // CHECK5-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 988 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 989 // CHECK5-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 990 // CHECK5-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4 991 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0 992 // CHECK5-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 993 // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4 994 // CHECK5-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]] 995 // CHECK5-NEXT: ret void 996 // 997 // 998 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker 999 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 1000 // CHECK6-NEXT: entry: 1001 // CHECK6-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 1002 // CHECK6-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 1003 // CHECK6-NEXT: store i8* null, i8** [[WORK_FN]], align 4 1004 // CHECK6-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 1005 // CHECK6-NEXT: br label [[DOTAWAIT_WORK:%.*]] 1006 // CHECK6: .await.work: 1007 // CHECK6-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1008 // CHECK6-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 1009 // CHECK6-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 1010 // CHECK6-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 1011 // CHECK6-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 1012 // CHECK6-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 1013 // CHECK6-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 1014 // CHECK6: .select.workers: 1015 // CHECK6-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 1016 // CHECK6-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 1017 // CHECK6-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 1018 // CHECK6: .execute.parallel: 1019 // CHECK6-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 1020 // CHECK6-NEXT: [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 4 1021 // CHECK6-NEXT: [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*) 1022 // CHECK6-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]] 1023 // CHECK6: .execute.fn: 1024 // CHECK6-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR3:[0-9]+]] 1025 // CHECK6-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 1026 // CHECK6: .check.next: 1027 // CHECK6-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 1028 // CHECK6-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]]) 1029 // CHECK6-NEXT: br label [[DOTTERMINATE_PARALLEL]] 1030 // CHECK6: .terminate.parallel: 1031 // CHECK6-NEXT: call void @__kmpc_kernel_end_parallel() 1032 // CHECK6-NEXT: br label [[DOTBARRIER_PARALLEL]] 1033 // CHECK6: .barrier.parallel: 1034 // CHECK6-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1035 // CHECK6-NEXT: br label [[DOTAWAIT_WORK]] 1036 // CHECK6: .exit: 1037 // CHECK6-NEXT: ret void 1038 // 1039 // 1040 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19 1041 // CHECK6-SAME: () #[[ATTR1:[0-9]+]] { 1042 // CHECK6-NEXT: entry: 1043 // CHECK6-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 1044 // CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 1045 // CHECK6-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 1046 // CHECK6-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1047 // CHECK6-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1048 // CHECK6-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1049 // CHECK6-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 1050 // CHECK6-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 1051 // CHECK6-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 1052 // CHECK6: .worker: 1053 // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker() #[[ATTR3]] 1054 // CHECK6-NEXT: br label [[DOTEXIT:%.*]] 1055 // CHECK6: .mastercheck: 1056 // CHECK6-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1057 // CHECK6-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1058 // CHECK6-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1059 // CHECK6-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 1060 // CHECK6-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 1061 // CHECK6-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 1062 // CHECK6-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 1063 // CHECK6-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 1064 // CHECK6-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 1065 // CHECK6: .master: 1066 // CHECK6-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1067 // CHECK6-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1068 // CHECK6-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 1069 // CHECK6-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 1070 // CHECK6-NEXT: call void @__kmpc_data_sharing_init_stack() 1071 // CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 1072 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4 1073 // CHECK6-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]] 1074 // CHECK6-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 1075 // CHECK6: .termination.notifier: 1076 // CHECK6-NEXT: call void @__kmpc_kernel_deinit(i16 1) 1077 // CHECK6-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1078 // CHECK6-NEXT: br label [[DOTEXIT]] 1079 // CHECK6: .exit: 1080 // CHECK6-NEXT: ret void 1081 // 1082 // 1083 // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__ 1084 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1085 // CHECK6-NEXT: entry: 1086 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1087 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1088 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1089 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 1090 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1091 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1092 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1093 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1094 // CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 1095 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1096 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1097 // CHECK6-NEXT: [[TMP0:%.*]] = call i8* @__kmpc_data_sharing_push_stack(i32 4, i16 1) 1098 // CHECK6-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to %struct._globalized_locals_ty* 1099 // CHECK6-NEXT: [[I:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[TMP1]], i32 0, i32 0 1100 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1101 // CHECK6-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 1102 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1103 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1104 // CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1105 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1106 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1107 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1108 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 1109 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1110 // CHECK6: cond.true: 1111 // CHECK6-NEXT: br label [[COND_END:%.*]] 1112 // CHECK6: cond.false: 1113 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1114 // CHECK6-NEXT: br label [[COND_END]] 1115 // CHECK6: cond.end: 1116 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1117 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1118 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1119 // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 1120 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1121 // CHECK6: omp.inner.for.cond: 1122 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1123 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1124 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1125 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1126 // CHECK6: omp.inner.for.body: 1127 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1128 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1129 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1130 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1131 // CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 1132 // CHECK6-NEXT: [[TMP11:%.*]] = bitcast i32* [[I]] to i8* 1133 // CHECK6-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4 1134 // CHECK6-NEXT: [[TMP12:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 1135 // CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP12]], i32 1) 1136 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1137 // CHECK6: omp.body.continue: 1138 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1139 // CHECK6: omp.inner.for.inc: 1140 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1141 // CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1 1142 // CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 1143 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 1144 // CHECK6: omp.inner.for.end: 1145 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1146 // CHECK6: omp.loop.exit: 1147 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 1148 // CHECK6-NEXT: call void @__kmpc_data_sharing_pop_stack(i8* [[TMP0]]) 1149 // CHECK6-NEXT: ret void 1150 // 1151 // 1152 // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1 1153 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { 1154 // CHECK6-NEXT: entry: 1155 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1156 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1157 // CHECK6-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 4 1158 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1159 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1160 // CHECK6-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 4 1161 // CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 4 1162 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1163 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 1164 // CHECK6-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 1165 // CHECK6-NEXT: ret void 1166 // 1167 // 1168 // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 1169 // CHECK6-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { 1170 // CHECK6-NEXT: entry: 1171 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 1172 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 1173 // CHECK6-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 1174 // CHECK6-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 1175 // CHECK6-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 1176 // CHECK6-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 1177 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 1178 // CHECK6-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 1179 // CHECK6-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4 1180 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0 1181 // CHECK6-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 1182 // CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4 1183 // CHECK6-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]] 1184 // CHECK6-NEXT: ret void 1185 // 1186