1 // Test target codegen - host bc file has to be created first. 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 4 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 6 // RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 7 // expected-no-diagnostics 8 #ifndef HEADER 9 #define HEADER 10 11 // Check that the execution mode of all 2 target regions is set to Generic Mode. 12 // CHECK-DAG: {{@__omp_offloading_.+l27}}_exec_mode = weak constant i8 1 13 // CHECK-DAG: {{@__omp_offloading_.+l32}}_exec_mode = weak constant i8 1 14 // CHECK-DAG: {{@__omp_offloading_.+l37}}_exec_mode = weak constant i8 0 15 16 template<typename tx> 17 tx ftemplate(int n) { 18 tx a = 0; 19 short aa = 0; 20 tx b[10]; 21 22 #pragma omp target teams if(0) 23 { 24 b[2] += 1; 25 } 26 27 #pragma omp target teams if(1) 28 { 29 a = '1'; 30 } 31 32 #pragma omp target teams if(n>40) 33 { 34 aa = 1; 35 } 36 37 #pragma omp target teams 38 { 39 #pragma omp parallel 40 #pragma omp parallel 41 aa = 1; 42 } 43 44 return a; 45 } 46 47 int bar(int n){ 48 int a = 0; 49 50 a += ftemplate<char>(n); 51 52 return a; 53 } 54 55 // CHECK-NOT: define {{.*}}void {{@__omp_offloading_.+template.+l22}}_worker() 56 57 58 59 60 61 62 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l27}}_worker() 63 // CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8, 64 // CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*, 65 // CHECK: store i8* null, i8** [[OMP_WORK_FN]], 66 // CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]], 67 // CHECK: br label {{%?}}[[AWAIT_WORK:.+]] 68 // 69 // CHECK: [[AWAIT_WORK]] 70 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 71 // CHECK: [[KPR:%.+]] = call i1 @__kmpc_kernel_parallel(i8** [[OMP_WORK_FN]]) 72 // CHECK: [[KPRB:%.+]] = zext i1 [[KPR]] to i8 73 // store i8 [[KPRB]], i8* [[OMP_EXEC_STATUS]], align 1 74 // CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 75 // CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null 76 // CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]] 77 // 78 // CHECK: [[SEL_WORKERS]] 79 // CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]] 80 // CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0 81 // CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]] 82 // 83 // CHECK: [[EXEC_PARALLEL]] 84 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 85 // 86 // CHECK: [[TERM_PARALLEL]] 87 // CHECK: call void @__kmpc_kernel_end_parallel() 88 // CHECK: br label {{%?}}[[BAR_PARALLEL]] 89 // 90 // CHECK: [[BAR_PARALLEL]] 91 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 92 // CHECK: br label {{%?}}[[AWAIT_WORK]] 93 // 94 // CHECK: [[EXIT]] 95 // CHECK: ret void 96 97 // CHECK: define {{.*}}void [[T1:@__omp_offloading_.+template.+l27]](i[[SZ:32|64]] [[A:%[^)]+]]) 98 // CHECK: store i[[SZ]] [[A]], i[[SZ]]* [[A_ADDR:%.+]], align 99 // CHECK: [[CONV:%.+]] = bitcast i[[SZ]]* [[A_ADDR]] to i8* 100 101 // CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 102 // CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 103 // CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 104 // CHECK-DAG: [[TH_LIMIT:%.+]] = sub nuw i32 [[NTH]], [[WS]] 105 // CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]] 106 // CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]] 107 // 108 // CHECK: [[WORKER]] 109 // CHECK: {{call|invoke}} void [[T1]]_worker() 110 // CHECK: br label {{%?}}[[EXIT:.+]] 111 // 112 // CHECK: [[CHECK_MASTER]] 113 // CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 114 // CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 115 // CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 116 // CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]], 117 // CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]] 118 // 119 // CHECK: [[MASTER]] 120 // CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 121 // CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 122 // CHECK: [[MTMP1:%.+]] = sub nuw i32 [[MNTH]], [[MWS]] 123 // CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]] 124 // 125 // CHECK-NOT: kmpc_fork_teams 126 // CHECK: [[A_VAL:%.+]] = load i8, i8* [[CONV]], align 127 // CHECK: [[ACP:%.+]] = bitcast i[[SZ]]* [[AC:%.+]] to i8* 128 // CHECK: store i8 [[A_VAL]], i8* [[ACP]], align 129 // CHECK: [[ACV:%.+]] = load i[[SZ]], i[[SZ]]* [[AC]], align 130 // CHECK: call void [[PARALLEL:@.+]](i32* %{{.+}}, i32* %{{.+}}, i[[SZ]] [[ACV]]) 131 // CHECK: br label {{%?}}[[TERMINATE:.+]] 132 // 133 // CHECK: [[TERMINATE]] 134 // CHECK: call void @__kmpc_kernel_deinit( 135 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 136 // CHECK: br label {{%?}}[[EXIT]] 137 // 138 // CHECK: [[EXIT]] 139 // CHECK: ret void 140 141 // CHECK: define internal void [[PARALLEL]](i32* noalias %{{.+}}, i32* noalias %{{.+}}, i[[SZ]] [[A_VAL:%.+]]) 142 // CHECK: [[A_ADDR:%.+]] = alloca i[[SZ]], 143 // CHECK: store i[[SZ]] [[A_VAL]], i[[SZ]]* [[A_ADDR]], 144 // CHECK: [[CONV:%.+]] = bitcast i[[SZ]]* [[A_ADDR]] to i8* 145 // CHECK: store i8 49, i8* [[CONV]], 146 // CHECK: ret void 147 148 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l32}}_worker() 149 // CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8, 150 // CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*, 151 // CHECK: store i8* null, i8** [[OMP_WORK_FN]], 152 // CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]], 153 // CHECK: br label {{%?}}[[AWAIT_WORK:.+]] 154 // 155 // CHECK: [[AWAIT_WORK]] 156 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 157 // CHECK: [[KPR:%.+]] = call i1 @__kmpc_kernel_parallel(i8** [[OMP_WORK_FN]]) 158 // CHECK: [[KPRB:%.+]] = zext i1 [[KPR]] to i8 159 // store i8 [[KPRB]], i8* [[OMP_EXEC_STATUS]], align 1 160 // CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 161 // CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null 162 // CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]] 163 // 164 // CHECK: [[SEL_WORKERS]] 165 // CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]] 166 // CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0 167 // CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]] 168 // 169 // CHECK: [[EXEC_PARALLEL]] 170 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 171 // 172 // CHECK: [[TERM_PARALLEL]] 173 // CHECK: call void @__kmpc_kernel_end_parallel() 174 // CHECK: br label {{%?}}[[BAR_PARALLEL]] 175 // 176 // CHECK: [[BAR_PARALLEL]] 177 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 178 // CHECK: br label {{%?}}[[AWAIT_WORK]] 179 // 180 // CHECK: [[EXIT]] 181 // CHECK: ret void 182 183 // CHECK: define {{.*}}void [[T2:@__omp_offloading_.+template.+l32]](i[[SZ:32|64]] [[AA:%[^)]+]]) 184 // CHECK: store i[[SZ]] [[AA]], i[[SZ]]* [[AA_ADDR:%.+]], align 185 // CHECK: [[CONV:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16* 186 187 // CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 188 // CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 189 // CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 190 // CHECK-DAG: [[TH_LIMIT:%.+]] = sub nuw i32 [[NTH]], [[WS]] 191 // CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]] 192 // CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]] 193 // 194 // CHECK: [[WORKER]] 195 // CHECK: {{call|invoke}} void [[T2]]_worker() 196 // CHECK: br label {{%?}}[[EXIT:.+]] 197 // 198 // CHECK: [[CHECK_MASTER]] 199 // CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 200 // CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 201 // CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 202 // CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]], 203 // CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]] 204 // 205 // CHECK: [[MASTER]] 206 // CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 207 // CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 208 // CHECK: [[MTMP1:%.+]] = sub nuw i32 [[MNTH]], [[MWS]] 209 // CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]] 210 // 211 // CHECK-NOT: kmpc_fork_teams 212 // CHECK: [[AA_VAL:%.+]] = load i16, i16* [[CONV]], align 213 // CHECK: [[ACP:%.+]] = bitcast i[[SZ]]* [[AC:%.+]] to i16* 214 // CHECK: store i16 [[AA_VAL]], i16* [[ACP]], align 215 // CHECK: [[ACV:%.+]] = load i[[SZ]], i[[SZ]]* [[AC]], align 216 // CHECK: call void [[PARALLEL:@.+]](i32* %{{.+}}, i32* %{{.+}}, i[[SZ]] [[ACV]]) 217 // CHECK: br label {{%?}}[[TERMINATE:.+]] 218 // 219 // CHECK: [[TERMINATE]] 220 // CHECK: call void @__kmpc_kernel_deinit( 221 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 222 // CHECK: br label {{%?}}[[EXIT]] 223 // 224 // CHECK: [[EXIT]] 225 // CHECK: ret void 226 227 // CHECK: define internal void [[PARALLEL]](i32* noalias %{{.+}}, i32* noalias %{{.+}}, i[[SZ]] [[A_VAL:%.+]]) 228 // CHECK: [[A_ADDR:%.+]] = alloca i[[SZ]], 229 // CHECK: store i[[SZ]] [[A_VAL]], i[[SZ]]* [[A_ADDR]], 230 // CHECK: [[CONV:%.+]] = bitcast i[[SZ]]* [[A_ADDR]] to i16* 231 // CHECK: store i16 1, i16* [[CONV]], 232 // CHECK: ret void 233 234 // CHECK: define weak void @__omp_offloading_{{.*}}ftemplate{{.*}}_l37( 235 // CHECK: call void @__kmpc_spmd_kernel_init(i32 {{.+}}, i16 1) 236 // CHECK: call void @__kmpc_data_sharing_init_stack_spmd 237 // CHECK-NOT: call i8* @__kmpc_data_sharing_push_stack( 238 // CHECK-NOT: call void @__kmpc_serialized_parallel( 239 // CHECK: call void [[L0:@.+]](i32* %{{.+}}, i32* %{{.+}}, i[[SZ]] %{{.+}}) 240 // CHECK-NOT: call void @__kmpc_end_serialized_parallel( 241 // CHECK-NOT: call void @__kmpc_data_sharing_pop_stack( 242 // CHECK: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 243 // CHECK: ret 244 245 // CHECK: define internal void [[L0]](i32* noalias %{{.+}}, i32* noalias %{{.+}}, i[[SZ]] %{{.+}}) 246 // CHECK: call void [[L1:@.+]](i32* %{{.+}}, i32* %{{.+}}, i16* %{{.+}}) 247 // CHECK: ret void 248 249 // CHECK: define internal void [[L1]](i32* noalias %{{.+}}, i32* noalias %{{.+}}, i16* nonnull align {{[0-9]+}} dereferenceable 250 // CHECK: call void @__kmpc_serialized_parallel( 251 // CHECK: call void [[L2:@.+]](i32* %{{.+}}, i32* %{{.+}}, i16* %{{.+}}) 252 // CHECK: call void @__kmpc_end_serialized_parallel( 253 // CHECK: ret void 254 255 // CHECK: define internal void [[L2]](i32* noalias %{{.+}}, i32* noalias %{{.+}}, i16* nonnull align {{[0-9]+}} dereferenceable 256 // CHECK: store i16 1, i16* % 257 // CHECK: ret void 258 259 #endif 260