1 // Test target codegen - host bc file has to be created first.
2 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
7 
8 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
9 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
10 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
11 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
12 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
13 
14 // expected-no-diagnostics
15 #ifndef HEADER
16 #define HEADER
17 
18 // Check that the execution mode of all 2 target regions on the gpu is set to non-SPMD Mode.
19 // CHECK-DAG: {{@__omp_offloading_.+l28}}_exec_mode = weak constant i8 0
20 // CHECK-DAG: {{@__omp_offloading_.+l33}}_exec_mode = weak constant i8 0
21 
22 template<typename tx>
23 tx ftemplate(int n) {
24   tx a = 0;
25   short aa = 0;
26   tx b[10];
27 
28   #pragma omp target parallel map(tofrom: aa) num_threads(1024)
29   {
30     aa += 1;
31   }
32 
33   #pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40) num_threads(n)
34   {
35     a += 1;
36     aa += 1;
37     b[2] += 1;
38   }
39 
40   return a;
41 }
42 
43 int bar(int n){
44   int a = 0;
45 
46   a += ftemplate<int>(n);
47 
48   return a;
49 }
50 
51 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l28}}(
52 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
53 // CHECK: store i16* {{%.+}}, i16** [[AA_ADDR]], align
54 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
55 // CHECK: [[THREAD_LIMIT:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
56 // CHECK: call void @__kmpc_spmd_kernel_init(i32 [[THREAD_LIMIT]], i16 1)
57 // CHECK: call void @__kmpc_data_sharing_init_stack_spmd()
58 // CHECK: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @{{.+}})
59 // CHECK: store i32 [[GTID]], i32* [[THREADID:%.+]],
60 // CHECK: call void [[OUTLINED:@.+]](i32* [[THREADID]], i32* %{{.+}}, i16* [[AA]])
61 // CHECK: call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
62 // CHECK: ret void
63 // CHECK: }
64 
65 // CHECK: define internal void [[OUTLINED]](i32* noalias %{{.+}}, i32* noalias %{{.+}}, i16* {{[^%]*}}[[ARG:%.+]])
66 // CHECK: = alloca i32*, align
67 // CHECK: = alloca i32*, align
68 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
69 // CHECK: store i16* [[ARG]], i16** [[AA_ADDR]], align
70 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
71 // CHECK: [[VAL:%.+]] = load i16, i16* [[AA]], align
72 // CHECK: store i16 {{%.+}}, i16* [[AA]], align
73 // CHECK: ret void
74 // CHECK: }
75 
76 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l33}}(
77 // CHECK: [[A_ADDR:%.+]] = alloca i32*, align
78 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
79 // CHECK: [[B_ADDR:%.+]] = alloca [10 x i32]*, align
80 // CHECK: store i32* {{%.+}}, i32** [[A_ADDR]], align
81 // CHECK: store i16* {{%.+}}, i16** [[AA_ADDR]], align
82 // CHECK: store [10 x i32]* {{%.+}}, [10 x i32]** [[B_ADDR]], align
83 // CHECK: [[A:%.+]] = load i32*, i32** [[A_ADDR]], align
84 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
85 // CHECK: [[B:%.+]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align
86 // CHECK: [[THREAD_LIMIT:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
87 // CHECK: call void @__kmpc_spmd_kernel_init(i32 [[THREAD_LIMIT]], i16 1)
88 // CHECK: call void @__kmpc_data_sharing_init_stack_spmd()
89 // CHECK: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @{{.+}})
90 // CHECK: store i32 [[GTID]], i32* [[THREADID:%.+]],
91 // CHECK: call void [[OUTLINED:@.+]](i32* [[THREADID]], i32* %{{.+}}, i32* [[A]], i16* [[AA]], [10 x i32]* [[B]])
92 // CHECK: call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
93 // CHECK: ret void
94 // CHECK: }
95 
96 // CHECK: define internal void [[OUTLINED]](i32* noalias %{{.+}}, i32* noalias %{{.+}}, i32* {{[^%]*}}[[ARG1:%.+]], i16* {{[^%]*}}[[ARG2:%.+]], [10 x i32]* {{[^%]*}}[[ARG3:%.+]])
97 // CHECK: = alloca i32*, align
98 // CHECK: = alloca i32*, align
99 // CHECK: [[A_ADDR:%.+]] = alloca i32*, align
100 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
101 // CHECK: [[B_ADDR:%.+]] = alloca [10 x i32]*, align
102 // CHECK: store i32* [[ARG1]], i32** [[A_ADDR]], align
103 // CHECK: store i16* [[ARG2]], i16** [[AA_ADDR]], align
104 // CHECK: store [10 x i32]* [[ARG3]], [10 x i32]** [[B_ADDR]], align
105 // CHECK: [[A:%.+]] = load i32*, i32** [[A_ADDR]], align
106 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
107 // CHECK: [[B:%.+]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align
108 // CHECK: store i32 {{%.+}}, i32* [[A]], align
109 // CHECK: store i16 {{%.+}}, i16* [[AA]], align
110 // CHECK: [[ELT:%.+]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]],
111 // CHECK: store i32 {{%.+}}, i32* [[ELT]], align
112 // CHECK: ret void
113 // CHECK: }
114 #endif
115