1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-function-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+"
2 // Test target codegen - host bc file has to be created first.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK1
5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK2
7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK3
8 
9 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
10 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK4
11 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
12 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK5
13 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK6
14 
15 // expected-no-diagnostics
16 #ifndef HEADER
17 #define HEADER
18 
19 template<typename tx>
20 tx ftemplate(int n) {
21   tx a = 0;
22   short aa = 0;
23   tx b[10];
24 
25   #pragma omp target parallel map(tofrom: aa) num_threads(1024)
26   {
27     aa += 1;
28   }
29 
30   #pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40) num_threads(n)
31   {
32     a += 1;
33     aa += 1;
34     b[2] += 1;
35   }
36 
37   return a;
38 }
39 
40 int bar(int n){
41   int a = 0;
42 
43   a += ftemplate<int>(n);
44 
45   return a;
46 }
47 
48 #endif
49 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
50 // CHECK1-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
51 // CHECK1-NEXT:  entry:
52 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
53 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
54 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
55 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
56 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
57 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
58 // CHECK1-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
59 // CHECK1-NEXT:    br label [[DOTEXECUTE:%.*]]
60 // CHECK1:       .execute:
61 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
62 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
63 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
64 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 8
65 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
66 // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i64 1)
67 // CHECK1-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
68 // CHECK1:       .omp.deinit:
69 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
70 // CHECK1-NEXT:    br label [[DOTEXIT:%.*]]
71 // CHECK1:       .exit:
72 // CHECK1-NEXT:    ret void
73 //
74 //
75 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
76 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
77 // CHECK1-NEXT:  entry:
78 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
79 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
80 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
81 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
82 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
83 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
84 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
85 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
86 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
87 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
88 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
89 // CHECK1-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
90 // CHECK1-NEXT:    ret void
91 //
92 //
93 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
94 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
95 // CHECK1-NEXT:  entry:
96 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
97 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
98 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
99 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
100 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 8
101 // CHECK1-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
102 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
103 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
104 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
105 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
106 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
107 // CHECK1-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
108 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
109 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
110 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
111 // CHECK1-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
112 // CHECK1-NEXT:    br label [[DOTEXECUTE:%.*]]
113 // CHECK1:       .execute:
114 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
115 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
116 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
117 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
118 // CHECK1-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 8
119 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
120 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
121 // CHECK1-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 8
122 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
123 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
124 // CHECK1-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 8
125 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
126 // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i64 3)
127 // CHECK1-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
128 // CHECK1:       .omp.deinit:
129 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
130 // CHECK1-NEXT:    br label [[DOTEXIT:%.*]]
131 // CHECK1:       .exit:
132 // CHECK1-NEXT:    ret void
133 //
134 //
135 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
136 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
137 // CHECK1-NEXT:  entry:
138 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
139 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
140 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
141 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
142 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
143 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
144 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
145 // CHECK1-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
146 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
147 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
148 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
149 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
150 // CHECK1-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
151 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
152 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
153 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
154 // CHECK1-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
155 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
156 // CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
157 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
158 // CHECK1-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
159 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 2
160 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
161 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
162 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
163 // CHECK1-NEXT:    ret void
164 //
165 //
166 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
167 // CHECK2-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
168 // CHECK2-NEXT:  entry:
169 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
170 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
171 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
172 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
173 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
174 // CHECK2-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
175 // CHECK2-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
176 // CHECK2-NEXT:    br label [[DOTEXECUTE:%.*]]
177 // CHECK2:       .execute:
178 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
179 // CHECK2-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
180 // CHECK2-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
181 // CHECK2-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 4
182 // CHECK2-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
183 // CHECK2-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i32 1)
184 // CHECK2-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
185 // CHECK2:       .omp.deinit:
186 // CHECK2-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
187 // CHECK2-NEXT:    br label [[DOTEXIT:%.*]]
188 // CHECK2:       .exit:
189 // CHECK2-NEXT:    ret void
190 //
191 //
192 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
193 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
194 // CHECK2-NEXT:  entry:
195 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
196 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
197 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
198 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
199 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
200 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
201 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
202 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
203 // CHECK2-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
204 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
205 // CHECK2-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
206 // CHECK2-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
207 // CHECK2-NEXT:    ret void
208 //
209 //
210 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
211 // CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
212 // CHECK2-NEXT:  entry:
213 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
214 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
215 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
216 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
217 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
218 // CHECK2-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
219 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
220 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
221 // CHECK2-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
222 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
223 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
224 // CHECK2-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
225 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
226 // CHECK2-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
227 // CHECK2-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
228 // CHECK2-NEXT:    br label [[DOTEXECUTE:%.*]]
229 // CHECK2:       .execute:
230 // CHECK2-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
231 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
232 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
233 // CHECK2-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
234 // CHECK2-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 4
235 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
236 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
237 // CHECK2-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
238 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
239 // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
240 // CHECK2-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 4
241 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
242 // CHECK2-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3)
243 // CHECK2-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
244 // CHECK2:       .omp.deinit:
245 // CHECK2-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
246 // CHECK2-NEXT:    br label [[DOTEXIT:%.*]]
247 // CHECK2:       .exit:
248 // CHECK2-NEXT:    ret void
249 //
250 //
251 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
252 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
253 // CHECK2-NEXT:  entry:
254 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
255 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
256 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
257 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
258 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
259 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
260 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
261 // CHECK2-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
262 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
263 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
264 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
265 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
266 // CHECK2-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
267 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
268 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
269 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
270 // CHECK2-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
271 // CHECK2-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
272 // CHECK2-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
273 // CHECK2-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
274 // CHECK2-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
275 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
276 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
277 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
278 // CHECK2-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
279 // CHECK2-NEXT:    ret void
280 //
281 //
282 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
283 // CHECK3-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
284 // CHECK3-NEXT:  entry:
285 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
286 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
287 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
288 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
289 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
290 // CHECK3-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
291 // CHECK3-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
292 // CHECK3-NEXT:    br label [[DOTEXECUTE:%.*]]
293 // CHECK3:       .execute:
294 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
295 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
296 // CHECK3-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
297 // CHECK3-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 4
298 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
299 // CHECK3-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i32 1)
300 // CHECK3-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
301 // CHECK3:       .omp.deinit:
302 // CHECK3-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
303 // CHECK3-NEXT:    br label [[DOTEXIT:%.*]]
304 // CHECK3:       .exit:
305 // CHECK3-NEXT:    ret void
306 //
307 //
308 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
309 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
310 // CHECK3-NEXT:  entry:
311 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
312 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
313 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
314 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
315 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
316 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
317 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
318 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
319 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
320 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
321 // CHECK3-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
322 // CHECK3-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
323 // CHECK3-NEXT:    ret void
324 //
325 //
326 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
327 // CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
328 // CHECK3-NEXT:  entry:
329 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
330 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
331 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
332 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
333 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
334 // CHECK3-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
335 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
336 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
337 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
338 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
339 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
340 // CHECK3-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
341 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
342 // CHECK3-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
343 // CHECK3-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
344 // CHECK3-NEXT:    br label [[DOTEXECUTE:%.*]]
345 // CHECK3:       .execute:
346 // CHECK3-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
347 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
348 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
349 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
350 // CHECK3-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 4
351 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
352 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
353 // CHECK3-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
354 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
355 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
356 // CHECK3-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 4
357 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
358 // CHECK3-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3)
359 // CHECK3-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
360 // CHECK3:       .omp.deinit:
361 // CHECK3-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
362 // CHECK3-NEXT:    br label [[DOTEXIT:%.*]]
363 // CHECK3:       .exit:
364 // CHECK3-NEXT:    ret void
365 //
366 //
367 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
368 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
369 // CHECK3-NEXT:  entry:
370 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
371 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
372 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
373 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
374 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
375 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
376 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
377 // CHECK3-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
378 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
379 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
380 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
381 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
382 // CHECK3-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
383 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
384 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
385 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
386 // CHECK3-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
387 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
388 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
389 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
390 // CHECK3-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
391 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
392 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
393 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
394 // CHECK3-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
395 // CHECK3-NEXT:    ret void
396 //
397 //
398 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
399 // CHECK4-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
400 // CHECK4-NEXT:  entry:
401 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
402 // CHECK4-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
403 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
404 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
405 // CHECK4-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
406 // CHECK4-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
407 // CHECK4-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
408 // CHECK4-NEXT:    br label [[DOTEXECUTE:%.*]]
409 // CHECK4:       .execute:
410 // CHECK4-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
411 // CHECK4-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
412 // CHECK4-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
413 // CHECK4-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 8
414 // CHECK4-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
415 // CHECK4-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i64 1)
416 // CHECK4-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
417 // CHECK4:       .omp.deinit:
418 // CHECK4-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
419 // CHECK4-NEXT:    br label [[DOTEXIT:%.*]]
420 // CHECK4:       .exit:
421 // CHECK4-NEXT:    ret void
422 //
423 //
424 // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__
425 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
426 // CHECK4-NEXT:  entry:
427 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
428 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
429 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
430 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
431 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
432 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
433 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
434 // CHECK4-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
435 // CHECK4-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
436 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
437 // CHECK4-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
438 // CHECK4-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
439 // CHECK4-NEXT:    ret void
440 //
441 //
442 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
443 // CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
444 // CHECK4-NEXT:  entry:
445 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
446 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
447 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
448 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
449 // CHECK4-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 8
450 // CHECK4-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
451 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
452 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
453 // CHECK4-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
454 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
455 // CHECK4-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
456 // CHECK4-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
457 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
458 // CHECK4-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
459 // CHECK4-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
460 // CHECK4-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
461 // CHECK4-NEXT:    br label [[DOTEXECUTE:%.*]]
462 // CHECK4:       .execute:
463 // CHECK4-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
464 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
465 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
466 // CHECK4-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
467 // CHECK4-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 8
468 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
469 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
470 // CHECK4-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 8
471 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
472 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
473 // CHECK4-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 8
474 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
475 // CHECK4-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i64 3)
476 // CHECK4-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
477 // CHECK4:       .omp.deinit:
478 // CHECK4-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
479 // CHECK4-NEXT:    br label [[DOTEXIT:%.*]]
480 // CHECK4:       .exit:
481 // CHECK4-NEXT:    ret void
482 //
483 //
484 // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1
485 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
486 // CHECK4-NEXT:  entry:
487 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
488 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
489 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
490 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
491 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
492 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
493 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
494 // CHECK4-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
495 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
496 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
497 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
498 // CHECK4-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
499 // CHECK4-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
500 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
501 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
502 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
503 // CHECK4-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
504 // CHECK4-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
505 // CHECK4-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
506 // CHECK4-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
507 // CHECK4-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
508 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 2
509 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
510 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
511 // CHECK4-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
512 // CHECK4-NEXT:    ret void
513 //
514 //
515 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
516 // CHECK5-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
517 // CHECK5-NEXT:  entry:
518 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
519 // CHECK5-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
520 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
521 // CHECK5-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
522 // CHECK5-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
523 // CHECK5-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
524 // CHECK5-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
525 // CHECK5-NEXT:    br label [[DOTEXECUTE:%.*]]
526 // CHECK5:       .execute:
527 // CHECK5-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
528 // CHECK5-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
529 // CHECK5-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
530 // CHECK5-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 4
531 // CHECK5-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
532 // CHECK5-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i32 1)
533 // CHECK5-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
534 // CHECK5:       .omp.deinit:
535 // CHECK5-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
536 // CHECK5-NEXT:    br label [[DOTEXIT:%.*]]
537 // CHECK5:       .exit:
538 // CHECK5-NEXT:    ret void
539 //
540 //
541 // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__
542 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
543 // CHECK5-NEXT:  entry:
544 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
545 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
546 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
547 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
548 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
549 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
550 // CHECK5-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
551 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
552 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
553 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
554 // CHECK5-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
555 // CHECK5-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
556 // CHECK5-NEXT:    ret void
557 //
558 //
559 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
560 // CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
561 // CHECK5-NEXT:  entry:
562 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
563 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
564 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
565 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
566 // CHECK5-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
567 // CHECK5-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
568 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
569 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
570 // CHECK5-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
571 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
572 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
573 // CHECK5-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
574 // CHECK5-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
575 // CHECK5-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
576 // CHECK5-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
577 // CHECK5-NEXT:    br label [[DOTEXECUTE:%.*]]
578 // CHECK5:       .execute:
579 // CHECK5-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
580 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
581 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
582 // CHECK5-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
583 // CHECK5-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 4
584 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
585 // CHECK5-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
586 // CHECK5-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
587 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
588 // CHECK5-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
589 // CHECK5-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 4
590 // CHECK5-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
591 // CHECK5-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3)
592 // CHECK5-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
593 // CHECK5:       .omp.deinit:
594 // CHECK5-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
595 // CHECK5-NEXT:    br label [[DOTEXIT:%.*]]
596 // CHECK5:       .exit:
597 // CHECK5-NEXT:    ret void
598 //
599 //
600 // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1
601 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
602 // CHECK5-NEXT:  entry:
603 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
604 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
605 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
606 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
607 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
608 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
609 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
610 // CHECK5-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
611 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
612 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
613 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
614 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
615 // CHECK5-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
616 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
617 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
618 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
619 // CHECK5-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
620 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
621 // CHECK5-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
622 // CHECK5-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
623 // CHECK5-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
624 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
625 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
626 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
627 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
628 // CHECK5-NEXT:    ret void
629 //
630 //
631 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
632 // CHECK6-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
633 // CHECK6-NEXT:  entry:
634 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
635 // CHECK6-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
636 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
637 // CHECK6-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
638 // CHECK6-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
639 // CHECK6-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
640 // CHECK6-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
641 // CHECK6-NEXT:    br label [[DOTEXECUTE:%.*]]
642 // CHECK6:       .execute:
643 // CHECK6-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
644 // CHECK6-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
645 // CHECK6-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
646 // CHECK6-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 4
647 // CHECK6-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
648 // CHECK6-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i32 1)
649 // CHECK6-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
650 // CHECK6:       .omp.deinit:
651 // CHECK6-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
652 // CHECK6-NEXT:    br label [[DOTEXIT:%.*]]
653 // CHECK6:       .exit:
654 // CHECK6-NEXT:    ret void
655 //
656 //
657 // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__
658 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
659 // CHECK6-NEXT:  entry:
660 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
661 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
662 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
663 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
664 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
665 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
666 // CHECK6-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
667 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
668 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
669 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
670 // CHECK6-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
671 // CHECK6-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
672 // CHECK6-NEXT:    ret void
673 //
674 //
675 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
676 // CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
677 // CHECK6-NEXT:  entry:
678 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
679 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
680 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
681 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
682 // CHECK6-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
683 // CHECK6-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
684 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
685 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
686 // CHECK6-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
687 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
688 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
689 // CHECK6-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
690 // CHECK6-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
691 // CHECK6-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
692 // CHECK6-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
693 // CHECK6-NEXT:    br label [[DOTEXECUTE:%.*]]
694 // CHECK6:       .execute:
695 // CHECK6-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
696 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
697 // CHECK6-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
698 // CHECK6-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
699 // CHECK6-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 4
700 // CHECK6-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
701 // CHECK6-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
702 // CHECK6-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
703 // CHECK6-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
704 // CHECK6-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
705 // CHECK6-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 4
706 // CHECK6-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
707 // CHECK6-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3)
708 // CHECK6-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
709 // CHECK6:       .omp.deinit:
710 // CHECK6-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
711 // CHECK6-NEXT:    br label [[DOTEXIT:%.*]]
712 // CHECK6:       .exit:
713 // CHECK6-NEXT:    ret void
714 //
715 //
716 // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1
717 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
718 // CHECK6-NEXT:  entry:
719 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
720 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
721 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
722 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
723 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
724 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
725 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
726 // CHECK6-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
727 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
728 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
729 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
730 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
731 // CHECK6-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
732 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
733 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
734 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
735 // CHECK6-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
736 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
737 // CHECK6-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
738 // CHECK6-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
739 // CHECK6-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
740 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
741 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
742 // CHECK6-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
743 // CHECK6-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
744 // CHECK6-NEXT:    ret void
745 //
746