1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test target codegen - host bc file has to be created first.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2
7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK3
8 
9 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
10 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK4
11 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
12 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK5
13 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK6
14 
15 // expected-no-diagnostics
16 #ifndef HEADER
17 #define HEADER
18 
19 template<typename tx>
20 tx ftemplate(int n) {
21   tx a = 0;
22   short aa = 0;
23   tx b[10];
24 
25   #pragma omp target parallel map(tofrom: aa) num_threads(1024)
26   {
27     aa += 1;
28   }
29 
30   #pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40) num_threads(n)
31   {
32     a += 1;
33     aa += 1;
34     b[2] += 1;
35   }
36 
37   return a;
38 }
39 
40 int bar(int n){
41   int a = 0;
42 
43   a += ftemplate<int>(n);
44 
45   return a;
46 }
47 
48 #endif
49 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
50 // CHECK1-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
51 // CHECK1-NEXT:  entry:
52 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
53 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
54 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
55 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
56 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
57 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
58 // CHECK1-NEXT:    br label [[DOTEXECUTE:%.*]]
59 // CHECK1:       .execute:
60 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
61 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
62 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
63 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 8
64 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
65 // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i64 1)
66 // CHECK1-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
67 // CHECK1:       .omp.deinit:
68 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
69 // CHECK1-NEXT:    br label [[DOTEXIT:%.*]]
70 // CHECK1:       .exit:
71 // CHECK1-NEXT:    ret void
72 //
73 //
74 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
75 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
76 // CHECK1-NEXT:  entry:
77 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
78 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
79 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
80 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
81 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
82 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
83 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
84 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
85 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
86 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
87 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
88 // CHECK1-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
89 // CHECK1-NEXT:    ret void
90 //
91 //
92 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
93 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
94 // CHECK1-NEXT:  entry:
95 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
96 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
97 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
98 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
99 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 8
100 // CHECK1-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
101 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
102 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
103 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
104 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
105 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
106 // CHECK1-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
107 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
108 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
109 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
110 // CHECK1-NEXT:    br label [[DOTEXECUTE:%.*]]
111 // CHECK1:       .execute:
112 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
113 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
114 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
115 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
116 // CHECK1-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 8
117 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
118 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
119 // CHECK1-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 8
120 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
121 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
122 // CHECK1-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 8
123 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
124 // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i64 3)
125 // CHECK1-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
126 // CHECK1:       .omp.deinit:
127 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
128 // CHECK1-NEXT:    br label [[DOTEXIT:%.*]]
129 // CHECK1:       .exit:
130 // CHECK1-NEXT:    ret void
131 //
132 //
133 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
134 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
135 // CHECK1-NEXT:  entry:
136 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
137 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
138 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
139 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
140 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
141 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
142 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
143 // CHECK1-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
144 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
145 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
146 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
147 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
148 // CHECK1-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
149 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
150 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
151 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
152 // CHECK1-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
153 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
154 // CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
155 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
156 // CHECK1-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
157 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 2
158 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
159 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
160 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
161 // CHECK1-NEXT:    ret void
162 //
163 //
164 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
165 // CHECK2-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
166 // CHECK2-NEXT:  entry:
167 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
168 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
169 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
170 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
171 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
172 // CHECK2-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
173 // CHECK2-NEXT:    br label [[DOTEXECUTE:%.*]]
174 // CHECK2:       .execute:
175 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
176 // CHECK2-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
177 // CHECK2-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
178 // CHECK2-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 4
179 // CHECK2-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
180 // CHECK2-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i32 1)
181 // CHECK2-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
182 // CHECK2:       .omp.deinit:
183 // CHECK2-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
184 // CHECK2-NEXT:    br label [[DOTEXIT:%.*]]
185 // CHECK2:       .exit:
186 // CHECK2-NEXT:    ret void
187 //
188 //
189 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
190 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
191 // CHECK2-NEXT:  entry:
192 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
193 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
194 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
195 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
196 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
197 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
198 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
199 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
200 // CHECK2-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
201 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
202 // CHECK2-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
203 // CHECK2-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
204 // CHECK2-NEXT:    ret void
205 //
206 //
207 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
208 // CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
209 // CHECK2-NEXT:  entry:
210 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
211 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
212 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
213 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
214 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
215 // CHECK2-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
216 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
217 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
218 // CHECK2-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
219 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
220 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
221 // CHECK2-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
222 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
223 // CHECK2-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
224 // CHECK2-NEXT:    br label [[DOTEXECUTE:%.*]]
225 // CHECK2:       .execute:
226 // CHECK2-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
227 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
228 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
229 // CHECK2-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
230 // CHECK2-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 4
231 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
232 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
233 // CHECK2-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
234 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
235 // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
236 // CHECK2-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 4
237 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
238 // CHECK2-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3)
239 // CHECK2-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
240 // CHECK2:       .omp.deinit:
241 // CHECK2-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
242 // CHECK2-NEXT:    br label [[DOTEXIT:%.*]]
243 // CHECK2:       .exit:
244 // CHECK2-NEXT:    ret void
245 //
246 //
247 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
248 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
249 // CHECK2-NEXT:  entry:
250 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
251 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
252 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
253 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
254 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
255 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
256 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
257 // CHECK2-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
258 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
259 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
260 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
261 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
262 // CHECK2-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
263 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
264 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
265 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
266 // CHECK2-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
267 // CHECK2-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
268 // CHECK2-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
269 // CHECK2-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
270 // CHECK2-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
271 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
272 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
273 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
274 // CHECK2-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
275 // CHECK2-NEXT:    ret void
276 //
277 //
278 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
279 // CHECK3-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
280 // CHECK3-NEXT:  entry:
281 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
282 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
283 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
284 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
285 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
286 // CHECK3-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
287 // CHECK3-NEXT:    br label [[DOTEXECUTE:%.*]]
288 // CHECK3:       .execute:
289 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
290 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
291 // CHECK3-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
292 // CHECK3-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 4
293 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
294 // CHECK3-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i32 1)
295 // CHECK3-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
296 // CHECK3:       .omp.deinit:
297 // CHECK3-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
298 // CHECK3-NEXT:    br label [[DOTEXIT:%.*]]
299 // CHECK3:       .exit:
300 // CHECK3-NEXT:    ret void
301 //
302 //
303 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
304 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
305 // CHECK3-NEXT:  entry:
306 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
307 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
308 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
309 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
310 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
311 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
312 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
313 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
314 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
315 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
316 // CHECK3-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
317 // CHECK3-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
318 // CHECK3-NEXT:    ret void
319 //
320 //
321 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
322 // CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
323 // CHECK3-NEXT:  entry:
324 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
325 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
326 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
327 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
328 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
329 // CHECK3-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
330 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
331 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
332 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
333 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
334 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
335 // CHECK3-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
336 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
337 // CHECK3-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
338 // CHECK3-NEXT:    br label [[DOTEXECUTE:%.*]]
339 // CHECK3:       .execute:
340 // CHECK3-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
341 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
342 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
343 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
344 // CHECK3-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 4
345 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
346 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
347 // CHECK3-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
348 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
349 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
350 // CHECK3-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 4
351 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
352 // CHECK3-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3)
353 // CHECK3-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
354 // CHECK3:       .omp.deinit:
355 // CHECK3-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
356 // CHECK3-NEXT:    br label [[DOTEXIT:%.*]]
357 // CHECK3:       .exit:
358 // CHECK3-NEXT:    ret void
359 //
360 //
361 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
362 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
363 // CHECK3-NEXT:  entry:
364 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
365 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
366 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
367 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
368 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
369 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
370 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
371 // CHECK3-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
372 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
373 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
374 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
375 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
376 // CHECK3-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
377 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
378 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
379 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
380 // CHECK3-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
381 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
382 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
383 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
384 // CHECK3-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
385 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
386 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
387 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
388 // CHECK3-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
389 // CHECK3-NEXT:    ret void
390 //
391 //
392 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
393 // CHECK4-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
394 // CHECK4-NEXT:  entry:
395 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
396 // CHECK4-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
397 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
398 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
399 // CHECK4-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
400 // CHECK4-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
401 // CHECK4-NEXT:    br label [[DOTEXECUTE:%.*]]
402 // CHECK4:       .execute:
403 // CHECK4-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
404 // CHECK4-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
405 // CHECK4-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
406 // CHECK4-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 8
407 // CHECK4-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
408 // CHECK4-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i64 1)
409 // CHECK4-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
410 // CHECK4:       .omp.deinit:
411 // CHECK4-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
412 // CHECK4-NEXT:    br label [[DOTEXIT:%.*]]
413 // CHECK4:       .exit:
414 // CHECK4-NEXT:    ret void
415 //
416 //
417 // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__
418 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
419 // CHECK4-NEXT:  entry:
420 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
421 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
422 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
423 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
424 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
425 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
426 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
427 // CHECK4-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
428 // CHECK4-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
429 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
430 // CHECK4-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
431 // CHECK4-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
432 // CHECK4-NEXT:    ret void
433 //
434 //
435 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
436 // CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
437 // CHECK4-NEXT:  entry:
438 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
439 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
440 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
441 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
442 // CHECK4-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 8
443 // CHECK4-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
444 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
445 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
446 // CHECK4-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
447 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
448 // CHECK4-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
449 // CHECK4-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
450 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
451 // CHECK4-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
452 // CHECK4-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
453 // CHECK4-NEXT:    br label [[DOTEXECUTE:%.*]]
454 // CHECK4:       .execute:
455 // CHECK4-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
456 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
457 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
458 // CHECK4-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
459 // CHECK4-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 8
460 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
461 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
462 // CHECK4-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 8
463 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
464 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
465 // CHECK4-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 8
466 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
467 // CHECK4-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i64 3)
468 // CHECK4-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
469 // CHECK4:       .omp.deinit:
470 // CHECK4-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
471 // CHECK4-NEXT:    br label [[DOTEXIT:%.*]]
472 // CHECK4:       .exit:
473 // CHECK4-NEXT:    ret void
474 //
475 //
476 // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1
477 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
478 // CHECK4-NEXT:  entry:
479 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
480 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
481 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
482 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
483 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
484 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
485 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
486 // CHECK4-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
487 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
488 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
489 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
490 // CHECK4-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
491 // CHECK4-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
492 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
493 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
494 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
495 // CHECK4-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
496 // CHECK4-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
497 // CHECK4-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
498 // CHECK4-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
499 // CHECK4-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
500 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 2
501 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
502 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
503 // CHECK4-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
504 // CHECK4-NEXT:    ret void
505 //
506 //
507 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
508 // CHECK5-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
509 // CHECK5-NEXT:  entry:
510 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
511 // CHECK5-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
512 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
513 // CHECK5-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
514 // CHECK5-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
515 // CHECK5-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
516 // CHECK5-NEXT:    br label [[DOTEXECUTE:%.*]]
517 // CHECK5:       .execute:
518 // CHECK5-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
519 // CHECK5-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
520 // CHECK5-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
521 // CHECK5-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 4
522 // CHECK5-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
523 // CHECK5-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i32 1)
524 // CHECK5-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
525 // CHECK5:       .omp.deinit:
526 // CHECK5-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
527 // CHECK5-NEXT:    br label [[DOTEXIT:%.*]]
528 // CHECK5:       .exit:
529 // CHECK5-NEXT:    ret void
530 //
531 //
532 // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__
533 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
534 // CHECK5-NEXT:  entry:
535 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
536 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
537 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
538 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
539 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
540 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
541 // CHECK5-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
542 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
543 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
544 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
545 // CHECK5-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
546 // CHECK5-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
547 // CHECK5-NEXT:    ret void
548 //
549 //
550 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
551 // CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
552 // CHECK5-NEXT:  entry:
553 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
554 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
555 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
556 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
557 // CHECK5-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
558 // CHECK5-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
559 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
560 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
561 // CHECK5-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
562 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
563 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
564 // CHECK5-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
565 // CHECK5-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
566 // CHECK5-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
567 // CHECK5-NEXT:    br label [[DOTEXECUTE:%.*]]
568 // CHECK5:       .execute:
569 // CHECK5-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
570 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
571 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
572 // CHECK5-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
573 // CHECK5-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 4
574 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
575 // CHECK5-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
576 // CHECK5-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
577 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
578 // CHECK5-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
579 // CHECK5-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 4
580 // CHECK5-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
581 // CHECK5-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3)
582 // CHECK5-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
583 // CHECK5:       .omp.deinit:
584 // CHECK5-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
585 // CHECK5-NEXT:    br label [[DOTEXIT:%.*]]
586 // CHECK5:       .exit:
587 // CHECK5-NEXT:    ret void
588 //
589 //
590 // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1
591 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
592 // CHECK5-NEXT:  entry:
593 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
594 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
595 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
596 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
597 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
598 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
599 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
600 // CHECK5-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
601 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
602 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
603 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
604 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
605 // CHECK5-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
606 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
607 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
608 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
609 // CHECK5-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
610 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
611 // CHECK5-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
612 // CHECK5-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
613 // CHECK5-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
614 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
615 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
616 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
617 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
618 // CHECK5-NEXT:    ret void
619 //
620 //
621 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
622 // CHECK6-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
623 // CHECK6-NEXT:  entry:
624 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
625 // CHECK6-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
626 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
627 // CHECK6-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
628 // CHECK6-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
629 // CHECK6-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
630 // CHECK6-NEXT:    br label [[DOTEXECUTE:%.*]]
631 // CHECK6:       .execute:
632 // CHECK6-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
633 // CHECK6-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
634 // CHECK6-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
635 // CHECK6-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 4
636 // CHECK6-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
637 // CHECK6-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i32 1)
638 // CHECK6-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
639 // CHECK6:       .omp.deinit:
640 // CHECK6-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
641 // CHECK6-NEXT:    br label [[DOTEXIT:%.*]]
642 // CHECK6:       .exit:
643 // CHECK6-NEXT:    ret void
644 //
645 //
646 // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__
647 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
648 // CHECK6-NEXT:  entry:
649 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
650 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
651 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
652 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
653 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
654 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
655 // CHECK6-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
656 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
657 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
658 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
659 // CHECK6-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
660 // CHECK6-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
661 // CHECK6-NEXT:    ret void
662 //
663 //
664 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
665 // CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
666 // CHECK6-NEXT:  entry:
667 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
668 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
669 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
670 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
671 // CHECK6-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
672 // CHECK6-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
673 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
674 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
675 // CHECK6-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
676 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
677 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
678 // CHECK6-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
679 // CHECK6-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
680 // CHECK6-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
681 // CHECK6-NEXT:    br label [[DOTEXECUTE:%.*]]
682 // CHECK6:       .execute:
683 // CHECK6-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
684 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
685 // CHECK6-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
686 // CHECK6-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
687 // CHECK6-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 4
688 // CHECK6-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
689 // CHECK6-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
690 // CHECK6-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
691 // CHECK6-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
692 // CHECK6-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
693 // CHECK6-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 4
694 // CHECK6-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
695 // CHECK6-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3)
696 // CHECK6-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
697 // CHECK6:       .omp.deinit:
698 // CHECK6-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
699 // CHECK6-NEXT:    br label [[DOTEXIT:%.*]]
700 // CHECK6:       .exit:
701 // CHECK6-NEXT:    ret void
702 //
703 //
704 // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1
705 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
706 // CHECK6-NEXT:  entry:
707 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
708 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
709 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
710 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
711 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
712 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
713 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
714 // CHECK6-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
715 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
716 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
717 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
718 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
719 // CHECK6-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
720 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
721 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
722 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
723 // CHECK6-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
724 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
725 // CHECK6-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
726 // CHECK6-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
727 // CHECK6-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
728 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
729 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
730 // CHECK6-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
731 // CHECK6-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
732 // CHECK6-NEXT:    ret void
733 //
734