1 // Test target codegen - host bc file has to be created first. 2 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 7 // expected-no-diagnostics 8 #ifndef HEADER 9 #define HEADER 10 11 // Check that the execution mode of all 2 target regions on the gpu is set to non-SPMD Mode. 12 // CHECK-DAG: {{@__omp_offloading_.+l21}}_exec_mode = weak constant i8 1 13 // CHECK-DAG: {{@__omp_offloading_.+l26}}_exec_mode = weak constant i8 1 14 15 template<typename tx> 16 tx ftemplate(int n) { 17 tx a = 0; 18 short aa = 0; 19 tx b[10]; 20 21 #pragma omp target parallel map(tofrom: aa) num_threads(1024) 22 { 23 aa += 1; 24 } 25 26 #pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40) num_threads(n) 27 { 28 a += 1; 29 aa += 1; 30 b[2] += 1; 31 } 32 33 return a; 34 } 35 36 int bar(int n){ 37 int a = 0; 38 39 a += ftemplate<int>(n); 40 41 return a; 42 } 43 44 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l21}}( 45 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align 46 // CHECK: store i16* {{%.+}}, i16** [[AA_ADDR]], align 47 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align 48 // CHECK: [[THREAD_LIMIT:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 49 // CHECK: call void @__kmpc_kernel_init(i32 50 // CHECK: call void @__kmpc_push_num_threads 51 // CHECK: call void @__kmpc_kernel_deinit(i16 1) 52 // CHECK: ret void 53 // CHECK: } 54 55 // CHECK: define internal void @{{.+}}(i32* noalias %{{.+}}, i32* noalias %{{.+}}, i16* {{[^%]*}}[[ARG:%.+]]) 56 // CHECK: = alloca i32*, align 57 // CHECK: = alloca i32*, align 58 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align 59 // CHECK: store i16* [[ARG]], i16** [[AA_ADDR]], align 60 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align 61 // CHECK: [[VAL:%.+]] = load i16, i16* [[AA]], align 62 // CHECK: store i16 {{%.+}}, i16* [[AA]], align 63 // CHECK: ret void 64 // CHECK: } 65 66 67 68 69 70 71 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l26}}( 72 // CHECK: [[A_ADDR:%.+]] = alloca i32*, align 73 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align 74 // CHECK: [[B_ADDR:%.+]] = alloca [10 x i32]*, align 75 // CHECK: store i32* {{%.+}}, i32** [[A_ADDR]], align 76 // CHECK: store i16* {{%.+}}, i16** [[AA_ADDR]], align 77 // CHECK: store [10 x i32]* {{%.+}}, [10 x i32]** [[B_ADDR]], align 78 // CHECK: [[A:%.+]] = load i32*, i32** [[A_ADDR]], align 79 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align 80 // CHECK: [[B:%.+]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 81 // CHECK: [[THREAD_LIMIT:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 82 // CHECK: call void @__kmpc_kernel_init(i32 83 // CHECK: call void @__kmpc_push_num_threads 84 // CHECK: call void @__kmpc_kernel_deinit(i16 1) 85 // CHECK: ret void 86 // CHECK: } 87 88 // CHECK: define internal void @{{.+}}(i32* noalias %{{.+}}, i32* noalias %{{.+}}, i32* {{[^%]*}}[[ARG1:%.+]], i16* {{[^%]*}}[[ARG2:%.+]], [10 x i32]* {{[^%]*}}[[ARG3:%.+]]) 89 // CHECK: = alloca i32*, align 90 // CHECK: = alloca i32*, align 91 // CHECK: [[A_ADDR:%.+]] = alloca i32*, align 92 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align 93 // CHECK: [[B_ADDR:%.+]] = alloca [10 x i32]*, align 94 // CHECK: store i32* [[ARG1]], i32** [[A_ADDR]], align 95 // CHECK: store i16* [[ARG2]], i16** [[AA_ADDR]], align 96 // CHECK: store [10 x i32]* [[ARG3]], [10 x i32]** [[B_ADDR]], align 97 // CHECK: [[A:%.+]] = load i32*, i32** [[A_ADDR]], align 98 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align 99 // CHECK: [[B:%.+]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 100 // CHECK: store i32 {{%.+}}, i32* [[A]], align 101 // CHECK: store i16 {{%.+}}, i16* [[AA]], align 102 // CHECK: [[ELT:%.+]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], 103 // CHECK: store i32 {{%.+}}, i32* [[ELT]], align 104 // CHECK: ret void 105 // CHECK: } 106 #endif 107