1 // Test target codegen - host bc file has to be created first. 2 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 7 8 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 9 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 10 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 11 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 12 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 13 14 // expected-no-diagnostics 15 #ifndef HEADER 16 #define HEADER 17 18 // Check that the execution mode of all 2 target regions on the gpu is set to SPMD Mode. 19 // CHECK-DAG: {{@__omp_offloading_.+l33}}_exec_mode = weak constant i8 0 20 // CHECK-DAG: {{@__omp_offloading_.+l38}}_exec_mode = weak constant i8 0 21 22 template<typename tx> 23 tx ftemplate(int n) { 24 tx a = 0; 25 short aa = 0; 26 tx b[10]; 27 28 #pragma omp target parallel if(target: 0) 29 { 30 a += 1; 31 } 32 33 #pragma omp target parallel map(tofrom: aa) 34 { 35 aa += 1; 36 } 37 38 #pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40) 39 { 40 a += 1; 41 aa += 1; 42 b[2] += 1; 43 } 44 45 return a; 46 } 47 48 int bar(int n){ 49 int a = 0; 50 51 a += ftemplate<int>(n); 52 53 return a; 54 } 55 56 // CHECK-NOT: define {{.*}}void {{@__omp_offloading_.+template.+l17}} 57 58 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l33}}( 59 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align 60 // CHECK-NOT: call i8* @__kmpc_data_sharing_push_stack 61 // CHECK: store i16* {{%.+}}, i16** [[AA_ADDR]], align 62 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align 63 // CHECK: [[THREAD_LIMIT:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 64 // CHECK: call void @__kmpc_spmd_kernel_init(i32 [[THREAD_LIMIT]], i16 1) 65 // CHECK: call void @__kmpc_data_sharing_init_stack_spmd 66 // CHECK: br label {{%?}}[[EXEC:.+]] 67 // 68 // CHECK: [[EXEC]] 69 // CHECK: {{call|invoke}} void [[OP1:@.+]]({{.+}}, {{.+}}, i16* [[AA]]) 70 // CHECK: br label {{%?}}[[DONE:.+]] 71 // 72 // CHECK: [[DONE]] 73 // CHECK: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 74 // CHECK: br label {{%?}}[[EXIT:.+]] 75 // 76 // CHECK: [[EXIT]] 77 // CHECK: ret void 78 // CHECK: } 79 80 // CHECK: define internal void [[OP1]](i32* noalias %.global_tid., i32* noalias %.bound_tid., i16* {{[^%]*}}[[ARG:%.+]]) 81 // CHECK: = alloca i32*, align 82 // CHECK: = alloca i32*, align 83 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align 84 // CHECK: store i16* [[ARG]], i16** [[AA_ADDR]], align 85 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align 86 // CHECK: [[VAL:%.+]] = load i16, i16* [[AA]], align 87 // CHECK: store i16 {{%.+}}, i16* [[AA]], align 88 // CHECK: ret void 89 // CHECK: } 90 91 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l38}}( 92 // CHECK: [[A_ADDR:%.+]] = alloca i32*, align 93 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align 94 // CHECK: [[B_ADDR:%.+]] = alloca [10 x i32]*, align 95 // CHECK: store i32* {{%.+}}, i32** [[A_ADDR]], align 96 // CHECK: store i16* {{%.+}}, i16** [[AA_ADDR]], align 97 // CHECK: store [10 x i32]* {{%.+}}, [10 x i32]** [[B_ADDR]], align 98 // CHECK: [[A:%.+]] = load i32*, i32** [[A_ADDR]], align 99 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align 100 // CHECK: [[B:%.+]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 101 // CHECK: [[THREAD_LIMIT:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 102 // CHECK: call void @__kmpc_spmd_kernel_init(i32 [[THREAD_LIMIT]], i16 1) 103 // CHECK: call void @__kmpc_data_sharing_init_stack_spmd 104 // CHECK: br label {{%?}}[[EXEC:.+]] 105 // 106 // CHECK: [[EXEC]] 107 // CHECK: {{call|invoke}} void [[OP2:@.+]]({{.+}}, {{.+}}, i32* [[A]], i16* [[AA]], [10 x i32]* [[B]]) 108 // CHECK: br label {{%?}}[[DONE:.+]] 109 // 110 // CHECK: [[DONE]] 111 // CHECK: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 112 // CHECK: br label {{%?}}[[EXIT:.+]] 113 // 114 // CHECK: [[EXIT]] 115 // CHECK: ret void 116 // CHECK: } 117 118 // CHECK: define internal void [[OP2]](i32* noalias %.global_tid., i32* noalias %.bound_tid., i32* {{[^%]*}}[[ARG1:%.+]], i16* {{[^%]*}}[[ARG2:%.+]], [10 x i32]* {{[^%]*}}[[ARG3:%.+]]) 119 // CHECK: = alloca i32*, align 120 // CHECK: = alloca i32*, align 121 // CHECK: [[A_ADDR:%.+]] = alloca i32*, align 122 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align 123 // CHECK: [[B_ADDR:%.+]] = alloca [10 x i32]*, align 124 // CHECK: store i32* [[ARG1]], i32** [[A_ADDR]], align 125 // CHECK: store i16* [[ARG2]], i16** [[AA_ADDR]], align 126 // CHECK: store [10 x i32]* [[ARG3]], [10 x i32]** [[B_ADDR]], align 127 // CHECK: [[A:%.+]] = load i32*, i32** [[A_ADDR]], align 128 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align 129 // CHECK: [[B:%.+]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 130 // CHECK: store i32 {{%.+}}, i32* [[A]], align 131 // CHECK: store i16 {{%.+}}, i16* [[AA]], align 132 // CHECK: [[ELT:%.+]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], 133 // CHECK: store i32 {{%.+}}, i32* [[ELT]], align 134 // CHECK: ret void 135 // CHECK: } 136 #endif 137