1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test target codegen - host bc file has to be created first.
3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
4 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2
7 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK3
8 
9 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK4
11 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
12 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK5
13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK6
14 
15 // expected-no-diagnostics
16 #ifndef HEADER
17 #define HEADER
18 
19 template<typename tx>
20 tx ftemplate(int n) {
21   tx a = 0;
22   short aa = 0;
23   tx b[10];
24 
25   #pragma omp target parallel if(target: 0)
26   {
27     a += 1;
28   }
29 
30   #pragma omp target parallel map(tofrom: aa)
31   {
32     aa += 1;
33   }
34 
35   #pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40)
36   {
37     a += 1;
38     aa += 1;
39     b[2] += 1;
40   }
41 
42   return a;
43 }
44 
45 int bar(int n){
46   int a = 0;
47 
48   a += ftemplate<int>(n);
49 
50   return a;
51 }
52 
53 #endif
54 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
55 // CHECK1-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
56 // CHECK1-NEXT:  entry:
57 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
58 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
59 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
60 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
61 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)
62 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
63 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
64 // CHECK1:       user_code.entry:
65 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
66 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
67 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8*
68 // CHECK1-NEXT:    store i8* [[TMP4]], i8** [[TMP3]], align 8
69 // CHECK1-NEXT:    [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
70 // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i64 1)
71 // CHECK1-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
72 // CHECK1-NEXT:    ret void
73 // CHECK1:       worker.exit:
74 // CHECK1-NEXT:    ret void
75 //
76 //
77 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
78 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
79 // CHECK1-NEXT:  entry:
80 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
81 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
82 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
83 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
84 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
85 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
86 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
87 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
88 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
89 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
90 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
91 // CHECK1-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
92 // CHECK1-NEXT:    ret void
93 //
94 //
95 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
96 // CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
97 // CHECK1-NEXT:  entry:
98 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
99 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
100 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
101 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 8
102 // CHECK1-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
103 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
104 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
105 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
106 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
107 // CHECK1-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
108 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true)
109 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
110 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
111 // CHECK1:       user_code.entry:
112 // CHECK1-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
113 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
114 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
115 // CHECK1-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 8
116 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
117 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
118 // CHECK1-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 8
119 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
120 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
121 // CHECK1-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 8
122 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
123 // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i64 3)
124 // CHECK1-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
125 // CHECK1-NEXT:    ret void
126 // CHECK1:       worker.exit:
127 // CHECK1-NEXT:    ret void
128 //
129 //
130 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
131 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
132 // CHECK1-NEXT:  entry:
133 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
134 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
135 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
136 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
137 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
138 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
139 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
140 // CHECK1-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
141 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
142 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
143 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
144 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
145 // CHECK1-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
146 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
147 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
148 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
149 // CHECK1-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
150 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
151 // CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
152 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
153 // CHECK1-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
154 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 2
155 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
156 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
157 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
158 // CHECK1-NEXT:    ret void
159 //
160 //
161 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
162 // CHECK2-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
163 // CHECK2-NEXT:  entry:
164 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
165 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
166 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
167 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
168 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)
169 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
170 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
171 // CHECK2:       user_code.entry:
172 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
173 // CHECK2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
174 // CHECK2-NEXT:    [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8*
175 // CHECK2-NEXT:    store i8* [[TMP4]], i8** [[TMP3]], align 4
176 // CHECK2-NEXT:    [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
177 // CHECK2-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1)
178 // CHECK2-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
179 // CHECK2-NEXT:    ret void
180 // CHECK2:       worker.exit:
181 // CHECK2-NEXT:    ret void
182 //
183 //
184 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
185 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
186 // CHECK2-NEXT:  entry:
187 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
188 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
189 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
190 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
191 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
192 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
193 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
194 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
195 // CHECK2-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
196 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
197 // CHECK2-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
198 // CHECK2-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
199 // CHECK2-NEXT:    ret void
200 //
201 //
202 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
203 // CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
204 // CHECK2-NEXT:  entry:
205 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
206 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
207 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
208 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
209 // CHECK2-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
210 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
211 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
212 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
213 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
214 // CHECK2-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
215 // CHECK2-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true)
216 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
217 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
218 // CHECK2:       user_code.entry:
219 // CHECK2-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
220 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
221 // CHECK2-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
222 // CHECK2-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 4
223 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
224 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
225 // CHECK2-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
226 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
227 // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
228 // CHECK2-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 4
229 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
230 // CHECK2-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3)
231 // CHECK2-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
232 // CHECK2-NEXT:    ret void
233 // CHECK2:       worker.exit:
234 // CHECK2-NEXT:    ret void
235 //
236 //
237 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
238 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
239 // CHECK2-NEXT:  entry:
240 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
241 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
242 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
243 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
244 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
245 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
246 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
247 // CHECK2-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
248 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
249 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
250 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
251 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
252 // CHECK2-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
253 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
254 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
255 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
256 // CHECK2-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
257 // CHECK2-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
258 // CHECK2-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
259 // CHECK2-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
260 // CHECK2-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
261 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
262 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
263 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
264 // CHECK2-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
265 // CHECK2-NEXT:    ret void
266 //
267 //
268 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
269 // CHECK3-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
270 // CHECK3-NEXT:  entry:
271 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
272 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
273 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
274 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
275 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)
276 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
277 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
278 // CHECK3:       user_code.entry:
279 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
280 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
281 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8*
282 // CHECK3-NEXT:    store i8* [[TMP4]], i8** [[TMP3]], align 4
283 // CHECK3-NEXT:    [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
284 // CHECK3-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1)
285 // CHECK3-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
286 // CHECK3-NEXT:    ret void
287 // CHECK3:       worker.exit:
288 // CHECK3-NEXT:    ret void
289 //
290 //
291 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
292 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
293 // CHECK3-NEXT:  entry:
294 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
295 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
296 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
297 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
298 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
299 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
300 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
301 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
302 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
303 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
304 // CHECK3-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
305 // CHECK3-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
306 // CHECK3-NEXT:    ret void
307 //
308 //
309 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
310 // CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
311 // CHECK3-NEXT:  entry:
312 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
313 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
314 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
315 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
316 // CHECK3-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
317 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
318 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
319 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
320 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
321 // CHECK3-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
322 // CHECK3-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true)
323 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
324 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
325 // CHECK3:       user_code.entry:
326 // CHECK3-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
327 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
328 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
329 // CHECK3-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 4
330 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
331 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
332 // CHECK3-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
333 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
334 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
335 // CHECK3-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 4
336 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
337 // CHECK3-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3)
338 // CHECK3-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
339 // CHECK3-NEXT:    ret void
340 // CHECK3:       worker.exit:
341 // CHECK3-NEXT:    ret void
342 //
343 //
344 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
345 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
346 // CHECK3-NEXT:  entry:
347 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
348 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
349 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
350 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
351 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
352 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
353 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
354 // CHECK3-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
355 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
356 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
357 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
358 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
359 // CHECK3-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
360 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
361 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
362 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
363 // CHECK3-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
364 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
365 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
366 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
367 // CHECK3-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
368 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
369 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
370 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
371 // CHECK3-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
372 // CHECK3-NEXT:    ret void
373 //
374 //
375 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
376 // CHECK4-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
377 // CHECK4-NEXT:  entry:
378 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
379 // CHECK4-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
380 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
381 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
382 // CHECK4-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)
383 // CHECK4-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
384 // CHECK4-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
385 // CHECK4:       user_code.entry:
386 // CHECK4-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
387 // CHECK4-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
388 // CHECK4-NEXT:    [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8*
389 // CHECK4-NEXT:    store i8* [[TMP4]], i8** [[TMP3]], align 8
390 // CHECK4-NEXT:    [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
391 // CHECK4-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i64 1)
392 // CHECK4-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
393 // CHECK4-NEXT:    ret void
394 // CHECK4:       worker.exit:
395 // CHECK4-NEXT:    ret void
396 //
397 //
398 // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__
399 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
400 // CHECK4-NEXT:  entry:
401 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
402 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
403 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
404 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
405 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
406 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
407 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
408 // CHECK4-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
409 // CHECK4-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
410 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
411 // CHECK4-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
412 // CHECK4-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
413 // CHECK4-NEXT:    ret void
414 //
415 //
416 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
417 // CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
418 // CHECK4-NEXT:  entry:
419 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
420 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
421 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
422 // CHECK4-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 8
423 // CHECK4-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
424 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
425 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
426 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
427 // CHECK4-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
428 // CHECK4-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
429 // CHECK4-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true)
430 // CHECK4-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
431 // CHECK4-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
432 // CHECK4:       user_code.entry:
433 // CHECK4-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
434 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
435 // CHECK4-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
436 // CHECK4-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 8
437 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
438 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
439 // CHECK4-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 8
440 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
441 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
442 // CHECK4-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 8
443 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
444 // CHECK4-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i64 3)
445 // CHECK4-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
446 // CHECK4-NEXT:    ret void
447 // CHECK4:       worker.exit:
448 // CHECK4-NEXT:    ret void
449 //
450 //
451 // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1
452 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
453 // CHECK4-NEXT:  entry:
454 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
455 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
456 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
457 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
458 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
459 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
460 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
461 // CHECK4-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
462 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
463 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
464 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
465 // CHECK4-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
466 // CHECK4-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
467 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
468 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
469 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
470 // CHECK4-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
471 // CHECK4-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
472 // CHECK4-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
473 // CHECK4-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
474 // CHECK4-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
475 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 2
476 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
477 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
478 // CHECK4-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
479 // CHECK4-NEXT:    ret void
480 //
481 //
482 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
483 // CHECK5-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
484 // CHECK5-NEXT:  entry:
485 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
486 // CHECK5-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
487 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
488 // CHECK5-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
489 // CHECK5-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)
490 // CHECK5-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
491 // CHECK5-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
492 // CHECK5:       user_code.entry:
493 // CHECK5-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
494 // CHECK5-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
495 // CHECK5-NEXT:    [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8*
496 // CHECK5-NEXT:    store i8* [[TMP4]], i8** [[TMP3]], align 4
497 // CHECK5-NEXT:    [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
498 // CHECK5-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1)
499 // CHECK5-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
500 // CHECK5-NEXT:    ret void
501 // CHECK5:       worker.exit:
502 // CHECK5-NEXT:    ret void
503 //
504 //
505 // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__
506 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
507 // CHECK5-NEXT:  entry:
508 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
509 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
510 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
511 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
512 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
513 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
514 // CHECK5-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
515 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
516 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
517 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
518 // CHECK5-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
519 // CHECK5-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
520 // CHECK5-NEXT:    ret void
521 //
522 //
523 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
524 // CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
525 // CHECK5-NEXT:  entry:
526 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
527 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
528 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
529 // CHECK5-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
530 // CHECK5-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
531 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
532 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
533 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
534 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
535 // CHECK5-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
536 // CHECK5-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true)
537 // CHECK5-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
538 // CHECK5-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
539 // CHECK5:       user_code.entry:
540 // CHECK5-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
541 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
542 // CHECK5-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
543 // CHECK5-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 4
544 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
545 // CHECK5-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
546 // CHECK5-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
547 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
548 // CHECK5-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
549 // CHECK5-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 4
550 // CHECK5-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
551 // CHECK5-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3)
552 // CHECK5-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
553 // CHECK5-NEXT:    ret void
554 // CHECK5:       worker.exit:
555 // CHECK5-NEXT:    ret void
556 //
557 //
558 // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1
559 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
560 // CHECK5-NEXT:  entry:
561 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
562 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
563 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
564 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
565 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
566 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
567 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
568 // CHECK5-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
569 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
570 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
571 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
572 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
573 // CHECK5-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
574 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
575 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
576 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
577 // CHECK5-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
578 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
579 // CHECK5-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
580 // CHECK5-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
581 // CHECK5-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
582 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
583 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
584 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
585 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
586 // CHECK5-NEXT:    ret void
587 //
588 //
589 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
590 // CHECK6-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
591 // CHECK6-NEXT:  entry:
592 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
593 // CHECK6-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
594 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
595 // CHECK6-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
596 // CHECK6-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)
597 // CHECK6-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
598 // CHECK6-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
599 // CHECK6:       user_code.entry:
600 // CHECK6-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
601 // CHECK6-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
602 // CHECK6-NEXT:    [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8*
603 // CHECK6-NEXT:    store i8* [[TMP4]], i8** [[TMP3]], align 4
604 // CHECK6-NEXT:    [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
605 // CHECK6-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1)
606 // CHECK6-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
607 // CHECK6-NEXT:    ret void
608 // CHECK6:       worker.exit:
609 // CHECK6-NEXT:    ret void
610 //
611 //
612 // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__
613 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
614 // CHECK6-NEXT:  entry:
615 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
616 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
617 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
618 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
619 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
620 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
621 // CHECK6-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
622 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
623 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
624 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
625 // CHECK6-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
626 // CHECK6-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
627 // CHECK6-NEXT:    ret void
628 //
629 //
630 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
631 // CHECK6-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
632 // CHECK6-NEXT:  entry:
633 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
634 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
635 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
636 // CHECK6-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
637 // CHECK6-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
638 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
639 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
640 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
641 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
642 // CHECK6-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
643 // CHECK6-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true)
644 // CHECK6-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
645 // CHECK6-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
646 // CHECK6:       user_code.entry:
647 // CHECK6-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
648 // CHECK6-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
649 // CHECK6-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8*
650 // CHECK6-NEXT:    store i8* [[TMP6]], i8** [[TMP5]], align 4
651 // CHECK6-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
652 // CHECK6-NEXT:    [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8*
653 // CHECK6-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
654 // CHECK6-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
655 // CHECK6-NEXT:    [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
656 // CHECK6-NEXT:    store i8* [[TMP10]], i8** [[TMP9]], align 4
657 // CHECK6-NEXT:    [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
658 // CHECK6-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3)
659 // CHECK6-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
660 // CHECK6-NEXT:    ret void
661 // CHECK6:       worker.exit:
662 // CHECK6-NEXT:    ret void
663 //
664 //
665 // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1
666 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
667 // CHECK6-NEXT:  entry:
668 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
669 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
670 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
671 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
672 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
673 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
674 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
675 // CHECK6-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
676 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
677 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
678 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
679 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
680 // CHECK6-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
681 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
682 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
683 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
684 // CHECK6-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
685 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
686 // CHECK6-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
687 // CHECK6-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
688 // CHECK6-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
689 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
690 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
691 // CHECK6-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
692 // CHECK6-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
693 // CHECK6-NEXT:    ret void
694 //
695