1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test target codegen - host bc file has to be created first.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2
7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK3
8 
9 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
10 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK4
11 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
12 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK5
13 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK6
14 
15 // expected-no-diagnostics
16 #ifndef HEADER
17 #define HEADER
18 
19 template<typename tx>
20 tx ftemplate(int n) {
21   tx a = 0;
22   short aa = 0;
23   tx b[10];
24 
25   #pragma omp target parallel if(target: 0)
26   {
27     a += 1;
28   }
29 
30   #pragma omp target parallel map(tofrom: aa)
31   {
32     aa += 1;
33   }
34 
35   #pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40)
36   {
37     a += 1;
38     aa += 1;
39     b[2] += 1;
40   }
41 
42   return a;
43 }
44 
45 int bar(int n){
46   int a = 0;
47 
48   a += ftemplate<int>(n);
49 
50   return a;
51 }
52 
53 #endif
54 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
55 // CHECK1-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
56 // CHECK1-NEXT:  entry:
57 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
58 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
59 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
60 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
61 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
62 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
63 // CHECK1-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
64 // CHECK1-NEXT:    br label [[DOTEXECUTE:%.*]]
65 // CHECK1:       .execute:
66 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
67 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
68 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
69 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 8
70 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
71 // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i64 1)
72 // CHECK1-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
73 // CHECK1:       .omp.deinit:
74 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
75 // CHECK1-NEXT:    br label [[DOTEXIT:%.*]]
76 // CHECK1:       .exit:
77 // CHECK1-NEXT:    ret void
78 //
79 //
80 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
81 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
82 // CHECK1-NEXT:  entry:
83 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
84 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
85 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
86 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
87 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
88 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
89 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
90 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
91 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
92 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
93 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
94 // CHECK1-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
95 // CHECK1-NEXT:    ret void
96 //
97 //
98 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
99 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
100 // CHECK1-NEXT:  entry:
101 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
102 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
103 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
104 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 8
105 // CHECK1-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
106 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
107 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
108 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
109 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
110 // CHECK1-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
111 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
112 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
113 // CHECK1-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
114 // CHECK1-NEXT:    br label [[DOTEXECUTE:%.*]]
115 // CHECK1:       .execute:
116 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
117 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
118 // CHECK1-NEXT:    [[TMP5:%.*]] = bitcast i32* [[TMP0]] to i8*
119 // CHECK1-NEXT:    store i8* [[TMP5]], i8** [[TMP4]], align 8
120 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
121 // CHECK1-NEXT:    [[TMP7:%.*]] = bitcast i16* [[TMP1]] to i8*
122 // CHECK1-NEXT:    store i8* [[TMP7]], i8** [[TMP6]], align 8
123 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
124 // CHECK1-NEXT:    [[TMP9:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
125 // CHECK1-NEXT:    store i8* [[TMP9]], i8** [[TMP8]], align 8
126 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
127 // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP10]], i64 3)
128 // CHECK1-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
129 // CHECK1:       .omp.deinit:
130 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
131 // CHECK1-NEXT:    br label [[DOTEXIT:%.*]]
132 // CHECK1:       .exit:
133 // CHECK1-NEXT:    ret void
134 //
135 //
136 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
137 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
138 // CHECK1-NEXT:  entry:
139 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
140 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
141 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
142 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
143 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
144 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
145 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
146 // CHECK1-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
147 // CHECK1-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
148 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
149 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
150 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
151 // CHECK1-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
152 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
153 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
154 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
155 // CHECK1-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
156 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
157 // CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
158 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
159 // CHECK1-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
160 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 2
161 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
162 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
163 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
164 // CHECK1-NEXT:    ret void
165 //
166 //
167 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
168 // CHECK2-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
169 // CHECK2-NEXT:  entry:
170 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
171 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
172 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
173 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
174 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
175 // CHECK2-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
176 // CHECK2-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
177 // CHECK2-NEXT:    br label [[DOTEXECUTE:%.*]]
178 // CHECK2:       .execute:
179 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
180 // CHECK2-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
181 // CHECK2-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
182 // CHECK2-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 4
183 // CHECK2-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
184 // CHECK2-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i32 1)
185 // CHECK2-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
186 // CHECK2:       .omp.deinit:
187 // CHECK2-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
188 // CHECK2-NEXT:    br label [[DOTEXIT:%.*]]
189 // CHECK2:       .exit:
190 // CHECK2-NEXT:    ret void
191 //
192 //
193 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
194 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
195 // CHECK2-NEXT:  entry:
196 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
197 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
198 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
199 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
200 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
201 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
202 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
203 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
204 // CHECK2-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
205 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
206 // CHECK2-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
207 // CHECK2-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
208 // CHECK2-NEXT:    ret void
209 //
210 //
211 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
212 // CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
213 // CHECK2-NEXT:  entry:
214 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
215 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
216 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
217 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
218 // CHECK2-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
219 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
220 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
221 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
222 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
223 // CHECK2-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
224 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
225 // CHECK2-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
226 // CHECK2-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
227 // CHECK2-NEXT:    br label [[DOTEXECUTE:%.*]]
228 // CHECK2:       .execute:
229 // CHECK2-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
230 // CHECK2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
231 // CHECK2-NEXT:    [[TMP5:%.*]] = bitcast i32* [[TMP0]] to i8*
232 // CHECK2-NEXT:    store i8* [[TMP5]], i8** [[TMP4]], align 4
233 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
234 // CHECK2-NEXT:    [[TMP7:%.*]] = bitcast i16* [[TMP1]] to i8*
235 // CHECK2-NEXT:    store i8* [[TMP7]], i8** [[TMP6]], align 4
236 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
237 // CHECK2-NEXT:    [[TMP9:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
238 // CHECK2-NEXT:    store i8* [[TMP9]], i8** [[TMP8]], align 4
239 // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
240 // CHECK2-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP10]], i32 3)
241 // CHECK2-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
242 // CHECK2:       .omp.deinit:
243 // CHECK2-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
244 // CHECK2-NEXT:    br label [[DOTEXIT:%.*]]
245 // CHECK2:       .exit:
246 // CHECK2-NEXT:    ret void
247 //
248 //
249 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
250 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
251 // CHECK2-NEXT:  entry:
252 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
253 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
254 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
255 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
256 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
257 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
258 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
259 // CHECK2-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
260 // CHECK2-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
261 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
262 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
263 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
264 // CHECK2-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
265 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
266 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
267 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
268 // CHECK2-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
269 // CHECK2-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
270 // CHECK2-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
271 // CHECK2-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
272 // CHECK2-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
273 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
274 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
275 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
276 // CHECK2-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
277 // CHECK2-NEXT:    ret void
278 //
279 //
280 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
281 // CHECK3-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
282 // CHECK3-NEXT:  entry:
283 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
284 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
285 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
286 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
287 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
288 // CHECK3-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
289 // CHECK3-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
290 // CHECK3-NEXT:    br label [[DOTEXECUTE:%.*]]
291 // CHECK3:       .execute:
292 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
293 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
294 // CHECK3-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
295 // CHECK3-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 4
296 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
297 // CHECK3-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i32 1)
298 // CHECK3-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
299 // CHECK3:       .omp.deinit:
300 // CHECK3-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
301 // CHECK3-NEXT:    br label [[DOTEXIT:%.*]]
302 // CHECK3:       .exit:
303 // CHECK3-NEXT:    ret void
304 //
305 //
306 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
307 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
308 // CHECK3-NEXT:  entry:
309 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
310 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
311 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
312 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
313 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
314 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
315 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
316 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
317 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
318 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
319 // CHECK3-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
320 // CHECK3-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
321 // CHECK3-NEXT:    ret void
322 //
323 //
324 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
325 // CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
326 // CHECK3-NEXT:  entry:
327 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
328 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
329 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
330 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
331 // CHECK3-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
332 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
333 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
334 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
335 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
336 // CHECK3-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
337 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
338 // CHECK3-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
339 // CHECK3-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
340 // CHECK3-NEXT:    br label [[DOTEXECUTE:%.*]]
341 // CHECK3:       .execute:
342 // CHECK3-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
343 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
344 // CHECK3-NEXT:    [[TMP5:%.*]] = bitcast i32* [[TMP0]] to i8*
345 // CHECK3-NEXT:    store i8* [[TMP5]], i8** [[TMP4]], align 4
346 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
347 // CHECK3-NEXT:    [[TMP7:%.*]] = bitcast i16* [[TMP1]] to i8*
348 // CHECK3-NEXT:    store i8* [[TMP7]], i8** [[TMP6]], align 4
349 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
350 // CHECK3-NEXT:    [[TMP9:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
351 // CHECK3-NEXT:    store i8* [[TMP9]], i8** [[TMP8]], align 4
352 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
353 // CHECK3-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP10]], i32 3)
354 // CHECK3-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
355 // CHECK3:       .omp.deinit:
356 // CHECK3-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
357 // CHECK3-NEXT:    br label [[DOTEXIT:%.*]]
358 // CHECK3:       .exit:
359 // CHECK3-NEXT:    ret void
360 //
361 //
362 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
363 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
364 // CHECK3-NEXT:  entry:
365 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
366 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
367 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
368 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
369 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
370 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
371 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
372 // CHECK3-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
373 // CHECK3-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
374 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
375 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
376 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
377 // CHECK3-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
378 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
379 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
380 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
381 // CHECK3-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
382 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
383 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
384 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
385 // CHECK3-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
386 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
387 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
388 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
389 // CHECK3-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
390 // CHECK3-NEXT:    ret void
391 //
392 //
393 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
394 // CHECK4-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
395 // CHECK4-NEXT:  entry:
396 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
397 // CHECK4-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
398 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
399 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
400 // CHECK4-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
401 // CHECK4-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
402 // CHECK4-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
403 // CHECK4-NEXT:    br label [[DOTEXECUTE:%.*]]
404 // CHECK4:       .execute:
405 // CHECK4-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
406 // CHECK4-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
407 // CHECK4-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
408 // CHECK4-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 8
409 // CHECK4-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
410 // CHECK4-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i64 1)
411 // CHECK4-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
412 // CHECK4:       .omp.deinit:
413 // CHECK4-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
414 // CHECK4-NEXT:    br label [[DOTEXIT:%.*]]
415 // CHECK4:       .exit:
416 // CHECK4-NEXT:    ret void
417 //
418 //
419 // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__
420 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
421 // CHECK4-NEXT:  entry:
422 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
423 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
424 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
425 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
426 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
427 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
428 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
429 // CHECK4-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
430 // CHECK4-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
431 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
432 // CHECK4-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
433 // CHECK4-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
434 // CHECK4-NEXT:    ret void
435 //
436 //
437 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
438 // CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
439 // CHECK4-NEXT:  entry:
440 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
441 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
442 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
443 // CHECK4-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 8
444 // CHECK4-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
445 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
446 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
447 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
448 // CHECK4-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
449 // CHECK4-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
450 // CHECK4-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
451 // CHECK4-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
452 // CHECK4-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
453 // CHECK4-NEXT:    br label [[DOTEXECUTE:%.*]]
454 // CHECK4:       .execute:
455 // CHECK4-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
456 // CHECK4-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
457 // CHECK4-NEXT:    [[TMP5:%.*]] = bitcast i32* [[TMP0]] to i8*
458 // CHECK4-NEXT:    store i8* [[TMP5]], i8** [[TMP4]], align 8
459 // CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
460 // CHECK4-NEXT:    [[TMP7:%.*]] = bitcast i16* [[TMP1]] to i8*
461 // CHECK4-NEXT:    store i8* [[TMP7]], i8** [[TMP6]], align 8
462 // CHECK4-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
463 // CHECK4-NEXT:    [[TMP9:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
464 // CHECK4-NEXT:    store i8* [[TMP9]], i8** [[TMP8]], align 8
465 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
466 // CHECK4-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP10]], i64 3)
467 // CHECK4-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
468 // CHECK4:       .omp.deinit:
469 // CHECK4-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
470 // CHECK4-NEXT:    br label [[DOTEXIT:%.*]]
471 // CHECK4:       .exit:
472 // CHECK4-NEXT:    ret void
473 //
474 //
475 // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1
476 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
477 // CHECK4-NEXT:  entry:
478 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
479 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
480 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
481 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 8
482 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
483 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
484 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
485 // CHECK4-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
486 // CHECK4-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 8
487 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
488 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
489 // CHECK4-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
490 // CHECK4-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
491 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
492 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
493 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
494 // CHECK4-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
495 // CHECK4-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
496 // CHECK4-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
497 // CHECK4-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
498 // CHECK4-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
499 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 2
500 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
501 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
502 // CHECK4-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
503 // CHECK4-NEXT:    ret void
504 //
505 //
506 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
507 // CHECK5-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
508 // CHECK5-NEXT:  entry:
509 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
510 // CHECK5-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
511 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
512 // CHECK5-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
513 // CHECK5-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
514 // CHECK5-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
515 // CHECK5-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
516 // CHECK5-NEXT:    br label [[DOTEXECUTE:%.*]]
517 // CHECK5:       .execute:
518 // CHECK5-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
519 // CHECK5-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
520 // CHECK5-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
521 // CHECK5-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 4
522 // CHECK5-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
523 // CHECK5-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i32 1)
524 // CHECK5-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
525 // CHECK5:       .omp.deinit:
526 // CHECK5-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
527 // CHECK5-NEXT:    br label [[DOTEXIT:%.*]]
528 // CHECK5:       .exit:
529 // CHECK5-NEXT:    ret void
530 //
531 //
532 // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__
533 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
534 // CHECK5-NEXT:  entry:
535 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
536 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
537 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
538 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
539 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
540 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
541 // CHECK5-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
542 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
543 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
544 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
545 // CHECK5-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
546 // CHECK5-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
547 // CHECK5-NEXT:    ret void
548 //
549 //
550 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
551 // CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
552 // CHECK5-NEXT:  entry:
553 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
554 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
555 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
556 // CHECK5-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
557 // CHECK5-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
558 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
559 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
560 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
561 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
562 // CHECK5-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
563 // CHECK5-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
564 // CHECK5-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
565 // CHECK5-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
566 // CHECK5-NEXT:    br label [[DOTEXECUTE:%.*]]
567 // CHECK5:       .execute:
568 // CHECK5-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
569 // CHECK5-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
570 // CHECK5-NEXT:    [[TMP5:%.*]] = bitcast i32* [[TMP0]] to i8*
571 // CHECK5-NEXT:    store i8* [[TMP5]], i8** [[TMP4]], align 4
572 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
573 // CHECK5-NEXT:    [[TMP7:%.*]] = bitcast i16* [[TMP1]] to i8*
574 // CHECK5-NEXT:    store i8* [[TMP7]], i8** [[TMP6]], align 4
575 // CHECK5-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
576 // CHECK5-NEXT:    [[TMP9:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
577 // CHECK5-NEXT:    store i8* [[TMP9]], i8** [[TMP8]], align 4
578 // CHECK5-NEXT:    [[TMP10:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
579 // CHECK5-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP10]], i32 3)
580 // CHECK5-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
581 // CHECK5:       .omp.deinit:
582 // CHECK5-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
583 // CHECK5-NEXT:    br label [[DOTEXIT:%.*]]
584 // CHECK5:       .exit:
585 // CHECK5-NEXT:    ret void
586 //
587 //
588 // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1
589 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
590 // CHECK5-NEXT:  entry:
591 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
592 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
593 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
594 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
595 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
596 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
597 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
598 // CHECK5-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
599 // CHECK5-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
600 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
601 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
602 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
603 // CHECK5-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
604 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
605 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
606 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
607 // CHECK5-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
608 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
609 // CHECK5-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
610 // CHECK5-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
611 // CHECK5-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
612 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
613 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
614 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
615 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
616 // CHECK5-NEXT:    ret void
617 //
618 //
619 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
620 // CHECK6-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
621 // CHECK6-NEXT:  entry:
622 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
623 // CHECK6-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
624 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
625 // CHECK6-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
626 // CHECK6-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
627 // CHECK6-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
628 // CHECK6-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
629 // CHECK6-NEXT:    br label [[DOTEXECUTE:%.*]]
630 // CHECK6:       .execute:
631 // CHECK6-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
632 // CHECK6-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
633 // CHECK6-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP0]] to i8*
634 // CHECK6-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 4
635 // CHECK6-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
636 // CHECK6-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i32 1)
637 // CHECK6-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
638 // CHECK6:       .omp.deinit:
639 // CHECK6-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
640 // CHECK6-NEXT:    br label [[DOTEXIT:%.*]]
641 // CHECK6:       .exit:
642 // CHECK6-NEXT:    ret void
643 //
644 //
645 // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__
646 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
647 // CHECK6-NEXT:  entry:
648 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
649 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
650 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
651 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
652 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
653 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
654 // CHECK6-NEXT:    [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
655 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
656 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
657 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
658 // CHECK6-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
659 // CHECK6-NEXT:    store i16 [[CONV1]], i16* [[TMP0]], align 2
660 // CHECK6-NEXT:    ret void
661 //
662 //
663 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
664 // CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
665 // CHECK6-NEXT:  entry:
666 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
667 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
668 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
669 // CHECK6-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4
670 // CHECK6-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
671 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
672 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
673 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
674 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
675 // CHECK6-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
676 // CHECK6-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
677 // CHECK6-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
678 // CHECK6-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
679 // CHECK6-NEXT:    br label [[DOTEXECUTE:%.*]]
680 // CHECK6:       .execute:
681 // CHECK6-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
682 // CHECK6-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
683 // CHECK6-NEXT:    [[TMP5:%.*]] = bitcast i32* [[TMP0]] to i8*
684 // CHECK6-NEXT:    store i8* [[TMP5]], i8** [[TMP4]], align 4
685 // CHECK6-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
686 // CHECK6-NEXT:    [[TMP7:%.*]] = bitcast i16* [[TMP1]] to i8*
687 // CHECK6-NEXT:    store i8* [[TMP7]], i8** [[TMP6]], align 4
688 // CHECK6-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
689 // CHECK6-NEXT:    [[TMP9:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
690 // CHECK6-NEXT:    store i8* [[TMP9]], i8** [[TMP8]], align 4
691 // CHECK6-NEXT:    [[TMP10:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
692 // CHECK6-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP10]], i32 3)
693 // CHECK6-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
694 // CHECK6:       .omp.deinit:
695 // CHECK6-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
696 // CHECK6-NEXT:    br label [[DOTEXIT:%.*]]
697 // CHECK6:       .exit:
698 // CHECK6-NEXT:    ret void
699 //
700 //
701 // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1
702 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
703 // CHECK6-NEXT:  entry:
704 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
705 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
706 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 4
707 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i16*, align 4
708 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
709 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
710 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
711 // CHECK6-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 4
712 // CHECK6-NEXT:    store i16* [[AA]], i16** [[AA_ADDR]], align 4
713 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
714 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
715 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
716 // CHECK6-NEXT:    [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
717 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
718 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
719 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
720 // CHECK6-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
721 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
722 // CHECK6-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
723 // CHECK6-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
724 // CHECK6-NEXT:    store i16 [[CONV2]], i16* [[TMP1]], align 2
725 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2
726 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
727 // CHECK6-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
728 // CHECK6-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
729 // CHECK6-NEXT:    ret void
730 //
731