1 // Test target codegen - host bc file has to be created first. 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 3 // RUN: %clang_cc1 -debug-info-kind=limited -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 4 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 5 // RUN: %clang_cc1 -debug-info-kind=limited -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 6 // expected-no-diagnostics 7 #ifndef HEADER 8 #define HEADER 9 10 template <typename tx, typename ty> 11 struct TT { 12 tx X; 13 ty Y; 14 }; 15 16 // TCHECK-DAG: [[TTII:%.+]] = type { i32, i32 } 17 // TCHECK-DAG: [[TTIC:%.+]] = type { i8, i8 } 18 // TCHECK-DAG: [[TT:%.+]] = type { i64, i8 } 19 // TCHECK-DAG: [[S1:%.+]] = type { double } 20 21 // TCHECK: @__omp_offloading_firstprivate__{{.+}}_e_l30 = internal addrspace(4) global [[TTII]] zeroinitializer 22 // TCHECK: @__omp_offloading_firstprivate__{{.+}}_ZTSK2TTIiiE_t_l143 = internal addrspace(4) global [[TTII]] zeroinitializer 23 // TCHECK: @__omp_offloading_firstprivate__{{.+}}_ZTSK2TTIccE_t_l143 = internal addrspace(4) global [[TTIC]] zeroinitializer 24 int foo(int n, double *ptr) { 25 int a = 0; 26 short aa = 0; 27 float b[10]; 28 double c[5][10]; 29 TT<long long, char> d; 30 const TT<int, int> e = {n, n}; 31 32 #pragma omp target firstprivate(a, e) map(tofrom \ 33 : b) 34 { 35 b[a] = a; 36 b[a] += e.X; 37 } 38 39 // TCHECK: define {{.*}}void @__omp_offloading_{{.+}}([10 x float] addrspace(1)* noalias [[B_IN:%.+]], i{{[0-9]+}} [[A_IN:%.+]], [[TTII]]* noalias [[E_IN:%.+]]) 40 // TCHECK-NOT: alloca [[TTII]], 41 // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}}, 42 // TCHECK-NOT: alloca [[TTII]], 43 // TCHECK-NOT: alloca i{{[0-9]+}}, 44 // TCHECK-64: call void @llvm.dbg.declare(metadata [10 x float] addrspace(1)** %{{.+}}, metadata !{{[0-9]+}}, metadata !DIExpression()) 45 // TCHECK: store i{{[0-9]+}} [[A_IN]], i{{[0-9]+}}* [[A_ADDR]], 46 // TCHECK: ret void 47 48 #pragma omp target firstprivate(aa, b, c, d) 49 { 50 aa += 1; 51 b[2] = 1.0; 52 c[1][2] = 1.0; 53 d.X = 1; 54 d.Y = 1; 55 } 56 57 // make sure that firstprivate variables are generated in all cases and that we use those instances for operations inside the 58 // target region 59 // TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(i{{[0-9]+}}{{.*}} [[A2_IN:%.+]], [10 x float]*{{.*}} [[B_IN:%.+]], [5 x [10 x double]]*{{.*}} [[C_IN:%.+]], [[TT]]*{{.*}} [[D_IN:%.+]]) 60 // TCHECK: [[A2_ADDR:%.+]] = alloca i{{[0-9]+}}, 61 // TCHECK: [[B_ADDR:%.+]] = alloca [10 x float]*, 62 // TCHECK: [[C_ADDR:%.+]] = alloca [5 x [10 x double]]*, 63 // TCHECK: [[D_ADDR:%.+]] = alloca [[TT]]*, 64 // TCHECK-NOT: alloca i{{[0-9]+}}, 65 // TCHECK: [[B_PRIV:%.+]] = alloca [10 x float], 66 // TCHECK: [[C_PRIV:%.+]] = alloca [5 x [10 x double]], 67 // TCHECK: [[D_PRIV:%.+]] = alloca [[TT]], 68 // TCHECK: store i{{[0-9]+}} [[A2_IN]], i{{[0-9]+}}* [[A2_ADDR]], 69 // TCHECK: store [10 x float]* [[B_IN]], [10 x float]** [[B_ADDR]], 70 // TCHECK: store [5 x [10 x double]]* [[C_IN]], [5 x [10 x double]]** [[C_ADDR]], 71 // TCHECK: store [[TT]]* [[D_IN]], [[TT]]** [[D_ADDR]], 72 // TCHECK: [[B_ADDR_REF:%.+]] = load [10 x float]*, [10 x float]** [[B_ADDR]], 73 // TCHECK: [[B_ADDR_REF:%.+]] = load [10 x float]*, [10 x float]** % 74 // TCHECK: [[C_ADDR_REF:%.+]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], 75 // TCHECK: [[C_ADDR_REF:%.+]] = load [5 x [10 x double]]*, [5 x [10 x double]]** % 76 // TCHECK: [[D_ADDR_REF:%.+]] = load [[TT]]*, [[TT]]** [[D_ADDR]], 77 // TCHECK: [[D_ADDR_REF:%.+]] = load [[TT]]*, [[TT]]** % 78 79 // firstprivate(aa): a_priv = a_in 80 81 // firstprivate(b): memcpy(b_priv,b_in) 82 // TCHECK: [[B_PRIV_BCAST:%.+]] = bitcast [10 x float]* [[B_PRIV]] to i8* 83 // TCHECK: [[B_ADDR_REF_BCAST:%.+]] = bitcast [10 x float]* [[B_ADDR_REF]] to i8* 84 // TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[B_PRIV_BCAST]], i8* align {{[0-9]+}} [[B_ADDR_REF_BCAST]], {{.+}}) 85 86 // firstprivate(c) 87 // TCHECK: [[C_PRIV_BCAST:%.+]] = bitcast [5 x [10 x double]]* [[C_PRIV]] to i8* 88 // TCHECK: [[C_IN_BCAST:%.+]] = bitcast [5 x [10 x double]]* [[C_ADDR_REF]] to i8* 89 // TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[C_PRIV_BCAST]], i8* align {{[0-9]+}} [[C_IN_BCAST]],{{.+}}) 90 91 // firstprivate(d) 92 // TCHECK: [[D_PRIV_BCAST:%.+]] = bitcast [[TT]]* [[D_PRIV]] to i8* 93 // TCHECK: [[D_IN_BCAST:%.+]] = bitcast [[TT]]* [[D_ADDR_REF]] to i8* 94 // TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[D_PRIV_BCAST]], i8* align {{[0-9]+}} [[D_IN_BCAST]],{{.+}}) 95 96 // TCHECK: load i16, i16* [[A2_ADDR]], 97 98 #pragma omp target firstprivate(ptr) 99 { 100 ptr[0]++; 101 } 102 103 // TCHECK: define weak void @__omp_offloading_{{.+}}(double* [[PTR_IN:%.+]]) 104 // TCHECK: [[PTR_ADDR:%.+]] = alloca double*, 105 // TCHECK-NOT: alloca double*, 106 // TCHECK: store double* [[PTR_IN]], double** [[PTR_ADDR]], 107 // TCHECK: [[PTR_IN_REF:%.+]] = load double*, double** [[PTR_ADDR]], 108 // TCHECK-NOT: store double* [[PTR_IN_REF]], double** {{%.+}}, 109 110 return a; 111 } 112 113 template <typename tx> 114 tx ftemplate(int n) { 115 tx a = 0; 116 tx b[10]; 117 118 #pragma omp target firstprivate(a, b) 119 { 120 a += 1; 121 b[2] += 1; 122 } 123 124 return a; 125 } 126 127 static int fstatic(int n) { 128 int a = 0; 129 char aaa = 0; 130 int b[10]; 131 132 #pragma omp target firstprivate(a, aaa, b) 133 { 134 a += 1; 135 aaa += 1; 136 b[2] += 1; 137 } 138 139 return a; 140 } 141 142 template <typename tx> 143 void fconst(const tx t) { 144 #pragma omp target firstprivate(t) 145 { } 146 } 147 148 // TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(i{{[0-9]+}}{{.*}} [[A_IN:%.+]], i{{[0-9]+}}{{.*}} [[A3_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]]) 149 // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}}, 150 // TCHECK: [[A3_ADDR:%.+]] = alloca i{{[0-9]+}}, 151 // TCHECK: [[B_ADDR:%.+]] = alloca [10 x i{{[0-9]+}}]*, 152 // TCHECK-NOT: alloca i{{[0-9]+}}, 153 // TCHECK: [[B_PRIV:%.+]] = alloca [10 x i{{[0-9]+}}], 154 // TCHECK: store i{{[0-9]+}} [[A_IN]], i{{[0-9]+}}* [[A_ADDR]], 155 // TCHECK: store i{{[0-9]+}} [[A3_IN]], i{{[0-9]+}}* [[A3_ADDR]], 156 // TCHECK: store [10 x i{{[0-9]+}}]* [[B_IN]], [10 x i{{[0-9]+}}]** [[B_ADDR]], 157 // TCHECK: [[B_ADDR_REF:%.+]] = load [10 x i{{[0-9]+}}]*, [10 x i{{[0-9]+}}]** [[B_ADDR]], 158 // TCHECK: [[B_ADDR_REF:%.+]] = load [10 x i{{[0-9]+}}]*, [10 x i{{[0-9]+}}]** % 159 160 // firstprivate(a): a_priv = a_in 161 162 // firstprivate(aaa) 163 164 // TCHECK-NOT: store i{{[0-9]+}} %{{.+}}, i{{[0-9]+}}* 165 166 // firstprivate(b) 167 // TCHECK: [[B_PRIV_BCAST:%.+]] = bitcast [10 x i{{[0-9]+}}]* [[B_PRIV]] to i8* 168 // TCHECK: [[B_IN_BCAST:%.+]] = bitcast [10 x i{{[0-9]+}}]* [[B_ADDR_REF]] to i8* 169 // TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[B_PRIV_BCAST]], i8* align {{[0-9]+}} [[B_IN_BCAST]],{{.+}}) 170 171 // TCHECK: ret void 172 173 struct S1 { 174 double a; 175 176 int r1(int n) { 177 int b = n + 1; 178 179 #pragma omp target firstprivate(b) 180 { 181 this->a = (double)b + 1.5; 182 } 183 184 return (int)b; 185 } 186 187 // TCHECK: define internal void @__omp_offloading_{{.+}}([[S1]]* [[TH:%.+]], i{{[0-9]+}} [[B_IN:%.+]]) 188 // TCHECK: [[TH_ADDR:%.+]] = alloca [[S1]]*, 189 // TCHECK: [[B_ADDR:%.+]] = alloca i{{[0-9]+}}, 190 // TCHECK-NOT: alloca i{{[0-9]+}}, 191 192 // TCHECK: store [[S1]]* [[TH]], [[S1]]** [[TH_ADDR]], 193 // TCHECK: store i{{[0-9]+}} [[B_IN]], i{{[0-9]+}}* [[B_ADDR]], 194 // TCHECK: [[TH_ADDR_REF:%.+]] = load [[S1]]*, [[S1]]** [[TH_ADDR]], 195 // TCHECK-64: [[B_ADDR_CONV:%.+]] = bitcast i{{[0-9]+}}* [[B_ADDR]] to i{{[0-9]+}}* 196 197 // firstprivate(b) 198 // TCHECK-NOT: store i{{[0-9]+}} %{{.+}}, i{{[0-9]+}}* 199 200 // TCHECK: ret void 201 }; 202 203 int bar(int n, double *ptr) { 204 int a = 0; 205 a += foo(n, ptr); 206 S1 S; 207 a += S.r1(n); 208 a += fstatic(n); 209 a += ftemplate<int>(n); 210 211 fconst(TT<int, int>{0, 0}); 212 fconst(TT<char, char>{0, 0}); 213 214 return a; 215 } 216 217 // template 218 219 // TCHECK: define internal void @__omp_offloading_{{.+}}(i{{[0-9]+}} [[A_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]]) 220 // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}}, 221 // TCHECK: [[B_ADDR:%.+]] = alloca [10 x i{{[0-9]+}}]*, 222 // TCHECK-NOT: alloca i{{[0-9]+}}, 223 // TCHECK: [[B_PRIV:%.+]] = alloca [10 x i{{[0-9]+}}], 224 // TCHECK: store i{{[0-9]+}} [[A_IN]], i{{[0-9]+}}* [[A_ADDR]], 225 // TCHECK: store [10 x i{{[0-9]+}}]* [[B_IN]], [10 x i{{[0-9]+}}]** [[B_ADDR]], 226 // TCHECK: [[B_ADDR_REF:%.+]] = load [10 x i{{[0-9]+}}]*, [10 x i{{[0-9]+}}]** [[B_ADDR]], 227 // TCHECK: [[B_ADDR_REF:%.+]] = load [10 x i{{[0-9]+}}]*, [10 x i{{[0-9]+}}]** % 228 229 // firstprivate(a) 230 // TCHECK-NOT: store i{{[0-9]+}} %{{.+}}, i{{[0-9]+}}* 231 232 // firstprivate(b) 233 // TCHECK: [[B_PRIV_BCAST:%.+]] = bitcast [10 x i{{[0-9]+}}]* [[B_PRIV]] to i8* 234 // TCHECK: [[B_IN_BCAST:%.+]] = bitcast [10 x i{{[0-9]+}}]* [[B_ADDR_REF]] to i8* 235 // TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[B_PRIV_BCAST]], i8* align {{[0-9]+}} [[B_IN_BCAST]],{{.+}}) 236 237 // TCHECK: ret void 238 239 #endif 240 241 // TCHECK-DAG: distinct !DISubprogram(linkageName: "__omp_offloading_{{.+}}_worker", 242 // TCHECK-DAG: distinct !DISubprogram(linkageName: "__omp_offloading_{{.+}}_worker", 243 // TCHECK-DAG: distinct !DISubprogram(linkageName: "__omp_offloading_{{.+}}_worker", 244 // TCHECK-DAG: distinct !DISubprogram(linkageName: "__omp_offloading_{{.+}}_worker", 245 // TCHECK-DAG: distinct !DISubprogram(linkageName: "__omp_offloading_{{.+}}_worker", 246