1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test target codegen - host bc file has to be created first. 3 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 4 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 6 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 7 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK3 8 // expected-no-diagnostics 9 10 #ifndef HEADER 11 #define HEADER 12 13 __thread int id; 14 15 int baz(int f, double &a); 16 17 template <typename tx, typename ty> 18 struct TT { 19 tx X; 20 ty Y; 21 tx &operator[](int i) { return X; } 22 }; 23 24 void targetBar(int *Ptr1, int *Ptr2) { 25 #pragma omp target map(Ptr1[:0], Ptr2) 26 #pragma omp parallel num_threads(2) 27 *Ptr1 = *Ptr2; 28 } 29 30 int foo(int n) { 31 int a = 0; 32 short aa = 0; 33 float b[10]; 34 float bn[n]; 35 double c[5][10]; 36 double cn[5][n]; 37 TT<long long, char> d; 38 39 #pragma omp target 40 { 41 } 42 43 #pragma omp target if (0) 44 { 45 } 46 47 #pragma omp target if (1) 48 { 49 aa += 1; 50 aa += 2; 51 } 52 53 #pragma omp target if (n > 20) 54 { 55 a += 1; 56 b[2] += 1.0; 57 bn[3] += 1.0; 58 c[1][2] += 1.0; 59 cn[1][3] += 1.0; 60 d.X += 1; 61 d.Y += 1; 62 d[0] += 1; 63 } 64 65 return a; 66 } 67 68 template <typename tx> 69 tx ftemplate(int n) { 70 tx a = 0; 71 short aa = 0; 72 tx b[10]; 73 74 #pragma omp target if (n > 40) 75 { 76 a += 1; 77 aa += 1; 78 b[2] += 1; 79 } 80 81 return a; 82 } 83 84 static int fstatic(int n) { 85 int a = 0; 86 short aa = 0; 87 char aaa = 0; 88 int b[10]; 89 90 #pragma omp target if (n > 50) 91 { 92 a += 1; 93 aa += 1; 94 aaa += 1; 95 b[2] += 1; 96 } 97 98 return a; 99 } 100 101 struct S1 { 102 double a; 103 104 int r1(int n) { 105 int b = n + 1; 106 short int c[2][n]; 107 108 #pragma omp target if (n > 60) 109 { 110 this->a = (double)b + 1.5; 111 c[1][1] = ++a; 112 baz(a, a); 113 } 114 115 return c[1][1] + (int)b; 116 } 117 }; 118 119 int bar(int n) { 120 int a = 0; 121 122 a += foo(n); 123 124 S1 S; 125 a += S.r1(n); 126 127 a += fstatic(n); 128 129 a += ftemplate<int>(n); 130 131 return a; 132 } 133 134 int baz(int f, double &a) { 135 #pragma omp parallel 136 f = 2 + a; 137 return f; 138 } 139 140 extern void assert(int) throw() __attribute__((__noreturn__)); 141 void unreachable_call() { 142 #pragma omp target 143 assert(0); 144 } 145 146 #endif 147 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9targetBarPiS__l25 148 // CHECK1-SAME: (i32* [[PTR1:%.*]], i32** nonnull align 8 dereferenceable(8) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] { 149 // CHECK1-NEXT: entry: 150 // CHECK1-NEXT: [[PTR1_ADDR:%.*]] = alloca i32*, align 8 151 // CHECK1-NEXT: [[PTR2_ADDR:%.*]] = alloca i32**, align 8 152 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 8 153 // CHECK1-NEXT: store i32* [[PTR1]], i32** [[PTR1_ADDR]], align 8 154 // CHECK1-NEXT: store i32** [[PTR2]], i32*** [[PTR2_ADDR]], align 8 155 // CHECK1-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PTR2_ADDR]], align 8 156 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) 157 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 158 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 159 // CHECK1: user_code.entry: 160 // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 161 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 162 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i32** [[PTR1_ADDR]] to i8* 163 // CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8 164 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 165 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i32** [[TMP0]] to i8* 166 // CHECK1-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8 167 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 168 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32*, i32*, i32**, i32**)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP7]], i64 2) 169 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) 170 // CHECK1-NEXT: ret void 171 // CHECK1: worker.exit: 172 // CHECK1-NEXT: ret void 173 // 174 // 175 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ 176 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 8 dereferenceable(8) [[PTR1:%.*]], i32** nonnull align 8 dereferenceable(8) [[PTR2:%.*]]) #[[ATTR1:[0-9]+]] { 177 // CHECK1-NEXT: entry: 178 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 179 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 180 // CHECK1-NEXT: [[PTR1_ADDR:%.*]] = alloca i32**, align 8 181 // CHECK1-NEXT: [[PTR2_ADDR:%.*]] = alloca i32**, align 8 182 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 183 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 184 // CHECK1-NEXT: store i32** [[PTR1]], i32*** [[PTR1_ADDR]], align 8 185 // CHECK1-NEXT: store i32** [[PTR2]], i32*** [[PTR2_ADDR]], align 8 186 // CHECK1-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PTR1_ADDR]], align 8 187 // CHECK1-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[PTR2_ADDR]], align 8 188 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 8 189 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 190 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP0]], align 8 191 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[TMP4]], align 4 192 // CHECK1-NEXT: ret void 193 // 194 // 195 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39 196 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 197 // CHECK1-NEXT: entry: 198 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 199 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 200 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 201 // CHECK1: user_code.entry: 202 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 203 // CHECK1-NEXT: ret void 204 // CHECK1: worker.exit: 205 // CHECK1-NEXT: ret void 206 // 207 // 208 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47 209 // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR4]] { 210 // CHECK1-NEXT: entry: 211 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 212 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 213 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 214 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 215 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 216 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 217 // CHECK1: user_code.entry: 218 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 219 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 220 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 221 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 222 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 223 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 224 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 225 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2 226 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 227 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 228 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 229 // CHECK1-NEXT: ret void 230 // CHECK1: worker.exit: 231 // CHECK1-NEXT: ret void 232 // 233 // 234 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53 235 // CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR4]] { 236 // CHECK1-NEXT: entry: 237 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 238 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 239 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 240 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 241 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 242 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 243 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 244 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 245 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 246 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 247 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 248 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 249 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 250 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 251 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 252 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 253 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 254 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 255 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 256 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 257 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 258 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 259 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 260 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 261 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 262 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 263 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 264 // CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 265 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1 266 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 267 // CHECK1: user_code.entry: 268 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 269 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 270 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 271 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 272 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 273 // CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP10]] to double 274 // CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 275 // CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 276 // CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 277 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 278 // CHECK1-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 279 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double 280 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 281 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 282 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 283 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 284 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 285 // CHECK1-NEXT: [[TMP12:%.*]] = load double, double* [[ARRAYIDX13]], align 8 286 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[TMP12]], 1.000000e+00 287 // CHECK1-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 288 // CHECK1-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP5]] 289 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP13]] 290 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 291 // CHECK1-NEXT: [[TMP14:%.*]] = load double, double* [[ARRAYIDX16]], align 8 292 // CHECK1-NEXT: [[ADD17:%.*]] = fadd double [[TMP14]], 1.000000e+00 293 // CHECK1-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 294 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 295 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[X]], align 8 296 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP15]], 1 297 // CHECK1-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 298 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 299 // CHECK1-NEXT: [[TMP16:%.*]] = load i8, i8* [[Y]], align 8 300 // CHECK1-NEXT: [[CONV19:%.*]] = sext i8 [[TMP16]] to i32 301 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 302 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 303 // CHECK1-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 304 // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 8 dereferenceable(8) i64* @_ZN2TTIxcEixEi(%struct.TT* nonnull align 8 dereferenceable(16) [[TMP7]], i32 0) #[[ATTR9:[0-9]+]] 305 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[CALL]], align 8 306 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP17]], 1 307 // CHECK1-NEXT: store i64 [[ADD22]], i64* [[CALL]], align 8 308 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 309 // CHECK1-NEXT: ret void 310 // CHECK1: worker.exit: 311 // CHECK1-NEXT: ret void 312 // 313 // 314 // CHECK1-LABEL: define {{[^@]+}}@_ZN2TTIxcEixEi 315 // CHECK1-SAME: (%struct.TT* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[I:%.*]]) #[[ATTR5:[0-9]+]] comdat align 2 { 316 // CHECK1-NEXT: entry: 317 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.TT*, align 8 318 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: store %struct.TT* [[THIS]], %struct.TT** [[THIS_ADDR]], align 8 320 // CHECK1-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 321 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.TT*, %struct.TT** [[THIS_ADDR]], align 8 322 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[THIS1]], i32 0, i32 0 323 // CHECK1-NEXT: ret i64* [[X]] 324 // 325 // 326 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90 327 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4]] { 328 // CHECK1-NEXT: entry: 329 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 330 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 331 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 332 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 333 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 334 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 335 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 336 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 337 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 338 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 339 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 340 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 341 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 342 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 343 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 344 // CHECK1: user_code.entry: 345 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 346 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1 347 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 348 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 349 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP3]] to i32 350 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 351 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 352 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 353 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV2]], align 1 354 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i32 355 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 356 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 357 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 358 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 359 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 360 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP5]], 1 361 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 362 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 363 // CHECK1-NEXT: ret void 364 // CHECK1: worker.exit: 365 // CHECK1-NEXT: ret void 366 // 367 // 368 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108 369 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR4]] { 370 // CHECK1-NEXT: entry: 371 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 372 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 373 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 374 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 375 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 376 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 377 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 378 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 379 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 380 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 381 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 382 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 383 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 384 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 385 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 386 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 387 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 388 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 389 // CHECK1: user_code.entry: 390 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4 391 // CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP5]] to double 392 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 393 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 394 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 395 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 396 // CHECK1-NEXT: [[TMP6:%.*]] = load double, double* [[A4]], align 8 397 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 398 // CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8 399 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 400 // CHECK1-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] 401 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP7]] 402 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 403 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 404 // CHECK1-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 405 // CHECK1-NEXT: [[TMP8:%.*]] = load double, double* [[A7]], align 8 406 // CHECK1-NEXT: [[CONV8:%.*]] = fptosi double [[TMP8]] to i32 407 // CHECK1-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 408 // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z3baziRd(i32 [[CONV8]], double* nonnull align 8 dereferenceable(8) [[A9]]) #[[ATTR9]] 409 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 410 // CHECK1-NEXT: ret void 411 // CHECK1: worker.exit: 412 // CHECK1-NEXT: ret void 413 // 414 // 415 // CHECK1-LABEL: define {{[^@]+}}@_Z3baziRd 416 // CHECK1-SAME: (i32 [[F1:%.*]], double* nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR5]] { 417 // CHECK1-NEXT: entry: 418 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 419 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 8 420 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 421 // CHECK1-NEXT: [[F:%.*]] = call align 8 i8* @__kmpc_alloc_shared(i64 4) 422 // CHECK1-NEXT: [[F_ON_STACK:%.*]] = bitcast i8* [[F]] to i32* 423 // CHECK1-NEXT: store i32 [[F1]], i32* [[F_ON_STACK]], align 4 424 // CHECK1-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 425 // CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[A_ADDR]], align 8 426 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 427 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i32* [[F_ON_STACK]] to i8* 428 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[TMP2]], align 8 429 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 430 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast double* [[TMP1]] to i8* 431 // CHECK1-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8 432 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 433 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, double*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP6]], i64 2) 434 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[F_ON_STACK]], align 4 435 // CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[F]], i64 4) 436 // CHECK1-NEXT: ret i32 [[TMP7]] 437 // 438 // 439 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142 440 // CHECK1-SAME: () #[[ATTR4]] { 441 // CHECK1-NEXT: entry: 442 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 443 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 444 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 445 // CHECK1: user_code.entry: 446 // CHECK1-NEXT: call void @_Z6asserti(i32 0) #[[ATTR10:[0-9]+]] 447 // CHECK1-NEXT: unreachable 448 // CHECK1: worker.exit: 449 // CHECK1-NEXT: ret void 450 // CHECK1: 1: 451 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 452 // CHECK1-NEXT: ret void 453 // 454 // 455 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74 456 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4]] { 457 // CHECK1-NEXT: entry: 458 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 459 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 460 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 461 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 462 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 463 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 464 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 465 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 466 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 467 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 468 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 469 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 470 // CHECK1: user_code.entry: 471 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 472 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1 473 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 474 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 475 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32 476 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 477 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 478 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 479 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 480 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 481 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP4]], 1 482 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 483 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 484 // CHECK1-NEXT: ret void 485 // CHECK1: worker.exit: 486 // CHECK1-NEXT: ret void 487 // 488 // 489 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 490 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[F:%.*]], double* nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] { 491 // CHECK1-NEXT: entry: 492 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 493 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 494 // CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 495 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 496 // CHECK1-NEXT: [[TMP:%.*]] = alloca double*, align 8 497 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 498 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 499 // CHECK1-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 500 // CHECK1-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 501 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[F_ADDR]], align 8 502 // CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[A_ADDR]], align 8 503 // CHECK1-NEXT: store double* [[TMP1]], double** [[TMP]], align 8 504 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8 505 // CHECK1-NEXT: [[TMP3:%.*]] = load double, double* [[TMP2]], align 8 506 // CHECK1-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]] 507 // CHECK1-NEXT: [[CONV:%.*]] = fptosi double [[ADD]] to i32 508 // CHECK1-NEXT: store i32 [[CONV]], i32* [[TMP0]], align 4 509 // CHECK1-NEXT: ret void 510 // 511 // 512 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 513 // CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR8:[0-9]+]] { 514 // CHECK1-NEXT: entry: 515 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 516 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 517 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 518 // CHECK1-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8 519 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 520 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 521 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 522 // CHECK1-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 523 // CHECK1-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8 524 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0 525 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 526 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 8 527 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 1 528 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to double** 529 // CHECK1-NEXT: [[TMP8:%.*]] = load double*, double** [[TMP7]], align 8 530 // CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], double* [[TMP8]]) #[[ATTR2:[0-9]+]] 531 // CHECK1-NEXT: ret void 532 // 533 // 534 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9targetBarPiS__l25 535 // CHECK2-SAME: (i32* [[PTR1:%.*]], i32** nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] { 536 // CHECK2-NEXT: entry: 537 // CHECK2-NEXT: [[PTR1_ADDR:%.*]] = alloca i32*, align 4 538 // CHECK2-NEXT: [[PTR2_ADDR:%.*]] = alloca i32**, align 4 539 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 4 540 // CHECK2-NEXT: store i32* [[PTR1]], i32** [[PTR1_ADDR]], align 4 541 // CHECK2-NEXT: store i32** [[PTR2]], i32*** [[PTR2_ADDR]], align 4 542 // CHECK2-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PTR2_ADDR]], align 4 543 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) 544 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 545 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 546 // CHECK2: user_code.entry: 547 // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 548 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 549 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i32** [[PTR1_ADDR]] to i8* 550 // CHECK2-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4 551 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 552 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i32** [[TMP0]] to i8* 553 // CHECK2-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4 554 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 555 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32*, i32*, i32**, i32**)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP7]], i32 2) 556 // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) 557 // CHECK2-NEXT: ret void 558 // CHECK2: worker.exit: 559 // CHECK2-NEXT: ret void 560 // 561 // 562 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ 563 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 4 dereferenceable(4) [[PTR1:%.*]], i32** nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR1:[0-9]+]] { 564 // CHECK2-NEXT: entry: 565 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 566 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 567 // CHECK2-NEXT: [[PTR1_ADDR:%.*]] = alloca i32**, align 4 568 // CHECK2-NEXT: [[PTR2_ADDR:%.*]] = alloca i32**, align 4 569 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 570 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 571 // CHECK2-NEXT: store i32** [[PTR1]], i32*** [[PTR1_ADDR]], align 4 572 // CHECK2-NEXT: store i32** [[PTR2]], i32*** [[PTR2_ADDR]], align 4 573 // CHECK2-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PTR1_ADDR]], align 4 574 // CHECK2-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[PTR2_ADDR]], align 4 575 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 4 576 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 577 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP0]], align 4 578 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[TMP4]], align 4 579 // CHECK2-NEXT: ret void 580 // 581 // 582 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39 583 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] { 584 // CHECK2-NEXT: entry: 585 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 586 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 587 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 588 // CHECK2: user_code.entry: 589 // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 590 // CHECK2-NEXT: ret void 591 // CHECK2: worker.exit: 592 // CHECK2-NEXT: ret void 593 // 594 // 595 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47 596 // CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR4]] { 597 // CHECK2-NEXT: entry: 598 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 599 // CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 600 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 601 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 602 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 603 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 604 // CHECK2: user_code.entry: 605 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 606 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 607 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 608 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 609 // CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 610 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 611 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 612 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2 613 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 614 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 615 // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 616 // CHECK2-NEXT: ret void 617 // CHECK2: worker.exit: 618 // CHECK2-NEXT: ret void 619 // 620 // 621 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53 622 // CHECK2-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR4]] { 623 // CHECK2-NEXT: entry: 624 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 625 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 626 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 627 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 628 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 629 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 630 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 631 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 632 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 633 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 634 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 635 // CHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 636 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 637 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 638 // CHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 639 // CHECK2-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 640 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 641 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 642 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 643 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 644 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 645 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 646 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 647 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 648 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 649 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 650 // CHECK2-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 651 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1 652 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 653 // CHECK2: user_code.entry: 654 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 655 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 656 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 657 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 658 // CHECK2-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 659 // CHECK2-NEXT: [[CONV:%.*]] = fpext float [[TMP10]] to double 660 // CHECK2-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 661 // CHECK2-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 662 // CHECK2-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 663 // CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 664 // CHECK2-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX7]], align 4 665 // CHECK2-NEXT: [[CONV8:%.*]] = fpext float [[TMP11]] to double 666 // CHECK2-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 667 // CHECK2-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 668 // CHECK2-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 669 // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 670 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 671 // CHECK2-NEXT: [[TMP12:%.*]] = load double, double* [[ARRAYIDX12]], align 8 672 // CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[TMP12]], 1.000000e+00 673 // CHECK2-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 674 // CHECK2-NEXT: [[TMP13:%.*]] = mul nsw i32 1, [[TMP5]] 675 // CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP13]] 676 // CHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 677 // CHECK2-NEXT: [[TMP14:%.*]] = load double, double* [[ARRAYIDX15]], align 8 678 // CHECK2-NEXT: [[ADD16:%.*]] = fadd double [[TMP14]], 1.000000e+00 679 // CHECK2-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 680 // CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 681 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[X]], align 8 682 // CHECK2-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP15]], 1 683 // CHECK2-NEXT: store i64 [[ADD17]], i64* [[X]], align 8 684 // CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 685 // CHECK2-NEXT: [[TMP16:%.*]] = load i8, i8* [[Y]], align 8 686 // CHECK2-NEXT: [[CONV18:%.*]] = sext i8 [[TMP16]] to i32 687 // CHECK2-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 688 // CHECK2-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 689 // CHECK2-NEXT: store i8 [[CONV20]], i8* [[Y]], align 8 690 // CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 8 dereferenceable(8) i64* @_ZN2TTIxcEixEi(%struct.TT* nonnull align 8 dereferenceable(16) [[TMP7]], i32 0) #[[ATTR9:[0-9]+]] 691 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[CALL]], align 8 692 // CHECK2-NEXT: [[ADD21:%.*]] = add nsw i64 [[TMP17]], 1 693 // CHECK2-NEXT: store i64 [[ADD21]], i64* [[CALL]], align 8 694 // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 695 // CHECK2-NEXT: ret void 696 // CHECK2: worker.exit: 697 // CHECK2-NEXT: ret void 698 // 699 // 700 // CHECK2-LABEL: define {{[^@]+}}@_ZN2TTIxcEixEi 701 // CHECK2-SAME: (%struct.TT* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[I:%.*]]) #[[ATTR5:[0-9]+]] comdat align 2 { 702 // CHECK2-NEXT: entry: 703 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.TT*, align 4 704 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 705 // CHECK2-NEXT: store %struct.TT* [[THIS]], %struct.TT** [[THIS_ADDR]], align 4 706 // CHECK2-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 707 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.TT*, %struct.TT** [[THIS_ADDR]], align 4 708 // CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[THIS1]], i32 0, i32 0 709 // CHECK2-NEXT: ret i64* [[X]] 710 // 711 // 712 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90 713 // CHECK2-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4]] { 714 // CHECK2-NEXT: entry: 715 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 716 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 717 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 718 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 719 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 720 // CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 721 // CHECK2-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 722 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 723 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 724 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 725 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 726 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 727 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 728 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 729 // CHECK2: user_code.entry: 730 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4 731 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1 732 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 733 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 734 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32 735 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 736 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 737 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 738 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1 739 // CHECK2-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 740 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 741 // CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 742 // CHECK2-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 743 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 744 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 745 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP5]], 1 746 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 747 // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 748 // CHECK2-NEXT: ret void 749 // CHECK2: worker.exit: 750 // CHECK2-NEXT: ret void 751 // 752 // 753 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108 754 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR4]] { 755 // CHECK2-NEXT: entry: 756 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 757 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 758 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 759 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 760 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 761 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 762 // CHECK2-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 763 // CHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 764 // CHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 765 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 766 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 767 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 768 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 769 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 770 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 771 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 772 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 773 // CHECK2: user_code.entry: 774 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4 775 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double 776 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 777 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 778 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 779 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 780 // CHECK2-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 781 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 782 // CHECK2-NEXT: store double [[INC]], double* [[A3]], align 8 783 // CHECK2-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 784 // CHECK2-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] 785 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP7]] 786 // CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 787 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 788 // CHECK2-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 789 // CHECK2-NEXT: [[TMP8:%.*]] = load double, double* [[A6]], align 8 790 // CHECK2-NEXT: [[CONV7:%.*]] = fptosi double [[TMP8]] to i32 791 // CHECK2-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 792 // CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z3baziRd(i32 [[CONV7]], double* nonnull align 8 dereferenceable(8) [[A8]]) #[[ATTR9]] 793 // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 794 // CHECK2-NEXT: ret void 795 // CHECK2: worker.exit: 796 // CHECK2-NEXT: ret void 797 // 798 // 799 // CHECK2-LABEL: define {{[^@]+}}@_Z3baziRd 800 // CHECK2-SAME: (i32 [[F1:%.*]], double* nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR5]] { 801 // CHECK2-NEXT: entry: 802 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 803 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 4 804 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 805 // CHECK2-NEXT: [[F:%.*]] = call align 8 i8* @__kmpc_alloc_shared(i32 4) 806 // CHECK2-NEXT: [[F_ON_STACK:%.*]] = bitcast i8* [[F]] to i32* 807 // CHECK2-NEXT: store i32 [[F1]], i32* [[F_ON_STACK]], align 4 808 // CHECK2-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 809 // CHECK2-NEXT: [[TMP1:%.*]] = load double*, double** [[A_ADDR]], align 4 810 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 811 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i32* [[F_ON_STACK]] to i8* 812 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[TMP2]], align 4 813 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 814 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast double* [[TMP1]] to i8* 815 // CHECK2-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 4 816 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 817 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, double*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP6]], i32 2) 818 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[F_ON_STACK]], align 4 819 // CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[F]], i32 4) 820 // CHECK2-NEXT: ret i32 [[TMP7]] 821 // 822 // 823 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142 824 // CHECK2-SAME: () #[[ATTR4]] { 825 // CHECK2-NEXT: entry: 826 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 827 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 828 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 829 // CHECK2: user_code.entry: 830 // CHECK2-NEXT: call void @_Z6asserti(i32 0) #[[ATTR10:[0-9]+]] 831 // CHECK2-NEXT: unreachable 832 // CHECK2: worker.exit: 833 // CHECK2-NEXT: ret void 834 // CHECK2: 1: 835 // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 836 // CHECK2-NEXT: ret void 837 // 838 // 839 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74 840 // CHECK2-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4]] { 841 // CHECK2-NEXT: entry: 842 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 843 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 844 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 845 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 846 // CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 847 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 848 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 849 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 850 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 851 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 852 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 853 // CHECK2: user_code.entry: 854 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4 855 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1 856 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 857 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 858 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP3]] to i32 859 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 860 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 861 // CHECK2-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 862 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 863 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 864 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP4]], 1 865 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 866 // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 867 // CHECK2-NEXT: ret void 868 // CHECK2: worker.exit: 869 // CHECK2-NEXT: ret void 870 // 871 // 872 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 873 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[F:%.*]], double* nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] { 874 // CHECK2-NEXT: entry: 875 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 876 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 877 // CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 878 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 879 // CHECK2-NEXT: [[TMP:%.*]] = alloca double*, align 4 880 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 881 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 882 // CHECK2-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 883 // CHECK2-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 884 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[F_ADDR]], align 4 885 // CHECK2-NEXT: [[TMP1:%.*]] = load double*, double** [[A_ADDR]], align 4 886 // CHECK2-NEXT: store double* [[TMP1]], double** [[TMP]], align 4 887 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 4 888 // CHECK2-NEXT: [[TMP3:%.*]] = load double, double* [[TMP2]], align 8 889 // CHECK2-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]] 890 // CHECK2-NEXT: [[CONV:%.*]] = fptosi double [[ADD]] to i32 891 // CHECK2-NEXT: store i32 [[CONV]], i32* [[TMP0]], align 4 892 // CHECK2-NEXT: ret void 893 // 894 // 895 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 896 // CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR8:[0-9]+]] { 897 // CHECK2-NEXT: entry: 898 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 899 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 900 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 901 // CHECK2-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 902 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 903 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 904 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 905 // CHECK2-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 906 // CHECK2-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4 907 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0 908 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 909 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4 910 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 1 911 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to double** 912 // CHECK2-NEXT: [[TMP8:%.*]] = load double*, double** [[TMP7]], align 4 913 // CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], double* [[TMP8]]) #[[ATTR2:[0-9]+]] 914 // CHECK2-NEXT: ret void 915 // 916 // 917 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9targetBarPiS__l25 918 // CHECK3-SAME: (i32* [[PTR1:%.*]], i32** nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] { 919 // CHECK3-NEXT: entry: 920 // CHECK3-NEXT: [[PTR1_ADDR:%.*]] = alloca i32*, align 4 921 // CHECK3-NEXT: [[PTR2_ADDR:%.*]] = alloca i32**, align 4 922 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 4 923 // CHECK3-NEXT: store i32* [[PTR1]], i32** [[PTR1_ADDR]], align 4 924 // CHECK3-NEXT: store i32** [[PTR2]], i32*** [[PTR2_ADDR]], align 4 925 // CHECK3-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PTR2_ADDR]], align 4 926 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) 927 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 928 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 929 // CHECK3: user_code.entry: 930 // CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 931 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 932 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i32** [[PTR1_ADDR]] to i8* 933 // CHECK3-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4 934 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 935 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i32** [[TMP0]] to i8* 936 // CHECK3-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4 937 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 938 // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32*, i32*, i32**, i32**)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP7]], i32 2) 939 // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) 940 // CHECK3-NEXT: ret void 941 // CHECK3: worker.exit: 942 // CHECK3-NEXT: ret void 943 // 944 // 945 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ 946 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 4 dereferenceable(4) [[PTR1:%.*]], i32** nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR1:[0-9]+]] { 947 // CHECK3-NEXT: entry: 948 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 949 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 950 // CHECK3-NEXT: [[PTR1_ADDR:%.*]] = alloca i32**, align 4 951 // CHECK3-NEXT: [[PTR2_ADDR:%.*]] = alloca i32**, align 4 952 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 953 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 954 // CHECK3-NEXT: store i32** [[PTR1]], i32*** [[PTR1_ADDR]], align 4 955 // CHECK3-NEXT: store i32** [[PTR2]], i32*** [[PTR2_ADDR]], align 4 956 // CHECK3-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PTR1_ADDR]], align 4 957 // CHECK3-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[PTR2_ADDR]], align 4 958 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 4 959 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 960 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP0]], align 4 961 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP4]], align 4 962 // CHECK3-NEXT: ret void 963 // 964 // 965 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39 966 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 967 // CHECK3-NEXT: entry: 968 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 969 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 970 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 971 // CHECK3: user_code.entry: 972 // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 973 // CHECK3-NEXT: ret void 974 // CHECK3: worker.exit: 975 // CHECK3-NEXT: ret void 976 // 977 // 978 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47 979 // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR4]] { 980 // CHECK3-NEXT: entry: 981 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 982 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 983 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 984 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 985 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 986 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 987 // CHECK3: user_code.entry: 988 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 989 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 990 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 991 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 992 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 993 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 994 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 995 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2 996 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 997 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 998 // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 999 // CHECK3-NEXT: ret void 1000 // CHECK3: worker.exit: 1001 // CHECK3-NEXT: ret void 1002 // 1003 // 1004 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53 1005 // CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR4]] { 1006 // CHECK3-NEXT: entry: 1007 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1008 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 1009 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1010 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 1011 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 1012 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1013 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 1014 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 1015 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 1016 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1017 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 1018 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1019 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 1020 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 1021 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1022 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 1023 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 1024 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 1025 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 1026 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1027 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 1028 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 1029 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1030 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 1031 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 1032 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 1033 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 1034 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1 1035 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 1036 // CHECK3: user_code.entry: 1037 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 1038 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 1039 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1040 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 1041 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 1042 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP10]] to double 1043 // CHECK3-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 1044 // CHECK3-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 1045 // CHECK3-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 1046 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 1047 // CHECK3-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX7]], align 4 1048 // CHECK3-NEXT: [[CONV8:%.*]] = fpext float [[TMP11]] to double 1049 // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 1050 // CHECK3-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 1051 // CHECK3-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 1052 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 1053 // CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 1054 // CHECK3-NEXT: [[TMP12:%.*]] = load double, double* [[ARRAYIDX12]], align 8 1055 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[TMP12]], 1.000000e+00 1056 // CHECK3-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 1057 // CHECK3-NEXT: [[TMP13:%.*]] = mul nsw i32 1, [[TMP5]] 1058 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP13]] 1059 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 1060 // CHECK3-NEXT: [[TMP14:%.*]] = load double, double* [[ARRAYIDX15]], align 8 1061 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP14]], 1.000000e+00 1062 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 1063 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1064 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[X]], align 8 1065 // CHECK3-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP15]], 1 1066 // CHECK3-NEXT: store i64 [[ADD17]], i64* [[X]], align 8 1067 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1068 // CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[Y]], align 8 1069 // CHECK3-NEXT: [[CONV18:%.*]] = sext i8 [[TMP16]] to i32 1070 // CHECK3-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 1071 // CHECK3-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 1072 // CHECK3-NEXT: store i8 [[CONV20]], i8* [[Y]], align 8 1073 // CHECK3-NEXT: [[CALL:%.*]] = call nonnull align 8 dereferenceable(8) i64* @_ZN2TTIxcEixEi(%struct.TT* nonnull align 8 dereferenceable(16) [[TMP7]], i32 0) #[[ATTR9:[0-9]+]] 1074 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[CALL]], align 8 1075 // CHECK3-NEXT: [[ADD21:%.*]] = add nsw i64 [[TMP17]], 1 1076 // CHECK3-NEXT: store i64 [[ADD21]], i64* [[CALL]], align 8 1077 // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 1078 // CHECK3-NEXT: ret void 1079 // CHECK3: worker.exit: 1080 // CHECK3-NEXT: ret void 1081 // 1082 // 1083 // CHECK3-LABEL: define {{[^@]+}}@_ZN2TTIxcEixEi 1084 // CHECK3-SAME: (%struct.TT* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[I:%.*]]) #[[ATTR5:[0-9]+]] comdat align 2 { 1085 // CHECK3-NEXT: entry: 1086 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.TT*, align 4 1087 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 1088 // CHECK3-NEXT: store %struct.TT* [[THIS]], %struct.TT** [[THIS_ADDR]], align 4 1089 // CHECK3-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 1090 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.TT*, %struct.TT** [[THIS_ADDR]], align 4 1091 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[THIS1]], i32 0, i32 0 1092 // CHECK3-NEXT: ret i64* [[X]] 1093 // 1094 // 1095 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90 1096 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4]] { 1097 // CHECK3-NEXT: entry: 1098 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1099 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1100 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 1101 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 1102 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1103 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1104 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 1105 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 1106 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1107 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 1108 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 1109 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 1110 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 1111 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 1112 // CHECK3: user_code.entry: 1113 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4 1114 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1 1115 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1116 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 1117 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32 1118 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 1119 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1120 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 1121 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1 1122 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 1123 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 1124 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 1125 // CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 1126 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 1127 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1128 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP5]], 1 1129 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 1130 // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 1131 // CHECK3-NEXT: ret void 1132 // CHECK3: worker.exit: 1133 // CHECK3-NEXT: ret void 1134 // 1135 // 1136 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108 1137 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR4]] { 1138 // CHECK3-NEXT: entry: 1139 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1140 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1141 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1142 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1143 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 1144 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1145 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1146 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1147 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1148 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 1149 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1150 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1151 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1152 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 1153 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 1154 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 1155 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 1156 // CHECK3: user_code.entry: 1157 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4 1158 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double 1159 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 1160 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1161 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 8 1162 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1163 // CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 1164 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 1165 // CHECK3-NEXT: store double [[INC]], double* [[A3]], align 8 1166 // CHECK3-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 1167 // CHECK3-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] 1168 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP7]] 1169 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 1170 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 1171 // CHECK3-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1172 // CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[A6]], align 8 1173 // CHECK3-NEXT: [[CONV7:%.*]] = fptosi double [[TMP8]] to i32 1174 // CHECK3-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1175 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3baziRd(i32 [[CONV7]], double* nonnull align 8 dereferenceable(8) [[A8]]) #[[ATTR9]] 1176 // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 1177 // CHECK3-NEXT: ret void 1178 // CHECK3: worker.exit: 1179 // CHECK3-NEXT: ret void 1180 // 1181 // 1182 // CHECK3-LABEL: define {{[^@]+}}@_Z3baziRd 1183 // CHECK3-SAME: (i32 [[F1:%.*]], double* nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR5]] { 1184 // CHECK3-NEXT: entry: 1185 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 1186 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 4 1187 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 1188 // CHECK3-NEXT: [[F:%.*]] = call align 8 i8* @__kmpc_alloc_shared(i32 4) 1189 // CHECK3-NEXT: [[F_ON_STACK:%.*]] = bitcast i8* [[F]] to i32* 1190 // CHECK3-NEXT: store i32 [[F1]], i32* [[F_ON_STACK]], align 4 1191 // CHECK3-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 1192 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[A_ADDR]], align 4 1193 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 1194 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i32* [[F_ON_STACK]] to i8* 1195 // CHECK3-NEXT: store i8* [[TMP3]], i8** [[TMP2]], align 4 1196 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 1197 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast double* [[TMP1]] to i8* 1198 // CHECK3-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 4 1199 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 1200 // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, double*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP6]], i32 2) 1201 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[F_ON_STACK]], align 4 1202 // CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[F]], i32 4) 1203 // CHECK3-NEXT: ret i32 [[TMP7]] 1204 // 1205 // 1206 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142 1207 // CHECK3-SAME: () #[[ATTR4]] { 1208 // CHECK3-NEXT: entry: 1209 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 1210 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 1211 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 1212 // CHECK3: user_code.entry: 1213 // CHECK3-NEXT: call void @_Z6asserti(i32 0) #[[ATTR10:[0-9]+]] 1214 // CHECK3-NEXT: unreachable 1215 // CHECK3: worker.exit: 1216 // CHECK3-NEXT: ret void 1217 // CHECK3: 1: 1218 // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 1219 // CHECK3-NEXT: ret void 1220 // 1221 // 1222 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74 1223 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4]] { 1224 // CHECK3-NEXT: entry: 1225 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1226 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1227 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 1228 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1229 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1230 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 1231 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1232 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 1233 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) 1234 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 1235 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 1236 // CHECK3: user_code.entry: 1237 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4 1238 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1 1239 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1240 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 1241 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP3]] to i32 1242 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 1243 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 1244 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 1245 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 1246 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1247 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP4]], 1 1248 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 1249 // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) 1250 // CHECK3-NEXT: ret void 1251 // CHECK3: worker.exit: 1252 // CHECK3-NEXT: ret void 1253 // 1254 // 1255 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 1256 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[F:%.*]], double* nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] { 1257 // CHECK3-NEXT: entry: 1258 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1259 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1260 // CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 1261 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 1262 // CHECK3-NEXT: [[TMP:%.*]] = alloca double*, align 4 1263 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1264 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1265 // CHECK3-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 1266 // CHECK3-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 1267 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[F_ADDR]], align 4 1268 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[A_ADDR]], align 4 1269 // CHECK3-NEXT: store double* [[TMP1]], double** [[TMP]], align 4 1270 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 4 1271 // CHECK3-NEXT: [[TMP3:%.*]] = load double, double* [[TMP2]], align 8 1272 // CHECK3-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]] 1273 // CHECK3-NEXT: [[CONV:%.*]] = fptosi double [[ADD]] to i32 1274 // CHECK3-NEXT: store i32 [[CONV]], i32* [[TMP0]], align 4 1275 // CHECK3-NEXT: ret void 1276 // 1277 // 1278 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 1279 // CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR8:[0-9]+]] { 1280 // CHECK3-NEXT: entry: 1281 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 1282 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 1283 // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 1284 // CHECK3-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 1285 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 1286 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 1287 // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 1288 // CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 1289 // CHECK3-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4 1290 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0 1291 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 1292 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4 1293 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 1 1294 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to double** 1295 // CHECK3-NEXT: [[TMP8:%.*]] = load double*, double** [[TMP7]], align 4 1296 // CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], double* [[TMP8]]) #[[ATTR2:[0-9]+]] 1297 // CHECK3-NEXT: ret void 1298 // 1299