1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test target codegen - host bc file has to be created first. 3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 4 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 7 // RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK3 8 // expected-no-diagnostics 9 10 #ifndef HEADER 11 #define HEADER 12 13 __thread int id; 14 15 int baz(int f, double &a); 16 17 template <typename tx, typename ty> 18 struct TT { 19 tx X; 20 ty Y; 21 tx &operator[](int i) { return X; } 22 }; 23 24 void targetBar(int *Ptr1, int *Ptr2) { 25 #pragma omp target map(Ptr1[:0], Ptr2) 26 #pragma omp parallel num_threads(2) 27 *Ptr1 = *Ptr2; 28 } 29 30 int foo(int n) { 31 int a = 0; 32 short aa = 0; 33 float b[10]; 34 float bn[n]; 35 double c[5][10]; 36 double cn[5][n]; 37 TT<long long, char> d; 38 39 #pragma omp target 40 { 41 } 42 43 #pragma omp target if (0) 44 { 45 } 46 47 #pragma omp target if (1) 48 { 49 aa += 1; 50 aa += 2; 51 } 52 53 #pragma omp target if (n > 20) 54 { 55 a += 1; 56 b[2] += 1.0; 57 bn[3] += 1.0; 58 c[1][2] += 1.0; 59 cn[1][3] += 1.0; 60 d.X += 1; 61 d.Y += 1; 62 d[0] += 1; 63 } 64 65 return a; 66 } 67 68 template <typename tx> 69 tx ftemplate(int n) { 70 tx a = 0; 71 short aa = 0; 72 tx b[10]; 73 74 #pragma omp target if (n > 40) 75 { 76 a += 1; 77 aa += 1; 78 b[2] += 1; 79 } 80 81 return a; 82 } 83 84 static int fstatic(int n) { 85 int a = 0; 86 short aa = 0; 87 char aaa = 0; 88 int b[10]; 89 90 #pragma omp target if (n > 50) 91 { 92 a += 1; 93 aa += 1; 94 aaa += 1; 95 b[2] += 1; 96 } 97 98 return a; 99 } 100 101 struct S1 { 102 double a; 103 104 int r1(int n) { 105 int b = n + 1; 106 short int c[2][n]; 107 108 #pragma omp target if (n > 60) 109 { 110 this->a = (double)b + 1.5; 111 c[1][1] = ++a; 112 baz(a, a); 113 } 114 115 return c[1][1] + (int)b; 116 } 117 }; 118 119 int bar(int n) { 120 int a = 0; 121 122 a += foo(n); 123 124 S1 S; 125 a += S.r1(n); 126 127 a += fstatic(n); 128 129 a += ftemplate<int>(n); 130 131 return a; 132 } 133 134 int baz(int f, double &a) { 135 #pragma omp parallel 136 f = 2 + a; 137 return f; 138 } 139 140 extern void assert(int) throw() __attribute__((__noreturn__)); 141 void unreachable_call() { 142 #pragma omp target 143 assert(0); 144 } 145 146 #endif 147 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9targetBarPiS__l25 148 // CHECK1-SAME: (i32* [[PTR1:%.*]], i32** nonnull align 8 dereferenceable(8) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] { 149 // CHECK1-NEXT: entry: 150 // CHECK1-NEXT: [[PTR1_ADDR:%.*]] = alloca i32*, align 8 151 // CHECK1-NEXT: [[PTR2_ADDR:%.*]] = alloca i32**, align 8 152 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 8 153 // CHECK1-NEXT: store i32* [[PTR1]], i32** [[PTR1_ADDR]], align 8 154 // CHECK1-NEXT: store i32** [[PTR2]], i32*** [[PTR2_ADDR]], align 8 155 // CHECK1-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PTR2_ADDR]], align 8 156 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 157 // CHECK1-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1) 158 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack_spmd() 159 // CHECK1-NEXT: br label [[DOTEXECUTE:%.*]] 160 // CHECK1: .execute: 161 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 162 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 163 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i32** [[PTR1_ADDR]] to i8* 164 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[TMP2]], align 8 165 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 166 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i32** [[TMP0]] to i8* 167 // CHECK1-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8 168 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 169 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32**, i32**)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP6]], i64 2) 170 // CHECK1-NEXT: br label [[DOTOMP_DEINIT:%.*]] 171 // CHECK1: .omp.deinit: 172 // CHECK1-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 173 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 174 // CHECK1: .exit: 175 // CHECK1-NEXT: ret void 176 // 177 // 178 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ 179 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 8 dereferenceable(8) [[PTR1:%.*]], i32** nonnull align 8 dereferenceable(8) [[PTR2:%.*]]) #[[ATTR0]] { 180 // CHECK1-NEXT: entry: 181 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 182 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 183 // CHECK1-NEXT: [[PTR1_ADDR:%.*]] = alloca i32**, align 8 184 // CHECK1-NEXT: [[PTR2_ADDR:%.*]] = alloca i32**, align 8 185 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 186 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 187 // CHECK1-NEXT: store i32** [[PTR1]], i32*** [[PTR1_ADDR]], align 8 188 // CHECK1-NEXT: store i32** [[PTR2]], i32*** [[PTR2_ADDR]], align 8 189 // CHECK1-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PTR1_ADDR]], align 8 190 // CHECK1-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[PTR2_ADDR]], align 8 191 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 8 192 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 193 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP0]], align 8 194 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[TMP4]], align 4 195 // CHECK1-NEXT: ret void 196 // 197 // 198 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39_worker 199 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 200 // CHECK1-NEXT: entry: 201 // CHECK1-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 202 // CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 203 // CHECK1-NEXT: store i8* null, i8** [[WORK_FN]], align 8 204 // CHECK1-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 205 // CHECK1-NEXT: br label [[DOTAWAIT_WORK:%.*]] 206 // CHECK1: .await.work: 207 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 208 // CHECK1-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 209 // CHECK1-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 210 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 211 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 212 // CHECK1-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 213 // CHECK1-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 214 // CHECK1: .select.workers: 215 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 216 // CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 217 // CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 218 // CHECK1: .execute.parallel: 219 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 220 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 221 // CHECK1-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 222 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 223 // CHECK1: .terminate.parallel: 224 // CHECK1-NEXT: call void @__kmpc_kernel_end_parallel() 225 // CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]] 226 // CHECK1: .barrier.parallel: 227 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 228 // CHECK1-NEXT: br label [[DOTAWAIT_WORK]] 229 // CHECK1: .exit: 230 // CHECK1-NEXT: ret void 231 // 232 // 233 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39 234 // CHECK1-SAME: () #[[ATTR0]] { 235 // CHECK1-NEXT: entry: 236 // CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 237 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 238 // CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 239 // CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 240 // CHECK1-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 241 // CHECK1-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 242 // CHECK1: .worker: 243 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39_worker() #[[ATTR2:[0-9]+]] 244 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 245 // CHECK1: .mastercheck: 246 // CHECK1-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 247 // CHECK1-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 248 // CHECK1-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 249 // CHECK1-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 250 // CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 251 // CHECK1-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 252 // CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 253 // CHECK1-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 254 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 255 // CHECK1: .master: 256 // CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 257 // CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 258 // CHECK1-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 259 // CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 260 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack() 261 // CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 262 // CHECK1: .termination.notifier: 263 // CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1) 264 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 265 // CHECK1-NEXT: br label [[DOTEXIT]] 266 // CHECK1: .exit: 267 // CHECK1-NEXT: ret void 268 // 269 // 270 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47_worker 271 // CHECK1-SAME: () #[[ATTR3]] { 272 // CHECK1-NEXT: entry: 273 // CHECK1-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 274 // CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 275 // CHECK1-NEXT: store i8* null, i8** [[WORK_FN]], align 8 276 // CHECK1-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 277 // CHECK1-NEXT: br label [[DOTAWAIT_WORK:%.*]] 278 // CHECK1: .await.work: 279 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 280 // CHECK1-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 281 // CHECK1-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 282 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 283 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 284 // CHECK1-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 285 // CHECK1-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 286 // CHECK1: .select.workers: 287 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 288 // CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 289 // CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 290 // CHECK1: .execute.parallel: 291 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 292 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 293 // CHECK1-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 294 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 295 // CHECK1: .terminate.parallel: 296 // CHECK1-NEXT: call void @__kmpc_kernel_end_parallel() 297 // CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]] 298 // CHECK1: .barrier.parallel: 299 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 300 // CHECK1-NEXT: br label [[DOTAWAIT_WORK]] 301 // CHECK1: .exit: 302 // CHECK1-NEXT: ret void 303 // 304 // 305 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47 306 // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { 307 // CHECK1-NEXT: entry: 308 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 309 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 310 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 311 // CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 312 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 313 // CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 314 // CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 315 // CHECK1-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 316 // CHECK1-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 317 // CHECK1: .worker: 318 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47_worker() #[[ATTR2]] 319 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 320 // CHECK1: .mastercheck: 321 // CHECK1-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 322 // CHECK1-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 323 // CHECK1-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 324 // CHECK1-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 325 // CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 326 // CHECK1-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 327 // CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 328 // CHECK1-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 329 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 330 // CHECK1: .master: 331 // CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 332 // CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 333 // CHECK1-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 334 // CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 335 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack() 336 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 8 337 // CHECK1-NEXT: [[CONV7:%.*]] = sext i16 [[TMP5]] to i32 338 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV7]], 1 339 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD]] to i16 340 // CHECK1-NEXT: store i16 [[CONV8]], i16* [[CONV]], align 8 341 // CHECK1-NEXT: [[TMP6:%.*]] = load i16, i16* [[CONV]], align 8 342 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP6]] to i32 343 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], 2 344 // CHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 345 // CHECK1-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 8 346 // CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 347 // CHECK1: .termination.notifier: 348 // CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1) 349 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 350 // CHECK1-NEXT: br label [[DOTEXIT]] 351 // CHECK1: .exit: 352 // CHECK1-NEXT: ret void 353 // 354 // 355 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53_worker 356 // CHECK1-SAME: () #[[ATTR3]] { 357 // CHECK1-NEXT: entry: 358 // CHECK1-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 359 // CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 360 // CHECK1-NEXT: store i8* null, i8** [[WORK_FN]], align 8 361 // CHECK1-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 362 // CHECK1-NEXT: br label [[DOTAWAIT_WORK:%.*]] 363 // CHECK1: .await.work: 364 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 365 // CHECK1-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 366 // CHECK1-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 367 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 368 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 369 // CHECK1-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 370 // CHECK1-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 371 // CHECK1: .select.workers: 372 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 373 // CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 374 // CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 375 // CHECK1: .execute.parallel: 376 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 377 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 378 // CHECK1-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 379 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 380 // CHECK1: .terminate.parallel: 381 // CHECK1-NEXT: call void @__kmpc_kernel_end_parallel() 382 // CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]] 383 // CHECK1: .barrier.parallel: 384 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 385 // CHECK1-NEXT: br label [[DOTAWAIT_WORK]] 386 // CHECK1: .exit: 387 // CHECK1-NEXT: ret void 388 // 389 // 390 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53 391 // CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 392 // CHECK1-NEXT: entry: 393 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 394 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 395 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 396 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 397 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 398 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 399 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 400 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 401 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 402 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 403 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 404 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 405 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 406 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 407 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 408 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 409 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 410 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 411 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 412 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 413 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 414 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 415 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 416 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 417 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 418 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 419 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 420 // CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 421 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 422 // CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 423 // CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 424 // CHECK1-NEXT: [[TMP8:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 425 // CHECK1-NEXT: br i1 [[TMP8]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 426 // CHECK1: .worker: 427 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53_worker() #[[ATTR2]] 428 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 429 // CHECK1: .mastercheck: 430 // CHECK1-NEXT: [[NVPTX_TID5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 431 // CHECK1-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 432 // CHECK1-NEXT: [[NVPTX_WARP_SIZE7:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 433 // CHECK1-NEXT: [[TMP9:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE7]], 1 434 // CHECK1-NEXT: [[TMP10:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS6]], 1 435 // CHECK1-NEXT: [[TMP11:%.*]] = xor i32 [[TMP9]], -1 436 // CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP10]], [[TMP11]] 437 // CHECK1-NEXT: [[TMP12:%.*]] = icmp eq i32 [[NVPTX_TID5]], [[MASTER_TID]] 438 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 439 // CHECK1: .master: 440 // CHECK1-NEXT: [[NVPTX_NUM_THREADS8:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 441 // CHECK1-NEXT: [[NVPTX_WARP_SIZE9:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 442 // CHECK1-NEXT: [[THREAD_LIMIT10:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS8]], [[NVPTX_WARP_SIZE9]] 443 // CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT10]], i16 1) 444 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack() 445 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8 446 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 447 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 448 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 449 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 450 // CHECK1-NEXT: [[CONV11:%.*]] = fpext float [[TMP14]] to double 451 // CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 452 // CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 453 // CHECK1-NEXT: store float [[CONV13]], float* [[ARRAYIDX]], align 4 454 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 455 // CHECK1-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX14]], align 4 456 // CHECK1-NEXT: [[CONV15:%.*]] = fpext float [[TMP15]] to double 457 // CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[CONV15]], 1.000000e+00 458 // CHECK1-NEXT: [[CONV17:%.*]] = fptrunc double [[ADD16]] to float 459 // CHECK1-NEXT: store float [[CONV17]], float* [[ARRAYIDX14]], align 4 460 // CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 461 // CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX18]], i64 0, i64 2 462 // CHECK1-NEXT: [[TMP16:%.*]] = load double, double* [[ARRAYIDX19]], align 8 463 // CHECK1-NEXT: [[ADD20:%.*]] = fadd double [[TMP16]], 1.000000e+00 464 // CHECK1-NEXT: store double [[ADD20]], double* [[ARRAYIDX19]], align 8 465 // CHECK1-NEXT: [[TMP17:%.*]] = mul nsw i64 1, [[TMP5]] 466 // CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP17]] 467 // CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX21]], i64 3 468 // CHECK1-NEXT: [[TMP18:%.*]] = load double, double* [[ARRAYIDX22]], align 8 469 // CHECK1-NEXT: [[ADD23:%.*]] = fadd double [[TMP18]], 1.000000e+00 470 // CHECK1-NEXT: store double [[ADD23]], double* [[ARRAYIDX22]], align 8 471 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 472 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[X]], align 8 473 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i64 [[TMP19]], 1 474 // CHECK1-NEXT: store i64 [[ADD24]], i64* [[X]], align 8 475 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 476 // CHECK1-NEXT: [[TMP20:%.*]] = load i8, i8* [[Y]], align 8 477 // CHECK1-NEXT: [[CONV25:%.*]] = sext i8 [[TMP20]] to i32 478 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[CONV25]], 1 479 // CHECK1-NEXT: [[CONV27:%.*]] = trunc i32 [[ADD26]] to i8 480 // CHECK1-NEXT: store i8 [[CONV27]], i8* [[Y]], align 8 481 // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 8 dereferenceable(8) i64* @_ZN2TTIxcEixEi(%struct.TT* nonnull align 8 dereferenceable(16) [[TMP7]], i32 0) #[[ATTR7:[0-9]+]] 482 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[CALL]], align 8 483 // CHECK1-NEXT: [[ADD28:%.*]] = add nsw i64 [[TMP21]], 1 484 // CHECK1-NEXT: store i64 [[ADD28]], i64* [[CALL]], align 8 485 // CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 486 // CHECK1: .termination.notifier: 487 // CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1) 488 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 489 // CHECK1-NEXT: br label [[DOTEXIT]] 490 // CHECK1: .exit: 491 // CHECK1-NEXT: ret void 492 // 493 // 494 // CHECK1-LABEL: define {{[^@]+}}@_ZN2TTIxcEixEi 495 // CHECK1-SAME: (%struct.TT* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[I:%.*]]) #[[ATTR5:[0-9]+]] comdat align 2 { 496 // CHECK1-NEXT: entry: 497 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.TT*, align 8 498 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 499 // CHECK1-NEXT: store %struct.TT* [[THIS]], %struct.TT** [[THIS_ADDR]], align 8 500 // CHECK1-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 501 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.TT*, %struct.TT** [[THIS_ADDR]], align 8 502 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[THIS1]], i32 0, i32 0 503 // CHECK1-NEXT: ret i64* [[X]] 504 // 505 // 506 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90_worker 507 // CHECK1-SAME: () #[[ATTR3]] { 508 // CHECK1-NEXT: entry: 509 // CHECK1-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 510 // CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 511 // CHECK1-NEXT: store i8* null, i8** [[WORK_FN]], align 8 512 // CHECK1-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 513 // CHECK1-NEXT: br label [[DOTAWAIT_WORK:%.*]] 514 // CHECK1: .await.work: 515 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 516 // CHECK1-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 517 // CHECK1-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 518 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 519 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 520 // CHECK1-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 521 // CHECK1-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 522 // CHECK1: .select.workers: 523 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 524 // CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 525 // CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 526 // CHECK1: .execute.parallel: 527 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 528 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 529 // CHECK1-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 530 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 531 // CHECK1: .terminate.parallel: 532 // CHECK1-NEXT: call void @__kmpc_kernel_end_parallel() 533 // CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]] 534 // CHECK1: .barrier.parallel: 535 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 536 // CHECK1-NEXT: br label [[DOTAWAIT_WORK]] 537 // CHECK1: .exit: 538 // CHECK1-NEXT: ret void 539 // 540 // 541 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90 542 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 543 // CHECK1-NEXT: entry: 544 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 545 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 546 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 547 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 548 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 549 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 550 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 551 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 552 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 553 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 554 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 555 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 556 // CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 557 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 558 // CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 559 // CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 560 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 561 // CHECK1-NEXT: br i1 [[TMP1]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 562 // CHECK1: .worker: 563 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90_worker() #[[ATTR2]] 564 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 565 // CHECK1: .mastercheck: 566 // CHECK1-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 567 // CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 568 // CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 569 // CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE5]], 1 570 // CHECK1-NEXT: [[TMP3:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], 1 571 // CHECK1-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], -1 572 // CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP3]], [[TMP4]] 573 // CHECK1-NEXT: [[TMP5:%.*]] = icmp eq i32 [[NVPTX_TID3]], [[MASTER_TID]] 574 // CHECK1-NEXT: br i1 [[TMP5]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 575 // CHECK1: .master: 576 // CHECK1-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 577 // CHECK1-NEXT: [[NVPTX_WARP_SIZE7:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 578 // CHECK1-NEXT: [[THREAD_LIMIT8:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS6]], [[NVPTX_WARP_SIZE7]] 579 // CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT8]], i16 1) 580 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack() 581 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8 582 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 583 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 584 // CHECK1-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV1]], align 8 585 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32 586 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], 1 587 // CHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 588 // CHECK1-NEXT: store i16 [[CONV11]], i16* [[CONV1]], align 8 589 // CHECK1-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV2]], align 8 590 // CHECK1-NEXT: [[CONV12:%.*]] = sext i8 [[TMP8]] to i32 591 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 592 // CHECK1-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 593 // CHECK1-NEXT: store i8 [[CONV14]], i8* [[CONV2]], align 8 594 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 595 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 596 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP9]], 1 597 // CHECK1-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4 598 // CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 599 // CHECK1: .termination.notifier: 600 // CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1) 601 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 602 // CHECK1-NEXT: br label [[DOTEXIT]] 603 // CHECK1: .exit: 604 // CHECK1-NEXT: ret void 605 // 606 // 607 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108_worker 608 // CHECK1-SAME: () #[[ATTR3]] { 609 // CHECK1-NEXT: entry: 610 // CHECK1-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 611 // CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 612 // CHECK1-NEXT: store i8* null, i8** [[WORK_FN]], align 8 613 // CHECK1-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 614 // CHECK1-NEXT: br label [[DOTAWAIT_WORK:%.*]] 615 // CHECK1: .await.work: 616 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 617 // CHECK1-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 618 // CHECK1-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 619 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 620 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 621 // CHECK1-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 622 // CHECK1-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 623 // CHECK1: .select.workers: 624 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 625 // CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 626 // CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 627 // CHECK1: .execute.parallel: 628 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 629 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 630 // CHECK1-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 631 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 632 // CHECK1: .terminate.parallel: 633 // CHECK1-NEXT: call void @__kmpc_kernel_end_parallel() 634 // CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]] 635 // CHECK1: .barrier.parallel: 636 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 637 // CHECK1-NEXT: br label [[DOTAWAIT_WORK]] 638 // CHECK1: .exit: 639 // CHECK1-NEXT: ret void 640 // 641 // 642 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108 643 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 644 // CHECK1-NEXT: entry: 645 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 646 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 647 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 648 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 649 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 650 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 651 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 652 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 653 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 654 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 655 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 656 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 657 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 658 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 659 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 660 // CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 661 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 662 // CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 663 // CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 664 // CHECK1-NEXT: [[TMP4:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 665 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 666 // CHECK1: .worker: 667 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108_worker() #[[ATTR2]] 668 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 669 // CHECK1: .mastercheck: 670 // CHECK1-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 671 // CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 672 // CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 673 // CHECK1-NEXT: [[TMP5:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE5]], 1 674 // CHECK1-NEXT: [[TMP6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], 1 675 // CHECK1-NEXT: [[TMP7:%.*]] = xor i32 [[TMP5]], -1 676 // CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP6]], [[TMP7]] 677 // CHECK1-NEXT: [[TMP8:%.*]] = icmp eq i32 [[NVPTX_TID3]], [[MASTER_TID]] 678 // CHECK1-NEXT: br i1 [[TMP8]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 679 // CHECK1: .master: 680 // CHECK1-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 681 // CHECK1-NEXT: [[NVPTX_WARP_SIZE7:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 682 // CHECK1-NEXT: [[THREAD_LIMIT8:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS6]], [[NVPTX_WARP_SIZE7]] 683 // CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT8]], i16 1) 684 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack() 685 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 686 // CHECK1-NEXT: [[CONV9:%.*]] = sitofp i32 [[TMP9]] to double 687 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV9]], 1.500000e+00 688 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 689 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 690 // CHECK1-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 691 // CHECK1-NEXT: [[TMP10:%.*]] = load double, double* [[A10]], align 8 692 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 693 // CHECK1-NEXT: store double [[INC]], double* [[A10]], align 8 694 // CHECK1-NEXT: [[CONV11:%.*]] = fptosi double [[INC]] to i16 695 // CHECK1-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]] 696 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP11]] 697 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 698 // CHECK1-NEXT: store i16 [[CONV11]], i16* [[ARRAYIDX12]], align 2 699 // CHECK1-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 700 // CHECK1-NEXT: [[TMP12:%.*]] = load double, double* [[A13]], align 8 701 // CHECK1-NEXT: [[CONV14:%.*]] = fptosi double [[TMP12]] to i32 702 // CHECK1-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 703 // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z3baziRd(i32 [[CONV14]], double* nonnull align 8 dereferenceable(8) [[A15]]) #[[ATTR7]] 704 // CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 705 // CHECK1: .termination.notifier: 706 // CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1) 707 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 708 // CHECK1-NEXT: br label [[DOTEXIT]] 709 // CHECK1: .exit: 710 // CHECK1-NEXT: ret void 711 // 712 // 713 // CHECK1-LABEL: define {{[^@]+}}@_Z3baziRd 714 // CHECK1-SAME: (i32 [[F3:%.*]], double* nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR5]] { 715 // CHECK1-NEXT: entry: 716 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 717 // CHECK1-NEXT: [[F2:%.*]] = alloca i32, align 4 718 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 719 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 8 720 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 721 // CHECK1-NEXT: [[TMP1:%.*]] = call i16 @__kmpc_parallel_level(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) 722 // CHECK1-NEXT: [[TMP2:%.*]] = icmp eq i16 [[TMP1]], 0 723 // CHECK1-NEXT: [[TMP3:%.*]] = call i8 @__kmpc_is_spmd_exec_mode() #[[ATTR2]] 724 // CHECK1-NEXT: [[TMP4:%.*]] = icmp ne i8 [[TMP3]], 0 725 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTSPMD:%.*]], label [[DOTNON_SPMD:%.*]] 726 // CHECK1: .spmd: 727 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 728 // CHECK1: .non-spmd: 729 // CHECK1-NEXT: [[TMP5:%.*]] = select i1 [[TMP2]], i64 4, i64 128 730 // CHECK1-NEXT: [[TMP6:%.*]] = call i8* @__kmpc_data_sharing_coalesced_push_stack(i64 [[TMP5]], i16 0) 731 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to %struct._globalized_locals_ty* 732 // CHECK1-NEXT: br label [[DOTEXIT]] 733 // CHECK1: .exit: 734 // CHECK1-NEXT: [[_SELECT_STACK:%.*]] = phi %struct._globalized_locals_ty* [ null, [[DOTSPMD]] ], [ [[TMP7]], [[DOTNON_SPMD]] ] 735 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast %struct._globalized_locals_ty* [[_SELECT_STACK]] to %struct._globalized_locals_ty.0* 736 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[_SELECT_STACK]], i32 0, i32 0 737 // CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 738 // CHECK1-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID]], 31 739 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [32 x i32], [32 x i32]* [[F]], i32 0, i32 [[NVPTX_LANE_ID]] 740 // CHECK1-NEXT: [[F1:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_0:%.*]], %struct._globalized_locals_ty.0* [[TMP8]], i32 0, i32 0 741 // CHECK1-NEXT: [[TMP10:%.*]] = select i1 [[TMP2]], i32* [[F1]], i32* [[TMP9]] 742 // CHECK1-NEXT: [[TMP11:%.*]] = select i1 [[TMP4]], i32* [[F2]], i32* [[TMP10]] 743 // CHECK1-NEXT: store i32 [[F3]], i32* [[TMP11]], align 4 744 // CHECK1-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 745 // CHECK1-NEXT: [[TMP12:%.*]] = load double*, double** [[A_ADDR]], align 8 746 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 747 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i32* [[TMP11]] to i8* 748 // CHECK1-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 749 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 750 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast double* [[TMP12]] to i8* 751 // CHECK1-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 752 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 753 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, double*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP17]], i64 2) 754 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP11]], align 4 755 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[RETVAL]], align 4 756 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTEXIT5:%.*]], label [[DOTNON_SPMD4:%.*]] 757 // CHECK1: .non-spmd4: 758 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct._globalized_locals_ty* [[_SELECT_STACK]] to i8* 759 // CHECK1-NEXT: call void @__kmpc_data_sharing_pop_stack(i8* [[TMP19]]) 760 // CHECK1-NEXT: br label [[DOTEXIT5]] 761 // CHECK1: .exit5: 762 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 763 // CHECK1-NEXT: ret i32 [[TMP20]] 764 // 765 // 766 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142_worker 767 // CHECK1-SAME: () #[[ATTR3]] { 768 // CHECK1-NEXT: entry: 769 // CHECK1-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 770 // CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 771 // CHECK1-NEXT: store i8* null, i8** [[WORK_FN]], align 8 772 // CHECK1-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 773 // CHECK1-NEXT: br label [[DOTAWAIT_WORK:%.*]] 774 // CHECK1: .await.work: 775 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 776 // CHECK1-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 777 // CHECK1-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 778 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 779 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 780 // CHECK1-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 781 // CHECK1-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 782 // CHECK1: .select.workers: 783 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 784 // CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 785 // CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 786 // CHECK1: .execute.parallel: 787 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 788 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 789 // CHECK1-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 790 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 791 // CHECK1: .terminate.parallel: 792 // CHECK1-NEXT: call void @__kmpc_kernel_end_parallel() 793 // CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]] 794 // CHECK1: .barrier.parallel: 795 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 796 // CHECK1-NEXT: br label [[DOTAWAIT_WORK]] 797 // CHECK1: .exit: 798 // CHECK1-NEXT: ret void 799 // 800 // 801 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142 802 // CHECK1-SAME: () #[[ATTR0]] { 803 // CHECK1-NEXT: entry: 804 // CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 805 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 806 // CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 807 // CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 808 // CHECK1-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 809 // CHECK1-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 810 // CHECK1: .worker: 811 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142_worker() #[[ATTR2]] 812 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 813 // CHECK1: .mastercheck: 814 // CHECK1-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 815 // CHECK1-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 816 // CHECK1-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 817 // CHECK1-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 818 // CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 819 // CHECK1-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 820 // CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 821 // CHECK1-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 822 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 823 // CHECK1: .master: 824 // CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 825 // CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 826 // CHECK1-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 827 // CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 828 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack() 829 // CHECK1-NEXT: call void @_Z6asserti(i32 0) #[[ATTR8:[0-9]+]] 830 // CHECK1-NEXT: unreachable 831 // CHECK1: 5: 832 // CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 833 // CHECK1: .termination.notifier: 834 // CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1) 835 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 836 // CHECK1-NEXT: br label [[DOTEXIT]] 837 // CHECK1: .exit: 838 // CHECK1-NEXT: ret void 839 // 840 // 841 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74_worker 842 // CHECK1-SAME: () #[[ATTR3]] { 843 // CHECK1-NEXT: entry: 844 // CHECK1-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 845 // CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 846 // CHECK1-NEXT: store i8* null, i8** [[WORK_FN]], align 8 847 // CHECK1-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 848 // CHECK1-NEXT: br label [[DOTAWAIT_WORK:%.*]] 849 // CHECK1: .await.work: 850 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 851 // CHECK1-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 852 // CHECK1-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 853 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 854 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 855 // CHECK1-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 856 // CHECK1-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 857 // CHECK1: .select.workers: 858 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 859 // CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 860 // CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 861 // CHECK1: .execute.parallel: 862 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 863 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 864 // CHECK1-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 865 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 866 // CHECK1: .terminate.parallel: 867 // CHECK1-NEXT: call void @__kmpc_kernel_end_parallel() 868 // CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]] 869 // CHECK1: .barrier.parallel: 870 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 871 // CHECK1-NEXT: br label [[DOTAWAIT_WORK]] 872 // CHECK1: .exit: 873 // CHECK1-NEXT: ret void 874 // 875 // 876 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74 877 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 878 // CHECK1-NEXT: entry: 879 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 880 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 881 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 882 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 883 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 884 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 885 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 886 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 887 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 888 // CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 889 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 890 // CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 891 // CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 892 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 893 // CHECK1-NEXT: br i1 [[TMP1]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 894 // CHECK1: .worker: 895 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74_worker() #[[ATTR2]] 896 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 897 // CHECK1: .mastercheck: 898 // CHECK1-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 899 // CHECK1-NEXT: [[NVPTX_NUM_THREADS3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 900 // CHECK1-NEXT: [[NVPTX_WARP_SIZE4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 901 // CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE4]], 1 902 // CHECK1-NEXT: [[TMP3:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS3]], 1 903 // CHECK1-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], -1 904 // CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP3]], [[TMP4]] 905 // CHECK1-NEXT: [[TMP5:%.*]] = icmp eq i32 [[NVPTX_TID2]], [[MASTER_TID]] 906 // CHECK1-NEXT: br i1 [[TMP5]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 907 // CHECK1: .master: 908 // CHECK1-NEXT: [[NVPTX_NUM_THREADS5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 909 // CHECK1-NEXT: [[NVPTX_WARP_SIZE6:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 910 // CHECK1-NEXT: [[THREAD_LIMIT7:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS5]], [[NVPTX_WARP_SIZE6]] 911 // CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT7]], i16 1) 912 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack() 913 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8 914 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 915 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 916 // CHECK1-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV1]], align 8 917 // CHECK1-NEXT: [[CONV8:%.*]] = sext i16 [[TMP7]] to i32 918 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], 1 919 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i16 920 // CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV1]], align 8 921 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 922 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 923 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP8]], 1 924 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[ARRAYIDX]], align 4 925 // CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 926 // CHECK1: .termination.notifier: 927 // CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1) 928 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 929 // CHECK1-NEXT: br label [[DOTEXIT]] 930 // CHECK1: .exit: 931 // CHECK1-NEXT: ret void 932 // 933 // 934 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 935 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[F:%.*]], double* nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR0]] { 936 // CHECK1-NEXT: entry: 937 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 938 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 939 // CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 940 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 941 // CHECK1-NEXT: [[TMP:%.*]] = alloca double*, align 8 942 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 943 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 944 // CHECK1-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 945 // CHECK1-NEXT: store double* [[A]], double** [[A_ADDR]], align 8 946 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[F_ADDR]], align 8 947 // CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[A_ADDR]], align 8 948 // CHECK1-NEXT: store double* [[TMP1]], double** [[TMP]], align 8 949 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8 950 // CHECK1-NEXT: [[TMP3:%.*]] = load double, double* [[TMP2]], align 8 951 // CHECK1-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]] 952 // CHECK1-NEXT: [[CONV:%.*]] = fptosi double [[ADD]] to i32 953 // CHECK1-NEXT: store i32 [[CONV]], i32* [[TMP0]], align 4 954 // CHECK1-NEXT: ret void 955 // 956 // 957 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 958 // CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { 959 // CHECK1-NEXT: entry: 960 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 961 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 962 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 963 // CHECK1-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8 964 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 965 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 966 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 967 // CHECK1-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 968 // CHECK1-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8 969 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0 970 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 971 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 8 972 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 1 973 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to double** 974 // CHECK1-NEXT: [[TMP8:%.*]] = load double*, double** [[TMP7]], align 8 975 // CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], double* [[TMP8]]) #[[ATTR2]] 976 // CHECK1-NEXT: ret void 977 // 978 // 979 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9targetBarPiS__l25 980 // CHECK2-SAME: (i32* [[PTR1:%.*]], i32** nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] { 981 // CHECK2-NEXT: entry: 982 // CHECK2-NEXT: [[PTR1_ADDR:%.*]] = alloca i32*, align 4 983 // CHECK2-NEXT: [[PTR2_ADDR:%.*]] = alloca i32**, align 4 984 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 4 985 // CHECK2-NEXT: store i32* [[PTR1]], i32** [[PTR1_ADDR]], align 4 986 // CHECK2-NEXT: store i32** [[PTR2]], i32*** [[PTR2_ADDR]], align 4 987 // CHECK2-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PTR2_ADDR]], align 4 988 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 989 // CHECK2-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1) 990 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack_spmd() 991 // CHECK2-NEXT: br label [[DOTEXECUTE:%.*]] 992 // CHECK2: .execute: 993 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 994 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 995 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i32** [[PTR1_ADDR]] to i8* 996 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[TMP2]], align 4 997 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 998 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i32** [[TMP0]] to i8* 999 // CHECK2-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 4 1000 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 1001 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32**, i32**)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP6]], i32 2) 1002 // CHECK2-NEXT: br label [[DOTOMP_DEINIT:%.*]] 1003 // CHECK2: .omp.deinit: 1004 // CHECK2-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 1005 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 1006 // CHECK2: .exit: 1007 // CHECK2-NEXT: ret void 1008 // 1009 // 1010 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ 1011 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 4 dereferenceable(4) [[PTR1:%.*]], i32** nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR0]] { 1012 // CHECK2-NEXT: entry: 1013 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1014 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1015 // CHECK2-NEXT: [[PTR1_ADDR:%.*]] = alloca i32**, align 4 1016 // CHECK2-NEXT: [[PTR2_ADDR:%.*]] = alloca i32**, align 4 1017 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1018 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1019 // CHECK2-NEXT: store i32** [[PTR1]], i32*** [[PTR1_ADDR]], align 4 1020 // CHECK2-NEXT: store i32** [[PTR2]], i32*** [[PTR2_ADDR]], align 4 1021 // CHECK2-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PTR1_ADDR]], align 4 1022 // CHECK2-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[PTR2_ADDR]], align 4 1023 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 4 1024 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1025 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP0]], align 4 1026 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[TMP4]], align 4 1027 // CHECK2-NEXT: ret void 1028 // 1029 // 1030 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39_worker 1031 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 1032 // CHECK2-NEXT: entry: 1033 // CHECK2-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 1034 // CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 1035 // CHECK2-NEXT: store i8* null, i8** [[WORK_FN]], align 4 1036 // CHECK2-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 1037 // CHECK2-NEXT: br label [[DOTAWAIT_WORK:%.*]] 1038 // CHECK2: .await.work: 1039 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1040 // CHECK2-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 1041 // CHECK2-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 1042 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 1043 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 1044 // CHECK2-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 1045 // CHECK2-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 1046 // CHECK2: .select.workers: 1047 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 1048 // CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 1049 // CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 1050 // CHECK2: .execute.parallel: 1051 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 1052 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 1053 // CHECK2-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 1054 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 1055 // CHECK2: .terminate.parallel: 1056 // CHECK2-NEXT: call void @__kmpc_kernel_end_parallel() 1057 // CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]] 1058 // CHECK2: .barrier.parallel: 1059 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1060 // CHECK2-NEXT: br label [[DOTAWAIT_WORK]] 1061 // CHECK2: .exit: 1062 // CHECK2-NEXT: ret void 1063 // 1064 // 1065 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39 1066 // CHECK2-SAME: () #[[ATTR0]] { 1067 // CHECK2-NEXT: entry: 1068 // CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1069 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1070 // CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1071 // CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 1072 // CHECK2-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 1073 // CHECK2-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 1074 // CHECK2: .worker: 1075 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39_worker() #[[ATTR2:[0-9]+]] 1076 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 1077 // CHECK2: .mastercheck: 1078 // CHECK2-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1079 // CHECK2-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1080 // CHECK2-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1081 // CHECK2-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 1082 // CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 1083 // CHECK2-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 1084 // CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 1085 // CHECK2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 1086 // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 1087 // CHECK2: .master: 1088 // CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1089 // CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1090 // CHECK2-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 1091 // CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 1092 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack() 1093 // CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 1094 // CHECK2: .termination.notifier: 1095 // CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1) 1096 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1097 // CHECK2-NEXT: br label [[DOTEXIT]] 1098 // CHECK2: .exit: 1099 // CHECK2-NEXT: ret void 1100 // 1101 // 1102 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47_worker 1103 // CHECK2-SAME: () #[[ATTR3]] { 1104 // CHECK2-NEXT: entry: 1105 // CHECK2-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 1106 // CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 1107 // CHECK2-NEXT: store i8* null, i8** [[WORK_FN]], align 4 1108 // CHECK2-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 1109 // CHECK2-NEXT: br label [[DOTAWAIT_WORK:%.*]] 1110 // CHECK2: .await.work: 1111 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1112 // CHECK2-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 1113 // CHECK2-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 1114 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 1115 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 1116 // CHECK2-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 1117 // CHECK2-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 1118 // CHECK2: .select.workers: 1119 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 1120 // CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 1121 // CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 1122 // CHECK2: .execute.parallel: 1123 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 1124 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 1125 // CHECK2-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 1126 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 1127 // CHECK2: .terminate.parallel: 1128 // CHECK2-NEXT: call void @__kmpc_kernel_end_parallel() 1129 // CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]] 1130 // CHECK2: .barrier.parallel: 1131 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1132 // CHECK2-NEXT: br label [[DOTAWAIT_WORK]] 1133 // CHECK2: .exit: 1134 // CHECK2-NEXT: ret void 1135 // 1136 // 1137 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47 1138 // CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { 1139 // CHECK2-NEXT: entry: 1140 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1141 // CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1142 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1143 // CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1144 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1145 // CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1146 // CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 1147 // CHECK2-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 1148 // CHECK2-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 1149 // CHECK2: .worker: 1150 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47_worker() #[[ATTR2]] 1151 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 1152 // CHECK2: .mastercheck: 1153 // CHECK2-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1154 // CHECK2-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1155 // CHECK2-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1156 // CHECK2-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 1157 // CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 1158 // CHECK2-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 1159 // CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 1160 // CHECK2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 1161 // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 1162 // CHECK2: .master: 1163 // CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1164 // CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1165 // CHECK2-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 1166 // CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 1167 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack() 1168 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 1169 // CHECK2-NEXT: [[CONV7:%.*]] = sext i16 [[TMP5]] to i32 1170 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV7]], 1 1171 // CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD]] to i16 1172 // CHECK2-NEXT: store i16 [[CONV8]], i16* [[CONV]], align 4 1173 // CHECK2-NEXT: [[TMP6:%.*]] = load i16, i16* [[CONV]], align 4 1174 // CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP6]] to i32 1175 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], 2 1176 // CHECK2-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 1177 // CHECK2-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 4 1178 // CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 1179 // CHECK2: .termination.notifier: 1180 // CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1) 1181 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1182 // CHECK2-NEXT: br label [[DOTEXIT]] 1183 // CHECK2: .exit: 1184 // CHECK2-NEXT: ret void 1185 // 1186 // 1187 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53_worker 1188 // CHECK2-SAME: () #[[ATTR3]] { 1189 // CHECK2-NEXT: entry: 1190 // CHECK2-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 1191 // CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 1192 // CHECK2-NEXT: store i8* null, i8** [[WORK_FN]], align 4 1193 // CHECK2-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 1194 // CHECK2-NEXT: br label [[DOTAWAIT_WORK:%.*]] 1195 // CHECK2: .await.work: 1196 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1197 // CHECK2-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 1198 // CHECK2-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 1199 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 1200 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 1201 // CHECK2-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 1202 // CHECK2-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 1203 // CHECK2: .select.workers: 1204 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 1205 // CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 1206 // CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 1207 // CHECK2: .execute.parallel: 1208 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 1209 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 1210 // CHECK2-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 1211 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 1212 // CHECK2: .terminate.parallel: 1213 // CHECK2-NEXT: call void @__kmpc_kernel_end_parallel() 1214 // CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]] 1215 // CHECK2: .barrier.parallel: 1216 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1217 // CHECK2-NEXT: br label [[DOTAWAIT_WORK]] 1218 // CHECK2: .exit: 1219 // CHECK2-NEXT: ret void 1220 // 1221 // 1222 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53 1223 // CHECK2-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 1224 // CHECK2-NEXT: entry: 1225 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1226 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 1227 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1228 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 1229 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 1230 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1231 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 1232 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 1233 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 1234 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1235 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 1236 // CHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1237 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 1238 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 1239 // CHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1240 // CHECK2-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 1241 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 1242 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 1243 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 1244 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1245 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 1246 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 1247 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1248 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 1249 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 1250 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 1251 // CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1252 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1253 // CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1254 // CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 1255 // CHECK2-NEXT: [[TMP8:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 1256 // CHECK2-NEXT: br i1 [[TMP8]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 1257 // CHECK2: .worker: 1258 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53_worker() #[[ATTR2]] 1259 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 1260 // CHECK2: .mastercheck: 1261 // CHECK2-NEXT: [[NVPTX_TID5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1262 // CHECK2-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1263 // CHECK2-NEXT: [[NVPTX_WARP_SIZE7:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1264 // CHECK2-NEXT: [[TMP9:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE7]], 1 1265 // CHECK2-NEXT: [[TMP10:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS6]], 1 1266 // CHECK2-NEXT: [[TMP11:%.*]] = xor i32 [[TMP9]], -1 1267 // CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP10]], [[TMP11]] 1268 // CHECK2-NEXT: [[TMP12:%.*]] = icmp eq i32 [[NVPTX_TID5]], [[MASTER_TID]] 1269 // CHECK2-NEXT: br i1 [[TMP12]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 1270 // CHECK2: .master: 1271 // CHECK2-NEXT: [[NVPTX_NUM_THREADS8:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1272 // CHECK2-NEXT: [[NVPTX_WARP_SIZE9:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1273 // CHECK2-NEXT: [[THREAD_LIMIT10:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS8]], [[NVPTX_WARP_SIZE9]] 1274 // CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT10]], i16 1) 1275 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack() 1276 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[A_ADDR]], align 4 1277 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 1278 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1279 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 1280 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1281 // CHECK2-NEXT: [[CONV:%.*]] = fpext float [[TMP14]] to double 1282 // CHECK2-NEXT: [[ADD11:%.*]] = fadd double [[CONV]], 1.000000e+00 1283 // CHECK2-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 1284 // CHECK2-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 1285 // CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 1286 // CHECK2-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX13]], align 4 1287 // CHECK2-NEXT: [[CONV14:%.*]] = fpext float [[TMP15]] to double 1288 // CHECK2-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 1289 // CHECK2-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 1290 // CHECK2-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 1291 // CHECK2-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 1292 // CHECK2-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 1293 // CHECK2-NEXT: [[TMP16:%.*]] = load double, double* [[ARRAYIDX18]], align 8 1294 // CHECK2-NEXT: [[ADD19:%.*]] = fadd double [[TMP16]], 1.000000e+00 1295 // CHECK2-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 1296 // CHECK2-NEXT: [[TMP17:%.*]] = mul nsw i32 1, [[TMP5]] 1297 // CHECK2-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP17]] 1298 // CHECK2-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 1299 // CHECK2-NEXT: [[TMP18:%.*]] = load double, double* [[ARRAYIDX21]], align 8 1300 // CHECK2-NEXT: [[ADD22:%.*]] = fadd double [[TMP18]], 1.000000e+00 1301 // CHECK2-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 1302 // CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1303 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[X]], align 8 1304 // CHECK2-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP19]], 1 1305 // CHECK2-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 1306 // CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1307 // CHECK2-NEXT: [[TMP20:%.*]] = load i8, i8* [[Y]], align 8 1308 // CHECK2-NEXT: [[CONV24:%.*]] = sext i8 [[TMP20]] to i32 1309 // CHECK2-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 1310 // CHECK2-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 1311 // CHECK2-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 1312 // CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 8 dereferenceable(8) i64* @_ZN2TTIxcEixEi(%struct.TT* nonnull align 8 dereferenceable(16) [[TMP7]], i32 0) #[[ATTR7:[0-9]+]] 1313 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[CALL]], align 8 1314 // CHECK2-NEXT: [[ADD27:%.*]] = add nsw i64 [[TMP21]], 1 1315 // CHECK2-NEXT: store i64 [[ADD27]], i64* [[CALL]], align 8 1316 // CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 1317 // CHECK2: .termination.notifier: 1318 // CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1) 1319 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1320 // CHECK2-NEXT: br label [[DOTEXIT]] 1321 // CHECK2: .exit: 1322 // CHECK2-NEXT: ret void 1323 // 1324 // 1325 // CHECK2-LABEL: define {{[^@]+}}@_ZN2TTIxcEixEi 1326 // CHECK2-SAME: (%struct.TT* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[I:%.*]]) #[[ATTR5:[0-9]+]] comdat align 2 { 1327 // CHECK2-NEXT: entry: 1328 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.TT*, align 4 1329 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 1330 // CHECK2-NEXT: store %struct.TT* [[THIS]], %struct.TT** [[THIS_ADDR]], align 4 1331 // CHECK2-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 1332 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.TT*, %struct.TT** [[THIS_ADDR]], align 4 1333 // CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[THIS1]], i32 0, i32 0 1334 // CHECK2-NEXT: ret i64* [[X]] 1335 // 1336 // 1337 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90_worker 1338 // CHECK2-SAME: () #[[ATTR3]] { 1339 // CHECK2-NEXT: entry: 1340 // CHECK2-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 1341 // CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 1342 // CHECK2-NEXT: store i8* null, i8** [[WORK_FN]], align 4 1343 // CHECK2-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 1344 // CHECK2-NEXT: br label [[DOTAWAIT_WORK:%.*]] 1345 // CHECK2: .await.work: 1346 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1347 // CHECK2-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 1348 // CHECK2-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 1349 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 1350 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 1351 // CHECK2-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 1352 // CHECK2-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 1353 // CHECK2: .select.workers: 1354 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 1355 // CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 1356 // CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 1357 // CHECK2: .execute.parallel: 1358 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 1359 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 1360 // CHECK2-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 1361 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 1362 // CHECK2: .terminate.parallel: 1363 // CHECK2-NEXT: call void @__kmpc_kernel_end_parallel() 1364 // CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]] 1365 // CHECK2: .barrier.parallel: 1366 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1367 // CHECK2-NEXT: br label [[DOTAWAIT_WORK]] 1368 // CHECK2: .exit: 1369 // CHECK2-NEXT: ret void 1370 // 1371 // 1372 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90 1373 // CHECK2-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 1374 // CHECK2-NEXT: entry: 1375 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1376 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1377 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 1378 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 1379 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1380 // CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1381 // CHECK2-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 1382 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 1383 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1384 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 1385 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 1386 // CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1387 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1388 // CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1389 // CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 1390 // CHECK2-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 1391 // CHECK2-NEXT: br i1 [[TMP1]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 1392 // CHECK2: .worker: 1393 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90_worker() #[[ATTR2]] 1394 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 1395 // CHECK2: .mastercheck: 1396 // CHECK2-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1397 // CHECK2-NEXT: [[NVPTX_NUM_THREADS3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1398 // CHECK2-NEXT: [[NVPTX_WARP_SIZE4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1399 // CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE4]], 1 1400 // CHECK2-NEXT: [[TMP3:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS3]], 1 1401 // CHECK2-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], -1 1402 // CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP3]], [[TMP4]] 1403 // CHECK2-NEXT: [[TMP5:%.*]] = icmp eq i32 [[NVPTX_TID2]], [[MASTER_TID]] 1404 // CHECK2-NEXT: br i1 [[TMP5]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 1405 // CHECK2: .master: 1406 // CHECK2-NEXT: [[NVPTX_NUM_THREADS5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1407 // CHECK2-NEXT: [[NVPTX_WARP_SIZE6:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1408 // CHECK2-NEXT: [[THREAD_LIMIT7:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS5]], [[NVPTX_WARP_SIZE6]] 1409 // CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT7]], i16 1) 1410 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack() 1411 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A_ADDR]], align 4 1412 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 1413 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1414 // CHECK2-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4 1415 // CHECK2-NEXT: [[CONV8:%.*]] = sext i16 [[TMP7]] to i32 1416 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], 1 1417 // CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i16 1418 // CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4 1419 // CHECK2-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV1]], align 4 1420 // CHECK2-NEXT: [[CONV11:%.*]] = sext i8 [[TMP8]] to i32 1421 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 1422 // CHECK2-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i8 1423 // CHECK2-NEXT: store i8 [[CONV13]], i8* [[CONV1]], align 4 1424 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 1425 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1426 // CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 1427 // CHECK2-NEXT: store i32 [[ADD14]], i32* [[ARRAYIDX]], align 4 1428 // CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 1429 // CHECK2: .termination.notifier: 1430 // CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1) 1431 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1432 // CHECK2-NEXT: br label [[DOTEXIT]] 1433 // CHECK2: .exit: 1434 // CHECK2-NEXT: ret void 1435 // 1436 // 1437 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108_worker 1438 // CHECK2-SAME: () #[[ATTR3]] { 1439 // CHECK2-NEXT: entry: 1440 // CHECK2-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 1441 // CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 1442 // CHECK2-NEXT: store i8* null, i8** [[WORK_FN]], align 4 1443 // CHECK2-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 1444 // CHECK2-NEXT: br label [[DOTAWAIT_WORK:%.*]] 1445 // CHECK2: .await.work: 1446 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1447 // CHECK2-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 1448 // CHECK2-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 1449 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 1450 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 1451 // CHECK2-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 1452 // CHECK2-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 1453 // CHECK2: .select.workers: 1454 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 1455 // CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 1456 // CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 1457 // CHECK2: .execute.parallel: 1458 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 1459 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 1460 // CHECK2-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 1461 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 1462 // CHECK2: .terminate.parallel: 1463 // CHECK2-NEXT: call void @__kmpc_kernel_end_parallel() 1464 // CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]] 1465 // CHECK2: .barrier.parallel: 1466 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1467 // CHECK2-NEXT: br label [[DOTAWAIT_WORK]] 1468 // CHECK2: .exit: 1469 // CHECK2-NEXT: ret void 1470 // 1471 // 1472 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108 1473 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 1474 // CHECK2-NEXT: entry: 1475 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1476 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1477 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1478 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1479 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 1480 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1481 // CHECK2-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1482 // CHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1483 // CHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1484 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 1485 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1486 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1487 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1488 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 1489 // CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1490 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1491 // CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1492 // CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 1493 // CHECK2-NEXT: [[TMP4:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 1494 // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 1495 // CHECK2: .worker: 1496 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108_worker() #[[ATTR2]] 1497 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 1498 // CHECK2: .mastercheck: 1499 // CHECK2-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1500 // CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1501 // CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1502 // CHECK2-NEXT: [[TMP5:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE5]], 1 1503 // CHECK2-NEXT: [[TMP6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], 1 1504 // CHECK2-NEXT: [[TMP7:%.*]] = xor i32 [[TMP5]], -1 1505 // CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP6]], [[TMP7]] 1506 // CHECK2-NEXT: [[TMP8:%.*]] = icmp eq i32 [[NVPTX_TID3]], [[MASTER_TID]] 1507 // CHECK2-NEXT: br i1 [[TMP8]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 1508 // CHECK2: .master: 1509 // CHECK2-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1510 // CHECK2-NEXT: [[NVPTX_WARP_SIZE7:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1511 // CHECK2-NEXT: [[THREAD_LIMIT8:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS6]], [[NVPTX_WARP_SIZE7]] 1512 // CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT8]], i16 1) 1513 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack() 1514 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[B_ADDR]], align 4 1515 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double 1516 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 1517 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1518 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 1519 // CHECK2-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1520 // CHECK2-NEXT: [[TMP10:%.*]] = load double, double* [[A9]], align 8 1521 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 1522 // CHECK2-NEXT: store double [[INC]], double* [[A9]], align 8 1523 // CHECK2-NEXT: [[CONV10:%.*]] = fptosi double [[INC]] to i16 1524 // CHECK2-NEXT: [[TMP11:%.*]] = mul nsw i32 1, [[TMP2]] 1525 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP11]] 1526 // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 1527 // CHECK2-NEXT: store i16 [[CONV10]], i16* [[ARRAYIDX11]], align 2 1528 // CHECK2-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1529 // CHECK2-NEXT: [[TMP12:%.*]] = load double, double* [[A12]], align 8 1530 // CHECK2-NEXT: [[CONV13:%.*]] = fptosi double [[TMP12]] to i32 1531 // CHECK2-NEXT: [[A14:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1532 // CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z3baziRd(i32 [[CONV13]], double* nonnull align 8 dereferenceable(8) [[A14]]) #[[ATTR7]] 1533 // CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 1534 // CHECK2: .termination.notifier: 1535 // CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1) 1536 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1537 // CHECK2-NEXT: br label [[DOTEXIT]] 1538 // CHECK2: .exit: 1539 // CHECK2-NEXT: ret void 1540 // 1541 // 1542 // CHECK2-LABEL: define {{[^@]+}}@_Z3baziRd 1543 // CHECK2-SAME: (i32 [[F3:%.*]], double* nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR5]] { 1544 // CHECK2-NEXT: entry: 1545 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1546 // CHECK2-NEXT: [[F2:%.*]] = alloca i32, align 4 1547 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 1548 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 4 1549 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 1550 // CHECK2-NEXT: [[TMP1:%.*]] = call i16 @__kmpc_parallel_level(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) 1551 // CHECK2-NEXT: [[TMP2:%.*]] = icmp eq i16 [[TMP1]], 0 1552 // CHECK2-NEXT: [[TMP3:%.*]] = call i8 @__kmpc_is_spmd_exec_mode() #[[ATTR2]] 1553 // CHECK2-NEXT: [[TMP4:%.*]] = icmp ne i8 [[TMP3]], 0 1554 // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTSPMD:%.*]], label [[DOTNON_SPMD:%.*]] 1555 // CHECK2: .spmd: 1556 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 1557 // CHECK2: .non-spmd: 1558 // CHECK2-NEXT: [[TMP5:%.*]] = select i1 [[TMP2]], i32 4, i32 128 1559 // CHECK2-NEXT: [[TMP6:%.*]] = call i8* @__kmpc_data_sharing_coalesced_push_stack(i32 [[TMP5]], i16 0) 1560 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to %struct._globalized_locals_ty* 1561 // CHECK2-NEXT: br label [[DOTEXIT]] 1562 // CHECK2: .exit: 1563 // CHECK2-NEXT: [[_SELECT_STACK:%.*]] = phi %struct._globalized_locals_ty* [ null, [[DOTSPMD]] ], [ [[TMP7]], [[DOTNON_SPMD]] ] 1564 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast %struct._globalized_locals_ty* [[_SELECT_STACK]] to %struct._globalized_locals_ty.0* 1565 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[_SELECT_STACK]], i32 0, i32 0 1566 // CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1567 // CHECK2-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID]], 31 1568 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [32 x i32], [32 x i32]* [[F]], i32 0, i32 [[NVPTX_LANE_ID]] 1569 // CHECK2-NEXT: [[F1:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_0:%.*]], %struct._globalized_locals_ty.0* [[TMP8]], i32 0, i32 0 1570 // CHECK2-NEXT: [[TMP10:%.*]] = select i1 [[TMP2]], i32* [[F1]], i32* [[TMP9]] 1571 // CHECK2-NEXT: [[TMP11:%.*]] = select i1 [[TMP4]], i32* [[F2]], i32* [[TMP10]] 1572 // CHECK2-NEXT: store i32 [[F3]], i32* [[TMP11]], align 4 1573 // CHECK2-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 1574 // CHECK2-NEXT: [[TMP12:%.*]] = load double*, double** [[A_ADDR]], align 4 1575 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 1576 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i32* [[TMP11]] to i8* 1577 // CHECK2-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 4 1578 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 1579 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast double* [[TMP12]] to i8* 1580 // CHECK2-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 4 1581 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 1582 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, double*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP17]], i32 2) 1583 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP11]], align 4 1584 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[RETVAL]], align 4 1585 // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTEXIT5:%.*]], label [[DOTNON_SPMD4:%.*]] 1586 // CHECK2: .non-spmd4: 1587 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct._globalized_locals_ty* [[_SELECT_STACK]] to i8* 1588 // CHECK2-NEXT: call void @__kmpc_data_sharing_pop_stack(i8* [[TMP19]]) 1589 // CHECK2-NEXT: br label [[DOTEXIT5]] 1590 // CHECK2: .exit5: 1591 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 1592 // CHECK2-NEXT: ret i32 [[TMP20]] 1593 // 1594 // 1595 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142_worker 1596 // CHECK2-SAME: () #[[ATTR3]] { 1597 // CHECK2-NEXT: entry: 1598 // CHECK2-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 1599 // CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 1600 // CHECK2-NEXT: store i8* null, i8** [[WORK_FN]], align 4 1601 // CHECK2-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 1602 // CHECK2-NEXT: br label [[DOTAWAIT_WORK:%.*]] 1603 // CHECK2: .await.work: 1604 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1605 // CHECK2-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 1606 // CHECK2-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 1607 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 1608 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 1609 // CHECK2-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 1610 // CHECK2-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 1611 // CHECK2: .select.workers: 1612 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 1613 // CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 1614 // CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 1615 // CHECK2: .execute.parallel: 1616 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 1617 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 1618 // CHECK2-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 1619 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 1620 // CHECK2: .terminate.parallel: 1621 // CHECK2-NEXT: call void @__kmpc_kernel_end_parallel() 1622 // CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]] 1623 // CHECK2: .barrier.parallel: 1624 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1625 // CHECK2-NEXT: br label [[DOTAWAIT_WORK]] 1626 // CHECK2: .exit: 1627 // CHECK2-NEXT: ret void 1628 // 1629 // 1630 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142 1631 // CHECK2-SAME: () #[[ATTR0]] { 1632 // CHECK2-NEXT: entry: 1633 // CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1634 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1635 // CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1636 // CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 1637 // CHECK2-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 1638 // CHECK2-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 1639 // CHECK2: .worker: 1640 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142_worker() #[[ATTR2]] 1641 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 1642 // CHECK2: .mastercheck: 1643 // CHECK2-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1644 // CHECK2-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1645 // CHECK2-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1646 // CHECK2-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 1647 // CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 1648 // CHECK2-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 1649 // CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 1650 // CHECK2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 1651 // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 1652 // CHECK2: .master: 1653 // CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1654 // CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1655 // CHECK2-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 1656 // CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 1657 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack() 1658 // CHECK2-NEXT: call void @_Z6asserti(i32 0) #[[ATTR8:[0-9]+]] 1659 // CHECK2-NEXT: unreachable 1660 // CHECK2: 5: 1661 // CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 1662 // CHECK2: .termination.notifier: 1663 // CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1) 1664 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1665 // CHECK2-NEXT: br label [[DOTEXIT]] 1666 // CHECK2: .exit: 1667 // CHECK2-NEXT: ret void 1668 // 1669 // 1670 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74_worker 1671 // CHECK2-SAME: () #[[ATTR3]] { 1672 // CHECK2-NEXT: entry: 1673 // CHECK2-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 1674 // CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 1675 // CHECK2-NEXT: store i8* null, i8** [[WORK_FN]], align 4 1676 // CHECK2-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 1677 // CHECK2-NEXT: br label [[DOTAWAIT_WORK:%.*]] 1678 // CHECK2: .await.work: 1679 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1680 // CHECK2-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 1681 // CHECK2-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 1682 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 1683 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 1684 // CHECK2-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 1685 // CHECK2-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 1686 // CHECK2: .select.workers: 1687 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 1688 // CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 1689 // CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 1690 // CHECK2: .execute.parallel: 1691 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 1692 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 1693 // CHECK2-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 1694 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 1695 // CHECK2: .terminate.parallel: 1696 // CHECK2-NEXT: call void @__kmpc_kernel_end_parallel() 1697 // CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]] 1698 // CHECK2: .barrier.parallel: 1699 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1700 // CHECK2-NEXT: br label [[DOTAWAIT_WORK]] 1701 // CHECK2: .exit: 1702 // CHECK2-NEXT: ret void 1703 // 1704 // 1705 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74 1706 // CHECK2-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 1707 // CHECK2-NEXT: entry: 1708 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1709 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1710 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 1711 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1712 // CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1713 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 1714 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1715 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 1716 // CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1717 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1718 // CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1719 // CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 1720 // CHECK2-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 1721 // CHECK2-NEXT: br i1 [[TMP1]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 1722 // CHECK2: .worker: 1723 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74_worker() #[[ATTR2]] 1724 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 1725 // CHECK2: .mastercheck: 1726 // CHECK2-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1727 // CHECK2-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1728 // CHECK2-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1729 // CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 1730 // CHECK2-NEXT: [[TMP3:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 1731 // CHECK2-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], -1 1732 // CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP3]], [[TMP4]] 1733 // CHECK2-NEXT: [[TMP5:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 1734 // CHECK2-NEXT: br i1 [[TMP5]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 1735 // CHECK2: .master: 1736 // CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1737 // CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1738 // CHECK2-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 1739 // CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 1740 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack() 1741 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A_ADDR]], align 4 1742 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 1743 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1744 // CHECK2-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4 1745 // CHECK2-NEXT: [[CONV7:%.*]] = sext i16 [[TMP7]] to i32 1746 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1 1747 // CHECK2-NEXT: [[CONV9:%.*]] = trunc i32 [[ADD8]] to i16 1748 // CHECK2-NEXT: store i16 [[CONV9]], i16* [[CONV]], align 4 1749 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 1750 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1751 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP8]], 1 1752 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[ARRAYIDX]], align 4 1753 // CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 1754 // CHECK2: .termination.notifier: 1755 // CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1) 1756 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1757 // CHECK2-NEXT: br label [[DOTEXIT]] 1758 // CHECK2: .exit: 1759 // CHECK2-NEXT: ret void 1760 // 1761 // 1762 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 1763 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[F:%.*]], double* nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR0]] { 1764 // CHECK2-NEXT: entry: 1765 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1766 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1767 // CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 1768 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 1769 // CHECK2-NEXT: [[TMP:%.*]] = alloca double*, align 4 1770 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1771 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1772 // CHECK2-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 1773 // CHECK2-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 1774 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[F_ADDR]], align 4 1775 // CHECK2-NEXT: [[TMP1:%.*]] = load double*, double** [[A_ADDR]], align 4 1776 // CHECK2-NEXT: store double* [[TMP1]], double** [[TMP]], align 4 1777 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 4 1778 // CHECK2-NEXT: [[TMP3:%.*]] = load double, double* [[TMP2]], align 8 1779 // CHECK2-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]] 1780 // CHECK2-NEXT: [[CONV:%.*]] = fptosi double [[ADD]] to i32 1781 // CHECK2-NEXT: store i32 [[CONV]], i32* [[TMP0]], align 4 1782 // CHECK2-NEXT: ret void 1783 // 1784 // 1785 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 1786 // CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { 1787 // CHECK2-NEXT: entry: 1788 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 1789 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 1790 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 1791 // CHECK2-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 1792 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 1793 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 1794 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 1795 // CHECK2-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 1796 // CHECK2-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4 1797 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0 1798 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 1799 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4 1800 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 1 1801 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to double** 1802 // CHECK2-NEXT: [[TMP8:%.*]] = load double*, double** [[TMP7]], align 4 1803 // CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], double* [[TMP8]]) #[[ATTR2]] 1804 // CHECK2-NEXT: ret void 1805 // 1806 // 1807 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9targetBarPiS__l25 1808 // CHECK3-SAME: (i32* [[PTR1:%.*]], i32** nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] { 1809 // CHECK3-NEXT: entry: 1810 // CHECK3-NEXT: [[PTR1_ADDR:%.*]] = alloca i32*, align 4 1811 // CHECK3-NEXT: [[PTR2_ADDR:%.*]] = alloca i32**, align 4 1812 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 4 1813 // CHECK3-NEXT: store i32* [[PTR1]], i32** [[PTR1_ADDR]], align 4 1814 // CHECK3-NEXT: store i32** [[PTR2]], i32*** [[PTR2_ADDR]], align 4 1815 // CHECK3-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PTR2_ADDR]], align 4 1816 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1817 // CHECK3-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1) 1818 // CHECK3-NEXT: call void @__kmpc_data_sharing_init_stack_spmd() 1819 // CHECK3-NEXT: br label [[DOTEXECUTE:%.*]] 1820 // CHECK3: .execute: 1821 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 1822 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 1823 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i32** [[PTR1_ADDR]] to i8* 1824 // CHECK3-NEXT: store i8* [[TMP3]], i8** [[TMP2]], align 4 1825 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 1826 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i32** [[TMP0]] to i8* 1827 // CHECK3-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 4 1828 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 1829 // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32**, i32**)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP6]], i32 2) 1830 // CHECK3-NEXT: br label [[DOTOMP_DEINIT:%.*]] 1831 // CHECK3: .omp.deinit: 1832 // CHECK3-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 1833 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 1834 // CHECK3: .exit: 1835 // CHECK3-NEXT: ret void 1836 // 1837 // 1838 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ 1839 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 4 dereferenceable(4) [[PTR1:%.*]], i32** nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR0]] { 1840 // CHECK3-NEXT: entry: 1841 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1842 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1843 // CHECK3-NEXT: [[PTR1_ADDR:%.*]] = alloca i32**, align 4 1844 // CHECK3-NEXT: [[PTR2_ADDR:%.*]] = alloca i32**, align 4 1845 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1846 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1847 // CHECK3-NEXT: store i32** [[PTR1]], i32*** [[PTR1_ADDR]], align 4 1848 // CHECK3-NEXT: store i32** [[PTR2]], i32*** [[PTR2_ADDR]], align 4 1849 // CHECK3-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PTR1_ADDR]], align 4 1850 // CHECK3-NEXT: [[TMP1:%.*]] = load i32**, i32*** [[PTR2_ADDR]], align 4 1851 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 4 1852 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1853 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP0]], align 4 1854 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP4]], align 4 1855 // CHECK3-NEXT: ret void 1856 // 1857 // 1858 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39_worker 1859 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1860 // CHECK3-NEXT: entry: 1861 // CHECK3-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 1862 // CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 1863 // CHECK3-NEXT: store i8* null, i8** [[WORK_FN]], align 4 1864 // CHECK3-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 1865 // CHECK3-NEXT: br label [[DOTAWAIT_WORK:%.*]] 1866 // CHECK3: .await.work: 1867 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1868 // CHECK3-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 1869 // CHECK3-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 1870 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 1871 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 1872 // CHECK3-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 1873 // CHECK3-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 1874 // CHECK3: .select.workers: 1875 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 1876 // CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 1877 // CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 1878 // CHECK3: .execute.parallel: 1879 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 1880 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 1881 // CHECK3-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 1882 // CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 1883 // CHECK3: .terminate.parallel: 1884 // CHECK3-NEXT: call void @__kmpc_kernel_end_parallel() 1885 // CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]] 1886 // CHECK3: .barrier.parallel: 1887 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1888 // CHECK3-NEXT: br label [[DOTAWAIT_WORK]] 1889 // CHECK3: .exit: 1890 // CHECK3-NEXT: ret void 1891 // 1892 // 1893 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39 1894 // CHECK3-SAME: () #[[ATTR0]] { 1895 // CHECK3-NEXT: entry: 1896 // CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1897 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1898 // CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1899 // CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 1900 // CHECK3-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 1901 // CHECK3-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 1902 // CHECK3: .worker: 1903 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39_worker() #[[ATTR2:[0-9]+]] 1904 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 1905 // CHECK3: .mastercheck: 1906 // CHECK3-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1907 // CHECK3-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1908 // CHECK3-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1909 // CHECK3-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 1910 // CHECK3-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 1911 // CHECK3-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 1912 // CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 1913 // CHECK3-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 1914 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 1915 // CHECK3: .master: 1916 // CHECK3-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1917 // CHECK3-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1918 // CHECK3-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 1919 // CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 1920 // CHECK3-NEXT: call void @__kmpc_data_sharing_init_stack() 1921 // CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 1922 // CHECK3: .termination.notifier: 1923 // CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1) 1924 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1925 // CHECK3-NEXT: br label [[DOTEXIT]] 1926 // CHECK3: .exit: 1927 // CHECK3-NEXT: ret void 1928 // 1929 // 1930 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47_worker 1931 // CHECK3-SAME: () #[[ATTR3]] { 1932 // CHECK3-NEXT: entry: 1933 // CHECK3-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 1934 // CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 1935 // CHECK3-NEXT: store i8* null, i8** [[WORK_FN]], align 4 1936 // CHECK3-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 1937 // CHECK3-NEXT: br label [[DOTAWAIT_WORK:%.*]] 1938 // CHECK3: .await.work: 1939 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1940 // CHECK3-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 1941 // CHECK3-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 1942 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 1943 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 1944 // CHECK3-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 1945 // CHECK3-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 1946 // CHECK3: .select.workers: 1947 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 1948 // CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 1949 // CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 1950 // CHECK3: .execute.parallel: 1951 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 1952 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 1953 // CHECK3-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 1954 // CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 1955 // CHECK3: .terminate.parallel: 1956 // CHECK3-NEXT: call void @__kmpc_kernel_end_parallel() 1957 // CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]] 1958 // CHECK3: .barrier.parallel: 1959 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 1960 // CHECK3-NEXT: br label [[DOTAWAIT_WORK]] 1961 // CHECK3: .exit: 1962 // CHECK3-NEXT: ret void 1963 // 1964 // 1965 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47 1966 // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { 1967 // CHECK3-NEXT: entry: 1968 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1969 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1970 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1971 // CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1972 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1973 // CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1974 // CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 1975 // CHECK3-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 1976 // CHECK3-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 1977 // CHECK3: .worker: 1978 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47_worker() #[[ATTR2]] 1979 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 1980 // CHECK3: .mastercheck: 1981 // CHECK3-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 1982 // CHECK3-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1983 // CHECK3-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1984 // CHECK3-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 1985 // CHECK3-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 1986 // CHECK3-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 1987 // CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 1988 // CHECK3-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 1989 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 1990 // CHECK3: .master: 1991 // CHECK3-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 1992 // CHECK3-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 1993 // CHECK3-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 1994 // CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 1995 // CHECK3-NEXT: call void @__kmpc_data_sharing_init_stack() 1996 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 1997 // CHECK3-NEXT: [[CONV7:%.*]] = sext i16 [[TMP5]] to i32 1998 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV7]], 1 1999 // CHECK3-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD]] to i16 2000 // CHECK3-NEXT: store i16 [[CONV8]], i16* [[CONV]], align 4 2001 // CHECK3-NEXT: [[TMP6:%.*]] = load i16, i16* [[CONV]], align 4 2002 // CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP6]] to i32 2003 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], 2 2004 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 2005 // CHECK3-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 4 2006 // CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 2007 // CHECK3: .termination.notifier: 2008 // CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1) 2009 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2010 // CHECK3-NEXT: br label [[DOTEXIT]] 2011 // CHECK3: .exit: 2012 // CHECK3-NEXT: ret void 2013 // 2014 // 2015 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53_worker 2016 // CHECK3-SAME: () #[[ATTR3]] { 2017 // CHECK3-NEXT: entry: 2018 // CHECK3-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 2019 // CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 2020 // CHECK3-NEXT: store i8* null, i8** [[WORK_FN]], align 4 2021 // CHECK3-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 2022 // CHECK3-NEXT: br label [[DOTAWAIT_WORK:%.*]] 2023 // CHECK3: .await.work: 2024 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2025 // CHECK3-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 2026 // CHECK3-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 2027 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 2028 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 2029 // CHECK3-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 2030 // CHECK3-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 2031 // CHECK3: .select.workers: 2032 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 2033 // CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 2034 // CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 2035 // CHECK3: .execute.parallel: 2036 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 2037 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 2038 // CHECK3-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 2039 // CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 2040 // CHECK3: .terminate.parallel: 2041 // CHECK3-NEXT: call void @__kmpc_kernel_end_parallel() 2042 // CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]] 2043 // CHECK3: .barrier.parallel: 2044 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2045 // CHECK3-NEXT: br label [[DOTAWAIT_WORK]] 2046 // CHECK3: .exit: 2047 // CHECK3-NEXT: ret void 2048 // 2049 // 2050 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53 2051 // CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 2052 // CHECK3-NEXT: entry: 2053 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2054 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2055 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2056 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2057 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2058 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2059 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2060 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2061 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2062 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2063 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2064 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2065 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2066 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2067 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2068 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2069 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2070 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2071 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2072 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2073 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2074 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2075 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2076 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2077 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2078 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2079 // CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 2080 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2081 // CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2082 // CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 2083 // CHECK3-NEXT: [[TMP8:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 2084 // CHECK3-NEXT: br i1 [[TMP8]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 2085 // CHECK3: .worker: 2086 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53_worker() #[[ATTR2]] 2087 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 2088 // CHECK3: .mastercheck: 2089 // CHECK3-NEXT: [[NVPTX_TID5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 2090 // CHECK3-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2091 // CHECK3-NEXT: [[NVPTX_WARP_SIZE7:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2092 // CHECK3-NEXT: [[TMP9:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE7]], 1 2093 // CHECK3-NEXT: [[TMP10:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS6]], 1 2094 // CHECK3-NEXT: [[TMP11:%.*]] = xor i32 [[TMP9]], -1 2095 // CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP10]], [[TMP11]] 2096 // CHECK3-NEXT: [[TMP12:%.*]] = icmp eq i32 [[NVPTX_TID5]], [[MASTER_TID]] 2097 // CHECK3-NEXT: br i1 [[TMP12]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 2098 // CHECK3: .master: 2099 // CHECK3-NEXT: [[NVPTX_NUM_THREADS8:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2100 // CHECK3-NEXT: [[NVPTX_WARP_SIZE9:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2101 // CHECK3-NEXT: [[THREAD_LIMIT10:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS8]], [[NVPTX_WARP_SIZE9]] 2102 // CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT10]], i16 1) 2103 // CHECK3-NEXT: call void @__kmpc_data_sharing_init_stack() 2104 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[A_ADDR]], align 4 2105 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 2106 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2107 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 2108 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2109 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP14]] to double 2110 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[CONV]], 1.000000e+00 2111 // CHECK3-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 2112 // CHECK3-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 2113 // CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 2114 // CHECK3-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX13]], align 4 2115 // CHECK3-NEXT: [[CONV14:%.*]] = fpext float [[TMP15]] to double 2116 // CHECK3-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 2117 // CHECK3-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 2118 // CHECK3-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 2119 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 2120 // CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 2121 // CHECK3-NEXT: [[TMP16:%.*]] = load double, double* [[ARRAYIDX18]], align 8 2122 // CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP16]], 1.000000e+00 2123 // CHECK3-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 2124 // CHECK3-NEXT: [[TMP17:%.*]] = mul nsw i32 1, [[TMP5]] 2125 // CHECK3-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP17]] 2126 // CHECK3-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 2127 // CHECK3-NEXT: [[TMP18:%.*]] = load double, double* [[ARRAYIDX21]], align 8 2128 // CHECK3-NEXT: [[ADD22:%.*]] = fadd double [[TMP18]], 1.000000e+00 2129 // CHECK3-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 2130 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2131 // CHECK3-NEXT: [[TMP19:%.*]] = load i64, i64* [[X]], align 8 2132 // CHECK3-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP19]], 1 2133 // CHECK3-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 2134 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2135 // CHECK3-NEXT: [[TMP20:%.*]] = load i8, i8* [[Y]], align 8 2136 // CHECK3-NEXT: [[CONV24:%.*]] = sext i8 [[TMP20]] to i32 2137 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 2138 // CHECK3-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 2139 // CHECK3-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 2140 // CHECK3-NEXT: [[CALL:%.*]] = call nonnull align 8 dereferenceable(8) i64* @_ZN2TTIxcEixEi(%struct.TT* nonnull align 8 dereferenceable(16) [[TMP7]], i32 0) #[[ATTR7:[0-9]+]] 2141 // CHECK3-NEXT: [[TMP21:%.*]] = load i64, i64* [[CALL]], align 8 2142 // CHECK3-NEXT: [[ADD27:%.*]] = add nsw i64 [[TMP21]], 1 2143 // CHECK3-NEXT: store i64 [[ADD27]], i64* [[CALL]], align 8 2144 // CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 2145 // CHECK3: .termination.notifier: 2146 // CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1) 2147 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2148 // CHECK3-NEXT: br label [[DOTEXIT]] 2149 // CHECK3: .exit: 2150 // CHECK3-NEXT: ret void 2151 // 2152 // 2153 // CHECK3-LABEL: define {{[^@]+}}@_ZN2TTIxcEixEi 2154 // CHECK3-SAME: (%struct.TT* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[I:%.*]]) #[[ATTR5:[0-9]+]] comdat align 2 { 2155 // CHECK3-NEXT: entry: 2156 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.TT*, align 4 2157 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 2158 // CHECK3-NEXT: store %struct.TT* [[THIS]], %struct.TT** [[THIS_ADDR]], align 4 2159 // CHECK3-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 2160 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.TT*, %struct.TT** [[THIS_ADDR]], align 4 2161 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[THIS1]], i32 0, i32 0 2162 // CHECK3-NEXT: ret i64* [[X]] 2163 // 2164 // 2165 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90_worker 2166 // CHECK3-SAME: () #[[ATTR3]] { 2167 // CHECK3-NEXT: entry: 2168 // CHECK3-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 2169 // CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 2170 // CHECK3-NEXT: store i8* null, i8** [[WORK_FN]], align 4 2171 // CHECK3-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 2172 // CHECK3-NEXT: br label [[DOTAWAIT_WORK:%.*]] 2173 // CHECK3: .await.work: 2174 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2175 // CHECK3-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 2176 // CHECK3-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 2177 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 2178 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 2179 // CHECK3-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 2180 // CHECK3-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 2181 // CHECK3: .select.workers: 2182 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 2183 // CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 2184 // CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 2185 // CHECK3: .execute.parallel: 2186 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 2187 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 2188 // CHECK3-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 2189 // CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 2190 // CHECK3: .terminate.parallel: 2191 // CHECK3-NEXT: call void @__kmpc_kernel_end_parallel() 2192 // CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]] 2193 // CHECK3: .barrier.parallel: 2194 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2195 // CHECK3-NEXT: br label [[DOTAWAIT_WORK]] 2196 // CHECK3: .exit: 2197 // CHECK3-NEXT: ret void 2198 // 2199 // 2200 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90 2201 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 2202 // CHECK3-NEXT: entry: 2203 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2204 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2205 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 2206 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2207 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2208 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2209 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 2210 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2211 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2212 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 2213 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2214 // CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 2215 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2216 // CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2217 // CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 2218 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 2219 // CHECK3-NEXT: br i1 [[TMP1]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 2220 // CHECK3: .worker: 2221 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90_worker() #[[ATTR2]] 2222 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 2223 // CHECK3: .mastercheck: 2224 // CHECK3-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 2225 // CHECK3-NEXT: [[NVPTX_NUM_THREADS3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2226 // CHECK3-NEXT: [[NVPTX_WARP_SIZE4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2227 // CHECK3-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE4]], 1 2228 // CHECK3-NEXT: [[TMP3:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS3]], 1 2229 // CHECK3-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], -1 2230 // CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP3]], [[TMP4]] 2231 // CHECK3-NEXT: [[TMP5:%.*]] = icmp eq i32 [[NVPTX_TID2]], [[MASTER_TID]] 2232 // CHECK3-NEXT: br i1 [[TMP5]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 2233 // CHECK3: .master: 2234 // CHECK3-NEXT: [[NVPTX_NUM_THREADS5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2235 // CHECK3-NEXT: [[NVPTX_WARP_SIZE6:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2236 // CHECK3-NEXT: [[THREAD_LIMIT7:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS5]], [[NVPTX_WARP_SIZE6]] 2237 // CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT7]], i16 1) 2238 // CHECK3-NEXT: call void @__kmpc_data_sharing_init_stack() 2239 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A_ADDR]], align 4 2240 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 2241 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2242 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4 2243 // CHECK3-NEXT: [[CONV8:%.*]] = sext i16 [[TMP7]] to i32 2244 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], 1 2245 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i16 2246 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4 2247 // CHECK3-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV1]], align 4 2248 // CHECK3-NEXT: [[CONV11:%.*]] = sext i8 [[TMP8]] to i32 2249 // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 2250 // CHECK3-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i8 2251 // CHECK3-NEXT: store i8 [[CONV13]], i8* [[CONV1]], align 4 2252 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 2253 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2254 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 2255 // CHECK3-NEXT: store i32 [[ADD14]], i32* [[ARRAYIDX]], align 4 2256 // CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 2257 // CHECK3: .termination.notifier: 2258 // CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1) 2259 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2260 // CHECK3-NEXT: br label [[DOTEXIT]] 2261 // CHECK3: .exit: 2262 // CHECK3-NEXT: ret void 2263 // 2264 // 2265 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108_worker 2266 // CHECK3-SAME: () #[[ATTR3]] { 2267 // CHECK3-NEXT: entry: 2268 // CHECK3-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 2269 // CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 2270 // CHECK3-NEXT: store i8* null, i8** [[WORK_FN]], align 4 2271 // CHECK3-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 2272 // CHECK3-NEXT: br label [[DOTAWAIT_WORK:%.*]] 2273 // CHECK3: .await.work: 2274 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2275 // CHECK3-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 2276 // CHECK3-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 2277 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 2278 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 2279 // CHECK3-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 2280 // CHECK3-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 2281 // CHECK3: .select.workers: 2282 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 2283 // CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 2284 // CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 2285 // CHECK3: .execute.parallel: 2286 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 2287 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 2288 // CHECK3-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 2289 // CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 2290 // CHECK3: .terminate.parallel: 2291 // CHECK3-NEXT: call void @__kmpc_kernel_end_parallel() 2292 // CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]] 2293 // CHECK3: .barrier.parallel: 2294 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2295 // CHECK3-NEXT: br label [[DOTAWAIT_WORK]] 2296 // CHECK3: .exit: 2297 // CHECK3-NEXT: ret void 2298 // 2299 // 2300 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108 2301 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 2302 // CHECK3-NEXT: entry: 2303 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2304 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2305 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2306 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2307 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 2308 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2309 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2310 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2311 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2312 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 2313 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2314 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2315 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2316 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 2317 // CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 2318 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2319 // CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2320 // CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 2321 // CHECK3-NEXT: [[TMP4:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 2322 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 2323 // CHECK3: .worker: 2324 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108_worker() #[[ATTR2]] 2325 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 2326 // CHECK3: .mastercheck: 2327 // CHECK3-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 2328 // CHECK3-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2329 // CHECK3-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2330 // CHECK3-NEXT: [[TMP5:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE5]], 1 2331 // CHECK3-NEXT: [[TMP6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], 1 2332 // CHECK3-NEXT: [[TMP7:%.*]] = xor i32 [[TMP5]], -1 2333 // CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP6]], [[TMP7]] 2334 // CHECK3-NEXT: [[TMP8:%.*]] = icmp eq i32 [[NVPTX_TID3]], [[MASTER_TID]] 2335 // CHECK3-NEXT: br i1 [[TMP8]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 2336 // CHECK3: .master: 2337 // CHECK3-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2338 // CHECK3-NEXT: [[NVPTX_WARP_SIZE7:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2339 // CHECK3-NEXT: [[THREAD_LIMIT8:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS6]], [[NVPTX_WARP_SIZE7]] 2340 // CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT8]], i16 1) 2341 // CHECK3-NEXT: call void @__kmpc_data_sharing_init_stack() 2342 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[B_ADDR]], align 4 2343 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double 2344 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2345 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2346 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 8 2347 // CHECK3-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 2348 // CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[A9]], align 8 2349 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 2350 // CHECK3-NEXT: store double [[INC]], double* [[A9]], align 8 2351 // CHECK3-NEXT: [[CONV10:%.*]] = fptosi double [[INC]] to i16 2352 // CHECK3-NEXT: [[TMP11:%.*]] = mul nsw i32 1, [[TMP2]] 2353 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP11]] 2354 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 2355 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[ARRAYIDX11]], align 2 2356 // CHECK3-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 2357 // CHECK3-NEXT: [[TMP12:%.*]] = load double, double* [[A12]], align 8 2358 // CHECK3-NEXT: [[CONV13:%.*]] = fptosi double [[TMP12]] to i32 2359 // CHECK3-NEXT: [[A14:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 2360 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3baziRd(i32 [[CONV13]], double* nonnull align 8 dereferenceable(8) [[A14]]) #[[ATTR7]] 2361 // CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 2362 // CHECK3: .termination.notifier: 2363 // CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1) 2364 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2365 // CHECK3-NEXT: br label [[DOTEXIT]] 2366 // CHECK3: .exit: 2367 // CHECK3-NEXT: ret void 2368 // 2369 // 2370 // CHECK3-LABEL: define {{[^@]+}}@_Z3baziRd 2371 // CHECK3-SAME: (i32 [[F3:%.*]], double* nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR5]] { 2372 // CHECK3-NEXT: entry: 2373 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2374 // CHECK3-NEXT: [[F2:%.*]] = alloca i32, align 4 2375 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 2376 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 4 2377 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 2378 // CHECK3-NEXT: [[TMP1:%.*]] = call i16 @__kmpc_parallel_level(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]) 2379 // CHECK3-NEXT: [[TMP2:%.*]] = icmp eq i16 [[TMP1]], 0 2380 // CHECK3-NEXT: [[TMP3:%.*]] = call i8 @__kmpc_is_spmd_exec_mode() #[[ATTR2]] 2381 // CHECK3-NEXT: [[TMP4:%.*]] = icmp ne i8 [[TMP3]], 0 2382 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTSPMD:%.*]], label [[DOTNON_SPMD:%.*]] 2383 // CHECK3: .spmd: 2384 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 2385 // CHECK3: .non-spmd: 2386 // CHECK3-NEXT: [[TMP5:%.*]] = select i1 [[TMP2]], i32 4, i32 128 2387 // CHECK3-NEXT: [[TMP6:%.*]] = call i8* @__kmpc_data_sharing_coalesced_push_stack(i32 [[TMP5]], i16 0) 2388 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to %struct._globalized_locals_ty* 2389 // CHECK3-NEXT: br label [[DOTEXIT]] 2390 // CHECK3: .exit: 2391 // CHECK3-NEXT: [[_SELECT_STACK:%.*]] = phi %struct._globalized_locals_ty* [ null, [[DOTSPMD]] ], [ [[TMP7]], [[DOTNON_SPMD]] ] 2392 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast %struct._globalized_locals_ty* [[_SELECT_STACK]] to %struct._globalized_locals_ty.0* 2393 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[_SELECT_STACK]], i32 0, i32 0 2394 // CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 2395 // CHECK3-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID]], 31 2396 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [32 x i32], [32 x i32]* [[F]], i32 0, i32 [[NVPTX_LANE_ID]] 2397 // CHECK3-NEXT: [[F1:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_0:%.*]], %struct._globalized_locals_ty.0* [[TMP8]], i32 0, i32 0 2398 // CHECK3-NEXT: [[TMP10:%.*]] = select i1 [[TMP2]], i32* [[F1]], i32* [[TMP9]] 2399 // CHECK3-NEXT: [[TMP11:%.*]] = select i1 [[TMP4]], i32* [[F2]], i32* [[TMP10]] 2400 // CHECK3-NEXT: store i32 [[F3]], i32* [[TMP11]], align 4 2401 // CHECK3-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 2402 // CHECK3-NEXT: [[TMP12:%.*]] = load double*, double** [[A_ADDR]], align 4 2403 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 2404 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i32* [[TMP11]] to i8* 2405 // CHECK3-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 4 2406 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 2407 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast double* [[TMP12]] to i8* 2408 // CHECK3-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 4 2409 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 2410 // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, double*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP17]], i32 2) 2411 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP11]], align 4 2412 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[RETVAL]], align 4 2413 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTEXIT5:%.*]], label [[DOTNON_SPMD4:%.*]] 2414 // CHECK3: .non-spmd4: 2415 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast %struct._globalized_locals_ty* [[_SELECT_STACK]] to i8* 2416 // CHECK3-NEXT: call void @__kmpc_data_sharing_pop_stack(i8* [[TMP19]]) 2417 // CHECK3-NEXT: br label [[DOTEXIT5]] 2418 // CHECK3: .exit5: 2419 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 2420 // CHECK3-NEXT: ret i32 [[TMP20]] 2421 // 2422 // 2423 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142_worker 2424 // CHECK3-SAME: () #[[ATTR3]] { 2425 // CHECK3-NEXT: entry: 2426 // CHECK3-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 2427 // CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 2428 // CHECK3-NEXT: store i8* null, i8** [[WORK_FN]], align 4 2429 // CHECK3-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 2430 // CHECK3-NEXT: br label [[DOTAWAIT_WORK:%.*]] 2431 // CHECK3: .await.work: 2432 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2433 // CHECK3-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 2434 // CHECK3-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 2435 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 2436 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 2437 // CHECK3-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 2438 // CHECK3-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 2439 // CHECK3: .select.workers: 2440 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 2441 // CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 2442 // CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 2443 // CHECK3: .execute.parallel: 2444 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 2445 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 2446 // CHECK3-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 2447 // CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 2448 // CHECK3: .terminate.parallel: 2449 // CHECK3-NEXT: call void @__kmpc_kernel_end_parallel() 2450 // CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]] 2451 // CHECK3: .barrier.parallel: 2452 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2453 // CHECK3-NEXT: br label [[DOTAWAIT_WORK]] 2454 // CHECK3: .exit: 2455 // CHECK3-NEXT: ret void 2456 // 2457 // 2458 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142 2459 // CHECK3-SAME: () #[[ATTR0]] { 2460 // CHECK3-NEXT: entry: 2461 // CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 2462 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2463 // CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2464 // CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 2465 // CHECK3-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 2466 // CHECK3-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 2467 // CHECK3: .worker: 2468 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142_worker() #[[ATTR2]] 2469 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 2470 // CHECK3: .mastercheck: 2471 // CHECK3-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 2472 // CHECK3-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2473 // CHECK3-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2474 // CHECK3-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 2475 // CHECK3-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 2476 // CHECK3-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 2477 // CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 2478 // CHECK3-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 2479 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 2480 // CHECK3: .master: 2481 // CHECK3-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2482 // CHECK3-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2483 // CHECK3-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 2484 // CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 2485 // CHECK3-NEXT: call void @__kmpc_data_sharing_init_stack() 2486 // CHECK3-NEXT: call void @_Z6asserti(i32 0) #[[ATTR8:[0-9]+]] 2487 // CHECK3-NEXT: unreachable 2488 // CHECK3: 5: 2489 // CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 2490 // CHECK3: .termination.notifier: 2491 // CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1) 2492 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2493 // CHECK3-NEXT: br label [[DOTEXIT]] 2494 // CHECK3: .exit: 2495 // CHECK3-NEXT: ret void 2496 // 2497 // 2498 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74_worker 2499 // CHECK3-SAME: () #[[ATTR3]] { 2500 // CHECK3-NEXT: entry: 2501 // CHECK3-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 2502 // CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 2503 // CHECK3-NEXT: store i8* null, i8** [[WORK_FN]], align 4 2504 // CHECK3-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 2505 // CHECK3-NEXT: br label [[DOTAWAIT_WORK:%.*]] 2506 // CHECK3: .await.work: 2507 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2508 // CHECK3-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 2509 // CHECK3-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 2510 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 2511 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 2512 // CHECK3-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 2513 // CHECK3-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 2514 // CHECK3: .select.workers: 2515 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 2516 // CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 2517 // CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 2518 // CHECK3: .execute.parallel: 2519 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 2520 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 2521 // CHECK3-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 2522 // CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 2523 // CHECK3: .terminate.parallel: 2524 // CHECK3-NEXT: call void @__kmpc_kernel_end_parallel() 2525 // CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]] 2526 // CHECK3: .barrier.parallel: 2527 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2528 // CHECK3-NEXT: br label [[DOTAWAIT_WORK]] 2529 // CHECK3: .exit: 2530 // CHECK3-NEXT: ret void 2531 // 2532 // 2533 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74 2534 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 2535 // CHECK3-NEXT: entry: 2536 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2537 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2538 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2539 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2540 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2541 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2542 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2543 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2544 // CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 2545 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2546 // CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2547 // CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 2548 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 2549 // CHECK3-NEXT: br i1 [[TMP1]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 2550 // CHECK3: .worker: 2551 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74_worker() #[[ATTR2]] 2552 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 2553 // CHECK3: .mastercheck: 2554 // CHECK3-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 2555 // CHECK3-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2556 // CHECK3-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2557 // CHECK3-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 2558 // CHECK3-NEXT: [[TMP3:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 2559 // CHECK3-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], -1 2560 // CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP3]], [[TMP4]] 2561 // CHECK3-NEXT: [[TMP5:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 2562 // CHECK3-NEXT: br i1 [[TMP5]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 2563 // CHECK3: .master: 2564 // CHECK3-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 2565 // CHECK3-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 2566 // CHECK3-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 2567 // CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 2568 // CHECK3-NEXT: call void @__kmpc_data_sharing_init_stack() 2569 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A_ADDR]], align 4 2570 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 2571 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2572 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4 2573 // CHECK3-NEXT: [[CONV7:%.*]] = sext i16 [[TMP7]] to i32 2574 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1 2575 // CHECK3-NEXT: [[CONV9:%.*]] = trunc i32 [[ADD8]] to i16 2576 // CHECK3-NEXT: store i16 [[CONV9]], i16* [[CONV]], align 4 2577 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 2578 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2579 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP8]], 1 2580 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[ARRAYIDX]], align 4 2581 // CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 2582 // CHECK3: .termination.notifier: 2583 // CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1) 2584 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 2585 // CHECK3-NEXT: br label [[DOTEXIT]] 2586 // CHECK3: .exit: 2587 // CHECK3-NEXT: ret void 2588 // 2589 // 2590 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 2591 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[F:%.*]], double* nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR0]] { 2592 // CHECK3-NEXT: entry: 2593 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2594 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2595 // CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 2596 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 2597 // CHECK3-NEXT: [[TMP:%.*]] = alloca double*, align 4 2598 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2599 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2600 // CHECK3-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 2601 // CHECK3-NEXT: store double* [[A]], double** [[A_ADDR]], align 4 2602 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[F_ADDR]], align 4 2603 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[A_ADDR]], align 4 2604 // CHECK3-NEXT: store double* [[TMP1]], double** [[TMP]], align 4 2605 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 4 2606 // CHECK3-NEXT: [[TMP3:%.*]] = load double, double* [[TMP2]], align 8 2607 // CHECK3-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]] 2608 // CHECK3-NEXT: [[CONV:%.*]] = fptosi double [[ADD]] to i32 2609 // CHECK3-NEXT: store i32 [[CONV]], i32* [[TMP0]], align 4 2610 // CHECK3-NEXT: ret void 2611 // 2612 // 2613 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 2614 // CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { 2615 // CHECK3-NEXT: entry: 2616 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 2617 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 2618 // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 2619 // CHECK3-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 2620 // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 2621 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 2622 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 2623 // CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 2624 // CHECK3-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4 2625 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0 2626 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 2627 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4 2628 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 1 2629 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to double** 2630 // CHECK3-NEXT: [[TMP8:%.*]] = load double*, double** [[TMP7]], align 4 2631 // CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], double* [[TMP8]]) #[[ATTR2]] 2632 // CHECK3-NEXT: ret void 2633 // 2634