1 // Test target codegen - host bc file has to be created first. 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 4 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 6 // RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 7 // expected-no-diagnostics 8 #ifndef HEADER 9 #define HEADER 10 11 template<typename tx> 12 tx ftemplate(int n) { 13 tx a = 0; 14 short aa = 0; 15 tx b[10]; 16 17 #pragma omp target if(0) 18 { 19 #pragma omp parallel 20 { 21 int a = 41; 22 } 23 a += 1; 24 } 25 26 #pragma omp target 27 { 28 #pragma omp parallel 29 { 30 int a = 42; 31 } 32 #pragma omp parallel if(0) 33 { 34 int a = 43; 35 } 36 #pragma omp parallel if(1) 37 { 38 int a = 44; 39 } 40 a += 1; 41 } 42 43 #pragma omp target if(n>40) 44 { 45 #pragma omp parallel if(n>1000) 46 { 47 int a = 45; 48 } 49 a += 1; 50 aa += 1; 51 b[2] += 1; 52 } 53 54 #pragma omp target 55 { 56 #pragma omp parallel 57 { 58 #pragma omp critical 59 ++a; 60 } 61 ++a; 62 } 63 return a; 64 } 65 66 int bar(int n){ 67 int a = 0; 68 69 a += ftemplate<int>(n); 70 71 return a; 72 } 73 74 // CHECK-NOT: define {{.*}}void {{@__omp_offloading_.+template.+l17}}_worker() 75 76 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l26}}_worker() 77 // CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8, 78 // CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*, 79 // CHECK: store i8* null, i8** [[OMP_WORK_FN]], 80 // CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]], 81 // CHECK: br label {{%?}}[[AWAIT_WORK:.+]] 82 // 83 // CHECK: [[AWAIT_WORK]] 84 // CHECK: call void @llvm.nvvm.barrier0() 85 // CHECK: [[KPR:%.+]] = call i1 @__kmpc_kernel_parallel(i8** [[OMP_WORK_FN]] 86 // CHECK: [[KPRB:%.+]] = zext i1 [[KPR]] to i8 87 // store i8 [[KPRB]], i8* [[OMP_EXEC_STATUS]], align 1 88 // CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 89 // CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null 90 // CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]] 91 // 92 // CHECK: [[SEL_WORKERS]] 93 // CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]] 94 // CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0 95 // CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]] 96 // 97 // CHECK: [[EXEC_PARALLEL]] 98 // CHECK: [[WF1:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 99 // CHECK: [[WM1:%.+]] = icmp eq i8* [[WF1]], bitcast (void (i16, i32)* [[PARALLEL_FN1:@.+]]_wrapper to i8*) 100 // CHECK: br i1 [[WM1]], label {{%?}}[[EXEC_PFN1:.+]], label {{%?}}[[CHECK_NEXT1:.+]] 101 // 102 // CHECK: [[EXEC_PFN1]] 103 // CHECK: call void [[PARALLEL_FN1]]_wrapper( 104 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 105 // 106 // CHECK: [[CHECK_NEXT1]] 107 // CHECK: [[WF2:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 108 // CHECK: [[WM2:%.+]] = icmp eq i8* [[WF2]], bitcast (void (i16, i32)* [[PARALLEL_FN2:@.+]]_wrapper to i8*) 109 // CHECK: br i1 [[WM2]], label {{%?}}[[EXEC_PFN2:.+]], label {{%?}}[[CHECK_NEXT2:.+]] 110 // 111 // CHECK: [[EXEC_PFN2]] 112 // CHECK: call void [[PARALLEL_FN2]]_wrapper( 113 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 114 // 115 // CHECK: [[CHECK_NEXT2]] 116 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 117 // 118 // CHECK: [[TERM_PARALLEL]] 119 // CHECK: call void @__kmpc_kernel_end_parallel() 120 // CHECK: br label {{%?}}[[BAR_PARALLEL]] 121 // 122 // CHECK: [[BAR_PARALLEL]] 123 // CHECK: call void @llvm.nvvm.barrier0() 124 // CHECK: br label {{%?}}[[AWAIT_WORK]] 125 // 126 // CHECK: [[EXIT]] 127 // CHECK: ret void 128 129 // CHECK: define {{.*}}void [[T6:@__omp_offloading_.+template.+l26]](i[[SZ:32|64]] 130 // Create local storage for each capture. 131 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]], 132 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 133 // Store captures in the context. 134 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 135 // 136 // CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 137 // CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 138 // CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 139 // CHECK-DAG: [[TH_LIMIT:%.+]] = sub nuw i32 [[NTH]], [[WS]] 140 // CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]] 141 // CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]] 142 // 143 // CHECK: [[WORKER]] 144 // CHECK: {{call|invoke}} void [[T6]]_worker() 145 // CHECK: br label {{%?}}[[EXIT:.+]] 146 // 147 // CHECK: [[CHECK_MASTER]] 148 // CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 149 // CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 150 // CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 151 // CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]], 152 // CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]] 153 // 154 // CHECK: [[MASTER]] 155 // CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 156 // CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 157 // CHECK: [[MTMP1:%.+]] = sub nuw i32 [[MNTH]], [[MWS]] 158 // CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]] 159 // CHECK: call void @__kmpc_kernel_prepare_parallel(i8* bitcast (void (i16, i32)* [[PARALLEL_FN1]]_wrapper to i8*), 160 // CHECK: call void @llvm.nvvm.barrier0() 161 // CHECK: call void @llvm.nvvm.barrier0() 162 // CHECK: call void @__kmpc_serialized_parallel( 163 // CHECK: {{call|invoke}} void [[PARALLEL_FN3:@.+]]( 164 // CHECK: call void @__kmpc_end_serialized_parallel( 165 // CHECK: call void @__kmpc_kernel_prepare_parallel(i8* bitcast (void (i16, i32)* [[PARALLEL_FN2]]_wrapper to i8*), 166 // CHECK: call void @llvm.nvvm.barrier0() 167 // CHECK: call void @llvm.nvvm.barrier0() 168 // CHECK-64-DAG: load i32, i32* [[REF_A]] 169 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 170 // CHECK: br label {{%?}}[[TERMINATE:.+]] 171 // 172 // CHECK: [[TERMINATE]] 173 // CHECK: call void @__kmpc_kernel_deinit( 174 // CHECK: call void @llvm.nvvm.barrier0() 175 // CHECK: br label {{%?}}[[EXIT]] 176 // 177 // CHECK: [[EXIT]] 178 // CHECK: ret void 179 180 // CHECK-DAG: define internal void [[PARALLEL_FN1]]( 181 // CHECK: [[A:%.+]] = alloca i[[SZ:32|64]], 182 // CHECK: store i[[SZ]] 42, i[[SZ]]* %a, 183 // CHECK: ret void 184 185 // CHECK-DAG: define internal void [[PARALLEL_FN3]]( 186 // CHECK: [[A:%.+]] = alloca i[[SZ:32|64]], 187 // CHECK: store i[[SZ]] 43, i[[SZ]]* %a, 188 // CHECK: ret void 189 190 // CHECK-DAG: define internal void [[PARALLEL_FN2]]( 191 // CHECK: [[A:%.+]] = alloca i[[SZ:32|64]], 192 // CHECK: store i[[SZ]] 44, i[[SZ]]* %a, 193 // CHECK: ret void 194 195 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l43}}_worker() 196 // CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8, 197 // CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*, 198 // CHECK: store i8* null, i8** [[OMP_WORK_FN]], 199 // CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]], 200 // CHECK: br label {{%?}}[[AWAIT_WORK:.+]] 201 // 202 // CHECK: [[AWAIT_WORK]] 203 // CHECK: call void @llvm.nvvm.barrier0() 204 // CHECK: [[KPR:%.+]] = call i1 @__kmpc_kernel_parallel(i8** [[OMP_WORK_FN]], 205 // CHECK: [[KPRB:%.+]] = zext i1 [[KPR]] to i8 206 // store i8 [[KPRB]], i8* [[OMP_EXEC_STATUS]], align 1 207 // CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 208 // CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null 209 // CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]] 210 // 211 // CHECK: [[SEL_WORKERS]] 212 // CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]] 213 // CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0 214 // CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]] 215 // 216 // CHECK: [[EXEC_PARALLEL]] 217 // CHECK: [[WF:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 218 // CHECK: [[WM:%.+]] = icmp eq i8* [[WF]], bitcast (void (i16, i32)* [[PARALLEL_FN4:@.+]]_wrapper to i8*) 219 // CHECK: br i1 [[WM]], label {{%?}}[[EXEC_PFN:.+]], label {{%?}}[[CHECK_NEXT:.+]] 220 // 221 // CHECK: [[EXEC_PFN]] 222 // CHECK: call void [[PARALLEL_FN4]]_wrapper( 223 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 224 // 225 // CHECK: [[CHECK_NEXT]] 226 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 227 // 228 // CHECK: [[TERM_PARALLEL]] 229 // CHECK: call void @__kmpc_kernel_end_parallel() 230 // CHECK: br label {{%?}}[[BAR_PARALLEL]] 231 // 232 // CHECK: [[BAR_PARALLEL]] 233 // CHECK: call void @llvm.nvvm.barrier0() 234 // CHECK: br label {{%?}}[[AWAIT_WORK]] 235 // 236 // CHECK: [[EXIT]] 237 // CHECK: ret void 238 239 // CHECK: define {{.*}}void [[T6:@__omp_offloading_.+template.+l43]](i[[SZ:32|64]] 240 // Create local storage for each capture. 241 // CHECK: [[LOCAL_N:%.+]] = alloca i[[SZ]], 242 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]], 243 // CHECK: [[LOCAL_AA:%.+]] = alloca i[[SZ]], 244 // CHECK: [[LOCAL_B:%.+]] = alloca [10 x i32]* 245 // CHECK-DAG: store i[[SZ]] [[ARG_N:%.+]], i[[SZ]]* [[LOCAL_N]] 246 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 247 // CHECK-DAG: store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]] 248 // CHECK-DAG: store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]] 249 // Store captures in the context. 250 // CHECK-64-DAG:[[REF_N:%.+]] = bitcast i[[SZ]]* [[LOCAL_N]] to i32* 251 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 252 // CHECK-DAG: [[REF_AA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16* 253 // CHECK-DAG: [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]], 254 // 255 // CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 256 // CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 257 // CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 258 // CHECK-DAG: [[TH_LIMIT:%.+]] = sub nuw i32 [[NTH]], [[WS]] 259 // CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]] 260 // CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]] 261 // 262 // CHECK: [[WORKER]] 263 // CHECK: {{call|invoke}} void [[T6]]_worker() 264 // CHECK: br label {{%?}}[[EXIT:.+]] 265 // 266 // CHECK: [[CHECK_MASTER]] 267 // CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 268 // CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 269 // CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 270 // CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]], 271 // CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]] 272 // 273 // CHECK: [[MASTER]] 274 // CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 275 // CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 276 // CHECK: [[MTMP1:%.+]] = sub nuw i32 [[MNTH]], [[MWS]] 277 // CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]] 278 // CHECK-64: [[N:%.+]] = load i32, i32* [[REF_N]], 279 // CHECK-32: [[N:%.+]] = load i32, i32* [[LOCAL_N]], 280 // CHECK: [[CMP:%.+]] = icmp sgt i32 [[N]], 1000 281 // CHECK: br i1 [[CMP]], label {{%?}}[[IF_THEN:.+]], label {{%?}}[[IF_ELSE:.+]] 282 // 283 // CHECK: [[IF_THEN]] 284 // CHECK: call void @__kmpc_kernel_prepare_parallel(i8* bitcast (void (i16, i32)* [[PARALLEL_FN4]]_wrapper to i8*), 285 // CHECK: call void @llvm.nvvm.barrier0() 286 // CHECK: call void @llvm.nvvm.barrier0() 287 // CHECK: br label {{%?}}[[IF_END:.+]] 288 // 289 // CHECK: [[IF_ELSE]] 290 // CHECK: call void @__kmpc_serialized_parallel( 291 // CHECK: {{call|invoke}} void [[PARALLEL_FN4]]( 292 // CHECK: call void @__kmpc_end_serialized_parallel( 293 // br label [[IF_END]] 294 // 295 // CHECK: [[IF_END]] 296 // CHECK-64-DAG: load i32, i32* [[REF_A]] 297 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 298 // CHECK-DAG: load i16, i16* [[REF_AA]] 299 // CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 300 // 301 // CHECK: br label {{%?}}[[TERMINATE:.+]] 302 // 303 // CHECK: [[TERMINATE]] 304 // CHECK: call void @__kmpc_kernel_deinit( 305 // CHECK: call void @llvm.nvvm.barrier0() 306 // CHECK: br label {{%?}}[[EXIT]] 307 // 308 // CHECK: [[EXIT]] 309 // CHECK: ret void 310 311 // CHECK: define internal void [[PARALLEL_FN4]]( 312 // CHECK: [[A:%.+]] = alloca i[[SZ:32|64]], 313 // CHECK: store i[[SZ]] 45, i[[SZ]]* %a, 314 // CHECK: ret void 315 316 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l54}}_worker() 317 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l54}}( 318 // CHECK-32: [[A_ADDR:%.+]] = alloca i32, 319 // CHECK-64: [[A_ADDR:%.+]] = alloca i64, 320 // CHECK-64: [[CONV:%.+]] = bitcast i64* [[A_ADDR]] to i32* 321 // CHECK: [[STACK:%.+]] = call i8* @__kmpc_data_sharing_push_stack(i{{64|32}} 4, i16 0) 322 // CHECK: [[BC:%.+]] = bitcast i8* [[STACK]] to %struct._globalized_locals_ty* 323 // CHECK-32: [[A:%.+]] = load i32, i32* [[A_ADDR]], 324 // CHECK-64: [[A:%.+]] = load i32, i32* [[CONV]], 325 // CHECK: [[GLOBAL_A_ADDR:%.+]] = getelementptr inbounds %struct._globalized_locals_ty, %struct._globalized_locals_ty* [[BC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 326 // CHECK: store i32 [[A]], i32* [[GLOBAL_A_ADDR]], 327 328 // CHECK-LABEL: define internal void @{{.+}}(i32* noalias %{{.+}}, i32* noalias %{{.+}}, i32* dereferenceable{{.*}}) 329 // CHECK: [[CC:%.+]] = alloca i32, 330 // CHECK: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 331 // CHECK: [[NUM_THREADS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 332 // CHECK: store i32 0, i32* [[CC]], 333 // CHECK: br label 334 335 // CHECK: [[CC_VAL:%.+]] = load i32, i32* [[CC]], 336 // CHECK: [[RES:%.+]] = icmp slt i32 [[CC_VAL]], [[NUM_THREADS]] 337 // CHECK: br i1 [[RES]], label 338 339 // CHECK: [[CC_VAL:%.+]] = load i32, i32* [[CC]], 340 // CHECK: [[RES:%.+]] = icmp eq i32 [[TID]], [[CC_VAL]] 341 // CHECK: br i1 [[RES]], label 342 343 // CHECK: call void @llvm.nvvm.barrier0() 344 // CHECK: [[NEW_CC_VAL:%.+]] = add nsw i32 [[CC_VAL]], 1 345 // CHECK: store i32 [[NEW_CC_VAL]], i32* [[CC]], 346 // CHECK: br label 347 348 #endif 349