1 // Test target codegen - host bc file has to be created first. 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 4 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 6 // RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 7 // expected-no-diagnostics 8 #ifndef HEADER 9 #define HEADER 10 11 template<typename tx> 12 tx ftemplate(int n) { 13 tx a = 0; 14 short aa = 0; 15 tx b[10]; 16 17 #pragma omp target if(0) 18 { 19 #pragma omp parallel 20 { 21 int a = 41; 22 } 23 a += 1; 24 } 25 26 #pragma omp target 27 { 28 #pragma omp parallel 29 { 30 int a = 42; 31 } 32 #pragma omp parallel if(0) 33 { 34 int a = 43; 35 } 36 #pragma omp parallel if(1) 37 { 38 int a = 44; 39 } 40 a += 1; 41 } 42 43 #pragma omp target if(n>40) 44 { 45 #pragma omp parallel if(n>1000) 46 { 47 int a = 45; 48 } 49 a += 1; 50 aa += 1; 51 b[2] += 1; 52 } 53 54 #pragma omp target 55 { 56 #pragma omp parallel 57 { 58 #pragma omp critical 59 ++a; 60 } 61 ++a; 62 } 63 return a; 64 } 65 66 int bar(int n){ 67 int a = 0; 68 69 a += ftemplate<int>(n); 70 71 return a; 72 } 73 74 // CHECK: [[MEM_TY:%.+]] = type { [4 x i8] } 75 // CHECK-DAG: [[SHARED_GLOBAL_RD:@.+]] = weak addrspace(3) global [[MEM_TY]] zeroinitializer 76 // CHECK-DAG: [[KERNEL_PTR:@.+]] = internal addrspace(3) global i8* null 77 // CHECK-DAG: [[KERNEL_SIZE:@.+]] = internal unnamed_addr constant i{{64|32}} 4 78 // CHECK-DAG: [[KERNEL_SHARED:@.+]] = internal unnamed_addr constant i16 1 79 80 // CHECK-NOT: define {{.*}}void {{@__omp_offloading_.+template.+l17}}_worker() 81 82 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l26}}_worker() 83 // CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8, 84 // CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*, 85 // CHECK: store i8* null, i8** [[OMP_WORK_FN]], 86 // CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]], 87 // CHECK: br label {{%?}}[[AWAIT_WORK:.+]] 88 // 89 // CHECK: [[AWAIT_WORK]] 90 // CHECK: call void @llvm.nvvm.barrier0() 91 // CHECK: [[KPR:%.+]] = call i1 @__kmpc_kernel_parallel(i8** [[OMP_WORK_FN]] 92 // CHECK: [[KPRB:%.+]] = zext i1 [[KPR]] to i8 93 // store i8 [[KPRB]], i8* [[OMP_EXEC_STATUS]], align 1 94 // CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 95 // CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null 96 // CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]] 97 // 98 // CHECK: [[SEL_WORKERS]] 99 // CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]] 100 // CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0 101 // CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]] 102 // 103 // CHECK: [[EXEC_PARALLEL]] 104 // CHECK: [[WF1:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 105 // CHECK: [[WM1:%.+]] = icmp eq i8* [[WF1]], bitcast (void (i16, i32)* [[PARALLEL_FN1:@.+]]_wrapper to i8*) 106 // CHECK: br i1 [[WM1]], label {{%?}}[[EXEC_PFN1:.+]], label {{%?}}[[CHECK_NEXT1:.+]] 107 // 108 // CHECK: [[EXEC_PFN1]] 109 // CHECK: call void [[PARALLEL_FN1]]_wrapper( 110 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 111 // 112 // CHECK: [[CHECK_NEXT1]] 113 // CHECK: [[WF2:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 114 // CHECK: [[WM2:%.+]] = icmp eq i8* [[WF2]], bitcast (void (i16, i32)* [[PARALLEL_FN2:@.+]]_wrapper to i8*) 115 // CHECK: br i1 [[WM2]], label {{%?}}[[EXEC_PFN2:.+]], label {{%?}}[[CHECK_NEXT2:.+]] 116 // 117 // CHECK: [[EXEC_PFN2]] 118 // CHECK: call void [[PARALLEL_FN2]]_wrapper( 119 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 120 // 121 // CHECK: [[CHECK_NEXT2]] 122 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 123 // 124 // CHECK: [[TERM_PARALLEL]] 125 // CHECK: call void @__kmpc_kernel_end_parallel() 126 // CHECK: br label {{%?}}[[BAR_PARALLEL]] 127 // 128 // CHECK: [[BAR_PARALLEL]] 129 // CHECK: call void @llvm.nvvm.barrier0() 130 // CHECK: br label {{%?}}[[AWAIT_WORK]] 131 // 132 // CHECK: [[EXIT]] 133 // CHECK: ret void 134 135 // CHECK: define {{.*}}void [[T6:@__omp_offloading_.+template.+l26]](i[[SZ:32|64]] 136 // Create local storage for each capture. 137 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]], 138 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 139 // Store captures in the context. 140 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 141 // 142 // CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 143 // CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 144 // CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 145 // CHECK-DAG: [[TH_LIMIT:%.+]] = sub nuw i32 [[NTH]], [[WS]] 146 // CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]] 147 // CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]] 148 // 149 // CHECK: [[WORKER]] 150 // CHECK: {{call|invoke}} void [[T6]]_worker() 151 // CHECK: br label {{%?}}[[EXIT:.+]] 152 // 153 // CHECK: [[CHECK_MASTER]] 154 // CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 155 // CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 156 // CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 157 // CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]], 158 // CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]] 159 // 160 // CHECK: [[MASTER]] 161 // CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 162 // CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 163 // CHECK: [[MTMP1:%.+]] = sub nuw i32 [[MNTH]], [[MWS]] 164 // CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]] 165 // CHECK: call void @__kmpc_kernel_prepare_parallel(i8* bitcast (void (i16, i32)* [[PARALLEL_FN1]]_wrapper to i8*), 166 // CHECK: call void @llvm.nvvm.barrier0() 167 // CHECK: call void @llvm.nvvm.barrier0() 168 // CHECK: call void @__kmpc_serialized_parallel( 169 // CHECK: {{call|invoke}} void [[PARALLEL_FN3:@.+]]( 170 // CHECK: call void @__kmpc_end_serialized_parallel( 171 // CHECK: call void @__kmpc_kernel_prepare_parallel(i8* bitcast (void (i16, i32)* [[PARALLEL_FN2]]_wrapper to i8*), 172 // CHECK: call void @llvm.nvvm.barrier0() 173 // CHECK: call void @llvm.nvvm.barrier0() 174 // CHECK-64-DAG: load i32, i32* [[REF_A]] 175 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 176 // CHECK: br label {{%?}}[[TERMINATE:.+]] 177 // 178 // CHECK: [[TERMINATE]] 179 // CHECK: call void @__kmpc_kernel_deinit( 180 // CHECK: call void @llvm.nvvm.barrier0() 181 // CHECK: br label {{%?}}[[EXIT]] 182 // 183 // CHECK: [[EXIT]] 184 // CHECK: ret void 185 186 // CHECK-DAG: define internal void [[PARALLEL_FN1]]( 187 // CHECK: [[A:%.+]] = alloca i[[SZ:32|64]], 188 // CHECK: store i[[SZ]] 42, i[[SZ]]* %a, 189 // CHECK: ret void 190 191 // CHECK-DAG: define internal void [[PARALLEL_FN3]]( 192 // CHECK: [[A:%.+]] = alloca i[[SZ:32|64]], 193 // CHECK: store i[[SZ]] 43, i[[SZ]]* %a, 194 // CHECK: ret void 195 196 // CHECK-DAG: define internal void [[PARALLEL_FN2]]( 197 // CHECK: [[A:%.+]] = alloca i[[SZ:32|64]], 198 // CHECK: store i[[SZ]] 44, i[[SZ]]* %a, 199 // CHECK: ret void 200 201 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l43}}_worker() 202 // CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8, 203 // CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*, 204 // CHECK: store i8* null, i8** [[OMP_WORK_FN]], 205 // CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]], 206 // CHECK: br label {{%?}}[[AWAIT_WORK:.+]] 207 // 208 // CHECK: [[AWAIT_WORK]] 209 // CHECK: call void @llvm.nvvm.barrier0() 210 // CHECK: [[KPR:%.+]] = call i1 @__kmpc_kernel_parallel(i8** [[OMP_WORK_FN]], 211 // CHECK: [[KPRB:%.+]] = zext i1 [[KPR]] to i8 212 // store i8 [[KPRB]], i8* [[OMP_EXEC_STATUS]], align 1 213 // CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 214 // CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null 215 // CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]] 216 // 217 // CHECK: [[SEL_WORKERS]] 218 // CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]] 219 // CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0 220 // CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]] 221 // 222 // CHECK: [[EXEC_PARALLEL]] 223 // CHECK: [[WF:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 224 // CHECK: [[WM:%.+]] = icmp eq i8* [[WF]], bitcast (void (i16, i32)* [[PARALLEL_FN4:@.+]]_wrapper to i8*) 225 // CHECK: br i1 [[WM]], label {{%?}}[[EXEC_PFN:.+]], label {{%?}}[[CHECK_NEXT:.+]] 226 // 227 // CHECK: [[EXEC_PFN]] 228 // CHECK: call void [[PARALLEL_FN4]]_wrapper( 229 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 230 // 231 // CHECK: [[CHECK_NEXT]] 232 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 233 // 234 // CHECK: [[TERM_PARALLEL]] 235 // CHECK: call void @__kmpc_kernel_end_parallel() 236 // CHECK: br label {{%?}}[[BAR_PARALLEL]] 237 // 238 // CHECK: [[BAR_PARALLEL]] 239 // CHECK: call void @llvm.nvvm.barrier0() 240 // CHECK: br label {{%?}}[[AWAIT_WORK]] 241 // 242 // CHECK: [[EXIT]] 243 // CHECK: ret void 244 245 // CHECK: define {{.*}}void [[T6:@__omp_offloading_.+template.+l43]](i[[SZ:32|64]] 246 // Create local storage for each capture. 247 // CHECK: [[LOCAL_N:%.+]] = alloca i[[SZ]], 248 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]], 249 // CHECK: [[LOCAL_AA:%.+]] = alloca i[[SZ]], 250 // CHECK: [[LOCAL_B:%.+]] = alloca [10 x i32]* 251 // CHECK-DAG: store i[[SZ]] [[ARG_N:%.+]], i[[SZ]]* [[LOCAL_N]] 252 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 253 // CHECK-DAG: store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]] 254 // CHECK-DAG: store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]] 255 // Store captures in the context. 256 // CHECK-64-DAG:[[REF_N:%.+]] = bitcast i[[SZ]]* [[LOCAL_N]] to i32* 257 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 258 // CHECK-DAG: [[REF_AA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16* 259 // CHECK-DAG: [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]], 260 // 261 // CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 262 // CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 263 // CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 264 // CHECK-DAG: [[TH_LIMIT:%.+]] = sub nuw i32 [[NTH]], [[WS]] 265 // CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]] 266 // CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]] 267 // 268 // CHECK: [[WORKER]] 269 // CHECK: {{call|invoke}} void [[T6]]_worker() 270 // CHECK: br label {{%?}}[[EXIT:.+]] 271 // 272 // CHECK: [[CHECK_MASTER]] 273 // CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 274 // CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 275 // CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 276 // CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]], 277 // CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]] 278 // 279 // CHECK: [[MASTER]] 280 // CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 281 // CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 282 // CHECK: [[MTMP1:%.+]] = sub nuw i32 [[MNTH]], [[MWS]] 283 // CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]] 284 // CHECK-64: [[N:%.+]] = load i32, i32* [[REF_N]], 285 // CHECK-32: [[N:%.+]] = load i32, i32* [[LOCAL_N]], 286 // CHECK: [[CMP:%.+]] = icmp sgt i32 [[N]], 1000 287 // CHECK: br i1 [[CMP]], label {{%?}}[[IF_THEN:.+]], label {{%?}}[[IF_ELSE:.+]] 288 // 289 // CHECK: [[IF_THEN]] 290 // CHECK: call void @__kmpc_kernel_prepare_parallel(i8* bitcast (void (i16, i32)* [[PARALLEL_FN4]]_wrapper to i8*), 291 // CHECK: call void @llvm.nvvm.barrier0() 292 // CHECK: call void @llvm.nvvm.barrier0() 293 // CHECK: br label {{%?}}[[IF_END:.+]] 294 // 295 // CHECK: [[IF_ELSE]] 296 // CHECK: call void @__kmpc_serialized_parallel( 297 // CHECK: {{call|invoke}} void [[PARALLEL_FN4]]( 298 // CHECK: call void @__kmpc_end_serialized_parallel( 299 // br label [[IF_END]] 300 // 301 // CHECK: [[IF_END]] 302 // CHECK-64-DAG: load i32, i32* [[REF_A]] 303 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 304 // CHECK-DAG: load i16, i16* [[REF_AA]] 305 // CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 306 // 307 // CHECK: br label {{%?}}[[TERMINATE:.+]] 308 // 309 // CHECK: [[TERMINATE]] 310 // CHECK: call void @__kmpc_kernel_deinit( 311 // CHECK: call void @llvm.nvvm.barrier0() 312 // CHECK: br label {{%?}}[[EXIT]] 313 // 314 // CHECK: [[EXIT]] 315 // CHECK: ret void 316 317 // CHECK: define internal void [[PARALLEL_FN4]]( 318 // CHECK: [[A:%.+]] = alloca i[[SZ:32|64]], 319 // CHECK: store i[[SZ]] 45, i[[SZ]]* %a, 320 // CHECK: ret void 321 322 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l54}}_worker() 323 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l54}}( 324 // CHECK-32: [[A_ADDR:%.+]] = alloca i32, 325 // CHECK-64: [[A_ADDR:%.+]] = alloca i64, 326 // CHECK-64: [[CONV:%.+]] = bitcast i64* [[A_ADDR]] to i32* 327 // CHECK: [[IS_SHARED:%.+]] = load i16, i16* [[KERNEL_SHARED]], 328 // CHECK: [[SIZE:%.+]] = load i{{64|32}}, i{{64|32}}* [[KERNEL_SIZE]], 329 // CHECK: call void @__kmpc_get_team_static_memory(i8* addrspacecast (i8 addrspace(3)* getelementptr inbounds ([[MEM_TY]], [[MEM_TY]] addrspace(3)* [[SHARED_GLOBAL_RD]], i32 0, i32 0, i32 0) to i8*), i{{64|32}} [[SIZE]], i16 [[IS_SHARED]], i8** addrspacecast (i8* addrspace(3)* [[KERNEL_PTR]] to i8**)) 330 // CHECK: [[KERNEL_RD:%.+]] = load i8*, i8* addrspace(3)* [[KERNEL_PTR]], 331 // CHECK: [[STACK:%.+]] = getelementptr inbounds i8, i8* [[KERNEL_RD]], i{{64|32}} 0 332 // CHECK: [[BC:%.+]] = bitcast i8* [[STACK]] to %struct._globalized_locals_ty* 333 // CHECK-32: [[A:%.+]] = load i32, i32* [[A_ADDR]], 334 // CHECK-64: [[A:%.+]] = load i32, i32* [[CONV]], 335 // CHECK: [[GLOBAL_A_ADDR:%.+]] = getelementptr inbounds %struct._globalized_locals_ty, %struct._globalized_locals_ty* [[BC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 336 // CHECK: store i32 [[A]], i32* [[GLOBAL_A_ADDR]], 337 // CHECK: [[IS_SHARED:%.+]] = load i16, i16* [[KERNEL_SHARED]], 338 // CHECK: call void @__kmpc_restore_team_static_memory(i16 [[IS_SHARED]]) 339 340 // CHECK-LABEL: define internal void @{{.+}}(i32* noalias %{{.+}}, i32* noalias %{{.+}}, i32* dereferenceable{{.*}}) 341 // CHECK: [[CC:%.+]] = alloca i32, 342 // CHECK: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 343 // CHECK: [[NUM_THREADS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 344 // CHECK: store i32 0, i32* [[CC]], 345 // CHECK: br label 346 347 // CHECK: [[CC_VAL:%.+]] = load i32, i32* [[CC]], 348 // CHECK: [[RES:%.+]] = icmp slt i32 [[CC_VAL]], [[NUM_THREADS]] 349 // CHECK: br i1 [[RES]], label 350 351 // CHECK: [[CC_VAL:%.+]] = load i32, i32* [[CC]], 352 // CHECK: [[RES:%.+]] = icmp eq i32 [[TID]], [[CC_VAL]] 353 // CHECK: br i1 [[RES]], label 354 355 // CHECK: call void @llvm.nvvm.barrier0() 356 // CHECK: [[NEW_CC_VAL:%.+]] = add nsw i32 [[CC_VAL]], 1 357 // CHECK: store i32 [[NEW_CC_VAL]], i32* [[CC]], 358 // CHECK: br label 359 360 #endif 361