1 // Test target codegen - host bc file has to be created first. 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 4 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 6 // RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 7 // expected-no-diagnostics 8 #ifndef HEADER 9 #define HEADER 10 11 template<typename tx> 12 tx ftemplate(int n) { 13 tx a = 0; 14 short aa = 0; 15 tx b[10]; 16 17 #pragma omp target if(0) 18 { 19 #pragma omp parallel 20 { 21 int a = 41; 22 } 23 a += 1; 24 } 25 26 #pragma omp target 27 { 28 #pragma omp parallel 29 { 30 int a = 42; 31 } 32 #pragma omp parallel if(0) 33 { 34 int a = 43; 35 } 36 #pragma omp parallel if(1) 37 { 38 int a = 44; 39 } 40 a += 1; 41 } 42 43 #pragma omp target if(n>40) 44 { 45 #pragma omp parallel if(n>1000) 46 { 47 int a = 45; 48 #pragma omp barrier 49 } 50 a += 1; 51 aa += 1; 52 b[2] += 1; 53 } 54 55 #pragma omp target 56 { 57 #pragma omp parallel 58 { 59 #pragma omp critical 60 ++a; 61 } 62 ++a; 63 } 64 return a; 65 } 66 67 int bar(int n){ 68 int a = 0; 69 70 a += ftemplate<int>(n); 71 72 return a; 73 } 74 75 // CHECK: [[MEM_TY:%.+]] = type { [128 x i8] } 76 // CHECK-DAG: [[SHARED_GLOBAL_RD:@.+]] = common addrspace(3) global [[MEM_TY]] zeroinitializer 77 // CHECK-DAG: [[KERNEL_PTR:@.+]] = internal addrspace(3) global i8* null 78 // CHECK-DAG: [[KERNEL_SIZE:@.+]] = internal unnamed_addr constant i{{64|32}} 4 79 // CHECK-DAG: [[KERNEL_SHARED:@.+]] = internal unnamed_addr constant i16 1 80 81 // CHECK-NOT: define {{.*}}void {{@__omp_offloading_.+template.+l17}}_worker() 82 83 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l26}}_worker() 84 // CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8, 85 // CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*, 86 // CHECK: store i8* null, i8** [[OMP_WORK_FN]], 87 // CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]], 88 // CHECK: br label {{%?}}[[AWAIT_WORK:.+]] 89 // 90 // CHECK: [[AWAIT_WORK]] 91 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) #[[#CONVERGENT:]] 92 // CHECK: [[KPR:%.+]] = call i1 @__kmpc_kernel_parallel(i8** [[OMP_WORK_FN]] 93 // CHECK: [[KPRB:%.+]] = zext i1 [[KPR]] to i8 94 // store i8 [[KPRB]], i8* [[OMP_EXEC_STATUS]], align 1 95 // CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 96 // CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null 97 // CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]] 98 // 99 // CHECK: [[SEL_WORKERS]] 100 // CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]] 101 // CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0 102 // CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]] 103 // 104 // CHECK: [[EXEC_PARALLEL]] 105 // CHECK: [[WF1:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 106 // CHECK: [[WM1:%.+]] = icmp eq i8* [[WF1]], bitcast (void (i16, i32)* [[PARALLEL_FN1:@.+]]_wrapper to i8*) 107 // CHECK: br i1 [[WM1]], label {{%?}}[[EXEC_PFN1:.+]], label {{%?}}[[CHECK_NEXT1:.+]] 108 // 109 // CHECK: [[EXEC_PFN1]] 110 // CHECK: call void [[PARALLEL_FN1]]_wrapper( 111 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 112 // 113 // CHECK: [[CHECK_NEXT1]] 114 // CHECK: [[WF2:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 115 // CHECK: [[WM2:%.+]] = icmp eq i8* [[WF2]], bitcast (void (i16, i32)* [[PARALLEL_FN2:@.+]]_wrapper to i8*) 116 // CHECK: br i1 [[WM2]], label {{%?}}[[EXEC_PFN2:.+]], label {{%?}}[[CHECK_NEXT2:.+]] 117 // 118 // CHECK: [[EXEC_PFN2]] 119 // CHECK: call void [[PARALLEL_FN2]]_wrapper( 120 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 121 // 122 // CHECK: [[CHECK_NEXT2]] 123 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 124 // 125 // CHECK: [[TERM_PARALLEL]] 126 // CHECK: call void @__kmpc_kernel_end_parallel() 127 // CHECK: br label {{%?}}[[BAR_PARALLEL]] 128 // 129 // CHECK: [[BAR_PARALLEL]] 130 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 131 // CHECK: br label {{%?}}[[AWAIT_WORK]] 132 // 133 // CHECK: [[EXIT]] 134 // CHECK: ret void 135 136 // CHECK: define {{.*}}void [[T6:@__omp_offloading_.+template.+l26]](i[[SZ:32|64]] 137 // Create local storage for each capture. 138 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]], 139 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 140 // Store captures in the context. 141 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 142 // 143 // CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 144 // CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 145 // CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 146 // CHECK-DAG: [[TH_LIMIT:%.+]] = sub nuw i32 [[NTH]], [[WS]] 147 // CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]] 148 // CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]] 149 // 150 // CHECK: [[WORKER]] 151 // CHECK: {{call|invoke}} void [[T6]]_worker() 152 // CHECK: br label {{%?}}[[EXIT:.+]] 153 // 154 // CHECK: [[CHECK_MASTER]] 155 // CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 156 // CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 157 // CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 158 // CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]], 159 // CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]] 160 // 161 // CHECK: [[MASTER]] 162 // CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 163 // CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 164 // CHECK: [[MTMP1:%.+]] = sub nuw i32 [[MNTH]], [[MWS]] 165 // CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]] 166 // CHECK: call void @__kmpc_kernel_prepare_parallel(i8* bitcast (void (i16, i32)* [[PARALLEL_FN1]]_wrapper to i8*), 167 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 168 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 169 // CHECK: call void @__kmpc_serialized_parallel( 170 // CHECK: {{call|invoke}} void [[PARALLEL_FN3:@.+]]( 171 // CHECK: call void @__kmpc_end_serialized_parallel( 172 // CHECK: call void @__kmpc_kernel_prepare_parallel(i8* bitcast (void (i16, i32)* [[PARALLEL_FN2]]_wrapper to i8*), 173 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 174 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 175 // CHECK-64-DAG: load i32, i32* [[REF_A]] 176 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 177 // CHECK: br label {{%?}}[[TERMINATE:.+]] 178 // 179 // CHECK: [[TERMINATE]] 180 // CHECK: call void @__kmpc_kernel_deinit( 181 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 182 // CHECK: br label {{%?}}[[EXIT]] 183 // 184 // CHECK: [[EXIT]] 185 // CHECK: ret void 186 187 // CHECK-DAG: define internal void [[PARALLEL_FN1]]( 188 // CHECK: [[A:%.+]] = alloca i[[SZ:32|64]], 189 // CHECK: store i[[SZ]] 42, i[[SZ]]* %a, 190 // CHECK: ret void 191 192 // CHECK-DAG: define internal void [[PARALLEL_FN3]]( 193 // CHECK: [[A:%.+]] = alloca i[[SZ:32|64]], 194 // CHECK: store i[[SZ]] 43, i[[SZ]]* %a, 195 // CHECK: ret void 196 197 // CHECK-DAG: define internal void [[PARALLEL_FN2]]( 198 // CHECK: [[A:%.+]] = alloca i[[SZ:32|64]], 199 // CHECK: store i[[SZ]] 44, i[[SZ]]* %a, 200 // CHECK: ret void 201 202 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l43}}_worker() 203 // CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8, 204 // CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*, 205 // CHECK: store i8* null, i8** [[OMP_WORK_FN]], 206 // CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]], 207 // CHECK: br label {{%?}}[[AWAIT_WORK:.+]] 208 // 209 // CHECK: [[AWAIT_WORK]] 210 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 211 // CHECK: [[KPR:%.+]] = call i1 @__kmpc_kernel_parallel(i8** [[OMP_WORK_FN]], 212 // CHECK: [[KPRB:%.+]] = zext i1 [[KPR]] to i8 213 // store i8 [[KPRB]], i8* [[OMP_EXEC_STATUS]], align 1 214 // CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 215 // CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null 216 // CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]] 217 // 218 // CHECK: [[SEL_WORKERS]] 219 // CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]] 220 // CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0 221 // CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]] 222 // 223 // CHECK: [[EXEC_PARALLEL]] 224 // CHECK: [[WF:%.+]] = load i8*, i8** [[OMP_WORK_FN]], 225 // CHECK: [[WM:%.+]] = icmp eq i8* [[WF]], bitcast (void (i16, i32)* [[PARALLEL_FN4:@.+]]_wrapper to i8*) 226 // CHECK: br i1 [[WM]], label {{%?}}[[EXEC_PFN:.+]], label {{%?}}[[CHECK_NEXT:.+]] 227 // 228 // CHECK: [[EXEC_PFN]] 229 // CHECK: call void [[PARALLEL_FN4]]_wrapper( 230 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 231 // 232 // CHECK: [[CHECK_NEXT]] 233 // CHECK: br label {{%?}}[[TERM_PARALLEL:.+]] 234 // 235 // CHECK: [[TERM_PARALLEL]] 236 // CHECK: call void @__kmpc_kernel_end_parallel() 237 // CHECK: br label {{%?}}[[BAR_PARALLEL]] 238 // 239 // CHECK: [[BAR_PARALLEL]] 240 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 241 // CHECK: br label {{%?}}[[AWAIT_WORK]] 242 // 243 // CHECK: [[EXIT]] 244 // CHECK: ret void 245 246 // CHECK: define {{.*}}void [[T6:@__omp_offloading_.+template.+l43]](i[[SZ:32|64]] 247 // Create local storage for each capture. 248 // CHECK: [[LOCAL_N:%.+]] = alloca i[[SZ]], 249 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]], 250 // CHECK: [[LOCAL_AA:%.+]] = alloca i[[SZ]], 251 // CHECK: [[LOCAL_B:%.+]] = alloca [10 x i32]* 252 // CHECK-DAG: store i[[SZ]] [[ARG_N:%.+]], i[[SZ]]* [[LOCAL_N]] 253 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 254 // CHECK-DAG: store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]] 255 // CHECK-DAG: store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]] 256 // Store captures in the context. 257 // CHECK-64-DAG:[[REF_N:%.+]] = bitcast i[[SZ]]* [[LOCAL_N]] to i32* 258 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 259 // CHECK-DAG: [[REF_AA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16* 260 // CHECK-DAG: [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]], 261 // 262 // CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 263 // CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 264 // CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 265 // CHECK-DAG: [[TH_LIMIT:%.+]] = sub nuw i32 [[NTH]], [[WS]] 266 // CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]] 267 // CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]] 268 // 269 // CHECK: [[WORKER]] 270 // CHECK: {{call|invoke}} void [[T6]]_worker() 271 // CHECK: br label {{%?}}[[EXIT:.+]] 272 // 273 // CHECK: [[CHECK_MASTER]] 274 // CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 275 // CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 276 // CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 277 // CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]], 278 // CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]] 279 // 280 // CHECK: [[MASTER]] 281 // CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 282 // CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 283 // CHECK: [[MTMP1:%.+]] = sub nuw i32 [[MNTH]], [[MWS]] 284 // CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]] 285 // CHECK-64: [[N:%.+]] = load i32, i32* [[REF_N]], 286 // CHECK-32: [[N:%.+]] = load i32, i32* [[LOCAL_N]], 287 // CHECK: [[CMP:%.+]] = icmp sgt i32 [[N]], 1000 288 // CHECK: br i1 [[CMP]], label {{%?}}[[IF_THEN:.+]], label {{%?}}[[IF_ELSE:.+]] 289 // 290 // CHECK: [[IF_THEN]] 291 // CHECK: call void @__kmpc_kernel_prepare_parallel(i8* bitcast (void (i16, i32)* [[PARALLEL_FN4]]_wrapper to i8*), 292 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 293 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 294 // CHECK: br label {{%?}}[[IF_END:.+]] 295 // 296 // CHECK: [[IF_ELSE]] 297 // CHECK: call void @__kmpc_serialized_parallel( 298 // CHECK: {{call|invoke}} void [[PARALLEL_FN4]]( 299 // CHECK: call void @__kmpc_end_serialized_parallel( 300 // br label [[IF_END]] 301 // 302 // CHECK: [[IF_END]] 303 // CHECK-64-DAG: load i32, i32* [[REF_A]] 304 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 305 // CHECK-DAG: load i16, i16* [[REF_AA]] 306 // CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 307 // 308 // CHECK: br label {{%?}}[[TERMINATE:.+]] 309 // 310 // CHECK: [[TERMINATE]] 311 // CHECK: call void @__kmpc_kernel_deinit( 312 // CHECK: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 313 // CHECK: br label {{%?}}[[EXIT]] 314 // 315 // CHECK: [[EXIT]] 316 // CHECK: ret void 317 318 // CHECK: define internal void [[PARALLEL_FN4]]( 319 // CHECK: [[A:%.+]] = alloca i[[SZ:32|64]], 320 // CHECK: store i[[SZ]] 45, i[[SZ]]* %a, 321 // CHECK: call void @__kmpc_barrier(%struct.ident_t* @{{.+}}, i32 %{{.+}}) #[[#CONVERGENT:]] 322 // CHECK: ret void 323 324 // CHECK: declare void @__kmpc_barrier(%struct.ident_t*, i32) #[[#CONVERGENT]] 325 326 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l55}}_worker() 327 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l55}}( 328 // CHECK-32: [[A_ADDR:%.+]] = alloca i32, 329 // CHECK-64: [[A_ADDR:%.+]] = alloca i64, 330 // CHECK-64: [[CONV:%.+]] = bitcast i64* [[A_ADDR]] to i32* 331 // CHECK: [[IS_SHARED:%.+]] = load i16, i16* [[KERNEL_SHARED]], 332 // CHECK: [[SIZE:%.+]] = load i{{64|32}}, i{{64|32}}* [[KERNEL_SIZE]], 333 // CHECK: call void @__kmpc_get_team_static_memory(i16 0, i8* addrspacecast (i8 addrspace(3)* getelementptr inbounds ([[MEM_TY]], [[MEM_TY]] addrspace(3)* [[SHARED_GLOBAL_RD]], i32 0, i32 0, i32 0) to i8*), i{{64|32}} [[SIZE]], i16 [[IS_SHARED]], i8** addrspacecast (i8* addrspace(3)* [[KERNEL_PTR]] to i8**)) 334 // CHECK: [[KERNEL_RD:%.+]] = load i8*, i8* addrspace(3)* [[KERNEL_PTR]], 335 // CHECK: [[STACK:%.+]] = getelementptr inbounds i8, i8* [[KERNEL_RD]], i{{64|32}} 0 336 // CHECK: [[BC:%.+]] = bitcast i8* [[STACK]] to %struct._globalized_locals_ty* 337 // CHECK-32: [[A:%.+]] = load i32, i32* [[A_ADDR]], 338 // CHECK-64: [[A:%.+]] = load i32, i32* [[CONV]], 339 // CHECK: [[GLOBAL_A_ADDR:%.+]] = getelementptr inbounds %struct._globalized_locals_ty, %struct._globalized_locals_ty* [[BC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 340 // CHECK: store i32 [[A]], i32* [[GLOBAL_A_ADDR]], 341 // CHECK: [[IS_SHARED:%.+]] = load i16, i16* [[KERNEL_SHARED]], 342 // CHECK: call void @__kmpc_restore_team_static_memory(i16 0, i16 [[IS_SHARED]]) 343 344 // CHECK-LABEL: define internal void @{{.+}}(i32* noalias %{{.+}}, i32* noalias %{{.+}}, i32* dereferenceable{{.*}}) 345 // CHECK: [[CC:%.+]] = alloca i32, 346 // CHECK: [[MASK:%.+]] = call i32 @__kmpc_warp_active_thread_mask(){{$}} 347 // CHECK: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 348 // CHECK: [[NUM_THREADS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 349 // CHECK: store i32 0, i32* [[CC]], 350 // CHECK: br label 351 352 // CHECK: [[CC_VAL:%.+]] = load i32, i32* [[CC]], 353 // CHECK: [[RES:%.+]] = icmp slt i32 [[CC_VAL]], [[NUM_THREADS]] 354 // CHECK: br i1 [[RES]], label 355 356 // CHECK: [[CC_VAL:%.+]] = load i32, i32* [[CC]], 357 // CHECK: [[RES:%.+]] = icmp eq i32 [[TID]], [[CC_VAL]] 358 // CHECK: br i1 [[RES]], label 359 360 // CHECK: call void @__kmpc_critical( 361 // CHECK: load i32, i32* 362 // CHECK: add nsw i32 363 // CHECK: store i32 364 // CHECK: call void @__kmpc_end_critical( 365 366 // CHECK: call void @__kmpc_syncwarp(i32 [[MASK]]){{$}} 367 // CHECK: [[NEW_CC_VAL:%.+]] = add nsw i32 [[CC_VAL]], 1 368 // CHECK: store i32 [[NEW_CC_VAL]], i32* [[CC]], 369 // CHECK: br label 370 371 372 // CHECK: declare i32 @__kmpc_warp_active_thread_mask() #[[#CONVERGENT:]] 373 // CHECK: declare void @__kmpc_syncwarp(i32) #[[#CONVERGENT:]] 374 375 // CHECK: attributes #[[#CONVERGENT]] = {{.*}} convergent {{.*}} 376 377 #endif 378