1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test target codegen - host bc file has to be created first.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2
7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK3
8 
9 // expected-no-diagnostics
10 #ifndef HEADER
11 #define HEADER
12 
13 void work(int *C) {
14   #pragma omp atomic
15   ++(*C);
16 }
17 
18 void use(int *C) {
19   #pragma omp parallel num_threads(2)
20   work(C);
21 }
22 
23 int main() {
24   int C = 0;
25   #pragma omp target map(C)
26   {
27     use(&C);
28     #pragma omp parallel num_threads(2)
29     use(&C);
30   }
31 
32   return C;
33 }
34 
35 #endif
36 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25
37 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] {
38 // CHECK1-NEXT:  entry:
39 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 8
40 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
41 // CHECK1-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 8
42 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 8
43 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 false, i1 true, i1 true)
44 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
45 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
46 // CHECK1:       user_code.entry:
47 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
48 // CHECK1-NEXT:    call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR5:[0-9]+]]
49 // CHECK1-NEXT:    call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 2)
50 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
51 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8*
52 // CHECK1-NEXT:    store i8* [[TMP4]], i8** [[TMP3]], align 8
53 // CHECK1-NEXT:    [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
54 // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__ to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*), i8** [[TMP5]], i64 1)
55 // CHECK1-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 false, i1 true)
56 // CHECK1-NEXT:    ret void
57 // CHECK1:       worker.exit:
58 // CHECK1-NEXT:    ret void
59 //
60 //
61 // CHECK1-LABEL: define {{[^@]+}}@_Z3usePi
62 // CHECK1-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] {
63 // CHECK1-NEXT:  entry:
64 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 8
65 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
66 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
67 // CHECK1-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 8
68 // CHECK1-NEXT:    call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 2)
69 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
70 // CHECK1-NEXT:    [[TMP2:%.*]] = bitcast i32** [[C_ADDR]] to i8*
71 // CHECK1-NEXT:    store i8* [[TMP2]], i8** [[TMP1]], align 8
72 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
73 // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32**)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP3]], i64 1)
74 // CHECK1-NEXT:    ret void
75 //
76 //
77 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
78 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] {
79 // CHECK1-NEXT:  entry:
80 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
81 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
82 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 8
83 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
84 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
85 // CHECK1-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 8
86 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 8
87 // CHECK1-NEXT:    call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR5]]
88 // CHECK1-NEXT:    ret void
89 //
90 //
91 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___wrapper
92 // CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] {
93 // CHECK1-NEXT:  entry:
94 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
95 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
96 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
97 // CHECK1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
98 // CHECK1-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
99 // CHECK1-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
100 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
101 // CHECK1-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
102 // CHECK1-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8
103 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0
104 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
105 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 8
106 // CHECK1-NEXT:    call void @__omp_outlined__(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3:[0-9]+]]
107 // CHECK1-NEXT:    ret void
108 //
109 //
110 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
111 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR0]] {
112 // CHECK1-NEXT:  entry:
113 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
114 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
115 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32**, align 8
116 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
117 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
118 // CHECK1-NEXT:    store i32** [[C]], i32*** [[C_ADDR]], align 8
119 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32**, i32*** [[C_ADDR]], align 8
120 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 8
121 // CHECK1-NEXT:    call void @_Z4workPi(i32* [[TMP1]]) #[[ATTR5]]
122 // CHECK1-NEXT:    ret void
123 //
124 //
125 // CHECK1-LABEL: define {{[^@]+}}@_Z4workPi
126 // CHECK1-SAME: (i32* [[C:%.*]]) #[[ATTR1]] {
127 // CHECK1-NEXT:  entry:
128 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 8
129 // CHECK1-NEXT:    [[ATOMIC_TEMP:%.*]] = alloca i32, align 4
130 // CHECK1-NEXT:    [[ATOMIC_TEMP1:%.*]] = alloca i32, align 4
131 // CHECK1-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 8
132 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 8
133 // CHECK1-NEXT:    [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8*
134 // CHECK1-NEXT:    [[TMP2:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8*
135 // CHECK1-NEXT:    call void @__atomic_load(i64 4, i8* [[TMP1]], i8* [[TMP2]], i32 0) #[[ATTR5]]
136 // CHECK1-NEXT:    br label [[ATOMIC_CONT:%.*]]
137 // CHECK1:       atomic_cont:
138 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4
139 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
140 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[ATOMIC_TEMP1]], align 4
141 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8*
142 // CHECK1-NEXT:    [[TMP5:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8*
143 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i32* [[ATOMIC_TEMP1]] to i8*
144 // CHECK1-NEXT:    [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 4, i8* [[TMP4]], i8* [[TMP5]], i8* [[TMP6]], i32 0, i32 0) #[[ATTR5]]
145 // CHECK1-NEXT:    br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]]
146 // CHECK1:       atomic_exit:
147 // CHECK1-NEXT:    ret void
148 //
149 //
150 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
151 // CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] {
152 // CHECK1-NEXT:  entry:
153 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
154 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
155 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
156 // CHECK1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
157 // CHECK1-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
158 // CHECK1-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
159 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
160 // CHECK1-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
161 // CHECK1-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8
162 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0
163 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32***
164 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32**, i32*** [[TMP4]], align 8
165 // CHECK1-NEXT:    call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32** [[TMP5]]) #[[ATTR3]]
166 // CHECK1-NEXT:    ret void
167 //
168 //
169 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25
170 // CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] {
171 // CHECK2-NEXT:  entry:
172 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
173 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
174 // CHECK2-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
175 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4
176 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 false, i1 true, i1 true)
177 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
178 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
179 // CHECK2:       user_code.entry:
180 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
181 // CHECK2-NEXT:    call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR5:[0-9]+]]
182 // CHECK2-NEXT:    call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 2)
183 // CHECK2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
184 // CHECK2-NEXT:    [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8*
185 // CHECK2-NEXT:    store i8* [[TMP4]], i8** [[TMP3]], align 4
186 // CHECK2-NEXT:    [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
187 // CHECK2-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__ to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*), i8** [[TMP5]], i32 1)
188 // CHECK2-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 false, i1 true)
189 // CHECK2-NEXT:    ret void
190 // CHECK2:       worker.exit:
191 // CHECK2-NEXT:    ret void
192 //
193 //
194 // CHECK2-LABEL: define {{[^@]+}}@_Z3usePi
195 // CHECK2-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] {
196 // CHECK2-NEXT:  entry:
197 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
198 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
199 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
200 // CHECK2-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
201 // CHECK2-NEXT:    call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 2)
202 // CHECK2-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
203 // CHECK2-NEXT:    [[TMP2:%.*]] = bitcast i32** [[C_ADDR]] to i8*
204 // CHECK2-NEXT:    store i8* [[TMP2]], i8** [[TMP1]], align 4
205 // CHECK2-NEXT:    [[TMP3:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
206 // CHECK2-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32**)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP3]], i32 1)
207 // CHECK2-NEXT:    ret void
208 //
209 //
210 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
211 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] {
212 // CHECK2-NEXT:  entry:
213 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
214 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
215 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
216 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
217 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
218 // CHECK2-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
219 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4
220 // CHECK2-NEXT:    call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR5]]
221 // CHECK2-NEXT:    ret void
222 //
223 //
224 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined___wrapper
225 // CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] {
226 // CHECK2-NEXT:  entry:
227 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
228 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
229 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
230 // CHECK2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4
231 // CHECK2-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
232 // CHECK2-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
233 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
234 // CHECK2-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
235 // CHECK2-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4
236 // CHECK2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0
237 // CHECK2-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
238 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4
239 // CHECK2-NEXT:    call void @__omp_outlined__(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3:[0-9]+]]
240 // CHECK2-NEXT:    ret void
241 //
242 //
243 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
244 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] {
245 // CHECK2-NEXT:  entry:
246 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
247 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
248 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i32**, align 4
249 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
250 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
251 // CHECK2-NEXT:    store i32** [[C]], i32*** [[C_ADDR]], align 4
252 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32**, i32*** [[C_ADDR]], align 4
253 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 4
254 // CHECK2-NEXT:    call void @_Z4workPi(i32* [[TMP1]]) #[[ATTR5]]
255 // CHECK2-NEXT:    ret void
256 //
257 //
258 // CHECK2-LABEL: define {{[^@]+}}@_Z4workPi
259 // CHECK2-SAME: (i32* [[C:%.*]]) #[[ATTR1]] {
260 // CHECK2-NEXT:  entry:
261 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
262 // CHECK2-NEXT:    [[ATOMIC_TEMP:%.*]] = alloca i32, align 4
263 // CHECK2-NEXT:    [[ATOMIC_TEMP1:%.*]] = alloca i32, align 4
264 // CHECK2-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
265 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4
266 // CHECK2-NEXT:    [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8*
267 // CHECK2-NEXT:    [[TMP2:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8*
268 // CHECK2-NEXT:    call void @__atomic_load(i32 4, i8* [[TMP1]], i8* [[TMP2]], i32 0) #[[ATTR5]]
269 // CHECK2-NEXT:    br label [[ATOMIC_CONT:%.*]]
270 // CHECK2:       atomic_cont:
271 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4
272 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
273 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[ATOMIC_TEMP1]], align 4
274 // CHECK2-NEXT:    [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8*
275 // CHECK2-NEXT:    [[TMP5:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8*
276 // CHECK2-NEXT:    [[TMP6:%.*]] = bitcast i32* [[ATOMIC_TEMP1]] to i8*
277 // CHECK2-NEXT:    [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 4, i8* [[TMP4]], i8* [[TMP5]], i8* [[TMP6]], i32 0, i32 0) #[[ATTR5]]
278 // CHECK2-NEXT:    br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]]
279 // CHECK2:       atomic_exit:
280 // CHECK2-NEXT:    ret void
281 //
282 //
283 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
284 // CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] {
285 // CHECK2-NEXT:  entry:
286 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
287 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
288 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
289 // CHECK2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4
290 // CHECK2-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
291 // CHECK2-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
292 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
293 // CHECK2-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
294 // CHECK2-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4
295 // CHECK2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0
296 // CHECK2-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32***
297 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32**, i32*** [[TMP4]], align 4
298 // CHECK2-NEXT:    call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32** [[TMP5]]) #[[ATTR3]]
299 // CHECK2-NEXT:    ret void
300 //
301 //
302 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25
303 // CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] {
304 // CHECK3-NEXT:  entry:
305 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
306 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
307 // CHECK3-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
308 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4
309 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 false, i1 true, i1 true)
310 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
311 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
312 // CHECK3:       user_code.entry:
313 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
314 // CHECK3-NEXT:    call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR5:[0-9]+]]
315 // CHECK3-NEXT:    call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 2)
316 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
317 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8*
318 // CHECK3-NEXT:    store i8* [[TMP4]], i8** [[TMP3]], align 4
319 // CHECK3-NEXT:    [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
320 // CHECK3-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__ to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*), i8** [[TMP5]], i32 1)
321 // CHECK3-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 false, i1 true)
322 // CHECK3-NEXT:    ret void
323 // CHECK3:       worker.exit:
324 // CHECK3-NEXT:    ret void
325 //
326 //
327 // CHECK3-LABEL: define {{[^@]+}}@_Z3usePi
328 // CHECK3-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] {
329 // CHECK3-NEXT:  entry:
330 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
331 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
332 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
333 // CHECK3-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
334 // CHECK3-NEXT:    call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 2)
335 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
336 // CHECK3-NEXT:    [[TMP2:%.*]] = bitcast i32** [[C_ADDR]] to i8*
337 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[TMP1]], align 4
338 // CHECK3-NEXT:    [[TMP3:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
339 // CHECK3-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32**)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP3]], i32 1)
340 // CHECK3-NEXT:    ret void
341 //
342 //
343 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
344 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] {
345 // CHECK3-NEXT:  entry:
346 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
347 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
348 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
349 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
350 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
351 // CHECK3-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
352 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4
353 // CHECK3-NEXT:    call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR5]]
354 // CHECK3-NEXT:    ret void
355 //
356 //
357 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined___wrapper
358 // CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] {
359 // CHECK3-NEXT:  entry:
360 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
361 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
362 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
363 // CHECK3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4
364 // CHECK3-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
365 // CHECK3-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
366 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
367 // CHECK3-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
368 // CHECK3-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4
369 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0
370 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
371 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4
372 // CHECK3-NEXT:    call void @__omp_outlined__(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3:[0-9]+]]
373 // CHECK3-NEXT:    ret void
374 //
375 //
376 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
377 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] {
378 // CHECK3-NEXT:  entry:
379 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
380 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
381 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32**, align 4
382 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
383 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
384 // CHECK3-NEXT:    store i32** [[C]], i32*** [[C_ADDR]], align 4
385 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32**, i32*** [[C_ADDR]], align 4
386 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 4
387 // CHECK3-NEXT:    call void @_Z4workPi(i32* [[TMP1]]) #[[ATTR5]]
388 // CHECK3-NEXT:    ret void
389 //
390 //
391 // CHECK3-LABEL: define {{[^@]+}}@_Z4workPi
392 // CHECK3-SAME: (i32* [[C:%.*]]) #[[ATTR1]] {
393 // CHECK3-NEXT:  entry:
394 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
395 // CHECK3-NEXT:    [[ATOMIC_TEMP:%.*]] = alloca i32, align 4
396 // CHECK3-NEXT:    [[ATOMIC_TEMP1:%.*]] = alloca i32, align 4
397 // CHECK3-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
398 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4
399 // CHECK3-NEXT:    [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8*
400 // CHECK3-NEXT:    [[TMP2:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8*
401 // CHECK3-NEXT:    call void @__atomic_load(i32 4, i8* [[TMP1]], i8* [[TMP2]], i32 0) #[[ATTR5]]
402 // CHECK3-NEXT:    br label [[ATOMIC_CONT:%.*]]
403 // CHECK3:       atomic_cont:
404 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4
405 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
406 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[ATOMIC_TEMP1]], align 4
407 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8*
408 // CHECK3-NEXT:    [[TMP5:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8*
409 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i32* [[ATOMIC_TEMP1]] to i8*
410 // CHECK3-NEXT:    [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 4, i8* [[TMP4]], i8* [[TMP5]], i8* [[TMP6]], i32 0, i32 0) #[[ATTR5]]
411 // CHECK3-NEXT:    br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]]
412 // CHECK3:       atomic_exit:
413 // CHECK3-NEXT:    ret void
414 //
415 //
416 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
417 // CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] {
418 // CHECK3-NEXT:  entry:
419 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
420 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
421 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
422 // CHECK3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4
423 // CHECK3-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
424 // CHECK3-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
425 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
426 // CHECK3-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
427 // CHECK3-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4
428 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0
429 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32***
430 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32**, i32*** [[TMP4]], align 4
431 // CHECK3-NEXT:    call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32** [[TMP5]]) #[[ATTR3]]
432 // CHECK3-NEXT:    ret void
433 //
434