1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-function-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+"
2 // Test target codegen - host bc file has to be created first.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK1
5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK2
7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK3
8 
9 // expected-no-diagnostics
10 #ifndef HEADER
11 #define HEADER
12 
13 void work(int *C) {
14   #pragma omp atomic
15   ++(*C);
16 }
17 
18 void use(int *C) {
19   #pragma omp parallel num_threads(2)
20   work(C);
21 }
22 
23 int main() {
24   int C = 0;
25   #pragma omp target map(C)
26   {
27     use(&C);
28     #pragma omp parallel num_threads(2)
29     use(&C);
30   }
31 
32   return C;
33 }
34 
35 #endif
36 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_worker
37 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
38 // CHECK1-NEXT:  entry:
39 // CHECK1-NEXT:    [[WORK_FN:%.*]] = alloca i8*, align 8
40 // CHECK1-NEXT:    [[EXEC_STATUS:%.*]] = alloca i8, align 1
41 // CHECK1-NEXT:    store i8* null, i8** [[WORK_FN]], align 8
42 // CHECK1-NEXT:    store i8 0, i8* [[EXEC_STATUS]], align 1
43 // CHECK1-NEXT:    br label [[DOTAWAIT_WORK:%.*]]
44 // CHECK1:       .await.work:
45 // CHECK1-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
46 // CHECK1-NEXT:    [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]])
47 // CHECK1-NEXT:    [[TMP1:%.*]] = zext i1 [[TMP0]] to i8
48 // CHECK1-NEXT:    store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1
49 // CHECK1-NEXT:    [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8
50 // CHECK1-NEXT:    [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null
51 // CHECK1-NEXT:    br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]]
52 // CHECK1:       .select.workers:
53 // CHECK1-NEXT:    [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1
54 // CHECK1-NEXT:    [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0
55 // CHECK1-NEXT:    br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]]
56 // CHECK1:       .execute.parallel:
57 // CHECK1-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
58 // CHECK1-NEXT:    [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 8
59 // CHECK1-NEXT:    [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*)
60 // CHECK1-NEXT:    br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]]
61 // CHECK1:       .execute.fn:
62 // CHECK1-NEXT:    call void @__omp_outlined___wrapper(i16 0, i32 [[TMP4]]) #[[ATTR5:[0-9]+]]
63 // CHECK1-NEXT:    br label [[DOTTERMINATE_PARALLEL:%.*]]
64 // CHECK1:       .check.next:
65 // CHECK1-NEXT:    [[TMP6:%.*]] = load i8*, i8** [[WORK_FN]], align 8
66 // CHECK1-NEXT:    [[WORK_MATCH1:%.*]] = icmp eq i8* [[TMP6]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*)
67 // CHECK1-NEXT:    br i1 [[WORK_MATCH1]], label [[DOTEXECUTE_FN2:%.*]], label [[DOTCHECK_NEXT3:%.*]]
68 // CHECK1:       .execute.fn2:
69 // CHECK1-NEXT:    call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR5]]
70 // CHECK1-NEXT:    br label [[DOTTERMINATE_PARALLEL]]
71 // CHECK1:       .check.next3:
72 // CHECK1-NEXT:    [[TMP7:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)*
73 // CHECK1-NEXT:    call void [[TMP7]](i16 0, i32 [[TMP4]])
74 // CHECK1-NEXT:    br label [[DOTTERMINATE_PARALLEL]]
75 // CHECK1:       .terminate.parallel:
76 // CHECK1-NEXT:    call void @__kmpc_kernel_end_parallel()
77 // CHECK1-NEXT:    br label [[DOTBARRIER_PARALLEL]]
78 // CHECK1:       .barrier.parallel:
79 // CHECK1-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
80 // CHECK1-NEXT:    br label [[DOTAWAIT_WORK]]
81 // CHECK1:       .exit:
82 // CHECK1-NEXT:    ret void
83 //
84 //
85 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25
86 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1:[0-9]+]] {
87 // CHECK1-NEXT:  entry:
88 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 8
89 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
90 // CHECK1-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 8
91 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 8
92 // CHECK1-NEXT:    [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
93 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
94 // CHECK1-NEXT:    [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
95 // CHECK1-NEXT:    [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]
96 // CHECK1-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]
97 // CHECK1-NEXT:    br i1 [[TMP1]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]]
98 // CHECK1:       .worker:
99 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_worker() #[[ATTR5]]
100 // CHECK1-NEXT:    br label [[DOTEXIT:%.*]]
101 // CHECK1:       .mastercheck:
102 // CHECK1-NEXT:    [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
103 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
104 // CHECK1-NEXT:    [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
105 // CHECK1-NEXT:    [[TMP2:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1
106 // CHECK1-NEXT:    [[TMP3:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1
107 // CHECK1-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP2]], -1
108 // CHECK1-NEXT:    [[MASTER_TID:%.*]] = and i32 [[TMP3]], [[TMP4]]
109 // CHECK1-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]
110 // CHECK1-NEXT:    br i1 [[TMP5]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]
111 // CHECK1:       .master:
112 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
113 // CHECK1-NEXT:    [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
114 // CHECK1-NEXT:    [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]
115 // CHECK1-NEXT:    call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)
116 // CHECK1-NEXT:    call void @__kmpc_data_sharing_init_stack()
117 // CHECK1-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
118 // CHECK1-NEXT:    call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR7:[0-9]+]]
119 // CHECK1-NEXT:    call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 2)
120 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
121 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i32* [[TMP0]] to i8*
122 // CHECK1-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 8
123 // CHECK1-NEXT:    [[TMP9:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
124 // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP9]], i64 1)
125 // CHECK1-NEXT:    br label [[DOTTERMINATION_NOTIFIER:%.*]]
126 // CHECK1:       .termination.notifier:
127 // CHECK1-NEXT:    call void @__kmpc_kernel_deinit(i16 1)
128 // CHECK1-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
129 // CHECK1-NEXT:    br label [[DOTEXIT]]
130 // CHECK1:       .exit:
131 // CHECK1-NEXT:    ret void
132 //
133 //
134 // CHECK1-LABEL: define {{[^@]+}}@_Z3usePi
135 // CHECK1-SAME: (i32* [[C:%.*]]) #[[ATTR3:[0-9]+]] {
136 // CHECK1-NEXT:  entry:
137 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 8
138 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
139 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
140 // CHECK1-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 8
141 // CHECK1-NEXT:    call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 2)
142 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
143 // CHECK1-NEXT:    [[TMP2:%.*]] = bitcast i32** [[C_ADDR]] to i8*
144 // CHECK1-NEXT:    store i8* [[TMP2]], i8** [[TMP1]], align 8
145 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
146 // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32**)* @__omp_outlined__ to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*), i8** [[TMP3]], i64 1)
147 // CHECK1-NEXT:    ret void
148 //
149 //
150 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
151 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] {
152 // CHECK1-NEXT:  entry:
153 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
154 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
155 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32**, align 8
156 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
157 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
158 // CHECK1-NEXT:    store i32** [[C]], i32*** [[C_ADDR]], align 8
159 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32**, i32*** [[C_ADDR]], align 8
160 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 8
161 // CHECK1-NEXT:    call void @_Z4workPi(i32* [[TMP1]]) #[[ATTR7]]
162 // CHECK1-NEXT:    ret void
163 //
164 //
165 // CHECK1-LABEL: define {{[^@]+}}@_Z4workPi
166 // CHECK1-SAME: (i32* [[C:%.*]]) #[[ATTR3]] {
167 // CHECK1-NEXT:  entry:
168 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 8
169 // CHECK1-NEXT:    [[ATOMIC_TEMP:%.*]] = alloca i32, align 4
170 // CHECK1-NEXT:    [[ATOMIC_TEMP1:%.*]] = alloca i32, align 4
171 // CHECK1-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 8
172 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 8
173 // CHECK1-NEXT:    [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8*
174 // CHECK1-NEXT:    [[TMP2:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8*
175 // CHECK1-NEXT:    call void @__atomic_load(i64 4, i8* [[TMP1]], i8* [[TMP2]], i32 0) #[[ATTR7]]
176 // CHECK1-NEXT:    br label [[ATOMIC_CONT:%.*]]
177 // CHECK1:       atomic_cont:
178 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4
179 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
180 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[ATOMIC_TEMP1]], align 4
181 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8*
182 // CHECK1-NEXT:    [[TMP5:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8*
183 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i32* [[ATOMIC_TEMP1]] to i8*
184 // CHECK1-NEXT:    [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 4, i8* [[TMP4]], i8* [[TMP5]], i8* [[TMP6]], i32 0, i32 0) #[[ATTR7]]
185 // CHECK1-NEXT:    br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]]
186 // CHECK1:       atomic_exit:
187 // CHECK1-NEXT:    ret void
188 //
189 //
190 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___wrapper
191 // CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
192 // CHECK1-NEXT:  entry:
193 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
194 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
195 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
196 // CHECK1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
197 // CHECK1-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
198 // CHECK1-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
199 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
200 // CHECK1-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
201 // CHECK1-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8
202 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0
203 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32***
204 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32**, i32*** [[TMP4]], align 8
205 // CHECK1-NEXT:    call void @__omp_outlined__(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32** [[TMP5]]) #[[ATTR5]]
206 // CHECK1-NEXT:    ret void
207 //
208 //
209 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
210 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] {
211 // CHECK1-NEXT:  entry:
212 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
213 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
214 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 8
215 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
216 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
217 // CHECK1-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 8
218 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 8
219 // CHECK1-NEXT:    call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR7]]
220 // CHECK1-NEXT:    ret void
221 //
222 //
223 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
224 // CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
225 // CHECK1-NEXT:  entry:
226 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
227 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
228 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
229 // CHECK1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
230 // CHECK1-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
231 // CHECK1-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
232 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
233 // CHECK1-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
234 // CHECK1-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8
235 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0
236 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
237 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 8
238 // CHECK1-NEXT:    call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR5]]
239 // CHECK1-NEXT:    ret void
240 //
241 //
242 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_worker
243 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
244 // CHECK2-NEXT:  entry:
245 // CHECK2-NEXT:    [[WORK_FN:%.*]] = alloca i8*, align 4
246 // CHECK2-NEXT:    [[EXEC_STATUS:%.*]] = alloca i8, align 1
247 // CHECK2-NEXT:    store i8* null, i8** [[WORK_FN]], align 4
248 // CHECK2-NEXT:    store i8 0, i8* [[EXEC_STATUS]], align 1
249 // CHECK2-NEXT:    br label [[DOTAWAIT_WORK:%.*]]
250 // CHECK2:       .await.work:
251 // CHECK2-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
252 // CHECK2-NEXT:    [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]])
253 // CHECK2-NEXT:    [[TMP1:%.*]] = zext i1 [[TMP0]] to i8
254 // CHECK2-NEXT:    store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1
255 // CHECK2-NEXT:    [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4
256 // CHECK2-NEXT:    [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null
257 // CHECK2-NEXT:    br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]]
258 // CHECK2:       .select.workers:
259 // CHECK2-NEXT:    [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1
260 // CHECK2-NEXT:    [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0
261 // CHECK2-NEXT:    br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]]
262 // CHECK2:       .execute.parallel:
263 // CHECK2-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
264 // CHECK2-NEXT:    [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 4
265 // CHECK2-NEXT:    [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*)
266 // CHECK2-NEXT:    br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]]
267 // CHECK2:       .execute.fn:
268 // CHECK2-NEXT:    call void @__omp_outlined___wrapper(i16 0, i32 [[TMP4]]) #[[ATTR5:[0-9]+]]
269 // CHECK2-NEXT:    br label [[DOTTERMINATE_PARALLEL:%.*]]
270 // CHECK2:       .check.next:
271 // CHECK2-NEXT:    [[TMP6:%.*]] = load i8*, i8** [[WORK_FN]], align 4
272 // CHECK2-NEXT:    [[WORK_MATCH1:%.*]] = icmp eq i8* [[TMP6]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*)
273 // CHECK2-NEXT:    br i1 [[WORK_MATCH1]], label [[DOTEXECUTE_FN2:%.*]], label [[DOTCHECK_NEXT3:%.*]]
274 // CHECK2:       .execute.fn2:
275 // CHECK2-NEXT:    call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR5]]
276 // CHECK2-NEXT:    br label [[DOTTERMINATE_PARALLEL]]
277 // CHECK2:       .check.next3:
278 // CHECK2-NEXT:    [[TMP7:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)*
279 // CHECK2-NEXT:    call void [[TMP7]](i16 0, i32 [[TMP4]])
280 // CHECK2-NEXT:    br label [[DOTTERMINATE_PARALLEL]]
281 // CHECK2:       .terminate.parallel:
282 // CHECK2-NEXT:    call void @__kmpc_kernel_end_parallel()
283 // CHECK2-NEXT:    br label [[DOTBARRIER_PARALLEL]]
284 // CHECK2:       .barrier.parallel:
285 // CHECK2-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
286 // CHECK2-NEXT:    br label [[DOTAWAIT_WORK]]
287 // CHECK2:       .exit:
288 // CHECK2-NEXT:    ret void
289 //
290 //
291 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25
292 // CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1:[0-9]+]] {
293 // CHECK2-NEXT:  entry:
294 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
295 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
296 // CHECK2-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
297 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4
298 // CHECK2-NEXT:    [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
299 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
300 // CHECK2-NEXT:    [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
301 // CHECK2-NEXT:    [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]
302 // CHECK2-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]
303 // CHECK2-NEXT:    br i1 [[TMP1]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]]
304 // CHECK2:       .worker:
305 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_worker() #[[ATTR5]]
306 // CHECK2-NEXT:    br label [[DOTEXIT:%.*]]
307 // CHECK2:       .mastercheck:
308 // CHECK2-NEXT:    [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
309 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
310 // CHECK2-NEXT:    [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
311 // CHECK2-NEXT:    [[TMP2:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1
312 // CHECK2-NEXT:    [[TMP3:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1
313 // CHECK2-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP2]], -1
314 // CHECK2-NEXT:    [[MASTER_TID:%.*]] = and i32 [[TMP3]], [[TMP4]]
315 // CHECK2-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]
316 // CHECK2-NEXT:    br i1 [[TMP5]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]
317 // CHECK2:       .master:
318 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
319 // CHECK2-NEXT:    [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
320 // CHECK2-NEXT:    [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]
321 // CHECK2-NEXT:    call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)
322 // CHECK2-NEXT:    call void @__kmpc_data_sharing_init_stack()
323 // CHECK2-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
324 // CHECK2-NEXT:    call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR7:[0-9]+]]
325 // CHECK2-NEXT:    call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 2)
326 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
327 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i32* [[TMP0]] to i8*
328 // CHECK2-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
329 // CHECK2-NEXT:    [[TMP9:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
330 // CHECK2-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP9]], i32 1)
331 // CHECK2-NEXT:    br label [[DOTTERMINATION_NOTIFIER:%.*]]
332 // CHECK2:       .termination.notifier:
333 // CHECK2-NEXT:    call void @__kmpc_kernel_deinit(i16 1)
334 // CHECK2-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
335 // CHECK2-NEXT:    br label [[DOTEXIT]]
336 // CHECK2:       .exit:
337 // CHECK2-NEXT:    ret void
338 //
339 //
340 // CHECK2-LABEL: define {{[^@]+}}@_Z3usePi
341 // CHECK2-SAME: (i32* [[C:%.*]]) #[[ATTR3:[0-9]+]] {
342 // CHECK2-NEXT:  entry:
343 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
344 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
345 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
346 // CHECK2-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
347 // CHECK2-NEXT:    call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 2)
348 // CHECK2-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
349 // CHECK2-NEXT:    [[TMP2:%.*]] = bitcast i32** [[C_ADDR]] to i8*
350 // CHECK2-NEXT:    store i8* [[TMP2]], i8** [[TMP1]], align 4
351 // CHECK2-NEXT:    [[TMP3:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
352 // CHECK2-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32**)* @__omp_outlined__ to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*), i8** [[TMP3]], i32 1)
353 // CHECK2-NEXT:    ret void
354 //
355 //
356 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
357 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] {
358 // CHECK2-NEXT:  entry:
359 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
360 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
361 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i32**, align 4
362 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
363 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
364 // CHECK2-NEXT:    store i32** [[C]], i32*** [[C_ADDR]], align 4
365 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32**, i32*** [[C_ADDR]], align 4
366 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 4
367 // CHECK2-NEXT:    call void @_Z4workPi(i32* [[TMP1]]) #[[ATTR7]]
368 // CHECK2-NEXT:    ret void
369 //
370 //
371 // CHECK2-LABEL: define {{[^@]+}}@_Z4workPi
372 // CHECK2-SAME: (i32* [[C:%.*]]) #[[ATTR3]] {
373 // CHECK2-NEXT:  entry:
374 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
375 // CHECK2-NEXT:    [[ATOMIC_TEMP:%.*]] = alloca i32, align 4
376 // CHECK2-NEXT:    [[ATOMIC_TEMP1:%.*]] = alloca i32, align 4
377 // CHECK2-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
378 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4
379 // CHECK2-NEXT:    [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8*
380 // CHECK2-NEXT:    [[TMP2:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8*
381 // CHECK2-NEXT:    call void @__atomic_load(i32 4, i8* [[TMP1]], i8* [[TMP2]], i32 0) #[[ATTR7]]
382 // CHECK2-NEXT:    br label [[ATOMIC_CONT:%.*]]
383 // CHECK2:       atomic_cont:
384 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4
385 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
386 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[ATOMIC_TEMP1]], align 4
387 // CHECK2-NEXT:    [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8*
388 // CHECK2-NEXT:    [[TMP5:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8*
389 // CHECK2-NEXT:    [[TMP6:%.*]] = bitcast i32* [[ATOMIC_TEMP1]] to i8*
390 // CHECK2-NEXT:    [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 4, i8* [[TMP4]], i8* [[TMP5]], i8* [[TMP6]], i32 0, i32 0) #[[ATTR7]]
391 // CHECK2-NEXT:    br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]]
392 // CHECK2:       atomic_exit:
393 // CHECK2-NEXT:    ret void
394 //
395 //
396 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined___wrapper
397 // CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
398 // CHECK2-NEXT:  entry:
399 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
400 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
401 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
402 // CHECK2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4
403 // CHECK2-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
404 // CHECK2-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
405 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
406 // CHECK2-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
407 // CHECK2-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4
408 // CHECK2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0
409 // CHECK2-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32***
410 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32**, i32*** [[TMP4]], align 4
411 // CHECK2-NEXT:    call void @__omp_outlined__(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32** [[TMP5]]) #[[ATTR5]]
412 // CHECK2-NEXT:    ret void
413 //
414 //
415 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
416 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] {
417 // CHECK2-NEXT:  entry:
418 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
419 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
420 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
421 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
422 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
423 // CHECK2-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
424 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4
425 // CHECK2-NEXT:    call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR7]]
426 // CHECK2-NEXT:    ret void
427 //
428 //
429 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
430 // CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
431 // CHECK2-NEXT:  entry:
432 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
433 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
434 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
435 // CHECK2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4
436 // CHECK2-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
437 // CHECK2-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
438 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
439 // CHECK2-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
440 // CHECK2-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4
441 // CHECK2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0
442 // CHECK2-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
443 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4
444 // CHECK2-NEXT:    call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR5]]
445 // CHECK2-NEXT:    ret void
446 //
447 //
448 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_worker
449 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
450 // CHECK3-NEXT:  entry:
451 // CHECK3-NEXT:    [[WORK_FN:%.*]] = alloca i8*, align 4
452 // CHECK3-NEXT:    [[EXEC_STATUS:%.*]] = alloca i8, align 1
453 // CHECK3-NEXT:    store i8* null, i8** [[WORK_FN]], align 4
454 // CHECK3-NEXT:    store i8 0, i8* [[EXEC_STATUS]], align 1
455 // CHECK3-NEXT:    br label [[DOTAWAIT_WORK:%.*]]
456 // CHECK3:       .await.work:
457 // CHECK3-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
458 // CHECK3-NEXT:    [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]])
459 // CHECK3-NEXT:    [[TMP1:%.*]] = zext i1 [[TMP0]] to i8
460 // CHECK3-NEXT:    store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1
461 // CHECK3-NEXT:    [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4
462 // CHECK3-NEXT:    [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null
463 // CHECK3-NEXT:    br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]]
464 // CHECK3:       .select.workers:
465 // CHECK3-NEXT:    [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1
466 // CHECK3-NEXT:    [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0
467 // CHECK3-NEXT:    br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]]
468 // CHECK3:       .execute.parallel:
469 // CHECK3-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
470 // CHECK3-NEXT:    [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 4
471 // CHECK3-NEXT:    [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*)
472 // CHECK3-NEXT:    br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]]
473 // CHECK3:       .execute.fn:
474 // CHECK3-NEXT:    call void @__omp_outlined___wrapper(i16 0, i32 [[TMP4]]) #[[ATTR5:[0-9]+]]
475 // CHECK3-NEXT:    br label [[DOTTERMINATE_PARALLEL:%.*]]
476 // CHECK3:       .check.next:
477 // CHECK3-NEXT:    [[TMP6:%.*]] = load i8*, i8** [[WORK_FN]], align 4
478 // CHECK3-NEXT:    [[WORK_MATCH1:%.*]] = icmp eq i8* [[TMP6]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*)
479 // CHECK3-NEXT:    br i1 [[WORK_MATCH1]], label [[DOTEXECUTE_FN2:%.*]], label [[DOTCHECK_NEXT3:%.*]]
480 // CHECK3:       .execute.fn2:
481 // CHECK3-NEXT:    call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR5]]
482 // CHECK3-NEXT:    br label [[DOTTERMINATE_PARALLEL]]
483 // CHECK3:       .check.next3:
484 // CHECK3-NEXT:    [[TMP7:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)*
485 // CHECK3-NEXT:    call void [[TMP7]](i16 0, i32 [[TMP4]])
486 // CHECK3-NEXT:    br label [[DOTTERMINATE_PARALLEL]]
487 // CHECK3:       .terminate.parallel:
488 // CHECK3-NEXT:    call void @__kmpc_kernel_end_parallel()
489 // CHECK3-NEXT:    br label [[DOTBARRIER_PARALLEL]]
490 // CHECK3:       .barrier.parallel:
491 // CHECK3-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
492 // CHECK3-NEXT:    br label [[DOTAWAIT_WORK]]
493 // CHECK3:       .exit:
494 // CHECK3-NEXT:    ret void
495 //
496 //
497 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25
498 // CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1:[0-9]+]] {
499 // CHECK3-NEXT:  entry:
500 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
501 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
502 // CHECK3-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
503 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4
504 // CHECK3-NEXT:    [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
505 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
506 // CHECK3-NEXT:    [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
507 // CHECK3-NEXT:    [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]
508 // CHECK3-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]
509 // CHECK3-NEXT:    br i1 [[TMP1]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]]
510 // CHECK3:       .worker:
511 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_worker() #[[ATTR5]]
512 // CHECK3-NEXT:    br label [[DOTEXIT:%.*]]
513 // CHECK3:       .mastercheck:
514 // CHECK3-NEXT:    [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
515 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
516 // CHECK3-NEXT:    [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
517 // CHECK3-NEXT:    [[TMP2:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1
518 // CHECK3-NEXT:    [[TMP3:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1
519 // CHECK3-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP2]], -1
520 // CHECK3-NEXT:    [[MASTER_TID:%.*]] = and i32 [[TMP3]], [[TMP4]]
521 // CHECK3-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]
522 // CHECK3-NEXT:    br i1 [[TMP5]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]
523 // CHECK3:       .master:
524 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
525 // CHECK3-NEXT:    [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
526 // CHECK3-NEXT:    [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]
527 // CHECK3-NEXT:    call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)
528 // CHECK3-NEXT:    call void @__kmpc_data_sharing_init_stack()
529 // CHECK3-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
530 // CHECK3-NEXT:    call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR7:[0-9]+]]
531 // CHECK3-NEXT:    call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 2)
532 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
533 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i32* [[TMP0]] to i8*
534 // CHECK3-NEXT:    store i8* [[TMP8]], i8** [[TMP7]], align 4
535 // CHECK3-NEXT:    [[TMP9:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
536 // CHECK3-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP9]], i32 1)
537 // CHECK3-NEXT:    br label [[DOTTERMINATION_NOTIFIER:%.*]]
538 // CHECK3:       .termination.notifier:
539 // CHECK3-NEXT:    call void @__kmpc_kernel_deinit(i16 1)
540 // CHECK3-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
541 // CHECK3-NEXT:    br label [[DOTEXIT]]
542 // CHECK3:       .exit:
543 // CHECK3-NEXT:    ret void
544 //
545 //
546 // CHECK3-LABEL: define {{[^@]+}}@_Z3usePi
547 // CHECK3-SAME: (i32* [[C:%.*]]) #[[ATTR3:[0-9]+]] {
548 // CHECK3-NEXT:  entry:
549 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
550 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
551 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
552 // CHECK3-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
553 // CHECK3-NEXT:    call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 2)
554 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
555 // CHECK3-NEXT:    [[TMP2:%.*]] = bitcast i32** [[C_ADDR]] to i8*
556 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[TMP1]], align 4
557 // CHECK3-NEXT:    [[TMP3:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
558 // CHECK3-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32**)* @__omp_outlined__ to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*), i8** [[TMP3]], i32 1)
559 // CHECK3-NEXT:    ret void
560 //
561 //
562 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
563 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] {
564 // CHECK3-NEXT:  entry:
565 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
566 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
567 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32**, align 4
568 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
569 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
570 // CHECK3-NEXT:    store i32** [[C]], i32*** [[C_ADDR]], align 4
571 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32**, i32*** [[C_ADDR]], align 4
572 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 4
573 // CHECK3-NEXT:    call void @_Z4workPi(i32* [[TMP1]]) #[[ATTR7]]
574 // CHECK3-NEXT:    ret void
575 //
576 //
577 // CHECK3-LABEL: define {{[^@]+}}@_Z4workPi
578 // CHECK3-SAME: (i32* [[C:%.*]]) #[[ATTR3]] {
579 // CHECK3-NEXT:  entry:
580 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
581 // CHECK3-NEXT:    [[ATOMIC_TEMP:%.*]] = alloca i32, align 4
582 // CHECK3-NEXT:    [[ATOMIC_TEMP1:%.*]] = alloca i32, align 4
583 // CHECK3-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
584 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4
585 // CHECK3-NEXT:    [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8*
586 // CHECK3-NEXT:    [[TMP2:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8*
587 // CHECK3-NEXT:    call void @__atomic_load(i32 4, i8* [[TMP1]], i8* [[TMP2]], i32 0) #[[ATTR7]]
588 // CHECK3-NEXT:    br label [[ATOMIC_CONT:%.*]]
589 // CHECK3:       atomic_cont:
590 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4
591 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
592 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[ATOMIC_TEMP1]], align 4
593 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8*
594 // CHECK3-NEXT:    [[TMP5:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8*
595 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i32* [[ATOMIC_TEMP1]] to i8*
596 // CHECK3-NEXT:    [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 4, i8* [[TMP4]], i8* [[TMP5]], i8* [[TMP6]], i32 0, i32 0) #[[ATTR7]]
597 // CHECK3-NEXT:    br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]]
598 // CHECK3:       atomic_exit:
599 // CHECK3-NEXT:    ret void
600 //
601 //
602 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined___wrapper
603 // CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
604 // CHECK3-NEXT:  entry:
605 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
606 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
607 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
608 // CHECK3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4
609 // CHECK3-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
610 // CHECK3-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
611 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
612 // CHECK3-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
613 // CHECK3-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4
614 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0
615 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32***
616 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32**, i32*** [[TMP4]], align 4
617 // CHECK3-NEXT:    call void @__omp_outlined__(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32** [[TMP5]]) #[[ATTR5]]
618 // CHECK3-NEXT:    ret void
619 //
620 //
621 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
622 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] {
623 // CHECK3-NEXT:  entry:
624 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
625 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
626 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32*, align 4
627 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
628 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
629 // CHECK3-NEXT:    store i32* [[C]], i32** [[C_ADDR]], align 4
630 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4
631 // CHECK3-NEXT:    call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR7]]
632 // CHECK3-NEXT:    ret void
633 //
634 //
635 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
636 // CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
637 // CHECK3-NEXT:  entry:
638 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
639 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
640 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
641 // CHECK3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4
642 // CHECK3-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
643 // CHECK3-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
644 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
645 // CHECK3-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
646 // CHECK3-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4
647 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0
648 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
649 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4
650 // CHECK3-NEXT:    call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR5]]
651 // CHECK3-NEXT:    ret void
652 //
653