1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test target codegen - host bc file has to be created first. 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK3 8 9 // expected-no-diagnostics 10 #ifndef HEADER 11 #define HEADER 12 13 void work(); 14 15 void use() { 16 #pragma omp parallel 17 work(); 18 } 19 20 int main() { 21 #pragma omp target parallel 22 { use(); } 23 #pragma omp target 24 { use(); } 25 } 26 27 #endif 28 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 29 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 30 // CHECK1-NEXT: entry: 31 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 32 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 33 // CHECK1-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1) 34 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack_spmd() 35 // CHECK1-NEXT: br label [[DOTEXECUTE:%.*]] 36 // CHECK1: .execute: 37 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 38 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 39 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP1]], i64 0) 40 // CHECK1-NEXT: br label [[DOTOMP_DEINIT:%.*]] 41 // CHECK1: .omp.deinit: 42 // CHECK1-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 43 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 44 // CHECK1: .exit: 45 // CHECK1-NEXT: ret void 46 // 47 // 48 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ 49 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 50 // CHECK1-NEXT: entry: 51 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 52 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 53 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 54 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 55 // CHECK1-NEXT: call void @_Z3usev() #[[ATTR7:[0-9]+]] 56 // CHECK1-NEXT: ret void 57 // 58 // 59 // CHECK1-LABEL: define {{[^@]+}}@_Z3usev 60 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 61 // CHECK1-NEXT: entry: 62 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 63 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 64 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 65 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP1]], i64 0) 66 // CHECK1-NEXT: ret void 67 // 68 // 69 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker 70 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 71 // CHECK1-NEXT: entry: 72 // CHECK1-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 73 // CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 74 // CHECK1-NEXT: store i8* null, i8** [[WORK_FN]], align 8 75 // CHECK1-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 76 // CHECK1-NEXT: br label [[DOTAWAIT_WORK:%.*]] 77 // CHECK1: .await.work: 78 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 79 // CHECK1-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 80 // CHECK1-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 81 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 82 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 83 // CHECK1-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 84 // CHECK1-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 85 // CHECK1: .select.workers: 86 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 87 // CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 88 // CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 89 // CHECK1: .execute.parallel: 90 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 91 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 92 // CHECK1-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 93 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 94 // CHECK1: .terminate.parallel: 95 // CHECK1-NEXT: call void @__kmpc_kernel_end_parallel() 96 // CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]] 97 // CHECK1: .barrier.parallel: 98 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 99 // CHECK1-NEXT: br label [[DOTAWAIT_WORK]] 100 // CHECK1: .exit: 101 // CHECK1-NEXT: ret void 102 // 103 // 104 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 105 // CHECK1-SAME: () #[[ATTR0]] { 106 // CHECK1-NEXT: entry: 107 // CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 108 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 109 // CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 110 // CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 111 // CHECK1-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 112 // CHECK1-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 113 // CHECK1: .worker: 114 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker() #[[ATTR3:[0-9]+]] 115 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 116 // CHECK1: .mastercheck: 117 // CHECK1-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 118 // CHECK1-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 119 // CHECK1-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 120 // CHECK1-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 121 // CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 122 // CHECK1-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 123 // CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 124 // CHECK1-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 125 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 126 // CHECK1: .master: 127 // CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 128 // CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 129 // CHECK1-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 130 // CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 131 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack() 132 // CHECK1-NEXT: call void @_Z3usev() #[[ATTR7]] 133 // CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 134 // CHECK1: .termination.notifier: 135 // CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1) 136 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 137 // CHECK1-NEXT: br label [[DOTEXIT]] 138 // CHECK1: .exit: 139 // CHECK1-NEXT: ret void 140 // 141 // 142 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 143 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 144 // CHECK1-NEXT: entry: 145 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 146 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 147 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 148 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 149 // CHECK1-NEXT: call void @_Z4workv() #[[ATTR7]] 150 // CHECK1-NEXT: ret void 151 // 152 // 153 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 154 // CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR4]] { 155 // CHECK1-NEXT: entry: 156 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 157 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 158 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 159 // CHECK1-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8 160 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 161 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 162 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 163 // CHECK1-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 164 // CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]] 165 // CHECK1-NEXT: ret void 166 // 167 // 168 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 169 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 170 // CHECK2-NEXT: entry: 171 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 172 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 173 // CHECK2-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1) 174 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack_spmd() 175 // CHECK2-NEXT: br label [[DOTEXECUTE:%.*]] 176 // CHECK2: .execute: 177 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 178 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 179 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP1]], i32 0) 180 // CHECK2-NEXT: br label [[DOTOMP_DEINIT:%.*]] 181 // CHECK2: .omp.deinit: 182 // CHECK2-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 183 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 184 // CHECK2: .exit: 185 // CHECK2-NEXT: ret void 186 // 187 // 188 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ 189 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 190 // CHECK2-NEXT: entry: 191 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 192 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 193 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 194 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 195 // CHECK2-NEXT: call void @_Z3usev() #[[ATTR7:[0-9]+]] 196 // CHECK2-NEXT: ret void 197 // 198 // 199 // CHECK2-LABEL: define {{[^@]+}}@_Z3usev 200 // CHECK2-SAME: () #[[ATTR2:[0-9]+]] { 201 // CHECK2-NEXT: entry: 202 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 203 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 204 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 205 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP1]], i32 0) 206 // CHECK2-NEXT: ret void 207 // 208 // 209 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker 210 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] { 211 // CHECK2-NEXT: entry: 212 // CHECK2-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 213 // CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 214 // CHECK2-NEXT: store i8* null, i8** [[WORK_FN]], align 4 215 // CHECK2-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 216 // CHECK2-NEXT: br label [[DOTAWAIT_WORK:%.*]] 217 // CHECK2: .await.work: 218 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 219 // CHECK2-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 220 // CHECK2-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 221 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 222 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 223 // CHECK2-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 224 // CHECK2-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 225 // CHECK2: .select.workers: 226 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 227 // CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 228 // CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 229 // CHECK2: .execute.parallel: 230 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 231 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 232 // CHECK2-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 233 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 234 // CHECK2: .terminate.parallel: 235 // CHECK2-NEXT: call void @__kmpc_kernel_end_parallel() 236 // CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]] 237 // CHECK2: .barrier.parallel: 238 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 239 // CHECK2-NEXT: br label [[DOTAWAIT_WORK]] 240 // CHECK2: .exit: 241 // CHECK2-NEXT: ret void 242 // 243 // 244 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 245 // CHECK2-SAME: () #[[ATTR0]] { 246 // CHECK2-NEXT: entry: 247 // CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 248 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 249 // CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 250 // CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 251 // CHECK2-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 252 // CHECK2-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 253 // CHECK2: .worker: 254 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker() #[[ATTR3:[0-9]+]] 255 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 256 // CHECK2: .mastercheck: 257 // CHECK2-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 258 // CHECK2-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 259 // CHECK2-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 260 // CHECK2-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 261 // CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 262 // CHECK2-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 263 // CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 264 // CHECK2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 265 // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 266 // CHECK2: .master: 267 // CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 268 // CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 269 // CHECK2-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 270 // CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 271 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack() 272 // CHECK2-NEXT: call void @_Z3usev() #[[ATTR7]] 273 // CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 274 // CHECK2: .termination.notifier: 275 // CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1) 276 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 277 // CHECK2-NEXT: br label [[DOTEXIT]] 278 // CHECK2: .exit: 279 // CHECK2-NEXT: ret void 280 // 281 // 282 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 283 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 284 // CHECK2-NEXT: entry: 285 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 286 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 287 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 288 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 289 // CHECK2-NEXT: call void @_Z4workv() #[[ATTR7]] 290 // CHECK2-NEXT: ret void 291 // 292 // 293 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 294 // CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR4]] { 295 // CHECK2-NEXT: entry: 296 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 297 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 298 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 299 // CHECK2-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 300 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 301 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 302 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 303 // CHECK2-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 304 // CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]] 305 // CHECK2-NEXT: ret void 306 // 307 // 308 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 309 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 310 // CHECK3-NEXT: entry: 311 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 312 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 313 // CHECK3-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1) 314 // CHECK3-NEXT: call void @__kmpc_data_sharing_init_stack_spmd() 315 // CHECK3-NEXT: br label [[DOTEXECUTE:%.*]] 316 // CHECK3: .execute: 317 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 318 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 319 // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP1]], i32 0) 320 // CHECK3-NEXT: br label [[DOTOMP_DEINIT:%.*]] 321 // CHECK3: .omp.deinit: 322 // CHECK3-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 323 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 324 // CHECK3: .exit: 325 // CHECK3-NEXT: ret void 326 // 327 // 328 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ 329 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 330 // CHECK3-NEXT: entry: 331 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 332 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 333 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 334 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 335 // CHECK3-NEXT: call void @_Z3usev() #[[ATTR7:[0-9]+]] 336 // CHECK3-NEXT: ret void 337 // 338 // 339 // CHECK3-LABEL: define {{[^@]+}}@_Z3usev 340 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 341 // CHECK3-NEXT: entry: 342 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 343 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 344 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 345 // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP1]], i32 0) 346 // CHECK3-NEXT: ret void 347 // 348 // 349 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker 350 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 351 // CHECK3-NEXT: entry: 352 // CHECK3-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 353 // CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 354 // CHECK3-NEXT: store i8* null, i8** [[WORK_FN]], align 4 355 // CHECK3-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 356 // CHECK3-NEXT: br label [[DOTAWAIT_WORK:%.*]] 357 // CHECK3: .await.work: 358 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 359 // CHECK3-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 360 // CHECK3-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 361 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 362 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 363 // CHECK3-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 364 // CHECK3-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 365 // CHECK3: .select.workers: 366 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 367 // CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 368 // CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 369 // CHECK3: .execute.parallel: 370 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 371 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 372 // CHECK3-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 373 // CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 374 // CHECK3: .terminate.parallel: 375 // CHECK3-NEXT: call void @__kmpc_kernel_end_parallel() 376 // CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]] 377 // CHECK3: .barrier.parallel: 378 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 379 // CHECK3-NEXT: br label [[DOTAWAIT_WORK]] 380 // CHECK3: .exit: 381 // CHECK3-NEXT: ret void 382 // 383 // 384 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 385 // CHECK3-SAME: () #[[ATTR0]] { 386 // CHECK3-NEXT: entry: 387 // CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 388 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 389 // CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 390 // CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 391 // CHECK3-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 392 // CHECK3-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 393 // CHECK3: .worker: 394 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker() #[[ATTR3:[0-9]+]] 395 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 396 // CHECK3: .mastercheck: 397 // CHECK3-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 398 // CHECK3-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 399 // CHECK3-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 400 // CHECK3-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 401 // CHECK3-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 402 // CHECK3-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 403 // CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 404 // CHECK3-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 405 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 406 // CHECK3: .master: 407 // CHECK3-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 408 // CHECK3-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 409 // CHECK3-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 410 // CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 411 // CHECK3-NEXT: call void @__kmpc_data_sharing_init_stack() 412 // CHECK3-NEXT: call void @_Z3usev() #[[ATTR7]] 413 // CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 414 // CHECK3: .termination.notifier: 415 // CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1) 416 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 417 // CHECK3-NEXT: br label [[DOTEXIT]] 418 // CHECK3: .exit: 419 // CHECK3-NEXT: ret void 420 // 421 // 422 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 423 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 424 // CHECK3-NEXT: entry: 425 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 426 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 427 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 428 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 429 // CHECK3-NEXT: call void @_Z4workv() #[[ATTR7]] 430 // CHECK3-NEXT: ret void 431 // 432 // 433 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 434 // CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR4]] { 435 // CHECK3-NEXT: entry: 436 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 437 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 438 // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 439 // CHECK3-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 440 // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 441 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 442 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 443 // CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 444 // CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]] 445 // CHECK3-NEXT: ret void 446 // 447