1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-function-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" 2 // Test target codegen - host bc file has to be created first. 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK1 5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK2 7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK3 8 9 // expected-no-diagnostics 10 #ifndef HEADER 11 #define HEADER 12 13 void work(); 14 15 void use() { 16 #pragma omp parallel 17 work(); 18 } 19 20 int main() { 21 #pragma omp target parallel 22 { use(); } 23 #pragma omp target 24 { use(); } 25 } 26 27 #endif 28 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 29 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 30 // CHECK1-NEXT: entry: 31 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 32 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 33 // CHECK1-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1) 34 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack_spmd() 35 // CHECK1-NEXT: br label [[DOTEXECUTE:%.*]] 36 // CHECK1: .execute: 37 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 38 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 39 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP1]], i64 0) 40 // CHECK1-NEXT: br label [[DOTOMP_DEINIT:%.*]] 41 // CHECK1: .omp.deinit: 42 // CHECK1-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 43 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 44 // CHECK1: .exit: 45 // CHECK1-NEXT: ret void 46 // 47 // 48 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ 49 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 50 // CHECK1-NEXT: entry: 51 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 52 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 53 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 54 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 55 // CHECK1-NEXT: call void @_Z3usev() #[[ATTR7:[0-9]+]] 56 // CHECK1-NEXT: ret void 57 // 58 // 59 // CHECK1-LABEL: define {{[^@]+}}@_Z3usev 60 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 61 // CHECK1-NEXT: entry: 62 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 63 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 64 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 65 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP1]], i64 0) 66 // CHECK1-NEXT: ret void 67 // 68 // 69 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 70 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 71 // CHECK1-NEXT: entry: 72 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 73 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 74 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 75 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 76 // CHECK1-NEXT: call void @_Z4workv() #[[ATTR7]] 77 // CHECK1-NEXT: ret void 78 // 79 // 80 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker 81 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] { 82 // CHECK1-NEXT: entry: 83 // CHECK1-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 84 // CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 85 // CHECK1-NEXT: store i8* null, i8** [[WORK_FN]], align 8 86 // CHECK1-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 87 // CHECK1-NEXT: br label [[DOTAWAIT_WORK:%.*]] 88 // CHECK1: .await.work: 89 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 90 // CHECK1-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 91 // CHECK1-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 92 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 93 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 94 // CHECK1-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 95 // CHECK1-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 96 // CHECK1: .select.workers: 97 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 98 // CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 99 // CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 100 // CHECK1: .execute.parallel: 101 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 102 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 103 // CHECK1-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 104 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 105 // CHECK1: .terminate.parallel: 106 // CHECK1-NEXT: call void @__kmpc_kernel_end_parallel() 107 // CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]] 108 // CHECK1: .barrier.parallel: 109 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 110 // CHECK1-NEXT: br label [[DOTAWAIT_WORK]] 111 // CHECK1: .exit: 112 // CHECK1-NEXT: ret void 113 // 114 // 115 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 116 // CHECK1-SAME: () #[[ATTR0]] { 117 // CHECK1-NEXT: entry: 118 // CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 119 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 120 // CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 121 // CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 122 // CHECK1-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 123 // CHECK1-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 124 // CHECK1: .worker: 125 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker() #[[ATTR4:[0-9]+]] 126 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 127 // CHECK1: .mastercheck: 128 // CHECK1-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 129 // CHECK1-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 130 // CHECK1-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 131 // CHECK1-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 132 // CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 133 // CHECK1-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 134 // CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 135 // CHECK1-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 136 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 137 // CHECK1: .master: 138 // CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 139 // CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 140 // CHECK1-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 141 // CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 142 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack() 143 // CHECK1-NEXT: call void @_Z3usev() #[[ATTR7]] 144 // CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 145 // CHECK1: .termination.notifier: 146 // CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1) 147 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 148 // CHECK1-NEXT: br label [[DOTEXIT]] 149 // CHECK1: .exit: 150 // CHECK1-NEXT: ret void 151 // 152 // 153 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 154 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 155 // CHECK2-NEXT: entry: 156 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 157 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 158 // CHECK2-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1) 159 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack_spmd() 160 // CHECK2-NEXT: br label [[DOTEXECUTE:%.*]] 161 // CHECK2: .execute: 162 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 163 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 164 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP1]], i32 0) 165 // CHECK2-NEXT: br label [[DOTOMP_DEINIT:%.*]] 166 // CHECK2: .omp.deinit: 167 // CHECK2-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 168 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 169 // CHECK2: .exit: 170 // CHECK2-NEXT: ret void 171 // 172 // 173 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ 174 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 175 // CHECK2-NEXT: entry: 176 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 177 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 178 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 179 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 180 // CHECK2-NEXT: call void @_Z3usev() #[[ATTR7:[0-9]+]] 181 // CHECK2-NEXT: ret void 182 // 183 // 184 // CHECK2-LABEL: define {{[^@]+}}@_Z3usev 185 // CHECK2-SAME: () #[[ATTR2:[0-9]+]] { 186 // CHECK2-NEXT: entry: 187 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 188 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 189 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 190 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP1]], i32 0) 191 // CHECK2-NEXT: ret void 192 // 193 // 194 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 195 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 196 // CHECK2-NEXT: entry: 197 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 198 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 199 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 200 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 201 // CHECK2-NEXT: call void @_Z4workv() #[[ATTR7]] 202 // CHECK2-NEXT: ret void 203 // 204 // 205 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker 206 // CHECK2-SAME: () #[[ATTR5:[0-9]+]] { 207 // CHECK2-NEXT: entry: 208 // CHECK2-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 209 // CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 210 // CHECK2-NEXT: store i8* null, i8** [[WORK_FN]], align 4 211 // CHECK2-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 212 // CHECK2-NEXT: br label [[DOTAWAIT_WORK:%.*]] 213 // CHECK2: .await.work: 214 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 215 // CHECK2-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 216 // CHECK2-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 217 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 218 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 219 // CHECK2-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 220 // CHECK2-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 221 // CHECK2: .select.workers: 222 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 223 // CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 224 // CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 225 // CHECK2: .execute.parallel: 226 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 227 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 228 // CHECK2-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 229 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 230 // CHECK2: .terminate.parallel: 231 // CHECK2-NEXT: call void @__kmpc_kernel_end_parallel() 232 // CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]] 233 // CHECK2: .barrier.parallel: 234 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 235 // CHECK2-NEXT: br label [[DOTAWAIT_WORK]] 236 // CHECK2: .exit: 237 // CHECK2-NEXT: ret void 238 // 239 // 240 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 241 // CHECK2-SAME: () #[[ATTR0]] { 242 // CHECK2-NEXT: entry: 243 // CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 244 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 245 // CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 246 // CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 247 // CHECK2-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 248 // CHECK2-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 249 // CHECK2: .worker: 250 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker() #[[ATTR4:[0-9]+]] 251 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 252 // CHECK2: .mastercheck: 253 // CHECK2-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 254 // CHECK2-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 255 // CHECK2-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 256 // CHECK2-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 257 // CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 258 // CHECK2-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 259 // CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 260 // CHECK2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 261 // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 262 // CHECK2: .master: 263 // CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 264 // CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 265 // CHECK2-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 266 // CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 267 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack() 268 // CHECK2-NEXT: call void @_Z3usev() #[[ATTR7]] 269 // CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 270 // CHECK2: .termination.notifier: 271 // CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1) 272 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 273 // CHECK2-NEXT: br label [[DOTEXIT]] 274 // CHECK2: .exit: 275 // CHECK2-NEXT: ret void 276 // 277 // 278 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 279 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 280 // CHECK3-NEXT: entry: 281 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 282 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 283 // CHECK3-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1) 284 // CHECK3-NEXT: call void @__kmpc_data_sharing_init_stack_spmd() 285 // CHECK3-NEXT: br label [[DOTEXECUTE:%.*]] 286 // CHECK3: .execute: 287 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 288 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 289 // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP1]], i32 0) 290 // CHECK3-NEXT: br label [[DOTOMP_DEINIT:%.*]] 291 // CHECK3: .omp.deinit: 292 // CHECK3-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 293 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 294 // CHECK3: .exit: 295 // CHECK3-NEXT: ret void 296 // 297 // 298 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ 299 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 300 // CHECK3-NEXT: entry: 301 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 302 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 303 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 304 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 305 // CHECK3-NEXT: call void @_Z3usev() #[[ATTR7:[0-9]+]] 306 // CHECK3-NEXT: ret void 307 // 308 // 309 // CHECK3-LABEL: define {{[^@]+}}@_Z3usev 310 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 311 // CHECK3-NEXT: entry: 312 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 313 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 314 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 315 // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP1]], i32 0) 316 // CHECK3-NEXT: ret void 317 // 318 // 319 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 320 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 321 // CHECK3-NEXT: entry: 322 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 323 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 324 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 325 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 326 // CHECK3-NEXT: call void @_Z4workv() #[[ATTR7]] 327 // CHECK3-NEXT: ret void 328 // 329 // 330 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker 331 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] { 332 // CHECK3-NEXT: entry: 333 // CHECK3-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 334 // CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 335 // CHECK3-NEXT: store i8* null, i8** [[WORK_FN]], align 4 336 // CHECK3-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 337 // CHECK3-NEXT: br label [[DOTAWAIT_WORK:%.*]] 338 // CHECK3: .await.work: 339 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 340 // CHECK3-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 341 // CHECK3-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 342 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 343 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 344 // CHECK3-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 345 // CHECK3-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 346 // CHECK3: .select.workers: 347 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 348 // CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 349 // CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 350 // CHECK3: .execute.parallel: 351 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 352 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 353 // CHECK3-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 354 // CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 355 // CHECK3: .terminate.parallel: 356 // CHECK3-NEXT: call void @__kmpc_kernel_end_parallel() 357 // CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]] 358 // CHECK3: .barrier.parallel: 359 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 360 // CHECK3-NEXT: br label [[DOTAWAIT_WORK]] 361 // CHECK3: .exit: 362 // CHECK3-NEXT: ret void 363 // 364 // 365 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 366 // CHECK3-SAME: () #[[ATTR0]] { 367 // CHECK3-NEXT: entry: 368 // CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 369 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 370 // CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 371 // CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 372 // CHECK3-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 373 // CHECK3-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 374 // CHECK3: .worker: 375 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker() #[[ATTR4:[0-9]+]] 376 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 377 // CHECK3: .mastercheck: 378 // CHECK3-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 379 // CHECK3-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 380 // CHECK3-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 381 // CHECK3-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 382 // CHECK3-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 383 // CHECK3-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 384 // CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 385 // CHECK3-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 386 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 387 // CHECK3: .master: 388 // CHECK3-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 389 // CHECK3-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 390 // CHECK3-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 391 // CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 392 // CHECK3-NEXT: call void @__kmpc_data_sharing_init_stack() 393 // CHECK3-NEXT: call void @_Z3usev() #[[ATTR7]] 394 // CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 395 // CHECK3: .termination.notifier: 396 // CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1) 397 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 398 // CHECK3-NEXT: br label [[DOTEXIT]] 399 // CHECK3: .exit: 400 // CHECK3-NEXT: ret void 401 // 402