1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test target codegen - host bc file has to be created first. 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK3 8 9 // expected-no-diagnostics 10 #ifndef HEADER 11 #define HEADER 12 13 void work(); 14 15 void use() { 16 #pragma omp parallel 17 work(); 18 } 19 20 int main() { 21 #pragma omp target parallel 22 { use(); } 23 #pragma omp target 24 { use(); } 25 } 26 27 #endif 28 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 29 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 30 // CHECK1-NEXT: entry: 31 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 32 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 33 // CHECK1-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1) 34 // CHECK1-NEXT: br label [[DOTEXECUTE:%.*]] 35 // CHECK1: .execute: 36 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 37 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 38 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP1]], i64 0) 39 // CHECK1-NEXT: br label [[DOTOMP_DEINIT:%.*]] 40 // CHECK1: .omp.deinit: 41 // CHECK1-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 42 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 43 // CHECK1: .exit: 44 // CHECK1-NEXT: ret void 45 // 46 // 47 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ 48 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 49 // CHECK1-NEXT: entry: 50 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 51 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 52 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 53 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 54 // CHECK1-NEXT: call void @_Z3usev() #[[ATTR7:[0-9]+]] 55 // CHECK1-NEXT: ret void 56 // 57 // 58 // CHECK1-LABEL: define {{[^@]+}}@_Z3usev 59 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 60 // CHECK1-NEXT: entry: 61 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 62 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 63 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 64 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP1]], i64 0) 65 // CHECK1-NEXT: ret void 66 // 67 // 68 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker 69 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 70 // CHECK1-NEXT: entry: 71 // CHECK1-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 72 // CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 73 // CHECK1-NEXT: store i8* null, i8** [[WORK_FN]], align 8 74 // CHECK1-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 75 // CHECK1-NEXT: br label [[DOTAWAIT_WORK:%.*]] 76 // CHECK1: .await.work: 77 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 78 // CHECK1-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 79 // CHECK1-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 80 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 81 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 82 // CHECK1-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 83 // CHECK1-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 84 // CHECK1: .select.workers: 85 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 86 // CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 87 // CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 88 // CHECK1: .execute.parallel: 89 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 90 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 91 // CHECK1-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 92 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 93 // CHECK1: .terminate.parallel: 94 // CHECK1-NEXT: call void @__kmpc_kernel_end_parallel() 95 // CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]] 96 // CHECK1: .barrier.parallel: 97 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 98 // CHECK1-NEXT: br label [[DOTAWAIT_WORK]] 99 // CHECK1: .exit: 100 // CHECK1-NEXT: ret void 101 // 102 // 103 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 104 // CHECK1-SAME: () #[[ATTR0]] { 105 // CHECK1-NEXT: entry: 106 // CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 107 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 108 // CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 109 // CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 110 // CHECK1-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 111 // CHECK1-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 112 // CHECK1: .worker: 113 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker() #[[ATTR3:[0-9]+]] 114 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 115 // CHECK1: .mastercheck: 116 // CHECK1-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 117 // CHECK1-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 118 // CHECK1-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 119 // CHECK1-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 120 // CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 121 // CHECK1-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 122 // CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 123 // CHECK1-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 124 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 125 // CHECK1: .master: 126 // CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 127 // CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 128 // CHECK1-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 129 // CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 130 // CHECK1-NEXT: call void @_Z3usev() #[[ATTR7]] 131 // CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 132 // CHECK1: .termination.notifier: 133 // CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1) 134 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 135 // CHECK1-NEXT: br label [[DOTEXIT]] 136 // CHECK1: .exit: 137 // CHECK1-NEXT: ret void 138 // 139 // 140 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 141 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 142 // CHECK1-NEXT: entry: 143 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 144 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 145 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 146 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 147 // CHECK1-NEXT: call void @_Z4workv() #[[ATTR7]] 148 // CHECK1-NEXT: ret void 149 // 150 // 151 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 152 // CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR4]] { 153 // CHECK1-NEXT: entry: 154 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 155 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 156 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 157 // CHECK1-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8 158 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 159 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 160 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 161 // CHECK1-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 162 // CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]] 163 // CHECK1-NEXT: ret void 164 // 165 // 166 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 167 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 168 // CHECK2-NEXT: entry: 169 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 170 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 171 // CHECK2-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1) 172 // CHECK2-NEXT: br label [[DOTEXECUTE:%.*]] 173 // CHECK2: .execute: 174 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 175 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 176 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP1]], i32 0) 177 // CHECK2-NEXT: br label [[DOTOMP_DEINIT:%.*]] 178 // CHECK2: .omp.deinit: 179 // CHECK2-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 180 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 181 // CHECK2: .exit: 182 // CHECK2-NEXT: ret void 183 // 184 // 185 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ 186 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 187 // CHECK2-NEXT: entry: 188 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 189 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 190 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 191 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 192 // CHECK2-NEXT: call void @_Z3usev() #[[ATTR7:[0-9]+]] 193 // CHECK2-NEXT: ret void 194 // 195 // 196 // CHECK2-LABEL: define {{[^@]+}}@_Z3usev 197 // CHECK2-SAME: () #[[ATTR2:[0-9]+]] { 198 // CHECK2-NEXT: entry: 199 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 200 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 201 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 202 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP1]], i32 0) 203 // CHECK2-NEXT: ret void 204 // 205 // 206 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker 207 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] { 208 // CHECK2-NEXT: entry: 209 // CHECK2-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 210 // CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 211 // CHECK2-NEXT: store i8* null, i8** [[WORK_FN]], align 4 212 // CHECK2-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 213 // CHECK2-NEXT: br label [[DOTAWAIT_WORK:%.*]] 214 // CHECK2: .await.work: 215 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 216 // CHECK2-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 217 // CHECK2-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 218 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 219 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 220 // CHECK2-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 221 // CHECK2-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 222 // CHECK2: .select.workers: 223 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 224 // CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 225 // CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 226 // CHECK2: .execute.parallel: 227 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 228 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 229 // CHECK2-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 230 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 231 // CHECK2: .terminate.parallel: 232 // CHECK2-NEXT: call void @__kmpc_kernel_end_parallel() 233 // CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]] 234 // CHECK2: .barrier.parallel: 235 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 236 // CHECK2-NEXT: br label [[DOTAWAIT_WORK]] 237 // CHECK2: .exit: 238 // CHECK2-NEXT: ret void 239 // 240 // 241 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 242 // CHECK2-SAME: () #[[ATTR0]] { 243 // CHECK2-NEXT: entry: 244 // CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 245 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 246 // CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 247 // CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 248 // CHECK2-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 249 // CHECK2-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 250 // CHECK2: .worker: 251 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker() #[[ATTR3:[0-9]+]] 252 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 253 // CHECK2: .mastercheck: 254 // CHECK2-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 255 // CHECK2-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 256 // CHECK2-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 257 // CHECK2-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 258 // CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 259 // CHECK2-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 260 // CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 261 // CHECK2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 262 // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 263 // CHECK2: .master: 264 // CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 265 // CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 266 // CHECK2-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 267 // CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 268 // CHECK2-NEXT: call void @_Z3usev() #[[ATTR7]] 269 // CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 270 // CHECK2: .termination.notifier: 271 // CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1) 272 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 273 // CHECK2-NEXT: br label [[DOTEXIT]] 274 // CHECK2: .exit: 275 // CHECK2-NEXT: ret void 276 // 277 // 278 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 279 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 280 // CHECK2-NEXT: entry: 281 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 282 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 283 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 284 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 285 // CHECK2-NEXT: call void @_Z4workv() #[[ATTR7]] 286 // CHECK2-NEXT: ret void 287 // 288 // 289 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 290 // CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR4]] { 291 // CHECK2-NEXT: entry: 292 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 293 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 294 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 295 // CHECK2-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 296 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 297 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 298 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 299 // CHECK2-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 300 // CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]] 301 // CHECK2-NEXT: ret void 302 // 303 // 304 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 305 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 306 // CHECK3-NEXT: entry: 307 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 308 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 309 // CHECK3-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1) 310 // CHECK3-NEXT: br label [[DOTEXECUTE:%.*]] 311 // CHECK3: .execute: 312 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 313 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 314 // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP1]], i32 0) 315 // CHECK3-NEXT: br label [[DOTOMP_DEINIT:%.*]] 316 // CHECK3: .omp.deinit: 317 // CHECK3-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 1) 318 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 319 // CHECK3: .exit: 320 // CHECK3-NEXT: ret void 321 // 322 // 323 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ 324 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 325 // CHECK3-NEXT: entry: 326 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 327 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 328 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 329 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 330 // CHECK3-NEXT: call void @_Z3usev() #[[ATTR7:[0-9]+]] 331 // CHECK3-NEXT: ret void 332 // 333 // 334 // CHECK3-LABEL: define {{[^@]+}}@_Z3usev 335 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 336 // CHECK3-NEXT: entry: 337 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 338 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 339 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 340 // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP1]], i32 0) 341 // CHECK3-NEXT: ret void 342 // 343 // 344 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker 345 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 346 // CHECK3-NEXT: entry: 347 // CHECK3-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 4 348 // CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 349 // CHECK3-NEXT: store i8* null, i8** [[WORK_FN]], align 4 350 // CHECK3-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 351 // CHECK3-NEXT: br label [[DOTAWAIT_WORK:%.*]] 352 // CHECK3: .await.work: 353 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 354 // CHECK3-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 355 // CHECK3-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 356 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 357 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4 358 // CHECK3-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 359 // CHECK3-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 360 // CHECK3: .select.workers: 361 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 362 // CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 363 // CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 364 // CHECK3: .execute.parallel: 365 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 366 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 367 // CHECK3-NEXT: call void [[TMP5]](i16 0, i32 [[TMP4]]) 368 // CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 369 // CHECK3: .terminate.parallel: 370 // CHECK3-NEXT: call void @__kmpc_kernel_end_parallel() 371 // CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]] 372 // CHECK3: .barrier.parallel: 373 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 374 // CHECK3-NEXT: br label [[DOTAWAIT_WORK]] 375 // CHECK3: .exit: 376 // CHECK3-NEXT: ret void 377 // 378 // 379 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 380 // CHECK3-SAME: () #[[ATTR0]] { 381 // CHECK3-NEXT: entry: 382 // CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 383 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 384 // CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 385 // CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 386 // CHECK3-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 387 // CHECK3-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 388 // CHECK3: .worker: 389 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_worker() #[[ATTR3:[0-9]+]] 390 // CHECK3-NEXT: br label [[DOTEXIT:%.*]] 391 // CHECK3: .mastercheck: 392 // CHECK3-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 393 // CHECK3-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 394 // CHECK3-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 395 // CHECK3-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 396 // CHECK3-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 397 // CHECK3-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 398 // CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 399 // CHECK3-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 400 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 401 // CHECK3: .master: 402 // CHECK3-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 403 // CHECK3-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 404 // CHECK3-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 405 // CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 406 // CHECK3-NEXT: call void @_Z3usev() #[[ATTR7]] 407 // CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 408 // CHECK3: .termination.notifier: 409 // CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1) 410 // CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 411 // CHECK3-NEXT: br label [[DOTEXIT]] 412 // CHECK3: .exit: 413 // CHECK3-NEXT: ret void 414 // 415 // 416 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 417 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 418 // CHECK3-NEXT: entry: 419 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 420 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 421 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 422 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 423 // CHECK3-NEXT: call void @_Z4workv() #[[ATTR7]] 424 // CHECK3-NEXT: ret void 425 // 426 // 427 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 428 // CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR4]] { 429 // CHECK3-NEXT: entry: 430 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 431 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 432 // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 433 // CHECK3-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 434 // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 435 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 436 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 437 // CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 438 // CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]] 439 // CHECK3-NEXT: ret void 440 // 441