1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test device global memory data sharing codegen. 3 ///==========================================================================/// 4 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1 7 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns -fopenmp-cuda-parallel-target-regions | FileCheck %s --check-prefix=CHECK2 8 9 // expected-no-diagnostics 10 11 #ifndef HEADER 12 #define HEADER 13 14 void test_ds(){ 15 #pragma omp target 16 { 17 int a = 10; 18 #pragma omp parallel 19 { 20 a = 1000; 21 } 22 int b = 100; 23 int c = 1000; 24 #pragma omp parallel private(c) 25 { 26 int *c1 = &c; 27 b = a + 10000; 28 } 29 } 30 } 31 32 #endif 33 34 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7test_dsv_l15_worker 35 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 36 // CHECK1-NEXT: entry: 37 // CHECK1-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 38 // CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 39 // CHECK1-NEXT: store i8* null, i8** [[WORK_FN]], align 8 40 // CHECK1-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 41 // CHECK1-NEXT: br label [[DOTAWAIT_WORK:%.*]] 42 // CHECK1: .await.work: 43 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 44 // CHECK1-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 45 // CHECK1-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 46 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 47 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 48 // CHECK1-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 49 // CHECK1-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 50 // CHECK1: .select.workers: 51 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 52 // CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 53 // CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 54 // CHECK1: .execute.parallel: 55 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 56 // CHECK1-NEXT: [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 8 57 // CHECK1-NEXT: [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*) 58 // CHECK1-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]] 59 // CHECK1: .execute.fn: 60 // CHECK1-NEXT: call void @__omp_outlined___wrapper(i16 0, i32 [[TMP4]]) #[[ATTR3:[0-9]+]] 61 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 62 // CHECK1: .check.next: 63 // CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[WORK_FN]], align 8 64 // CHECK1-NEXT: [[WORK_MATCH1:%.*]] = icmp eq i8* [[TMP6]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*) 65 // CHECK1-NEXT: br i1 [[WORK_MATCH1]], label [[DOTEXECUTE_FN2:%.*]], label [[DOTCHECK_NEXT3:%.*]] 66 // CHECK1: .execute.fn2: 67 // CHECK1-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR3]] 68 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL]] 69 // CHECK1: .check.next3: 70 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 71 // CHECK1-NEXT: call void [[TMP7]](i16 0, i32 [[TMP4]]) 72 // CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL]] 73 // CHECK1: .terminate.parallel: 74 // CHECK1-NEXT: call void @__kmpc_kernel_end_parallel() 75 // CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]] 76 // CHECK1: .barrier.parallel: 77 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 78 // CHECK1-NEXT: br label [[DOTAWAIT_WORK]] 79 // CHECK1: .exit: 80 // CHECK1-NEXT: ret void 81 // 82 // 83 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7test_dsv_l15 84 // CHECK1-SAME: () #[[ATTR1:[0-9]+]] { 85 // CHECK1-NEXT: entry: 86 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 87 // CHECK1-NEXT: [[C:%.*]] = alloca i32, align 4 88 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS7:%.*]] = alloca [2 x i8*], align 8 89 // CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 90 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 91 // CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 92 // CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 93 // CHECK1-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 94 // CHECK1-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 95 // CHECK1: .worker: 96 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7test_dsv_l15_worker() #[[ATTR3]] 97 // CHECK1-NEXT: br label [[DOTEXIT:%.*]] 98 // CHECK1: .mastercheck: 99 // CHECK1-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 100 // CHECK1-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 101 // CHECK1-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 102 // CHECK1-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 103 // CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 104 // CHECK1-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 105 // CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 106 // CHECK1-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 107 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 108 // CHECK1: .master: 109 // CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 110 // CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 111 // CHECK1-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 112 // CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 113 // CHECK1-NEXT: call void @__kmpc_data_sharing_init_stack() 114 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* @"_openmp_static_kernel$is_shared", align 2 115 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* @"_openmp_static_kernel$size", align 8 116 // CHECK1-NEXT: call void @__kmpc_get_team_static_memory(i16 0, i8* addrspacecast (i8 addrspace(3)* getelementptr inbounds (%"union._shared_openmp_static_memory_type_$_", %"union._shared_openmp_static_memory_type_$_" addrspace(3)* @"_openmp_shared_static_glob_rd_$_", i32 0, i32 0, i32 0) to i8*), i64 [[TMP6]], i16 [[TMP5]], i8** addrspacecast (i8* addrspace(3)* @"_openmp_kernel_static_glob_rd$ptr" to i8**)) 117 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8* addrspace(3)* @"_openmp_kernel_static_glob_rd$ptr", align 8 118 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, i8* [[TMP7]], i64 0 119 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast i8* [[TMP8]] to %struct._globalized_locals_ty* 120 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[TMP9]], i32 0, i32 0 121 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], %struct._globalized_locals_ty* [[TMP9]], i32 0, i32 1 122 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 123 // CHECK1-NEXT: store i32 10, i32* [[A]], align 4 124 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 125 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i32* [[A]] to i8* 126 // CHECK1-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8 127 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 128 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__ to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*), i8** [[TMP13]], i64 1) 129 // CHECK1-NEXT: store i32 100, i32* [[B]], align 4 130 // CHECK1-NEXT: store i32 1000, i32* [[C]], align 4 131 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS7]], i64 0, i64 0 132 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[B]] to i8* 133 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 134 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS7]], i64 0, i64 1 135 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i32* [[A]] to i8* 136 // CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8 137 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS7]] to i8** 138 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP18]], i64 2) 139 // CHECK1-NEXT: [[TMP19:%.*]] = load i16, i16* @"_openmp_static_kernel$is_shared", align 2 140 // CHECK1-NEXT: call void @__kmpc_restore_team_static_memory(i16 0, i16 [[TMP19]]) 141 // CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 142 // CHECK1: .termination.notifier: 143 // CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1) 144 // CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 145 // CHECK1-NEXT: br label [[DOTEXIT]] 146 // CHECK1: .exit: 147 // CHECK1-NEXT: ret void 148 // 149 // 150 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ 151 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { 152 // CHECK1-NEXT: entry: 153 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 154 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 155 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 156 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 157 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 158 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 159 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 160 // CHECK1-NEXT: store i32 1000, i32* [[TMP0]], align 4 161 // CHECK1-NEXT: ret void 162 // 163 // 164 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___wrapper 165 // CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { 166 // CHECK1-NEXT: entry: 167 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 168 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 169 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 170 // CHECK1-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8 171 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 172 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 173 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 174 // CHECK1-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 175 // CHECK1-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8 176 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0 177 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 178 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 8 179 // CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]] 180 // CHECK1-NEXT: ret void 181 // 182 // 183 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 184 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { 185 // CHECK1-NEXT: entry: 186 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 187 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 188 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 189 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 190 // CHECK1-NEXT: [[C:%.*]] = alloca i32, align 4 191 // CHECK1-NEXT: [[C1:%.*]] = alloca i32*, align 8 192 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 193 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 194 // CHECK1-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 195 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 196 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[B_ADDR]], align 8 197 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 198 // CHECK1-NEXT: store i32* [[C]], i32** [[C1]], align 8 199 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 200 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 10000 201 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 202 // CHECK1-NEXT: ret void 203 // 204 // 205 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 206 // CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { 207 // CHECK1-NEXT: entry: 208 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 209 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 210 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 211 // CHECK1-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8 212 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 213 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 214 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 215 // CHECK1-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 216 // CHECK1-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8 217 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0 218 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 219 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 8 220 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 1 221 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32** 222 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP7]], align 8 223 // CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]]) #[[ATTR3]] 224 // CHECK1-NEXT: ret void 225 // 226 // 227 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7test_dsv_l15_worker 228 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 229 // CHECK2-NEXT: entry: 230 // CHECK2-NEXT: [[WORK_FN:%.*]] = alloca i8*, align 8 231 // CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1 232 // CHECK2-NEXT: store i8* null, i8** [[WORK_FN]], align 8 233 // CHECK2-NEXT: store i8 0, i8* [[EXEC_STATUS]], align 1 234 // CHECK2-NEXT: br label [[DOTAWAIT_WORK:%.*]] 235 // CHECK2: .await.work: 236 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 237 // CHECK2-NEXT: [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]]) 238 // CHECK2-NEXT: [[TMP1:%.*]] = zext i1 [[TMP0]] to i8 239 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1 240 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 8 241 // CHECK2-NEXT: [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null 242 // CHECK2-NEXT: br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]] 243 // CHECK2: .select.workers: 244 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1 245 // CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0 246 // CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]] 247 // CHECK2: .execute.parallel: 248 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 249 // CHECK2-NEXT: [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 8 250 // CHECK2-NEXT: [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*) 251 // CHECK2-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]] 252 // CHECK2: .execute.fn: 253 // CHECK2-NEXT: call void @__omp_outlined___wrapper(i16 0, i32 [[TMP4]]) #[[ATTR3:[0-9]+]] 254 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]] 255 // CHECK2: .check.next: 256 // CHECK2-NEXT: [[TMP6:%.*]] = load i8*, i8** [[WORK_FN]], align 8 257 // CHECK2-NEXT: [[WORK_MATCH1:%.*]] = icmp eq i8* [[TMP6]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*) 258 // CHECK2-NEXT: br i1 [[WORK_MATCH1]], label [[DOTEXECUTE_FN2:%.*]], label [[DOTCHECK_NEXT3:%.*]] 259 // CHECK2: .execute.fn2: 260 // CHECK2-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR3]] 261 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL]] 262 // CHECK2: .check.next3: 263 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)* 264 // CHECK2-NEXT: call void [[TMP7]](i16 0, i32 [[TMP4]]) 265 // CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL]] 266 // CHECK2: .terminate.parallel: 267 // CHECK2-NEXT: call void @__kmpc_kernel_end_parallel() 268 // CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]] 269 // CHECK2: .barrier.parallel: 270 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 271 // CHECK2-NEXT: br label [[DOTAWAIT_WORK]] 272 // CHECK2: .exit: 273 // CHECK2-NEXT: ret void 274 // 275 // 276 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7test_dsv_l15 277 // CHECK2-SAME: () #[[ATTR1:[0-9]+]] { 278 // CHECK2-NEXT: entry: 279 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 280 // CHECK2-NEXT: [[C:%.*]] = alloca i32, align 4 281 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS7:%.*]] = alloca [2 x i8*], align 8 282 // CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 283 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 284 // CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 285 // CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]] 286 // CHECK2-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]] 287 // CHECK2-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]] 288 // CHECK2: .worker: 289 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7test_dsv_l15_worker() #[[ATTR3]] 290 // CHECK2-NEXT: br label [[DOTEXIT:%.*]] 291 // CHECK2: .mastercheck: 292 // CHECK2-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() 293 // CHECK2-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 294 // CHECK2-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 295 // CHECK2-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1 296 // CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1 297 // CHECK2-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 298 // CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]] 299 // CHECK2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]] 300 // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]] 301 // CHECK2: .master: 302 // CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() 303 // CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() 304 // CHECK2-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]] 305 // CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1) 306 // CHECK2-NEXT: call void @__kmpc_data_sharing_init_stack() 307 // CHECK2-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_data_sharing_push_stack(i64 8, i16 1) 308 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct._globalized_locals_ty* 309 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[TMP6]], i32 0, i32 0 310 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], %struct._globalized_locals_ty* [[TMP6]], i32 0, i32 1 311 // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 312 // CHECK2-NEXT: store i32 10, i32* [[A]], align 4 313 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 314 // CHECK2-NEXT: [[TMP9:%.*]] = bitcast i32* [[A]] to i8* 315 // CHECK2-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 8 316 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 317 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__ to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*), i8** [[TMP10]], i64 1) 318 // CHECK2-NEXT: store i32 100, i32* [[B]], align 4 319 // CHECK2-NEXT: store i32 1000, i32* [[C]], align 4 320 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS7]], i64 0, i64 0 321 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i32* [[B]] to i8* 322 // CHECK2-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8 323 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS7]], i64 0, i64 1 324 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i32* [[A]] to i8* 325 // CHECK2-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 326 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS7]] to i8** 327 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP15]], i64 2) 328 // CHECK2-NEXT: call void @__kmpc_data_sharing_pop_stack(i8* [[TMP5]]) 329 // CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]] 330 // CHECK2: .termination.notifier: 331 // CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1) 332 // CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0) 333 // CHECK2-NEXT: br label [[DOTEXIT]] 334 // CHECK2: .exit: 335 // CHECK2-NEXT: ret void 336 // 337 // 338 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ 339 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { 340 // CHECK2-NEXT: entry: 341 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 342 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 343 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 344 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 345 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 346 // CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 347 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 348 // CHECK2-NEXT: store i32 1000, i32* [[TMP0]], align 4 349 // CHECK2-NEXT: ret void 350 // 351 // 352 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined___wrapper 353 // CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { 354 // CHECK2-NEXT: entry: 355 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 356 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 357 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 358 // CHECK2-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8 359 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 360 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 361 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 362 // CHECK2-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 363 // CHECK2-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8 364 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0 365 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 366 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 8 367 // CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]] 368 // CHECK2-NEXT: ret void 369 // 370 // 371 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 372 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { 373 // CHECK2-NEXT: entry: 374 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 375 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 376 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 377 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 378 // CHECK2-NEXT: [[C:%.*]] = alloca i32, align 4 379 // CHECK2-NEXT: [[C1:%.*]] = alloca i32*, align 8 380 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 381 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 382 // CHECK2-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 383 // CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 384 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[B_ADDR]], align 8 385 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 386 // CHECK2-NEXT: store i32* [[C]], i32** [[C1]], align 8 387 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 388 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 10000 389 // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 390 // CHECK2-NEXT: ret void 391 // 392 // 393 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper 394 // CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { 395 // CHECK2-NEXT: entry: 396 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 397 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 398 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 399 // CHECK2-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8 400 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 401 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 402 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 403 // CHECK2-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) 404 // CHECK2-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8 405 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0 406 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 407 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 8 408 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 1 409 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32** 410 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP7]], align 8 411 // CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]]) #[[ATTR3]] 412 // CHECK2-NEXT: ret void 413 // 414