1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
8 
9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
15 
16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
19 
20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
23 
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27 
28 template <typename T>
29 T tmain() {
30   T t_var = T();
31   T vec[] = {1, 2};
32 #pragma omp target
33 #pragma omp teams
34 #pragma omp distribute simd reduction(+: t_var)
35   for (int i = 0; i < 2; ++i) {
36     t_var += (T) i;
37   }
38   return T();
39 }
40 
41 int main() {
42   static int sivar;
43 #ifdef LAMBDA
44   [&]() {
45 #pragma omp target
46 #pragma omp teams
47 #pragma omp distribute simd reduction(+: sivar)
48   for (int i = 0; i < 2; ++i) {
49 
50     // Skip global and bound tid vars
51 
52 
53     sivar += i;
54 
55     [&]() {
56 
57       sivar += 4;
58 
59     }();
60   }
61   }();
62   return 0;
63 #else
64 #pragma omp target
65 #pragma omp teams
66 #pragma omp distribute simd reduction(+: sivar)
67   for (int i = 0; i < 2; ++i) {
68     sivar += i;
69   }
70   return tmain<int>();
71 #endif
72 }
73 
74 
75 
76 // Skip global and bound tid vars
77 
78 
79 
80 
81 // Skip global and bound tid vars
82 
83 
84 #endif
85 // CHECK1-LABEL: define {{[^@]+}}@main
86 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
87 // CHECK1-NEXT:  entry:
88 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
89 // CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
90 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
91 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
92 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
93 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
94 // CHECK1-NEXT:    store i32 0, i32* [[RETVAL]], align 4
95 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
96 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
97 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
98 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
99 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
100 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
101 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP3]], align 8
102 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
103 // CHECK1-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
104 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP5]], align 8
105 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
106 // CHECK1-NEXT:    store i8* null, i8** [[TMP6]], align 8
107 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
108 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
109 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
110 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
111 // CHECK1-NEXT:    store i32 1, i32* [[TMP9]], align 4
112 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
113 // CHECK1-NEXT:    store i32 1, i32* [[TMP10]], align 4
114 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
115 // CHECK1-NEXT:    store i8** [[TMP7]], i8*** [[TMP11]], align 8
116 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
117 // CHECK1-NEXT:    store i8** [[TMP8]], i8*** [[TMP12]], align 8
118 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
119 // CHECK1-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP13]], align 8
120 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
121 // CHECK1-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP14]], align 8
122 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
123 // CHECK1-NEXT:    store i8** null, i8*** [[TMP15]], align 8
124 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
125 // CHECK1-NEXT:    store i8** null, i8*** [[TMP16]], align 8
126 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
127 // CHECK1-NEXT:    store i64 2, i64* [[TMP17]], align 8
128 // CHECK1-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
129 // CHECK1-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
130 // CHECK1-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
131 // CHECK1:       omp_offload.failed:
132 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i64 [[TMP1]]) #[[ATTR2:[0-9]+]]
133 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
134 // CHECK1:       omp_offload.cont:
135 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
136 // CHECK1-NEXT:    ret i32 [[CALL]]
137 //
138 //
139 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64
140 // CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {
141 // CHECK1-NEXT:  entry:
142 // CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
143 // CHECK1-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
144 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
145 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]])
146 // CHECK1-NEXT:    ret void
147 //
148 //
149 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
150 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
151 // CHECK1-NEXT:  entry:
152 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
153 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
154 // CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
155 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
156 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
157 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
158 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
159 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
160 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
161 // CHECK1-NEXT:    [[SIVAR1:%.*]] = alloca i32, align 4
162 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
163 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
164 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
165 // CHECK1-NEXT:    store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
166 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
167 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
168 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
169 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
170 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
171 // CHECK1-NEXT:    store i32 0, i32* [[SIVAR1]], align 4
172 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
173 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
174 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
175 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
176 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
177 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
178 // CHECK1:       cond.true:
179 // CHECK1-NEXT:    br label [[COND_END:%.*]]
180 // CHECK1:       cond.false:
181 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
182 // CHECK1-NEXT:    br label [[COND_END]]
183 // CHECK1:       cond.end:
184 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
185 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
186 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
187 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
188 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
189 // CHECK1:       omp.inner.for.cond:
190 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
191 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5
192 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
193 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
194 // CHECK1:       omp.inner.for.body:
195 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
196 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
197 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
198 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
199 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
200 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !5
201 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
202 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5
203 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
204 // CHECK1:       omp.body.continue:
205 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
206 // CHECK1:       omp.inner.for.inc:
207 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
208 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
209 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
210 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
211 // CHECK1:       omp.inner.for.end:
212 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
213 // CHECK1:       omp.loop.exit:
214 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
215 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
216 // CHECK1-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
217 // CHECK1-NEXT:    br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
218 // CHECK1:       .omp.final.then:
219 // CHECK1-NEXT:    store i32 2, i32* [[I]], align 4
220 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
221 // CHECK1:       .omp.final.done:
222 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[TMP0]], align 4
223 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[SIVAR1]], align 4
224 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
225 // CHECK1-NEXT:    store i32 [[ADD5]], i32* [[TMP0]], align 4
226 // CHECK1-NEXT:    ret void
227 //
228 //
229 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
230 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] comdat {
231 // CHECK1-NEXT:  entry:
232 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
233 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
234 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
235 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
236 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
237 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
238 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
239 // CHECK1-NEXT:    store i32 0, i32* [[T_VAR]], align 4
240 // CHECK1-NEXT:    [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
241 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
242 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4
243 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
244 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV]], align 4
245 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
246 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
247 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64*
248 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP4]], align 8
249 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
250 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
251 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP6]], align 8
252 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
253 // CHECK1-NEXT:    store i8* null, i8** [[TMP7]], align 8
254 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
255 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
256 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
257 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
258 // CHECK1-NEXT:    store i32 1, i32* [[TMP10]], align 4
259 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
260 // CHECK1-NEXT:    store i32 1, i32* [[TMP11]], align 4
261 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
262 // CHECK1-NEXT:    store i8** [[TMP8]], i8*** [[TMP12]], align 8
263 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
264 // CHECK1-NEXT:    store i8** [[TMP9]], i8*** [[TMP13]], align 8
265 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
266 // CHECK1-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64** [[TMP14]], align 8
267 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
268 // CHECK1-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i64** [[TMP15]], align 8
269 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
270 // CHECK1-NEXT:    store i8** null, i8*** [[TMP16]], align 8
271 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
272 // CHECK1-NEXT:    store i8** null, i8*** [[TMP17]], align 8
273 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
274 // CHECK1-NEXT:    store i64 2, i64* [[TMP18]], align 8
275 // CHECK1-NEXT:    [[TMP19:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
276 // CHECK1-NEXT:    [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
277 // CHECK1-NEXT:    br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
278 // CHECK1:       omp_offload.failed:
279 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP2]]) #[[ATTR2]]
280 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
281 // CHECK1:       omp_offload.cont:
282 // CHECK1-NEXT:    ret i32 0
283 //
284 //
285 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32
286 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] {
287 // CHECK1-NEXT:  entry:
288 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
289 // CHECK1-NEXT:    store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
290 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
291 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]])
292 // CHECK1-NEXT:    ret void
293 //
294 //
295 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
296 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
297 // CHECK1-NEXT:  entry:
298 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
299 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
300 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
301 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
302 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
303 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
304 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
305 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
306 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
307 // CHECK1-NEXT:    [[T_VAR1:%.*]] = alloca i32, align 4
308 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
309 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
310 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
311 // CHECK1-NEXT:    store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
312 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
313 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
314 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
315 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
316 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
317 // CHECK1-NEXT:    store i32 0, i32* [[T_VAR1]], align 4
318 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
319 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
320 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
321 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
322 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
323 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
324 // CHECK1:       cond.true:
325 // CHECK1-NEXT:    br label [[COND_END:%.*]]
326 // CHECK1:       cond.false:
327 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
328 // CHECK1-NEXT:    br label [[COND_END]]
329 // CHECK1:       cond.end:
330 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
331 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
332 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
333 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
334 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
335 // CHECK1:       omp.inner.for.cond:
336 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
337 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
338 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
339 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
340 // CHECK1:       omp.inner.for.body:
341 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
342 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
343 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
344 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
345 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
346 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !11
347 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
348 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11
349 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
350 // CHECK1:       omp.body.continue:
351 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
352 // CHECK1:       omp.inner.for.inc:
353 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
354 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
355 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
356 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
357 // CHECK1:       omp.inner.for.end:
358 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
359 // CHECK1:       omp.loop.exit:
360 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
361 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
362 // CHECK1-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
363 // CHECK1-NEXT:    br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
364 // CHECK1:       .omp.final.then:
365 // CHECK1-NEXT:    store i32 2, i32* [[I]], align 4
366 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
367 // CHECK1:       .omp.final.done:
368 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[TMP0]], align 4
369 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[T_VAR1]], align 4
370 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
371 // CHECK1-NEXT:    store i32 [[ADD5]], i32* [[TMP0]], align 4
372 // CHECK1-NEXT:    ret void
373 //
374 //
375 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
376 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] {
377 // CHECK1-NEXT:  entry:
378 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
379 // CHECK1-NEXT:    ret void
380 //
381 //
382 // CHECK3-LABEL: define {{[^@]+}}@main
383 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
384 // CHECK3-NEXT:  entry:
385 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
386 // CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 4
387 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
388 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
389 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
390 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
391 // CHECK3-NEXT:    store i32 0, i32* [[RETVAL]], align 4
392 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
393 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[SIVAR_CASTED]], align 4
394 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
395 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
396 // CHECK3-NEXT:    [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
397 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP3]], align 4
398 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
399 // CHECK3-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
400 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP5]], align 4
401 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
402 // CHECK3-NEXT:    store i8* null, i8** [[TMP6]], align 4
403 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
404 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
405 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
406 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
407 // CHECK3-NEXT:    store i32 1, i32* [[TMP9]], align 4
408 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
409 // CHECK3-NEXT:    store i32 1, i32* [[TMP10]], align 4
410 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
411 // CHECK3-NEXT:    store i8** [[TMP7]], i8*** [[TMP11]], align 4
412 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
413 // CHECK3-NEXT:    store i8** [[TMP8]], i8*** [[TMP12]], align 4
414 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
415 // CHECK3-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP13]], align 4
416 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
417 // CHECK3-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP14]], align 4
418 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
419 // CHECK3-NEXT:    store i8** null, i8*** [[TMP15]], align 4
420 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
421 // CHECK3-NEXT:    store i8** null, i8*** [[TMP16]], align 4
422 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
423 // CHECK3-NEXT:    store i64 2, i64* [[TMP17]], align 8
424 // CHECK3-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
425 // CHECK3-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
426 // CHECK3-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
427 // CHECK3:       omp_offload.failed:
428 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i32 [[TMP1]]) #[[ATTR2:[0-9]+]]
429 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
430 // CHECK3:       omp_offload.cont:
431 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
432 // CHECK3-NEXT:    ret i32 [[CALL]]
433 //
434 //
435 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64
436 // CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {
437 // CHECK3-NEXT:  entry:
438 // CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4
439 // CHECK3-NEXT:    store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
440 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[SIVAR_ADDR]])
441 // CHECK3-NEXT:    ret void
442 //
443 //
444 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
445 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
446 // CHECK3-NEXT:  entry:
447 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
448 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
449 // CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32*, align 4
450 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
451 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
452 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
453 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
454 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
455 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
456 // CHECK3-NEXT:    [[SIVAR1:%.*]] = alloca i32, align 4
457 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
458 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
459 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
460 // CHECK3-NEXT:    store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4
461 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4
462 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
463 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
464 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
465 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
466 // CHECK3-NEXT:    store i32 0, i32* [[SIVAR1]], align 4
467 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
468 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
469 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
470 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
471 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
472 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
473 // CHECK3:       cond.true:
474 // CHECK3-NEXT:    br label [[COND_END:%.*]]
475 // CHECK3:       cond.false:
476 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
477 // CHECK3-NEXT:    br label [[COND_END]]
478 // CHECK3:       cond.end:
479 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
480 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
481 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
482 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
483 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
484 // CHECK3:       omp.inner.for.cond:
485 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
486 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
487 // CHECK3-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
488 // CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
489 // CHECK3:       omp.inner.for.body:
490 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
491 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
492 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
493 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
494 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
495 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !6
496 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
497 // CHECK3-NEXT:    store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6
498 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
499 // CHECK3:       omp.body.continue:
500 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
501 // CHECK3:       omp.inner.for.inc:
502 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
503 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
504 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
505 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
506 // CHECK3:       omp.inner.for.end:
507 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
508 // CHECK3:       omp.loop.exit:
509 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
510 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
511 // CHECK3-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
512 // CHECK3-NEXT:    br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
513 // CHECK3:       .omp.final.then:
514 // CHECK3-NEXT:    store i32 2, i32* [[I]], align 4
515 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
516 // CHECK3:       .omp.final.done:
517 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[TMP0]], align 4
518 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[SIVAR1]], align 4
519 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
520 // CHECK3-NEXT:    store i32 [[ADD5]], i32* [[TMP0]], align 4
521 // CHECK3-NEXT:    ret void
522 //
523 //
524 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
525 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] comdat {
526 // CHECK3-NEXT:  entry:
527 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
528 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
529 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
530 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
531 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
532 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
533 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
534 // CHECK3-NEXT:    store i32 0, i32* [[T_VAR]], align 4
535 // CHECK3-NEXT:    [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
536 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
537 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4
538 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4
539 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
540 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
541 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32*
542 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[TMP4]], align 4
543 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
544 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
545 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[TMP6]], align 4
546 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
547 // CHECK3-NEXT:    store i8* null, i8** [[TMP7]], align 4
548 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
549 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
550 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
551 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
552 // CHECK3-NEXT:    store i32 1, i32* [[TMP10]], align 4
553 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
554 // CHECK3-NEXT:    store i32 1, i32* [[TMP11]], align 4
555 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
556 // CHECK3-NEXT:    store i8** [[TMP8]], i8*** [[TMP12]], align 4
557 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
558 // CHECK3-NEXT:    store i8** [[TMP9]], i8*** [[TMP13]], align 4
559 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
560 // CHECK3-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64** [[TMP14]], align 4
561 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
562 // CHECK3-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i64** [[TMP15]], align 4
563 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
564 // CHECK3-NEXT:    store i8** null, i8*** [[TMP16]], align 4
565 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
566 // CHECK3-NEXT:    store i8** null, i8*** [[TMP17]], align 4
567 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
568 // CHECK3-NEXT:    store i64 2, i64* [[TMP18]], align 8
569 // CHECK3-NEXT:    [[TMP19:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
570 // CHECK3-NEXT:    [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
571 // CHECK3-NEXT:    br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
572 // CHECK3:       omp_offload.failed:
573 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP2]]) #[[ATTR2]]
574 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
575 // CHECK3:       omp_offload.cont:
576 // CHECK3-NEXT:    ret i32 0
577 //
578 //
579 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32
580 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] {
581 // CHECK3-NEXT:  entry:
582 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
583 // CHECK3-NEXT:    store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
584 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]])
585 // CHECK3-NEXT:    ret void
586 //
587 //
588 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
589 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
590 // CHECK3-NEXT:  entry:
591 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
592 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
593 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32*, align 4
594 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
595 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
596 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
597 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
598 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
599 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
600 // CHECK3-NEXT:    [[T_VAR1:%.*]] = alloca i32, align 4
601 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
602 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
603 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
604 // CHECK3-NEXT:    store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4
605 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4
606 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
607 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
608 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
609 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
610 // CHECK3-NEXT:    store i32 0, i32* [[T_VAR1]], align 4
611 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
612 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
613 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
614 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
615 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
616 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
617 // CHECK3:       cond.true:
618 // CHECK3-NEXT:    br label [[COND_END:%.*]]
619 // CHECK3:       cond.false:
620 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
621 // CHECK3-NEXT:    br label [[COND_END]]
622 // CHECK3:       cond.end:
623 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
624 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
625 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
626 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
627 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
628 // CHECK3:       omp.inner.for.cond:
629 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
630 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
631 // CHECK3-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
632 // CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
633 // CHECK3:       omp.inner.for.body:
634 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
635 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
636 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
637 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
638 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12
639 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !12
640 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
641 // CHECK3-NEXT:    store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12
642 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
643 // CHECK3:       omp.body.continue:
644 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
645 // CHECK3:       omp.inner.for.inc:
646 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
647 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
648 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
649 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
650 // CHECK3:       omp.inner.for.end:
651 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
652 // CHECK3:       omp.loop.exit:
653 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
654 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
655 // CHECK3-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
656 // CHECK3-NEXT:    br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
657 // CHECK3:       .omp.final.then:
658 // CHECK3-NEXT:    store i32 2, i32* [[I]], align 4
659 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
660 // CHECK3:       .omp.final.done:
661 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[TMP0]], align 4
662 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[T_VAR1]], align 4
663 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
664 // CHECK3-NEXT:    store i32 [[ADD5]], i32* [[TMP0]], align 4
665 // CHECK3-NEXT:    ret void
666 //
667 //
668 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
669 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] {
670 // CHECK3-NEXT:  entry:
671 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
672 // CHECK3-NEXT:    ret void
673 //
674 //
675 // CHECK5-LABEL: define {{[^@]+}}@main
676 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
677 // CHECK5-NEXT:  entry:
678 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
679 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
680 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
681 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
682 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
683 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
684 // CHECK5-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
685 // CHECK5-NEXT:    store i32 0, i32* [[RETVAL]], align 4
686 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
687 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
688 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
689 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
690 // CHECK5-NEXT:    store i32 0, i32* [[SIVAR]], align 4
691 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
692 // CHECK5:       omp.inner.for.cond:
693 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
694 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
695 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
696 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
697 // CHECK5:       omp.inner.for.body:
698 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
699 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
700 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
701 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
702 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
703 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2
704 // CHECK5-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
705 // CHECK5-NEXT:    store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !2
706 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
707 // CHECK5:       omp.body.continue:
708 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
709 // CHECK5:       omp.inner.for.inc:
710 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
711 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
712 // CHECK5-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
713 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
714 // CHECK5:       omp.inner.for.end:
715 // CHECK5-NEXT:    store i32 2, i32* [[I]], align 4
716 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
717 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4
718 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]
719 // CHECK5-NEXT:    store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4
720 // CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
721 // CHECK5-NEXT:    ret i32 [[CALL]]
722 //
723 //
724 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
725 // CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat {
726 // CHECK5-NEXT:  entry:
727 // CHECK5-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
728 // CHECK5-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
729 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
730 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
731 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
732 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
733 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
734 // CHECK5-NEXT:    [[T_VAR1:%.*]] = alloca i32, align 4
735 // CHECK5-NEXT:    store i32 0, i32* [[T_VAR]], align 4
736 // CHECK5-NEXT:    [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
737 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
738 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
739 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
740 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
741 // CHECK5-NEXT:    store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
742 // CHECK5-NEXT:    store i32 0, i32* [[T_VAR1]], align 4
743 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
744 // CHECK5:       omp.inner.for.cond:
745 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
746 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
747 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
748 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
749 // CHECK5:       omp.inner.for.body:
750 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
751 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
752 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
753 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
754 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
755 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !6
756 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
757 // CHECK5-NEXT:    store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !6
758 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
759 // CHECK5:       omp.body.continue:
760 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
761 // CHECK5:       omp.inner.for.inc:
762 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
763 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1
764 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
765 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
766 // CHECK5:       omp.inner.for.end:
767 // CHECK5-NEXT:    store i32 2, i32* [[I]], align 4
768 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
769 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4
770 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
771 // CHECK5-NEXT:    store i32 [[ADD4]], i32* [[T_VAR]], align 4
772 // CHECK5-NEXT:    ret i32 0
773 //
774 //
775 // CHECK7-LABEL: define {{[^@]+}}@main
776 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
777 // CHECK7-NEXT:  entry:
778 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
779 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
780 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
781 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
782 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
783 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
784 // CHECK7-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
785 // CHECK7-NEXT:    store i32 0, i32* [[RETVAL]], align 4
786 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
787 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
788 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
789 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
790 // CHECK7-NEXT:    store i32 0, i32* [[SIVAR]], align 4
791 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
792 // CHECK7:       omp.inner.for.cond:
793 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
794 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
795 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
796 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
797 // CHECK7:       omp.inner.for.body:
798 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
799 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
800 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
801 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
802 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
803 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3
804 // CHECK7-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
805 // CHECK7-NEXT:    store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !3
806 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
807 // CHECK7:       omp.body.continue:
808 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
809 // CHECK7:       omp.inner.for.inc:
810 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
811 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
812 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
813 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
814 // CHECK7:       omp.inner.for.end:
815 // CHECK7-NEXT:    store i32 2, i32* [[I]], align 4
816 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
817 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4
818 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]
819 // CHECK7-NEXT:    store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4
820 // CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
821 // CHECK7-NEXT:    ret i32 [[CALL]]
822 //
823 //
824 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
825 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat {
826 // CHECK7-NEXT:  entry:
827 // CHECK7-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
828 // CHECK7-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
829 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
830 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
831 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
832 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
833 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
834 // CHECK7-NEXT:    [[T_VAR1:%.*]] = alloca i32, align 4
835 // CHECK7-NEXT:    store i32 0, i32* [[T_VAR]], align 4
836 // CHECK7-NEXT:    [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
837 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
838 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
839 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
840 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
841 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
842 // CHECK7-NEXT:    store i32 0, i32* [[T_VAR1]], align 4
843 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
844 // CHECK7:       omp.inner.for.cond:
845 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
846 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
847 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
848 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
849 // CHECK7:       omp.inner.for.body:
850 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
851 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
852 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
853 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
854 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
855 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !7
856 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
857 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !7
858 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
859 // CHECK7:       omp.body.continue:
860 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
861 // CHECK7:       omp.inner.for.inc:
862 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
863 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1
864 // CHECK7-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
865 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
866 // CHECK7:       omp.inner.for.end:
867 // CHECK7-NEXT:    store i32 2, i32* [[I]], align 4
868 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
869 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4
870 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
871 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[T_VAR]], align 4
872 // CHECK7-NEXT:    ret i32 0
873 //
874 //
875 // CHECK9-LABEL: define {{[^@]+}}@main
876 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
877 // CHECK9-NEXT:  entry:
878 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
879 // CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
880 // CHECK9-NEXT:    store i32 0, i32* [[RETVAL]], align 4
881 // CHECK9-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
882 // CHECK9-NEXT:    ret i32 0
883 //
884 //
885 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45
886 // CHECK9-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
887 // CHECK9-NEXT:  entry:
888 // CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
889 // CHECK9-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
890 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
891 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]])
892 // CHECK9-NEXT:    ret void
893 //
894 //
895 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
896 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] {
897 // CHECK9-NEXT:  entry:
898 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
899 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
900 // CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
901 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
902 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
903 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
904 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
905 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
906 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
907 // CHECK9-NEXT:    [[SIVAR1:%.*]] = alloca i32, align 4
908 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
909 // CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
910 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
911 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
912 // CHECK9-NEXT:    store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
913 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
914 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
915 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
916 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
917 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
918 // CHECK9-NEXT:    store i32 0, i32* [[SIVAR1]], align 4
919 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
920 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
921 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
922 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
923 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
924 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
925 // CHECK9:       cond.true:
926 // CHECK9-NEXT:    br label [[COND_END:%.*]]
927 // CHECK9:       cond.false:
928 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
929 // CHECK9-NEXT:    br label [[COND_END]]
930 // CHECK9:       cond.end:
931 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
932 // CHECK9-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
933 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
934 // CHECK9-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
935 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
936 // CHECK9:       omp.inner.for.cond:
937 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
938 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4
939 // CHECK9-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
940 // CHECK9-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
941 // CHECK9:       omp.inner.for.body:
942 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
943 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
944 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
945 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
946 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4
947 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !4
948 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
949 // CHECK9-NEXT:    store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4
950 // CHECK9-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
951 // CHECK9-NEXT:    store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4
952 // CHECK9-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4
953 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
954 // CHECK9:       omp.body.continue:
955 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
956 // CHECK9:       omp.inner.for.inc:
957 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
958 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
959 // CHECK9-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
960 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
961 // CHECK9:       omp.inner.for.end:
962 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
963 // CHECK9:       omp.loop.exit:
964 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
965 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
966 // CHECK9-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
967 // CHECK9-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
968 // CHECK9:       .omp.final.then:
969 // CHECK9-NEXT:    store i32 2, i32* [[I]], align 4
970 // CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]
971 // CHECK9:       .omp.final.done:
972 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, i32* [[TMP0]], align 4
973 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, i32* [[SIVAR1]], align 4
974 // CHECK9-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
975 // CHECK9-NEXT:    store i32 [[ADD5]], i32* [[TMP0]], align 4
976 // CHECK9-NEXT:    ret void
977 //
978 //
979 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
980 // CHECK9-SAME: () #[[ATTR4:[0-9]+]] {
981 // CHECK9-NEXT:  entry:
982 // CHECK9-NEXT:    call void @__tgt_register_requires(i64 1)
983 // CHECK9-NEXT:    ret void
984 //
985 //
986 // CHECK11-LABEL: define {{[^@]+}}@main
987 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
988 // CHECK11-NEXT:  entry:
989 // CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
990 // CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
991 // CHECK11-NEXT:    store i32 0, i32* [[RETVAL]], align 4
992 // CHECK11-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
993 // CHECK11-NEXT:    ret i32 0
994 //
995