1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 template <typename T> 29 T tmain() { 30 T t_var = T(); 31 T vec[] = {1, 2}; 32 #pragma omp target 33 #pragma omp teams 34 #pragma omp distribute simd reduction(+: t_var) 35 for (int i = 0; i < 2; ++i) { 36 t_var += (T) i; 37 } 38 return T(); 39 } 40 41 int main() { 42 static int sivar; 43 #ifdef LAMBDA 44 [&]() { 45 #pragma omp target 46 #pragma omp teams 47 #pragma omp distribute simd reduction(+: sivar) 48 for (int i = 0; i < 2; ++i) { 49 50 // Skip global and bound tid vars 51 52 53 sivar += i; 54 55 [&]() { 56 57 sivar += 4; 58 59 }(); 60 } 61 }(); 62 return 0; 63 #else 64 #pragma omp target 65 #pragma omp teams 66 #pragma omp distribute simd reduction(+: sivar) 67 for (int i = 0; i < 2; ++i) { 68 sivar += i; 69 } 70 return tmain<int>(); 71 #endif 72 } 73 74 75 76 // Skip global and bound tid vars 77 78 79 80 81 // Skip global and bound tid vars 82 83 84 #endif 85 // CHECK1-LABEL: define {{[^@]+}}@main 86 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 87 // CHECK1-NEXT: entry: 88 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 89 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 90 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 91 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 92 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 93 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 94 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 95 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 96 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 97 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 98 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 99 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 100 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 101 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 102 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 103 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 104 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 105 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 106 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 107 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 108 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 109 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 110 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 111 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 112 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 113 // CHECK1: omp_offload.failed: 114 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] 115 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 116 // CHECK1: omp_offload.cont: 117 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 118 // CHECK1-NEXT: ret i32 [[CALL]] 119 // 120 // 121 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 122 // CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 123 // CHECK1-NEXT: entry: 124 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 125 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 126 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 127 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 128 // CHECK1-NEXT: ret void 129 // 130 // 131 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 132 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 133 // CHECK1-NEXT: entry: 134 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 135 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 136 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 137 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 138 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 139 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 140 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 141 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 142 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 143 // CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 144 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 145 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 146 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 147 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 148 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 149 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 150 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 151 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 152 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 153 // CHECK1-NEXT: store i32 0, i32* [[SIVAR1]], align 4 154 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 155 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 156 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 157 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 158 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 159 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 160 // CHECK1: cond.true: 161 // CHECK1-NEXT: br label [[COND_END:%.*]] 162 // CHECK1: cond.false: 163 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 164 // CHECK1-NEXT: br label [[COND_END]] 165 // CHECK1: cond.end: 166 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 167 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 168 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 169 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 170 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 171 // CHECK1: omp.inner.for.cond: 172 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 173 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 174 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 175 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 176 // CHECK1: omp.inner.for.body: 177 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 178 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 179 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 180 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 181 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 182 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !5 183 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 184 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5 185 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 186 // CHECK1: omp.body.continue: 187 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 188 // CHECK1: omp.inner.for.inc: 189 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 190 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 191 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 192 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 193 // CHECK1: omp.inner.for.end: 194 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 195 // CHECK1: omp.loop.exit: 196 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 197 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 198 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 199 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 200 // CHECK1: .omp.final.then: 201 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 202 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 203 // CHECK1: .omp.final.done: 204 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP0]], align 4 205 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[SIVAR1]], align 4 206 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] 207 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 208 // CHECK1-NEXT: ret void 209 // 210 // 211 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 212 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] comdat { 213 // CHECK1-NEXT: entry: 214 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 215 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 216 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 217 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 218 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 219 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 220 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 221 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 222 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 223 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 224 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 225 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 226 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 227 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 228 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 229 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* 230 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 231 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 232 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 233 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 234 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 235 // CHECK1-NEXT: store i8* null, i8** [[TMP7]], align 8 236 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 237 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 238 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 239 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 240 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 241 // CHECK1-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 242 // CHECK1: omp_offload.failed: 243 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP2]]) #[[ATTR2]] 244 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 245 // CHECK1: omp_offload.cont: 246 // CHECK1-NEXT: ret i32 0 247 // 248 // 249 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 250 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { 251 // CHECK1-NEXT: entry: 252 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 253 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 254 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 255 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) 256 // CHECK1-NEXT: ret void 257 // 258 // 259 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 260 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 261 // CHECK1-NEXT: entry: 262 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 263 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 264 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 265 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 266 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 267 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 268 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 269 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 270 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 271 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 272 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 273 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 274 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 275 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 276 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 277 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 278 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 279 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 280 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 281 // CHECK1-NEXT: store i32 0, i32* [[T_VAR1]], align 4 282 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 283 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 284 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 285 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 286 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 287 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 288 // CHECK1: cond.true: 289 // CHECK1-NEXT: br label [[COND_END:%.*]] 290 // CHECK1: cond.false: 291 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 292 // CHECK1-NEXT: br label [[COND_END]] 293 // CHECK1: cond.end: 294 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 295 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 296 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 297 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 298 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 299 // CHECK1: omp.inner.for.cond: 300 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 301 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 302 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 303 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 304 // CHECK1: omp.inner.for.body: 305 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 306 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 307 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 308 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 309 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 310 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !11 311 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 312 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11 313 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 314 // CHECK1: omp.body.continue: 315 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 316 // CHECK1: omp.inner.for.inc: 317 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 318 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 319 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 320 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 321 // CHECK1: omp.inner.for.end: 322 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 323 // CHECK1: omp.loop.exit: 324 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 325 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 326 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 327 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 328 // CHECK1: .omp.final.then: 329 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 330 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 331 // CHECK1: .omp.final.done: 332 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP0]], align 4 333 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR1]], align 4 334 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] 335 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 336 // CHECK1-NEXT: ret void 337 // 338 // 339 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 340 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] { 341 // CHECK1-NEXT: entry: 342 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 343 // CHECK1-NEXT: ret void 344 // 345 // 346 // CHECK3-LABEL: define {{[^@]+}}@main 347 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 348 // CHECK3-NEXT: entry: 349 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 350 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 351 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 352 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 353 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 354 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 355 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 356 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 357 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[SIVAR_CASTED]], align 4 358 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 359 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 360 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 361 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 362 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 363 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 364 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 365 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 366 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4 367 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 368 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 369 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 370 // CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 371 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 372 // CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 373 // CHECK3: omp_offload.failed: 374 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] 375 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 376 // CHECK3: omp_offload.cont: 377 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 378 // CHECK3-NEXT: ret i32 [[CALL]] 379 // 380 // 381 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 382 // CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 383 // CHECK3-NEXT: entry: 384 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 385 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 386 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[SIVAR_ADDR]]) 387 // CHECK3-NEXT: ret void 388 // 389 // 390 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 391 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 392 // CHECK3-NEXT: entry: 393 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 394 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 395 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 396 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 397 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 398 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 399 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 400 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 401 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 402 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 403 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 404 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 405 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 406 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 407 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 408 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 409 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 410 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 411 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 412 // CHECK3-NEXT: store i32 0, i32* [[SIVAR1]], align 4 413 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 414 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 415 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 416 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 417 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 418 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 419 // CHECK3: cond.true: 420 // CHECK3-NEXT: br label [[COND_END:%.*]] 421 // CHECK3: cond.false: 422 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 423 // CHECK3-NEXT: br label [[COND_END]] 424 // CHECK3: cond.end: 425 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 426 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 427 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 428 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 429 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 430 // CHECK3: omp.inner.for.cond: 431 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 432 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 433 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 434 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 435 // CHECK3: omp.inner.for.body: 436 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 437 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 438 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 439 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 440 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 441 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !6 442 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 443 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6 444 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 445 // CHECK3: omp.body.continue: 446 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 447 // CHECK3: omp.inner.for.inc: 448 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 449 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 450 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 451 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 452 // CHECK3: omp.inner.for.end: 453 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 454 // CHECK3: omp.loop.exit: 455 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 456 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 457 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 458 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 459 // CHECK3: .omp.final.then: 460 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 461 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 462 // CHECK3: .omp.final.done: 463 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP0]], align 4 464 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[SIVAR1]], align 4 465 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] 466 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 467 // CHECK3-NEXT: ret void 468 // 469 // 470 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 471 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] comdat { 472 // CHECK3-NEXT: entry: 473 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 474 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 475 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 476 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 477 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 478 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 479 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 480 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 481 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 482 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 483 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 484 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 485 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 486 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 487 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 488 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 489 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 490 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 491 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 492 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 493 // CHECK3-NEXT: store i8* null, i8** [[TMP7]], align 4 494 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 495 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 496 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 497 // CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 498 // CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 499 // CHECK3-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 500 // CHECK3: omp_offload.failed: 501 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP2]]) #[[ATTR2]] 502 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 503 // CHECK3: omp_offload.cont: 504 // CHECK3-NEXT: ret i32 0 505 // 506 // 507 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 508 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { 509 // CHECK3-NEXT: entry: 510 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 511 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 512 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]]) 513 // CHECK3-NEXT: ret void 514 // 515 // 516 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 517 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 518 // CHECK3-NEXT: entry: 519 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 520 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 521 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 522 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 523 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 524 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 525 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 526 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 527 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 528 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 529 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 530 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 531 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 532 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 533 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 534 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 535 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 536 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 537 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 538 // CHECK3-NEXT: store i32 0, i32* [[T_VAR1]], align 4 539 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 540 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 541 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 542 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 543 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 544 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 545 // CHECK3: cond.true: 546 // CHECK3-NEXT: br label [[COND_END:%.*]] 547 // CHECK3: cond.false: 548 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 549 // CHECK3-NEXT: br label [[COND_END]] 550 // CHECK3: cond.end: 551 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 552 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 553 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 554 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 555 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 556 // CHECK3: omp.inner.for.cond: 557 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 558 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 559 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 560 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 561 // CHECK3: omp.inner.for.body: 562 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 563 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 564 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 565 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 566 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 567 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !12 568 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 569 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12 570 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 571 // CHECK3: omp.body.continue: 572 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 573 // CHECK3: omp.inner.for.inc: 574 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 575 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 576 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 577 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 578 // CHECK3: omp.inner.for.end: 579 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 580 // CHECK3: omp.loop.exit: 581 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 582 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 583 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 584 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 585 // CHECK3: .omp.final.then: 586 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 587 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 588 // CHECK3: .omp.final.done: 589 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP0]], align 4 590 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR1]], align 4 591 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] 592 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 593 // CHECK3-NEXT: ret void 594 // 595 // 596 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 597 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] { 598 // CHECK3-NEXT: entry: 599 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 600 // CHECK3-NEXT: ret void 601 // 602 // 603 // CHECK5-LABEL: define {{[^@]+}}@main 604 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 605 // CHECK5-NEXT: entry: 606 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 607 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 608 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 609 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 610 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 611 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 612 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 613 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 614 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 615 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 616 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 617 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 618 // CHECK5-NEXT: store i32 0, i32* [[SIVAR]], align 4 619 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 620 // CHECK5: omp.inner.for.cond: 621 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 622 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 623 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 624 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 625 // CHECK5: omp.inner.for.body: 626 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 627 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 628 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 629 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 630 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 631 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2 632 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 633 // CHECK5-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !2 634 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 635 // CHECK5: omp.body.continue: 636 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 637 // CHECK5: omp.inner.for.inc: 638 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 639 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 640 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 641 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 642 // CHECK5: omp.inner.for.end: 643 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 644 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 645 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 646 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 647 // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 648 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 649 // CHECK5-NEXT: ret i32 [[CALL]] 650 // 651 // 652 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 653 // CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { 654 // CHECK5-NEXT: entry: 655 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 656 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 657 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 658 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 659 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 660 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 661 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 662 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 663 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 664 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 665 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 666 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 667 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 668 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 669 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 670 // CHECK5-NEXT: store i32 0, i32* [[T_VAR1]], align 4 671 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 672 // CHECK5: omp.inner.for.cond: 673 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 674 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 675 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 676 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 677 // CHECK5: omp.inner.for.body: 678 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 679 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 680 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 681 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 682 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 683 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !6 684 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 685 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !6 686 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 687 // CHECK5: omp.body.continue: 688 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 689 // CHECK5: omp.inner.for.inc: 690 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 691 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 692 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 693 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 694 // CHECK5: omp.inner.for.end: 695 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 696 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 697 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 698 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 699 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 700 // CHECK5-NEXT: ret i32 0 701 // 702 // 703 // CHECK7-LABEL: define {{[^@]+}}@main 704 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 705 // CHECK7-NEXT: entry: 706 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 707 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 708 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 709 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 710 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 711 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 712 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 713 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 714 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 715 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 716 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 717 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 718 // CHECK7-NEXT: store i32 0, i32* [[SIVAR]], align 4 719 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 720 // CHECK7: omp.inner.for.cond: 721 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 722 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 723 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 724 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 725 // CHECK7: omp.inner.for.body: 726 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 727 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 728 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 729 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 730 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 731 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3 732 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 733 // CHECK7-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !3 734 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 735 // CHECK7: omp.body.continue: 736 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 737 // CHECK7: omp.inner.for.inc: 738 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 739 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 740 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 741 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 742 // CHECK7: omp.inner.for.end: 743 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 744 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 745 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 746 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 747 // CHECK7-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 748 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 749 // CHECK7-NEXT: ret i32 [[CALL]] 750 // 751 // 752 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 753 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { 754 // CHECK7-NEXT: entry: 755 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 756 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 757 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 758 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 759 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 760 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 761 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 762 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 763 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 764 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 765 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 766 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 767 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 768 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 769 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 770 // CHECK7-NEXT: store i32 0, i32* [[T_VAR1]], align 4 771 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 772 // CHECK7: omp.inner.for.cond: 773 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 774 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 775 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 776 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 777 // CHECK7: omp.inner.for.body: 778 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 779 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 780 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 781 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 782 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 783 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !7 784 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 785 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !7 786 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 787 // CHECK7: omp.body.continue: 788 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 789 // CHECK7: omp.inner.for.inc: 790 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 791 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 792 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 793 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 794 // CHECK7: omp.inner.for.end: 795 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 796 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 797 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 798 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 799 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 800 // CHECK7-NEXT: ret i32 0 801 // 802 // 803 // CHECK9-LABEL: define {{[^@]+}}@main 804 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 805 // CHECK9-NEXT: entry: 806 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 807 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 808 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 809 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 810 // CHECK9-NEXT: ret i32 0 811 // 812 // 813 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 814 // CHECK9-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 815 // CHECK9-NEXT: entry: 816 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 817 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 818 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 819 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 820 // CHECK9-NEXT: ret void 821 // 822 // 823 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 824 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { 825 // CHECK9-NEXT: entry: 826 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 827 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 828 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 829 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 830 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 831 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 832 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 833 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 834 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 835 // CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 836 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 837 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 838 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 839 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 840 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 841 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 842 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 843 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 844 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 845 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 846 // CHECK9-NEXT: store i32 0, i32* [[SIVAR1]], align 4 847 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 848 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 849 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 850 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 851 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 852 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 853 // CHECK9: cond.true: 854 // CHECK9-NEXT: br label [[COND_END:%.*]] 855 // CHECK9: cond.false: 856 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 857 // CHECK9-NEXT: br label [[COND_END]] 858 // CHECK9: cond.end: 859 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 860 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 861 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 862 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 863 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 864 // CHECK9: omp.inner.for.cond: 865 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 866 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 867 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 868 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 869 // CHECK9: omp.inner.for.body: 870 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 871 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 872 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 873 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 874 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 875 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !4 876 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 877 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4 878 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 879 // CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4 880 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4 881 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 882 // CHECK9: omp.body.continue: 883 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 884 // CHECK9: omp.inner.for.inc: 885 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 886 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 887 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 888 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 889 // CHECK9: omp.inner.for.end: 890 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 891 // CHECK9: omp.loop.exit: 892 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 893 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 894 // CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 895 // CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 896 // CHECK9: .omp.final.then: 897 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 898 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 899 // CHECK9: .omp.final.done: 900 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP0]], align 4 901 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR1]], align 4 902 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 903 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 904 // CHECK9-NEXT: ret void 905 // 906 // 907 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 908 // CHECK9-SAME: () #[[ATTR4:[0-9]+]] { 909 // CHECK9-NEXT: entry: 910 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 911 // CHECK9-NEXT: ret void 912 // 913 // 914 // CHECK11-LABEL: define {{[^@]+}}@main 915 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 916 // CHECK11-NEXT: entry: 917 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 918 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 919 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 920 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 921 // CHECK11-NEXT: ret i32 0 922 // 923