1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-version=45 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 9 // Test host codegen. 10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 16 17 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 18 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 19 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 20 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 24 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 26 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 27 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 28 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 29 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 30 31 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) 32 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 33 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 35 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 36 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 37 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19 38 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 39 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 40 41 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 42 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 43 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 44 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 45 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 46 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 48 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 49 50 // expected-no-diagnostics 51 #ifndef HEADER 52 #define HEADER 53 54 55 void without_schedule_clause(float *a, float *b, float *c, float *d) { 56 #pragma omp target 57 #pragma omp teams 58 #pragma omp distribute 59 for (int i = 33; i < 32000000; i += 7) { 60 a[i] = b[i] * c[i] * d[i]; 61 } 62 } 63 64 // ... loop body ... 65 66 67 void static_not_chunked(float *a, float *b, float *c, float *d) { 68 #pragma omp target 69 #pragma omp teams 70 #pragma omp distribute dist_schedule(static) 71 for (int i = 32000000; i > 33; i += -7) { 72 a[i] = b[i] * c[i] * d[i]; 73 } 74 } 75 76 // ... loop body ... 77 78 79 void static_chunked(float *a, float *b, float *c, float *d) { 80 #pragma omp target 81 #pragma omp teams 82 #pragma omp distribute dist_schedule(static, 5) 83 for (unsigned i = 131071; i <= 2147483647; i += 127) { 84 a[i] = b[i] * c[i] * d[i]; 85 } 86 } 87 88 // ... loop body ... 89 90 void test_precond() { 91 char a = 0; 92 #pragma omp target 93 #pragma omp teams 94 #pragma omp distribute 95 for(char i = a; i < 10; ++i); 96 } 97 98 // a is passed as a parameter to the outlined functions 99 // ..many loads of %0.. 100 101 // no templates for now, as these require special handling in target regions and/or declare target 102 103 104 template <typename T> 105 T ftemplate() { 106 short aa = 0; 107 108 #pragma omp target 109 #pragma omp teams 110 #pragma omp distribute dist_schedule(static, aa) 111 for (int i = 0; i < 100; i++) { 112 } 113 return T(); 114 } 115 116 int fint(void) { return ftemplate<int>(); } 117 118 #endif 119 // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 120 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 121 // CHECK1-NEXT: entry: 122 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 123 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 124 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 125 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 126 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 127 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 128 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 129 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 130 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 131 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 132 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 133 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 134 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 135 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 136 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 137 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 138 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 139 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 140 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 141 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 142 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 143 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 144 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 145 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 146 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 147 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 148 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 149 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 150 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 151 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 152 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 153 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 154 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 155 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 156 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 157 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 158 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 159 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 160 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 161 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 162 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 163 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 164 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 165 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 166 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 167 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 168 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 169 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 170 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 171 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 172 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 173 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 174 // CHECK1-NEXT: store i32 1, i32* [[TMP26]], align 4 175 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 176 // CHECK1-NEXT: store i32 4, i32* [[TMP27]], align 4 177 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 178 // CHECK1-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 8 179 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 180 // CHECK1-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 8 181 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 182 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP30]], align 8 183 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 184 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 8 185 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 186 // CHECK1-NEXT: store i8** null, i8*** [[TMP32]], align 8 187 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 188 // CHECK1-NEXT: store i8** null, i8*** [[TMP33]], align 8 189 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 190 // CHECK1-NEXT: store i64 4571424, i64* [[TMP34]], align 8 191 // CHECK1-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 192 // CHECK1-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0 193 // CHECK1-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 194 // CHECK1: omp_offload.failed: 195 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2:[0-9]+]] 196 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 197 // CHECK1: omp_offload.cont: 198 // CHECK1-NEXT: ret void 199 // 200 // 201 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 202 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { 203 // CHECK1-NEXT: entry: 204 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 205 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 206 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 207 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 208 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 209 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 210 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 211 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 212 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 213 // CHECK1-NEXT: ret void 214 // 215 // 216 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 217 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 218 // CHECK1-NEXT: entry: 219 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 220 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 221 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 222 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 223 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 224 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 225 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 226 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 227 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 228 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 229 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 230 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 231 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 232 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 233 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 234 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 235 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 236 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 237 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 238 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 239 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 240 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 241 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 242 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 243 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 244 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 245 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 246 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 247 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 248 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 249 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 250 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 251 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 252 // CHECK1: cond.true: 253 // CHECK1-NEXT: br label [[COND_END:%.*]] 254 // CHECK1: cond.false: 255 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 256 // CHECK1-NEXT: br label [[COND_END]] 257 // CHECK1: cond.end: 258 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 259 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 260 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 261 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 262 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 263 // CHECK1: omp.inner.for.cond: 264 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 265 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 266 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 267 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 268 // CHECK1: omp.inner.for.body: 269 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 270 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 271 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 272 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 273 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 274 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 275 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 276 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 277 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 278 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 279 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 280 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 281 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 282 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 283 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 284 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 285 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 286 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 287 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 288 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 289 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 290 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 291 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 292 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 293 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 294 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 295 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 296 // CHECK1: omp.body.continue: 297 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 298 // CHECK1: omp.inner.for.inc: 299 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 300 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 301 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 302 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 303 // CHECK1: omp.inner.for.end: 304 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 305 // CHECK1: omp.loop.exit: 306 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 307 // CHECK1-NEXT: ret void 308 // 309 // 310 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 311 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 312 // CHECK1-NEXT: entry: 313 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 314 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 315 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 316 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 317 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 318 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 319 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 320 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 321 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 322 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 323 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 324 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 325 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 326 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 327 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 328 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 329 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 330 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 331 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 332 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 333 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 334 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 335 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 336 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 337 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 338 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 339 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 340 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 341 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 342 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 343 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 344 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 345 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 346 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 347 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 348 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 349 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 350 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 351 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 352 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 353 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 354 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 355 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 356 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 357 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 358 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 359 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 360 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 361 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 362 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 363 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 364 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 365 // CHECK1-NEXT: store i32 1, i32* [[TMP26]], align 4 366 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 367 // CHECK1-NEXT: store i32 4, i32* [[TMP27]], align 4 368 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 369 // CHECK1-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 8 370 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 371 // CHECK1-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 8 372 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 373 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64** [[TMP30]], align 8 374 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 375 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i64** [[TMP31]], align 8 376 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 377 // CHECK1-NEXT: store i8** null, i8*** [[TMP32]], align 8 378 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 379 // CHECK1-NEXT: store i8** null, i8*** [[TMP33]], align 8 380 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 381 // CHECK1-NEXT: store i64 4571424, i64* [[TMP34]], align 8 382 // CHECK1-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 383 // CHECK1-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0 384 // CHECK1-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 385 // CHECK1: omp_offload.failed: 386 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 387 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 388 // CHECK1: omp_offload.cont: 389 // CHECK1-NEXT: ret void 390 // 391 // 392 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 393 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 394 // CHECK1-NEXT: entry: 395 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 396 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 397 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 398 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 399 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 400 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 401 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 402 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 403 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 404 // CHECK1-NEXT: ret void 405 // 406 // 407 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 408 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 409 // CHECK1-NEXT: entry: 410 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 411 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 412 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 413 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 414 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 415 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 416 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 417 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 418 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 419 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 420 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 421 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 422 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 423 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 424 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 425 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 426 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 427 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 428 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 429 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 430 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 431 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 432 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 433 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 434 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 435 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 436 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 437 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 438 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 439 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 440 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 441 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 442 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 443 // CHECK1: cond.true: 444 // CHECK1-NEXT: br label [[COND_END:%.*]] 445 // CHECK1: cond.false: 446 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 447 // CHECK1-NEXT: br label [[COND_END]] 448 // CHECK1: cond.end: 449 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 450 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 451 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 452 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 453 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 454 // CHECK1: omp.inner.for.cond: 455 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 456 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 457 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 458 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 459 // CHECK1: omp.inner.for.body: 460 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 461 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 462 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 463 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4 464 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 465 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 466 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 467 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 468 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 469 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 470 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 471 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 472 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 473 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 474 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 475 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 476 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 477 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 478 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 479 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 480 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 481 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 482 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 483 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 484 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 485 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 486 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 487 // CHECK1: omp.body.continue: 488 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 489 // CHECK1: omp.inner.for.inc: 490 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 491 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 492 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 493 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 494 // CHECK1: omp.inner.for.end: 495 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 496 // CHECK1: omp.loop.exit: 497 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 498 // CHECK1-NEXT: ret void 499 // 500 // 501 // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 502 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 503 // CHECK1-NEXT: entry: 504 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 505 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 506 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 507 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 508 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 509 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 510 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 511 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 512 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 513 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 514 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 515 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 516 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 517 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 518 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 519 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 520 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 521 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 522 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 523 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 524 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 525 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 526 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 527 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 528 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 529 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 530 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 531 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 532 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 533 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 534 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 535 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 536 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 537 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 538 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 539 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 540 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 541 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 542 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 543 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 544 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 545 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 546 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 547 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 548 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 549 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 550 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 551 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 552 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 553 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 554 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 555 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 556 // CHECK1-NEXT: store i32 1, i32* [[TMP26]], align 4 557 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 558 // CHECK1-NEXT: store i32 4, i32* [[TMP27]], align 4 559 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 560 // CHECK1-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 8 561 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 562 // CHECK1-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 8 563 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 564 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP30]], align 8 565 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 566 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP31]], align 8 567 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 568 // CHECK1-NEXT: store i8** null, i8*** [[TMP32]], align 8 569 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 570 // CHECK1-NEXT: store i8** null, i8*** [[TMP33]], align 8 571 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 572 // CHECK1-NEXT: store i64 16908289, i64* [[TMP34]], align 8 573 // CHECK1-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 574 // CHECK1-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0 575 // CHECK1-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 576 // CHECK1: omp_offload.failed: 577 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 578 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 579 // CHECK1: omp_offload.cont: 580 // CHECK1-NEXT: ret void 581 // 582 // 583 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 584 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 585 // CHECK1-NEXT: entry: 586 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 587 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 588 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 589 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 590 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 591 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 592 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 593 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 594 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 595 // CHECK1-NEXT: ret void 596 // 597 // 598 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 599 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 600 // CHECK1-NEXT: entry: 601 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 602 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 603 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 604 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 605 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 606 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 607 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 608 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 609 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 610 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 611 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 612 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 613 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 614 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 615 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 616 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 617 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 618 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 619 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 620 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 621 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 622 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 623 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 624 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 625 // CHECK1-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 626 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 627 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 628 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 629 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 630 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 631 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 632 // CHECK1: omp.dispatch.cond: 633 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 634 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 635 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 636 // CHECK1: cond.true: 637 // CHECK1-NEXT: br label [[COND_END:%.*]] 638 // CHECK1: cond.false: 639 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 640 // CHECK1-NEXT: br label [[COND_END]] 641 // CHECK1: cond.end: 642 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 643 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 644 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 645 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 646 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 647 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 648 // CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 649 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 650 // CHECK1: omp.dispatch.body: 651 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 652 // CHECK1: omp.inner.for.cond: 653 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 654 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 655 // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 656 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 657 // CHECK1: omp.inner.for.body: 658 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 659 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 660 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 661 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 662 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !10 663 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 664 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 665 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 666 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 667 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !10 668 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 669 // CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 670 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 671 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !10 672 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 673 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !10 674 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 675 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 676 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 677 // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !10 678 // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 679 // CHECK1-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !10 680 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 681 // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 682 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 683 // CHECK1-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !10 684 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 685 // CHECK1: omp.body.continue: 686 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 687 // CHECK1: omp.inner.for.inc: 688 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 689 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 690 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 691 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 692 // CHECK1: omp.inner.for.end: 693 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 694 // CHECK1: omp.dispatch.inc: 695 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 696 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 697 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 698 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 699 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 700 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 701 // CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 702 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 703 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 704 // CHECK1: omp.dispatch.end: 705 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 706 // CHECK1-NEXT: ret void 707 // 708 // 709 // CHECK1-LABEL: define {{[^@]+}}@_Z12test_precondv 710 // CHECK1-SAME: () #[[ATTR0]] { 711 // CHECK1-NEXT: entry: 712 // CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1 713 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 714 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 715 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 716 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 717 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 718 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 719 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 720 // CHECK1-NEXT: store i8 0, i8* [[A]], align 1 721 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 722 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* 723 // CHECK1-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 724 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 725 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 726 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 727 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 728 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 729 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 730 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 731 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 732 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 733 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 734 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 735 // CHECK1-NEXT: [[TMP9:%.*]] = load i8, i8* [[A]], align 1 736 // CHECK1-NEXT: store i8 [[TMP9]], i8* [[DOTCAPTURE_EXPR_]], align 1 737 // CHECK1-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 738 // CHECK1-NEXT: [[CONV2:%.*]] = sext i8 [[TMP10]] to i32 739 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV2]] 740 // CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 741 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 742 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 743 // CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 744 // CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 745 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 746 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 747 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[ADD5]] to i64 748 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 749 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 750 // CHECK1-NEXT: store i32 1, i32* [[TMP13]], align 4 751 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 752 // CHECK1-NEXT: store i32 1, i32* [[TMP14]], align 4 753 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 754 // CHECK1-NEXT: store i8** [[TMP7]], i8*** [[TMP15]], align 8 755 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 756 // CHECK1-NEXT: store i8** [[TMP8]], i8*** [[TMP16]], align 8 757 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 758 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64** [[TMP17]], align 8 759 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 760 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP18]], align 8 761 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 762 // CHECK1-NEXT: store i8** null, i8*** [[TMP19]], align 8 763 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 764 // CHECK1-NEXT: store i8** null, i8*** [[TMP20]], align 8 765 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 766 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 767 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 768 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 769 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 770 // CHECK1: omp_offload.failed: 771 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i64 [[TMP1]]) #[[ATTR2]] 772 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 773 // CHECK1: omp_offload.cont: 774 // CHECK1-NEXT: ret void 775 // 776 // 777 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 778 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { 779 // CHECK1-NEXT: entry: 780 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 781 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 782 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* 783 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]]) 784 // CHECK1-NEXT: ret void 785 // 786 // 787 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 788 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 789 // CHECK1-NEXT: entry: 790 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 791 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 792 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 793 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 794 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 795 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 796 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 797 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 798 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 799 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 800 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 801 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 802 // CHECK1-NEXT: [[I5:%.*]] = alloca i8, align 1 803 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 804 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 805 // CHECK1-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 806 // CHECK1-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 807 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 808 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 809 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 810 // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 811 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 812 // CHECK1-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 813 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 814 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 815 // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 816 // CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 817 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 818 // CHECK1-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 819 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 820 // CHECK1-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 821 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 822 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 823 // CHECK1: omp.precond.then: 824 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 825 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 826 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 827 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 828 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 829 // CHECK1-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 830 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 831 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 832 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 833 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 834 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 835 // CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 836 // CHECK1: cond.true: 837 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 838 // CHECK1-NEXT: br label [[COND_END:%.*]] 839 // CHECK1: cond.false: 840 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 841 // CHECK1-NEXT: br label [[COND_END]] 842 // CHECK1: cond.end: 843 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 844 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 845 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 846 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 847 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 848 // CHECK1: omp.inner.for.cond: 849 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 850 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 851 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 852 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 853 // CHECK1: omp.inner.for.body: 854 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 855 // CHECK1-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 856 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 857 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 858 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 859 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 860 // CHECK1-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 861 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 862 // CHECK1: omp.body.continue: 863 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 864 // CHECK1: omp.inner.for.inc: 865 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 866 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 867 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 868 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 869 // CHECK1: omp.inner.for.end: 870 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 871 // CHECK1: omp.loop.exit: 872 // CHECK1-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 873 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 874 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 875 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 876 // CHECK1: omp.precond.end: 877 // CHECK1-NEXT: ret void 878 // 879 // 880 // CHECK1-LABEL: define {{[^@]+}}@_Z4fintv 881 // CHECK1-SAME: () #[[ATTR0]] { 882 // CHECK1-NEXT: entry: 883 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() 884 // CHECK1-NEXT: ret i32 [[CALL]] 885 // 886 // 887 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 888 // CHECK1-SAME: () #[[ATTR0]] comdat { 889 // CHECK1-NEXT: entry: 890 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 891 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 892 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 893 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 894 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 895 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 896 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 897 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 898 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 899 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 900 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 901 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 902 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 903 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 904 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 905 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 906 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 907 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 908 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 909 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 910 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 911 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 912 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 913 // CHECK1-NEXT: store i32 1, i32* [[TMP9]], align 4 914 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 915 // CHECK1-NEXT: store i32 1, i32* [[TMP10]], align 4 916 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 917 // CHECK1-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 8 918 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 919 // CHECK1-NEXT: store i8** [[TMP8]], i8*** [[TMP12]], align 8 920 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 921 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64** [[TMP13]], align 8 922 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 923 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP14]], align 8 924 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 925 // CHECK1-NEXT: store i8** null, i8*** [[TMP15]], align 8 926 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 927 // CHECK1-NEXT: store i8** null, i8*** [[TMP16]], align 8 928 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 929 // CHECK1-NEXT: store i64 100, i64* [[TMP17]], align 8 930 // CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 931 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 932 // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 933 // CHECK1: omp_offload.failed: 934 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i64 [[TMP1]]) #[[ATTR2]] 935 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 936 // CHECK1: omp_offload.cont: 937 // CHECK1-NEXT: ret i32 0 938 // 939 // 940 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 941 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { 942 // CHECK1-NEXT: entry: 943 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 944 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 945 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 946 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 947 // CHECK1-NEXT: ret void 948 // 949 // 950 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 951 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 952 // CHECK1-NEXT: entry: 953 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 954 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 955 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 956 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 957 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 958 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 959 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 960 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 961 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 962 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 963 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 964 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 965 // CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 966 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 967 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 968 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 969 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 970 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 971 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 972 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 973 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 974 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 975 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 976 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 977 // CHECK1: omp.dispatch.cond: 978 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 979 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 980 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 981 // CHECK1: cond.true: 982 // CHECK1-NEXT: br label [[COND_END:%.*]] 983 // CHECK1: cond.false: 984 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 985 // CHECK1-NEXT: br label [[COND_END]] 986 // CHECK1: cond.end: 987 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 988 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 989 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 990 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 991 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 992 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 993 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 994 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 995 // CHECK1: omp.dispatch.body: 996 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 997 // CHECK1: omp.inner.for.cond: 998 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 999 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 1000 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1001 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1002 // CHECK1: omp.inner.for.body: 1003 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 1004 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1005 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1006 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 1007 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1008 // CHECK1: omp.body.continue: 1009 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1010 // CHECK1: omp.inner.for.inc: 1011 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 1012 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 1013 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 1014 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 1015 // CHECK1: omp.inner.for.end: 1016 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1017 // CHECK1: omp.dispatch.inc: 1018 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1019 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1020 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 1021 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 1022 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1023 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1024 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 1025 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 1026 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1027 // CHECK1: omp.dispatch.end: 1028 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 1029 // CHECK1-NEXT: ret void 1030 // 1031 // 1032 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1033 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 1034 // CHECK1-NEXT: entry: 1035 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1036 // CHECK1-NEXT: ret void 1037 // 1038 // 1039 // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 1040 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 1041 // CHECK3-NEXT: entry: 1042 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1043 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1044 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1045 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1046 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1047 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1048 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1049 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1050 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1051 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1052 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1053 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1054 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 1055 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 1056 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 1057 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 1058 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1059 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 1060 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 1061 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1062 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 1063 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 1064 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1065 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1066 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1067 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 1068 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 1069 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1070 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 1071 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 1072 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1073 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1074 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1075 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 1076 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 1077 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1078 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1079 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 1080 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1081 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1082 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1083 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 1084 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 1085 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1086 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 1087 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 1088 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1089 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1090 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1091 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1092 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1093 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1094 // CHECK3-NEXT: store i32 1, i32* [[TMP26]], align 4 1095 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1096 // CHECK3-NEXT: store i32 4, i32* [[TMP27]], align 4 1097 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1098 // CHECK3-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 4 1099 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1100 // CHECK3-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 4 1101 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1102 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP30]], align 4 1103 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1104 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 4 1105 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1106 // CHECK3-NEXT: store i8** null, i8*** [[TMP32]], align 4 1107 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1108 // CHECK3-NEXT: store i8** null, i8*** [[TMP33]], align 4 1109 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1110 // CHECK3-NEXT: store i64 4571424, i64* [[TMP34]], align 8 1111 // CHECK3-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1112 // CHECK3-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0 1113 // CHECK3-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1114 // CHECK3: omp_offload.failed: 1115 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2:[0-9]+]] 1116 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1117 // CHECK3: omp_offload.cont: 1118 // CHECK3-NEXT: ret void 1119 // 1120 // 1121 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 1122 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { 1123 // CHECK3-NEXT: entry: 1124 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1125 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1126 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1127 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1128 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1129 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1130 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1131 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1132 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1133 // CHECK3-NEXT: ret void 1134 // 1135 // 1136 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1137 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 1138 // CHECK3-NEXT: entry: 1139 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1140 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1141 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 1142 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 1143 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 1144 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 1145 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1146 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1147 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1148 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1149 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1150 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1151 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1152 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1153 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1154 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 1155 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 1156 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 1157 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 1158 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 1159 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 1160 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 1161 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 1162 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1163 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1164 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1165 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1166 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1167 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1168 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1169 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1170 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1171 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1172 // CHECK3: cond.true: 1173 // CHECK3-NEXT: br label [[COND_END:%.*]] 1174 // CHECK3: cond.false: 1175 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1176 // CHECK3-NEXT: br label [[COND_END]] 1177 // CHECK3: cond.end: 1178 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1179 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1180 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1181 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1182 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1183 // CHECK3: omp.inner.for.cond: 1184 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1185 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1186 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1187 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1188 // CHECK3: omp.inner.for.body: 1189 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1190 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1191 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 1192 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1193 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 1194 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1195 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 1196 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1197 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 1198 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1199 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 1200 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 1201 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 1202 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 1203 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1204 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 1205 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 1206 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 1207 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 1208 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1209 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 1210 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 1211 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1212 // CHECK3: omp.body.continue: 1213 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1214 // CHECK3: omp.inner.for.inc: 1215 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1216 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 1217 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 1218 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1219 // CHECK3: omp.inner.for.end: 1220 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1221 // CHECK3: omp.loop.exit: 1222 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1223 // CHECK3-NEXT: ret void 1224 // 1225 // 1226 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1227 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1228 // CHECK3-NEXT: entry: 1229 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1230 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1231 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1232 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1233 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1234 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1235 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1236 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1237 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1238 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1239 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1240 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1241 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 1242 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 1243 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 1244 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 1245 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1246 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 1247 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 1248 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1249 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 1250 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 1251 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1252 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1253 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1254 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 1255 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 1256 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1257 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 1258 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 1259 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1260 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1261 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1262 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 1263 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 1264 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1265 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1266 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 1267 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1268 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1269 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1270 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 1271 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 1272 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1273 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 1274 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 1275 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1276 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1277 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1278 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1279 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1280 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1281 // CHECK3-NEXT: store i32 1, i32* [[TMP26]], align 4 1282 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1283 // CHECK3-NEXT: store i32 4, i32* [[TMP27]], align 4 1284 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1285 // CHECK3-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 4 1286 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1287 // CHECK3-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 4 1288 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1289 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64** [[TMP30]], align 4 1290 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1291 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i64** [[TMP31]], align 4 1292 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1293 // CHECK3-NEXT: store i8** null, i8*** [[TMP32]], align 4 1294 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1295 // CHECK3-NEXT: store i8** null, i8*** [[TMP33]], align 4 1296 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1297 // CHECK3-NEXT: store i64 4571424, i64* [[TMP34]], align 8 1298 // CHECK3-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1299 // CHECK3-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0 1300 // CHECK3-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1301 // CHECK3: omp_offload.failed: 1302 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 1303 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1304 // CHECK3: omp_offload.cont: 1305 // CHECK3-NEXT: ret void 1306 // 1307 // 1308 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 1309 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 1310 // CHECK3-NEXT: entry: 1311 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1312 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1313 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1314 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1315 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1316 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1317 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1318 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1319 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1320 // CHECK3-NEXT: ret void 1321 // 1322 // 1323 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 1324 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 1325 // CHECK3-NEXT: entry: 1326 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1327 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1328 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 1329 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 1330 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 1331 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 1332 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1333 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1334 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1335 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1336 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1337 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1338 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1339 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1340 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1341 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 1342 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 1343 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 1344 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 1345 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 1346 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 1347 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 1348 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 1349 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1350 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1351 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1352 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1353 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1354 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1355 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1356 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1357 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1358 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1359 // CHECK3: cond.true: 1360 // CHECK3-NEXT: br label [[COND_END:%.*]] 1361 // CHECK3: cond.false: 1362 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1363 // CHECK3-NEXT: br label [[COND_END]] 1364 // CHECK3: cond.end: 1365 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1366 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1367 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1368 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1369 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1370 // CHECK3: omp.inner.for.cond: 1371 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1372 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1373 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1374 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1375 // CHECK3: omp.inner.for.body: 1376 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1377 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1378 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1379 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4 1380 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 1381 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1382 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 1383 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1384 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 1385 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1386 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 1387 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 1388 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 1389 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 1390 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1391 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 1392 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 1393 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 1394 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 1395 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1396 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 1397 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 1398 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1399 // CHECK3: omp.body.continue: 1400 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1401 // CHECK3: omp.inner.for.inc: 1402 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1403 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 1404 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1405 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1406 // CHECK3: omp.inner.for.end: 1407 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1408 // CHECK3: omp.loop.exit: 1409 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1410 // CHECK3-NEXT: ret void 1411 // 1412 // 1413 // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 1414 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1415 // CHECK3-NEXT: entry: 1416 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1417 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1418 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1419 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1420 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1421 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1422 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1423 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1424 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1425 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1426 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1427 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1428 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 1429 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 1430 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 1431 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 1432 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1433 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 1434 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 1435 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1436 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 1437 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 1438 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1439 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1440 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1441 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 1442 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 1443 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1444 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 1445 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 1446 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1447 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1448 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1449 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 1450 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 1451 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1452 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1453 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 1454 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1455 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1456 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1457 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 1458 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 1459 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1460 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 1461 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 1462 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1463 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1464 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1465 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1466 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1467 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1468 // CHECK3-NEXT: store i32 1, i32* [[TMP26]], align 4 1469 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1470 // CHECK3-NEXT: store i32 4, i32* [[TMP27]], align 4 1471 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1472 // CHECK3-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 4 1473 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1474 // CHECK3-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 4 1475 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1476 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP30]], align 4 1477 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1478 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP31]], align 4 1479 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1480 // CHECK3-NEXT: store i8** null, i8*** [[TMP32]], align 4 1481 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1482 // CHECK3-NEXT: store i8** null, i8*** [[TMP33]], align 4 1483 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1484 // CHECK3-NEXT: store i64 16908289, i64* [[TMP34]], align 8 1485 // CHECK3-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1486 // CHECK3-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0 1487 // CHECK3-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1488 // CHECK3: omp_offload.failed: 1489 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 1490 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1491 // CHECK3: omp_offload.cont: 1492 // CHECK3-NEXT: ret void 1493 // 1494 // 1495 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 1496 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 1497 // CHECK3-NEXT: entry: 1498 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1499 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1500 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1501 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1502 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1503 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1504 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1505 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1506 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1507 // CHECK3-NEXT: ret void 1508 // 1509 // 1510 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 1511 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 1512 // CHECK3-NEXT: entry: 1513 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1514 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1515 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 1516 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 1517 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 1518 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 1519 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1520 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1521 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1522 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1523 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1524 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1525 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1526 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1527 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1528 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 1529 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 1530 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 1531 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 1532 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 1533 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 1534 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 1535 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 1536 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1537 // CHECK3-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 1538 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1539 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1540 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1541 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1542 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 1543 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1544 // CHECK3: omp.dispatch.cond: 1545 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1546 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 1547 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1548 // CHECK3: cond.true: 1549 // CHECK3-NEXT: br label [[COND_END:%.*]] 1550 // CHECK3: cond.false: 1551 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1552 // CHECK3-NEXT: br label [[COND_END]] 1553 // CHECK3: cond.end: 1554 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1555 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1556 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1557 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1558 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1559 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1560 // CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 1561 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1562 // CHECK3: omp.dispatch.body: 1563 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1564 // CHECK3: omp.inner.for.cond: 1565 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1566 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 1567 // CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 1568 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1569 // CHECK3: omp.inner.for.body: 1570 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1571 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 1572 // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 1573 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 1574 // CHECK3-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !11 1575 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1576 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 1577 // CHECK3-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 1578 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !11 1579 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1580 // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 1581 // CHECK3-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !11 1582 // CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 1583 // CHECK3-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !11 1584 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1585 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 1586 // CHECK3-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !11 1587 // CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 1588 // CHECK3-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !11 1589 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1590 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 1591 // CHECK3-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !11 1592 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1593 // CHECK3: omp.body.continue: 1594 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1595 // CHECK3: omp.inner.for.inc: 1596 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1597 // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 1598 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1599 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 1600 // CHECK3: omp.inner.for.end: 1601 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1602 // CHECK3: omp.dispatch.inc: 1603 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1604 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1605 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 1606 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 1607 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1608 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1609 // CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 1610 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 1611 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1612 // CHECK3: omp.dispatch.end: 1613 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1614 // CHECK3-NEXT: ret void 1615 // 1616 // 1617 // CHECK3-LABEL: define {{[^@]+}}@_Z12test_precondv 1618 // CHECK3-SAME: () #[[ATTR0]] { 1619 // CHECK3-NEXT: entry: 1620 // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 1621 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1622 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1623 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1624 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1625 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 1626 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1627 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1628 // CHECK3-NEXT: store i8 0, i8* [[A]], align 1 1629 // CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 1630 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[A_CASTED]] to i8* 1631 // CHECK3-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 1632 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 1633 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1634 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 1635 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 1636 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1637 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 1638 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 1639 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1640 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4 1641 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1642 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1643 // CHECK3-NEXT: [[TMP9:%.*]] = load i8, i8* [[A]], align 1 1644 // CHECK3-NEXT: store i8 [[TMP9]], i8* [[DOTCAPTURE_EXPR_]], align 1 1645 // CHECK3-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1646 // CHECK3-NEXT: [[CONV2:%.*]] = sext i8 [[TMP10]] to i32 1647 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV2]] 1648 // CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 1649 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 1650 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1651 // CHECK3-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 1652 // CHECK3-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1653 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1654 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 1655 // CHECK3-NEXT: [[TMP12:%.*]] = zext i32 [[ADD5]] to i64 1656 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1657 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1658 // CHECK3-NEXT: store i32 1, i32* [[TMP13]], align 4 1659 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1660 // CHECK3-NEXT: store i32 1, i32* [[TMP14]], align 4 1661 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1662 // CHECK3-NEXT: store i8** [[TMP7]], i8*** [[TMP15]], align 4 1663 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1664 // CHECK3-NEXT: store i8** [[TMP8]], i8*** [[TMP16]], align 4 1665 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1666 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64** [[TMP17]], align 4 1667 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1668 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP18]], align 4 1669 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1670 // CHECK3-NEXT: store i8** null, i8*** [[TMP19]], align 4 1671 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1672 // CHECK3-NEXT: store i8** null, i8*** [[TMP20]], align 4 1673 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1674 // CHECK3-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 1675 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1676 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1677 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1678 // CHECK3: omp_offload.failed: 1679 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i32 [[TMP1]]) #[[ATTR2]] 1680 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1681 // CHECK3: omp_offload.cont: 1682 // CHECK3-NEXT: ret void 1683 // 1684 // 1685 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 1686 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { 1687 // CHECK3-NEXT: entry: 1688 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1689 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1690 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* 1691 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]]) 1692 // CHECK3-NEXT: ret void 1693 // 1694 // 1695 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 1696 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 1697 // CHECK3-NEXT: entry: 1698 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1699 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1700 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 1701 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1702 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 1703 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1704 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1705 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 1706 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1707 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1708 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1709 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1710 // CHECK3-NEXT: [[I5:%.*]] = alloca i8, align 1 1711 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1712 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1713 // CHECK3-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 1714 // CHECK3-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 1715 // CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 1716 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 1717 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1718 // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 1719 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 1720 // CHECK3-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 1721 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 1722 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1723 // CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 1724 // CHECK3-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1725 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1726 // CHECK3-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 1727 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1728 // CHECK3-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 1729 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 1730 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1731 // CHECK3: omp.precond.then: 1732 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1733 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1734 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 1735 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1736 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1737 // CHECK3-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1738 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 1739 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1740 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1741 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1742 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 1743 // CHECK3-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1744 // CHECK3: cond.true: 1745 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1746 // CHECK3-NEXT: br label [[COND_END:%.*]] 1747 // CHECK3: cond.false: 1748 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1749 // CHECK3-NEXT: br label [[COND_END]] 1750 // CHECK3: cond.end: 1751 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 1752 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1753 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1754 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 1755 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1756 // CHECK3: omp.inner.for.cond: 1757 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1758 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1759 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 1760 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1761 // CHECK3: omp.inner.for.body: 1762 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1763 // CHECK3-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 1764 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1765 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 1766 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 1767 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 1768 // CHECK3-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 1769 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1770 // CHECK3: omp.body.continue: 1771 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1772 // CHECK3: omp.inner.for.inc: 1773 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1774 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 1775 // CHECK3-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 1776 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1777 // CHECK3: omp.inner.for.end: 1778 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1779 // CHECK3: omp.loop.exit: 1780 // CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1781 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 1782 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 1783 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 1784 // CHECK3: omp.precond.end: 1785 // CHECK3-NEXT: ret void 1786 // 1787 // 1788 // CHECK3-LABEL: define {{[^@]+}}@_Z4fintv 1789 // CHECK3-SAME: () #[[ATTR0]] { 1790 // CHECK3-NEXT: entry: 1791 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() 1792 // CHECK3-NEXT: ret i32 [[CALL]] 1793 // 1794 // 1795 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 1796 // CHECK3-SAME: () #[[ATTR0]] comdat { 1797 // CHECK3-NEXT: entry: 1798 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1799 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1800 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1801 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1802 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1803 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1804 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 1805 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 1806 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 1807 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 1808 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 1809 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1810 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 1811 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 1812 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1813 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 1814 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 1815 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1816 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4 1817 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1818 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1819 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1820 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1821 // CHECK3-NEXT: store i32 1, i32* [[TMP9]], align 4 1822 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1823 // CHECK3-NEXT: store i32 1, i32* [[TMP10]], align 4 1824 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1825 // CHECK3-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 4 1826 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1827 // CHECK3-NEXT: store i8** [[TMP8]], i8*** [[TMP12]], align 4 1828 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1829 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64** [[TMP13]], align 4 1830 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1831 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP14]], align 4 1832 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1833 // CHECK3-NEXT: store i8** null, i8*** [[TMP15]], align 4 1834 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1835 // CHECK3-NEXT: store i8** null, i8*** [[TMP16]], align 4 1836 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1837 // CHECK3-NEXT: store i64 100, i64* [[TMP17]], align 8 1838 // CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1839 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 1840 // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1841 // CHECK3: omp_offload.failed: 1842 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i32 [[TMP1]]) #[[ATTR2]] 1843 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1844 // CHECK3: omp_offload.cont: 1845 // CHECK3-NEXT: ret i32 0 1846 // 1847 // 1848 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 1849 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { 1850 // CHECK3-NEXT: entry: 1851 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1852 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1853 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1854 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 1855 // CHECK3-NEXT: ret void 1856 // 1857 // 1858 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 1859 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 1860 // CHECK3-NEXT: entry: 1861 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1862 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1863 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 1864 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1865 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1866 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1867 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1868 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1869 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1870 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1871 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1872 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1873 // CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 1874 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 1875 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1876 // CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 1877 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1878 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1879 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 1880 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 1881 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1882 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1883 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 1884 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1885 // CHECK3: omp.dispatch.cond: 1886 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1887 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1888 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1889 // CHECK3: cond.true: 1890 // CHECK3-NEXT: br label [[COND_END:%.*]] 1891 // CHECK3: cond.false: 1892 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1893 // CHECK3-NEXT: br label [[COND_END]] 1894 // CHECK3: cond.end: 1895 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1896 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1897 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1898 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 1899 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1900 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1901 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1902 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1903 // CHECK3: omp.dispatch.body: 1904 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1905 // CHECK3: omp.inner.for.cond: 1906 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1907 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 1908 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1909 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1910 // CHECK3: omp.inner.for.body: 1911 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1912 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1913 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1914 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 1915 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1916 // CHECK3: omp.body.continue: 1917 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1918 // CHECK3: omp.inner.for.inc: 1919 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1920 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 1921 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1922 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 1923 // CHECK3: omp.inner.for.end: 1924 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1925 // CHECK3: omp.dispatch.inc: 1926 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1927 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1928 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 1929 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 1930 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1931 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1932 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 1933 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 1934 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1935 // CHECK3: omp.dispatch.end: 1936 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 1937 // CHECK3-NEXT: ret void 1938 // 1939 // 1940 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1941 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1942 // CHECK3-NEXT: entry: 1943 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1944 // CHECK3-NEXT: ret void 1945 // 1946 // 1947 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 1948 // CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 1949 // CHECK17-NEXT: entry: 1950 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1951 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1952 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1953 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1954 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1955 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1956 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1957 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1958 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1959 // CHECK17-NEXT: ret void 1960 // 1961 // 1962 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 1963 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 1964 // CHECK17-NEXT: entry: 1965 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1966 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1967 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1968 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1969 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1970 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1971 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1972 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 1973 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1974 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1975 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1976 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1977 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 1978 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1979 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1980 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1981 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1982 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1983 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1984 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1985 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1986 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1987 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1988 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1989 // CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1990 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1991 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1992 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1993 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1994 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1995 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1996 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1997 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1998 // CHECK17: cond.true: 1999 // CHECK17-NEXT: br label [[COND_END:%.*]] 2000 // CHECK17: cond.false: 2001 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2002 // CHECK17-NEXT: br label [[COND_END]] 2003 // CHECK17: cond.end: 2004 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2005 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2006 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2007 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2008 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2009 // CHECK17: omp.inner.for.cond: 2010 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2011 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2012 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2013 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2014 // CHECK17: omp.inner.for.body: 2015 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2016 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 2017 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 2018 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2019 // CHECK17-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 2020 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2021 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 2022 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 2023 // CHECK17-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2024 // CHECK17-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 2025 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2026 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 2027 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 2028 // CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 2029 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 2030 // CHECK17-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 2031 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2032 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 2033 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 2034 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 2035 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 2036 // CHECK17-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 2037 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2038 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 2039 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 2040 // CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 2041 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2042 // CHECK17: omp.body.continue: 2043 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2044 // CHECK17: omp.inner.for.inc: 2045 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2046 // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 2047 // CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 2048 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 2049 // CHECK17: omp.inner.for.end: 2050 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2051 // CHECK17: omp.loop.exit: 2052 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2053 // CHECK17-NEXT: ret void 2054 // 2055 // 2056 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 2057 // CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2058 // CHECK17-NEXT: entry: 2059 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2060 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2061 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2062 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2063 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2064 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2065 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2066 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2067 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2068 // CHECK17-NEXT: ret void 2069 // 2070 // 2071 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 2072 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 2073 // CHECK17-NEXT: entry: 2074 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2075 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2076 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2077 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2078 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2079 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2080 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2081 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 2082 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2083 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2084 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2085 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2086 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 2087 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2088 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2089 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2090 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2091 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2092 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2093 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2094 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 2095 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 2096 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 2097 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2098 // CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2099 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2100 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2101 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2102 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2103 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2104 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2105 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 2106 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2107 // CHECK17: cond.true: 2108 // CHECK17-NEXT: br label [[COND_END:%.*]] 2109 // CHECK17: cond.false: 2110 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2111 // CHECK17-NEXT: br label [[COND_END]] 2112 // CHECK17: cond.end: 2113 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2114 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2115 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2116 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2117 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2118 // CHECK17: omp.inner.for.cond: 2119 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2120 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2121 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2122 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2123 // CHECK17: omp.inner.for.body: 2124 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2125 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 2126 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 2127 // CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4 2128 // CHECK17-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 2129 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2130 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 2131 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 2132 // CHECK17-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2133 // CHECK17-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 2134 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2135 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 2136 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 2137 // CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 2138 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 2139 // CHECK17-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 2140 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2141 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 2142 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 2143 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 2144 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 2145 // CHECK17-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 2146 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2147 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 2148 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 2149 // CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 2150 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2151 // CHECK17: omp.body.continue: 2152 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2153 // CHECK17: omp.inner.for.inc: 2154 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2155 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 2156 // CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2157 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 2158 // CHECK17: omp.inner.for.end: 2159 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2160 // CHECK17: omp.loop.exit: 2161 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2162 // CHECK17-NEXT: ret void 2163 // 2164 // 2165 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 2166 // CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2167 // CHECK17-NEXT: entry: 2168 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2169 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2170 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2171 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2172 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2173 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2174 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2175 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2176 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2177 // CHECK17-NEXT: ret void 2178 // 2179 // 2180 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 2181 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 2182 // CHECK17-NEXT: entry: 2183 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2184 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2185 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2186 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2187 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2188 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2189 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2190 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 2191 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2192 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2193 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2194 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2195 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 2196 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2197 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2198 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2199 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2200 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2201 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2202 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2203 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 2204 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 2205 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 2206 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2207 // CHECK17-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 2208 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2209 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2210 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2211 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2212 // CHECK17-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 2213 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2214 // CHECK17: omp.dispatch.cond: 2215 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2216 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 2217 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2218 // CHECK17: cond.true: 2219 // CHECK17-NEXT: br label [[COND_END:%.*]] 2220 // CHECK17: cond.false: 2221 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2222 // CHECK17-NEXT: br label [[COND_END]] 2223 // CHECK17: cond.end: 2224 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2225 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2226 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2227 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2228 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2229 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2230 // CHECK17-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 2231 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2232 // CHECK17: omp.dispatch.body: 2233 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2234 // CHECK17: omp.inner.for.cond: 2235 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2236 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 2237 // CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 2238 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2239 // CHECK17: omp.inner.for.body: 2240 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2241 // CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 2242 // CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 2243 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 2244 // CHECK17-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !11 2245 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 2246 // CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 2247 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 2248 // CHECK17-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 2249 // CHECK17-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !11 2250 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 2251 // CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 2252 // CHECK17-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 2253 // CHECK17-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !11 2254 // CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 2255 // CHECK17-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !11 2256 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 2257 // CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 2258 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 2259 // CHECK17-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !11 2260 // CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 2261 // CHECK17-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !11 2262 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 2263 // CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 2264 // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 2265 // CHECK17-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !11 2266 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2267 // CHECK17: omp.body.continue: 2268 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2269 // CHECK17: omp.inner.for.inc: 2270 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2271 // CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 2272 // CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2273 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 2274 // CHECK17: omp.inner.for.end: 2275 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2276 // CHECK17: omp.dispatch.inc: 2277 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2278 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2279 // CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 2280 // CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 2281 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2282 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2283 // CHECK17-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 2284 // CHECK17-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 2285 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 2286 // CHECK17: omp.dispatch.end: 2287 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2288 // CHECK17-NEXT: ret void 2289 // 2290 // 2291 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 2292 // CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0]] { 2293 // CHECK17-NEXT: entry: 2294 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2295 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2296 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* 2297 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) 2298 // CHECK17-NEXT: ret void 2299 // 2300 // 2301 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 2302 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 2303 // CHECK17-NEXT: entry: 2304 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2305 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2306 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 2307 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2308 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 2309 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2310 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2311 // CHECK17-NEXT: [[I:%.*]] = alloca i8, align 1 2312 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2313 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2314 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2315 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2316 // CHECK17-NEXT: [[I5:%.*]] = alloca i8, align 1 2317 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2318 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2319 // CHECK17-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 2320 // CHECK17-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 2321 // CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 2322 // CHECK17-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 2323 // CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2324 // CHECK17-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 2325 // CHECK17-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 2326 // CHECK17-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 2327 // CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 2328 // CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2329 // CHECK17-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 2330 // CHECK17-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2331 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2332 // CHECK17-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 2333 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2334 // CHECK17-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 2335 // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 2336 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2337 // CHECK17: omp.precond.then: 2338 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2339 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2340 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 2341 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2342 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2343 // CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2344 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 2345 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2346 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2347 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2348 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 2349 // CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2350 // CHECK17: cond.true: 2351 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2352 // CHECK17-NEXT: br label [[COND_END:%.*]] 2353 // CHECK17: cond.false: 2354 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2355 // CHECK17-NEXT: br label [[COND_END]] 2356 // CHECK17: cond.end: 2357 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 2358 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2359 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2360 // CHECK17-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 2361 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2362 // CHECK17: omp.inner.for.cond: 2363 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2364 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2365 // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 2366 // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2367 // CHECK17: omp.inner.for.body: 2368 // CHECK17-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2369 // CHECK17-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 2370 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2371 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 2372 // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 2373 // CHECK17-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 2374 // CHECK17-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 2375 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2376 // CHECK17: omp.body.continue: 2377 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2378 // CHECK17: omp.inner.for.inc: 2379 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2380 // CHECK17-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 2381 // CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 2382 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 2383 // CHECK17: omp.inner.for.end: 2384 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2385 // CHECK17: omp.loop.exit: 2386 // CHECK17-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2387 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 2388 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 2389 // CHECK17-NEXT: br label [[OMP_PRECOND_END]] 2390 // CHECK17: omp.precond.end: 2391 // CHECK17-NEXT: ret void 2392 // 2393 // 2394 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 2395 // CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 2396 // CHECK17-NEXT: entry: 2397 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2398 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2399 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2400 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) 2401 // CHECK17-NEXT: ret void 2402 // 2403 // 2404 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 2405 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 2406 // CHECK17-NEXT: entry: 2407 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2408 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2409 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 2410 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2411 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 2412 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2413 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2414 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2415 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2416 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 2417 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2418 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2419 // CHECK17-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 2420 // CHECK17-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 2421 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2422 // CHECK17-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 2423 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2424 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2425 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 2426 // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2427 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2428 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2429 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 2430 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2431 // CHECK17: omp.dispatch.cond: 2432 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2433 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2434 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2435 // CHECK17: cond.true: 2436 // CHECK17-NEXT: br label [[COND_END:%.*]] 2437 // CHECK17: cond.false: 2438 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2439 // CHECK17-NEXT: br label [[COND_END]] 2440 // CHECK17: cond.end: 2441 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2442 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2443 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2444 // CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 2445 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2446 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2447 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2448 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2449 // CHECK17: omp.dispatch.body: 2450 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2451 // CHECK17: omp.inner.for.cond: 2452 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2453 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 2454 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2455 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2456 // CHECK17: omp.inner.for.body: 2457 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2458 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 2459 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2460 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 2461 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2462 // CHECK17: omp.body.continue: 2463 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2464 // CHECK17: omp.inner.for.inc: 2465 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2466 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 2467 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2468 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 2469 // CHECK17: omp.inner.for.end: 2470 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2471 // CHECK17: omp.dispatch.inc: 2472 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2473 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2474 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 2475 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 2476 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2477 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2478 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 2479 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 2480 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 2481 // CHECK17: omp.dispatch.end: 2482 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 2483 // CHECK17-NEXT: ret void 2484 // 2485 // 2486 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 2487 // CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 2488 // CHECK19-NEXT: entry: 2489 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2490 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2491 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2492 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2493 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2494 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2495 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2496 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2497 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2498 // CHECK19-NEXT: ret void 2499 // 2500 // 2501 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 2502 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 2503 // CHECK19-NEXT: entry: 2504 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2505 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2506 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 2507 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 2508 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 2509 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 2510 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2511 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 2512 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2513 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2514 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2515 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2516 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 2517 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2518 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2519 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 2520 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 2521 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 2522 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 2523 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 2524 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 2525 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 2526 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 2527 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2528 // CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2529 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2530 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2531 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2532 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2533 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2534 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2535 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 2536 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2537 // CHECK19: cond.true: 2538 // CHECK19-NEXT: br label [[COND_END:%.*]] 2539 // CHECK19: cond.false: 2540 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2541 // CHECK19-NEXT: br label [[COND_END]] 2542 // CHECK19: cond.end: 2543 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2544 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2545 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2546 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2547 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2548 // CHECK19: omp.inner.for.cond: 2549 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2550 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2551 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2552 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2553 // CHECK19: omp.inner.for.body: 2554 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2555 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 2556 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 2557 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2558 // CHECK19-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 2559 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2560 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 2561 // CHECK19-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2562 // CHECK19-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 2563 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2564 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 2565 // CHECK19-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2566 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 2567 // CHECK19-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 2568 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2569 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 2570 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2571 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 2572 // CHECK19-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 2573 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2574 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 2575 // CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 2576 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2577 // CHECK19: omp.body.continue: 2578 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2579 // CHECK19: omp.inner.for.inc: 2580 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2581 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 2582 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 2583 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 2584 // CHECK19: omp.inner.for.end: 2585 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2586 // CHECK19: omp.loop.exit: 2587 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2588 // CHECK19-NEXT: ret void 2589 // 2590 // 2591 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 2592 // CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2593 // CHECK19-NEXT: entry: 2594 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2595 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2596 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2597 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2598 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2599 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2600 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2601 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2602 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2603 // CHECK19-NEXT: ret void 2604 // 2605 // 2606 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 2607 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 2608 // CHECK19-NEXT: entry: 2609 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2610 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2611 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 2612 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 2613 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 2614 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 2615 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2616 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 2617 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2618 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2619 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2620 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2621 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 2622 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2623 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2624 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 2625 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 2626 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 2627 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 2628 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 2629 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 2630 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 2631 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 2632 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2633 // CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2634 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2635 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2636 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2637 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2638 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2639 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2640 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 2641 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2642 // CHECK19: cond.true: 2643 // CHECK19-NEXT: br label [[COND_END:%.*]] 2644 // CHECK19: cond.false: 2645 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2646 // CHECK19-NEXT: br label [[COND_END]] 2647 // CHECK19: cond.end: 2648 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2649 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2650 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2651 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2652 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2653 // CHECK19: omp.inner.for.cond: 2654 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2655 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2656 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2657 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2658 // CHECK19: omp.inner.for.body: 2659 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2660 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 2661 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 2662 // CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4 2663 // CHECK19-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 2664 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2665 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 2666 // CHECK19-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2667 // CHECK19-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 2668 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2669 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 2670 // CHECK19-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2671 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 2672 // CHECK19-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 2673 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2674 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 2675 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2676 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 2677 // CHECK19-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 2678 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2679 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 2680 // CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 2681 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2682 // CHECK19: omp.body.continue: 2683 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2684 // CHECK19: omp.inner.for.inc: 2685 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2686 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 2687 // CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2688 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 2689 // CHECK19: omp.inner.for.end: 2690 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2691 // CHECK19: omp.loop.exit: 2692 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2693 // CHECK19-NEXT: ret void 2694 // 2695 // 2696 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 2697 // CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2698 // CHECK19-NEXT: entry: 2699 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2700 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2701 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2702 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2703 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2704 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2705 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2706 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2707 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2708 // CHECK19-NEXT: ret void 2709 // 2710 // 2711 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 2712 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 2713 // CHECK19-NEXT: entry: 2714 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2715 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2716 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 2717 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 2718 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 2719 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 2720 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2721 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 2722 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2723 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2724 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2725 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2726 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 2727 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2728 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2729 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 2730 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 2731 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 2732 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 2733 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 2734 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 2735 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 2736 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 2737 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2738 // CHECK19-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 2739 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2740 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2741 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2742 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2743 // CHECK19-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 2744 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2745 // CHECK19: omp.dispatch.cond: 2746 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2747 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 2748 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2749 // CHECK19: cond.true: 2750 // CHECK19-NEXT: br label [[COND_END:%.*]] 2751 // CHECK19: cond.false: 2752 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2753 // CHECK19-NEXT: br label [[COND_END]] 2754 // CHECK19: cond.end: 2755 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2756 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2757 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2758 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2759 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2760 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2761 // CHECK19-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 2762 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2763 // CHECK19: omp.dispatch.body: 2764 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2765 // CHECK19: omp.inner.for.cond: 2766 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2767 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 2768 // CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 2769 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2770 // CHECK19: omp.inner.for.body: 2771 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2772 // CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 2773 // CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 2774 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 2775 // CHECK19-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !12 2776 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2777 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 2778 // CHECK19-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12 2779 // CHECK19-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !12 2780 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2781 // CHECK19-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 2782 // CHECK19-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !12 2783 // CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 2784 // CHECK19-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !12 2785 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2786 // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 2787 // CHECK19-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !12 2788 // CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 2789 // CHECK19-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !12 2790 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2791 // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 2792 // CHECK19-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !12 2793 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2794 // CHECK19: omp.body.continue: 2795 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2796 // CHECK19: omp.inner.for.inc: 2797 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2798 // CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 2799 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2800 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 2801 // CHECK19: omp.inner.for.end: 2802 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2803 // CHECK19: omp.dispatch.inc: 2804 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2805 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2806 // CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 2807 // CHECK19-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 2808 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2809 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2810 // CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 2811 // CHECK19-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 2812 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 2813 // CHECK19: omp.dispatch.end: 2814 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2815 // CHECK19-NEXT: ret void 2816 // 2817 // 2818 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 2819 // CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0]] { 2820 // CHECK19-NEXT: entry: 2821 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2822 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2823 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* 2824 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) 2825 // CHECK19-NEXT: ret void 2826 // 2827 // 2828 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 2829 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 2830 // CHECK19-NEXT: entry: 2831 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2832 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2833 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 2834 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2835 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 2836 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2837 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2838 // CHECK19-NEXT: [[I:%.*]] = alloca i8, align 1 2839 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2840 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2841 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2842 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2843 // CHECK19-NEXT: [[I5:%.*]] = alloca i8, align 1 2844 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2845 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2846 // CHECK19-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 2847 // CHECK19-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 2848 // CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 2849 // CHECK19-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 2850 // CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2851 // CHECK19-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 2852 // CHECK19-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 2853 // CHECK19-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 2854 // CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 2855 // CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2856 // CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 2857 // CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2858 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2859 // CHECK19-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 2860 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2861 // CHECK19-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 2862 // CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 2863 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2864 // CHECK19: omp.precond.then: 2865 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2866 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2867 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 2868 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2869 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2870 // CHECK19-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2871 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 2872 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2873 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2874 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2875 // CHECK19-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 2876 // CHECK19-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2877 // CHECK19: cond.true: 2878 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2879 // CHECK19-NEXT: br label [[COND_END:%.*]] 2880 // CHECK19: cond.false: 2881 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2882 // CHECK19-NEXT: br label [[COND_END]] 2883 // CHECK19: cond.end: 2884 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 2885 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2886 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2887 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 2888 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2889 // CHECK19: omp.inner.for.cond: 2890 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2891 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2892 // CHECK19-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 2893 // CHECK19-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2894 // CHECK19: omp.inner.for.body: 2895 // CHECK19-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2896 // CHECK19-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 2897 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2898 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 2899 // CHECK19-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 2900 // CHECK19-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 2901 // CHECK19-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 2902 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2903 // CHECK19: omp.body.continue: 2904 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2905 // CHECK19: omp.inner.for.inc: 2906 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2907 // CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 2908 // CHECK19-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 2909 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 2910 // CHECK19: omp.inner.for.end: 2911 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2912 // CHECK19: omp.loop.exit: 2913 // CHECK19-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2914 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 2915 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 2916 // CHECK19-NEXT: br label [[OMP_PRECOND_END]] 2917 // CHECK19: omp.precond.end: 2918 // CHECK19-NEXT: ret void 2919 // 2920 // 2921 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 2922 // CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 2923 // CHECK19-NEXT: entry: 2924 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2925 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2926 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2927 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) 2928 // CHECK19-NEXT: ret void 2929 // 2930 // 2931 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 2932 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 2933 // CHECK19-NEXT: entry: 2934 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2935 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2936 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 2937 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2938 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 2939 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2940 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2941 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2942 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2943 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 2944 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2945 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2946 // CHECK19-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 2947 // CHECK19-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 2948 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2949 // CHECK19-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 2950 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2951 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2952 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 2953 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2954 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2955 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2956 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 2957 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2958 // CHECK19: omp.dispatch.cond: 2959 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2960 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2961 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2962 // CHECK19: cond.true: 2963 // CHECK19-NEXT: br label [[COND_END:%.*]] 2964 // CHECK19: cond.false: 2965 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2966 // CHECK19-NEXT: br label [[COND_END]] 2967 // CHECK19: cond.end: 2968 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2969 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2970 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2971 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 2972 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2973 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2974 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2975 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2976 // CHECK19: omp.dispatch.body: 2977 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2978 // CHECK19: omp.inner.for.cond: 2979 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 2980 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 2981 // CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2982 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2983 // CHECK19: omp.inner.for.body: 2984 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 2985 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 2986 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2987 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 2988 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2989 // CHECK19: omp.body.continue: 2990 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2991 // CHECK19: omp.inner.for.inc: 2992 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 2993 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 2994 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 2995 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 2996 // CHECK19: omp.inner.for.end: 2997 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2998 // CHECK19: omp.dispatch.inc: 2999 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3000 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3001 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 3002 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 3003 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3004 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3005 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 3006 // CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 3007 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 3008 // CHECK19: omp.dispatch.end: 3009 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 3010 // CHECK19-NEXT: ret void 3011 // 3012