1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 6 // RUN: %clang_cc1 -verify -fopenmp-version=45 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 9 // Test host codegen. 10 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 13 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 14 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 16 17 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 18 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 19 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 20 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 23 24 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 25 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 26 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 27 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 28 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 29 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 30 31 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) 32 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 33 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 35 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 36 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 37 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19 38 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 39 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 40 41 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 42 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK21 43 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 44 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 45 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 46 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK23 47 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 49 50 // expected-no-diagnostics 51 #ifndef HEADER 52 #define HEADER 53 54 55 void without_schedule_clause(float *a, float *b, float *c, float *d) { 56 #pragma omp target 57 #pragma omp teams 58 #pragma omp distribute 59 for (int i = 33; i < 32000000; i += 7) { 60 a[i] = b[i] * c[i] * d[i]; 61 } 62 } 63 64 // ... loop body ... 65 66 67 void static_not_chunked(float *a, float *b, float *c, float *d) { 68 #pragma omp target 69 #pragma omp teams 70 #pragma omp distribute dist_schedule(static) 71 for (int i = 32000000; i > 33; i += -7) { 72 a[i] = b[i] * c[i] * d[i]; 73 } 74 } 75 76 // ... loop body ... 77 78 79 void static_chunked(float *a, float *b, float *c, float *d) { 80 #pragma omp target 81 #pragma omp teams 82 #pragma omp distribute dist_schedule(static, 5) 83 for (unsigned i = 131071; i <= 2147483647; i += 127) { 84 a[i] = b[i] * c[i] * d[i]; 85 } 86 } 87 88 // ... loop body ... 89 90 void test_precond() { 91 char a = 0; 92 #pragma omp target 93 #pragma omp teams 94 #pragma omp distribute 95 for(char i = a; i < 10; ++i); 96 } 97 98 // a is passed as a parameter to the outlined functions 99 // ..many loads of %0.. 100 101 // no templates for now, as these require special handling in target regions and/or declare target 102 103 104 template <typename T> 105 T ftemplate() { 106 short aa = 0; 107 108 #pragma omp target 109 #pragma omp teams 110 #pragma omp distribute dist_schedule(static, aa) 111 for (int i = 0; i < 100; i++) { 112 } 113 return T(); 114 } 115 116 int fint(void) { return ftemplate<int>(); } 117 118 #endif 119 // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 120 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 121 // CHECK1-NEXT: entry: 122 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 123 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 124 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 125 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 126 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 127 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 128 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 129 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 130 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 131 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 132 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 133 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 134 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 135 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 136 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 137 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 138 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 139 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 140 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 141 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 142 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 143 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 144 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 145 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 146 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 147 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 148 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 149 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 150 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 151 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 152 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 153 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 154 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 155 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 156 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 157 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 158 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 159 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 160 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 161 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 162 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 163 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 164 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 165 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 166 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 167 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 168 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 169 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 170 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 171 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 172 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 173 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 174 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 175 // CHECK1-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 176 // CHECK1: omp_offload.failed: 177 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2:[0-9]+]] 178 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 179 // CHECK1: omp_offload.cont: 180 // CHECK1-NEXT: ret void 181 // 182 // 183 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 184 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { 185 // CHECK1-NEXT: entry: 186 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 187 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 188 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 189 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 190 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 191 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 192 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 193 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 194 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 195 // CHECK1-NEXT: ret void 196 // 197 // 198 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 199 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 200 // CHECK1-NEXT: entry: 201 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 202 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 203 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 204 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 205 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 206 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 207 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 208 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 209 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 210 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 211 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 212 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 213 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 214 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 215 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 216 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 217 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 218 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 219 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 220 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 221 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 222 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 223 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 224 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 225 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 226 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 227 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 228 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 229 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 230 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 231 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 232 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 233 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 234 // CHECK1: cond.true: 235 // CHECK1-NEXT: br label [[COND_END:%.*]] 236 // CHECK1: cond.false: 237 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 238 // CHECK1-NEXT: br label [[COND_END]] 239 // CHECK1: cond.end: 240 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 241 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 242 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 243 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 244 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 245 // CHECK1: omp.inner.for.cond: 246 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 247 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 248 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 249 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 250 // CHECK1: omp.inner.for.body: 251 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 252 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 253 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 254 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 255 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 256 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 257 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 258 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 259 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 260 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 261 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 262 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 263 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 264 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 265 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 266 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 267 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 268 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 269 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 270 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 271 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 272 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 273 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 274 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 275 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 276 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 277 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 278 // CHECK1: omp.body.continue: 279 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 280 // CHECK1: omp.inner.for.inc: 281 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 282 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 283 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 284 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 285 // CHECK1: omp.inner.for.end: 286 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 287 // CHECK1: omp.loop.exit: 288 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 289 // CHECK1-NEXT: ret void 290 // 291 // 292 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 293 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 294 // CHECK1-NEXT: entry: 295 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 296 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 297 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 298 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 299 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 300 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 301 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 302 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 303 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 304 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 305 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 306 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 307 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 308 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 309 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 310 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 311 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 312 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 313 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 314 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 315 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 316 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 317 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 318 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 319 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 320 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 321 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 322 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 323 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 324 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 325 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 326 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 327 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 328 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 329 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 330 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 331 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 332 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 333 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 334 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 335 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 336 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 337 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 338 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 339 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 340 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 341 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 342 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 343 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 344 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 345 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 346 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 347 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 348 // CHECK1-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 349 // CHECK1: omp_offload.failed: 350 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 351 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 352 // CHECK1: omp_offload.cont: 353 // CHECK1-NEXT: ret void 354 // 355 // 356 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 357 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 358 // CHECK1-NEXT: entry: 359 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 360 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 361 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 362 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 363 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 364 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 365 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 366 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 367 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 368 // CHECK1-NEXT: ret void 369 // 370 // 371 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 372 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 373 // CHECK1-NEXT: entry: 374 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 375 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 376 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 377 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 378 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 379 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 380 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 381 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 382 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 383 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 384 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 385 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 386 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 387 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 388 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 389 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 390 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 391 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 392 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 393 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 394 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 395 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 396 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 397 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 398 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 399 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 400 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 401 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 402 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 403 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 404 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 405 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 406 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 407 // CHECK1: cond.true: 408 // CHECK1-NEXT: br label [[COND_END:%.*]] 409 // CHECK1: cond.false: 410 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 411 // CHECK1-NEXT: br label [[COND_END]] 412 // CHECK1: cond.end: 413 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 414 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 415 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 416 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 417 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 418 // CHECK1: omp.inner.for.cond: 419 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 420 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 421 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 422 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 423 // CHECK1: omp.inner.for.body: 424 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 425 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 426 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 427 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4 428 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 429 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 430 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 431 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 432 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 433 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 434 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 435 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 436 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 437 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 438 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 439 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 440 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 441 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 442 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 443 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 444 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 445 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 446 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 447 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 448 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 449 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 450 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 451 // CHECK1: omp.body.continue: 452 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 453 // CHECK1: omp.inner.for.inc: 454 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 455 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 456 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 457 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 458 // CHECK1: omp.inner.for.end: 459 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 460 // CHECK1: omp.loop.exit: 461 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 462 // CHECK1-NEXT: ret void 463 // 464 // 465 // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 466 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 467 // CHECK1-NEXT: entry: 468 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 469 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 470 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 471 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 472 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 473 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 474 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 475 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 476 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 477 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 478 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 479 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 480 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 481 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 482 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 483 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 484 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 485 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 486 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 487 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 488 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 489 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 490 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 491 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 492 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 493 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 494 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 495 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 496 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 497 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 498 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 499 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 500 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 501 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 502 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 503 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 504 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 505 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 506 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 507 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 508 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 509 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 510 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 511 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 512 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 513 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 514 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 515 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 516 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 517 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 518 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 519 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 520 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 521 // CHECK1-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 522 // CHECK1: omp_offload.failed: 523 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 524 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 525 // CHECK1: omp_offload.cont: 526 // CHECK1-NEXT: ret void 527 // 528 // 529 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 530 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 531 // CHECK1-NEXT: entry: 532 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 533 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 534 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 535 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 536 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 537 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 538 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 539 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 540 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 541 // CHECK1-NEXT: ret void 542 // 543 // 544 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 545 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 546 // CHECK1-NEXT: entry: 547 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 548 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 549 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 550 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 551 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 552 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 553 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 554 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 555 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 556 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 557 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 558 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 559 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 560 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 561 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 562 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 563 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 564 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 565 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 566 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 567 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 568 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 569 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 570 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 571 // CHECK1-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 572 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 573 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 574 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 575 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 576 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 577 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 578 // CHECK1: omp.dispatch.cond: 579 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 580 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 581 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 582 // CHECK1: cond.true: 583 // CHECK1-NEXT: br label [[COND_END:%.*]] 584 // CHECK1: cond.false: 585 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 586 // CHECK1-NEXT: br label [[COND_END]] 587 // CHECK1: cond.end: 588 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 589 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 590 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 591 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 592 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 593 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 594 // CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 595 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 596 // CHECK1: omp.dispatch.body: 597 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 598 // CHECK1: omp.inner.for.cond: 599 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 600 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 601 // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 602 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 603 // CHECK1: omp.inner.for.body: 604 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 605 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 606 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 607 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 608 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 609 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 610 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 611 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 612 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 613 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 614 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 615 // CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 616 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 617 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9 618 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 619 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 620 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 621 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 622 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 623 // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !9 624 // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 625 // CHECK1-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 626 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 627 // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 628 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 629 // CHECK1-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 630 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 631 // CHECK1: omp.body.continue: 632 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 633 // CHECK1: omp.inner.for.inc: 634 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 635 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 636 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 637 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 638 // CHECK1: omp.inner.for.end: 639 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 640 // CHECK1: omp.dispatch.inc: 641 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 642 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 643 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 644 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 645 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 646 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 647 // CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 648 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 649 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 650 // CHECK1: omp.dispatch.end: 651 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 652 // CHECK1-NEXT: ret void 653 // 654 // 655 // CHECK1-LABEL: define {{[^@]+}}@_Z12test_precondv 656 // CHECK1-SAME: () #[[ATTR0]] { 657 // CHECK1-NEXT: entry: 658 // CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1 659 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 660 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 661 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 662 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 663 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 664 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 665 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 666 // CHECK1-NEXT: store i8 0, i8* [[A]], align 1 667 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 668 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* 669 // CHECK1-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 670 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 671 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 672 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 673 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 674 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 675 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 676 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 677 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 678 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 679 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 680 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 681 // CHECK1-NEXT: [[TMP9:%.*]] = load i8, i8* [[A]], align 1 682 // CHECK1-NEXT: store i8 [[TMP9]], i8* [[DOTCAPTURE_EXPR_]], align 1 683 // CHECK1-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 684 // CHECK1-NEXT: [[CONV2:%.*]] = sext i8 [[TMP10]] to i32 685 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV2]] 686 // CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 687 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 688 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 689 // CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 690 // CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 691 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 692 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 693 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[ADD5]] to i64 694 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP12]]) 695 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 696 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 697 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 698 // CHECK1: omp_offload.failed: 699 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i64 [[TMP1]]) #[[ATTR2]] 700 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 701 // CHECK1: omp_offload.cont: 702 // CHECK1-NEXT: ret void 703 // 704 // 705 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 706 // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { 707 // CHECK1-NEXT: entry: 708 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 709 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 710 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* 711 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]]) 712 // CHECK1-NEXT: ret void 713 // 714 // 715 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 716 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 717 // CHECK1-NEXT: entry: 718 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 719 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 720 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 721 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 722 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 723 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 724 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 725 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 726 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 727 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 728 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 729 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 730 // CHECK1-NEXT: [[I5:%.*]] = alloca i8, align 1 731 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 732 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 733 // CHECK1-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 734 // CHECK1-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 735 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 736 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 737 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 738 // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 739 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 740 // CHECK1-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 741 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 742 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 743 // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 744 // CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 745 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 746 // CHECK1-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 747 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 748 // CHECK1-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 749 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 750 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 751 // CHECK1: omp.precond.then: 752 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 753 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 754 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 755 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 756 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 757 // CHECK1-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 758 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 759 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 760 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 761 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 762 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 763 // CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 764 // CHECK1: cond.true: 765 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 766 // CHECK1-NEXT: br label [[COND_END:%.*]] 767 // CHECK1: cond.false: 768 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 769 // CHECK1-NEXT: br label [[COND_END]] 770 // CHECK1: cond.end: 771 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 772 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 773 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 774 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 775 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 776 // CHECK1: omp.inner.for.cond: 777 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 778 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 779 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 780 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 781 // CHECK1: omp.inner.for.body: 782 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 783 // CHECK1-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 784 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 785 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 786 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 787 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 788 // CHECK1-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 789 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 790 // CHECK1: omp.body.continue: 791 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 792 // CHECK1: omp.inner.for.inc: 793 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 794 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 795 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 796 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 797 // CHECK1: omp.inner.for.end: 798 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 799 // CHECK1: omp.loop.exit: 800 // CHECK1-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 801 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 802 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 803 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 804 // CHECK1: omp.precond.end: 805 // CHECK1-NEXT: ret void 806 // 807 // 808 // CHECK1-LABEL: define {{[^@]+}}@_Z4fintv 809 // CHECK1-SAME: () #[[ATTR0]] { 810 // CHECK1-NEXT: entry: 811 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() 812 // CHECK1-NEXT: ret i32 [[CALL]] 813 // 814 // 815 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 816 // CHECK1-SAME: () #[[ATTR0]] comdat { 817 // CHECK1-NEXT: entry: 818 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 819 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 820 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 821 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 822 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 823 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 824 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 825 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 826 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 827 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 828 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 829 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 830 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 831 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 832 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 833 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 834 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 835 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 836 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 837 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 838 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 839 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 840 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 841 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 842 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 843 // CHECK1: omp_offload.failed: 844 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i64 [[TMP1]]) #[[ATTR2]] 845 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 846 // CHECK1: omp_offload.cont: 847 // CHECK1-NEXT: ret i32 0 848 // 849 // 850 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 851 // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] { 852 // CHECK1-NEXT: entry: 853 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 854 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 855 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 856 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 857 // CHECK1-NEXT: ret void 858 // 859 // 860 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 861 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 862 // CHECK1-NEXT: entry: 863 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 864 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 865 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 866 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 867 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 868 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 869 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 870 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 871 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 872 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 873 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 874 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 875 // CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 876 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 877 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 878 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 879 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 880 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 881 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 882 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 883 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 884 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 885 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 886 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 887 // CHECK1: omp.dispatch.cond: 888 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 889 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 890 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 891 // CHECK1: cond.true: 892 // CHECK1-NEXT: br label [[COND_END:%.*]] 893 // CHECK1: cond.false: 894 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 895 // CHECK1-NEXT: br label [[COND_END]] 896 // CHECK1: cond.end: 897 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 898 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 899 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 900 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 901 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 902 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 903 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 904 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 905 // CHECK1: omp.dispatch.body: 906 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 907 // CHECK1: omp.inner.for.cond: 908 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 909 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 910 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 911 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 912 // CHECK1: omp.inner.for.body: 913 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 914 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 915 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 916 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 917 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 918 // CHECK1: omp.body.continue: 919 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 920 // CHECK1: omp.inner.for.inc: 921 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 922 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 923 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 924 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 925 // CHECK1: omp.inner.for.end: 926 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 927 // CHECK1: omp.dispatch.inc: 928 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 929 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 930 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 931 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 932 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 933 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 934 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 935 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 936 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 937 // CHECK1: omp.dispatch.end: 938 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 939 // CHECK1-NEXT: ret void 940 // 941 // 942 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 943 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 944 // CHECK1-NEXT: entry: 945 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 946 // CHECK1-NEXT: ret void 947 // 948 // 949 // CHECK2-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 950 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 951 // CHECK2-NEXT: entry: 952 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 953 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 954 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 955 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 956 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 957 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 958 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 959 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 960 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 961 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 962 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 963 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 964 // CHECK2-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 965 // CHECK2-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 966 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 967 // CHECK2-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 968 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 969 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 970 // CHECK2-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 971 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 972 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 973 // CHECK2-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 974 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 975 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8 976 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 977 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 978 // CHECK2-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 979 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 980 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 981 // CHECK2-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 982 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 983 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8 984 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 985 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 986 // CHECK2-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 987 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 988 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 989 // CHECK2-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 990 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 991 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8 992 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 993 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 994 // CHECK2-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 995 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 996 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 997 // CHECK2-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 998 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 999 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8 1000 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1001 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1002 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 1003 // CHECK2-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1004 // CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 1005 // CHECK2-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1006 // CHECK2: omp_offload.failed: 1007 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2:[0-9]+]] 1008 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1009 // CHECK2: omp_offload.cont: 1010 // CHECK2-NEXT: ret void 1011 // 1012 // 1013 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 1014 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { 1015 // CHECK2-NEXT: entry: 1016 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1017 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1018 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1019 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1020 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1021 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1022 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1023 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1024 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1025 // CHECK2-NEXT: ret void 1026 // 1027 // 1028 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1029 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1030 // CHECK2-NEXT: entry: 1031 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1032 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1033 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1034 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1035 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1036 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1037 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1038 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1039 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1040 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1041 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1042 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1043 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1044 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1045 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1046 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1047 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1048 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1049 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1050 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1051 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1052 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1053 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1054 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1055 // CHECK2-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1056 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1057 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1058 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1059 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1060 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1061 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1062 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1063 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1064 // CHECK2: cond.true: 1065 // CHECK2-NEXT: br label [[COND_END:%.*]] 1066 // CHECK2: cond.false: 1067 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1068 // CHECK2-NEXT: br label [[COND_END]] 1069 // CHECK2: cond.end: 1070 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1071 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1072 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1073 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1074 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1075 // CHECK2: omp.inner.for.cond: 1076 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1077 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1078 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1079 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1080 // CHECK2: omp.inner.for.body: 1081 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1082 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1083 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 1084 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1085 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 1086 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1087 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 1088 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 1089 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1090 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 1091 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1092 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 1093 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 1094 // CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 1095 // CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 1096 // CHECK2-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 1097 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1098 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 1099 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 1100 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 1101 // CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 1102 // CHECK2-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 1103 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1104 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 1105 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 1106 // CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 1107 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1108 // CHECK2: omp.body.continue: 1109 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1110 // CHECK2: omp.inner.for.inc: 1111 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1112 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 1113 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 1114 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1115 // CHECK2: omp.inner.for.end: 1116 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1117 // CHECK2: omp.loop.exit: 1118 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1119 // CHECK2-NEXT: ret void 1120 // 1121 // 1122 // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1123 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1124 // CHECK2-NEXT: entry: 1125 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1126 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1127 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1128 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1129 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1130 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1131 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1132 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1133 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1134 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1135 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1136 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1137 // CHECK2-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 1138 // CHECK2-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 1139 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 1140 // CHECK2-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 1141 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1142 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 1143 // CHECK2-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 1144 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1145 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 1146 // CHECK2-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 1147 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1148 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8 1149 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1150 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 1151 // CHECK2-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 1152 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1153 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 1154 // CHECK2-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 1155 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1156 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8 1157 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1158 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 1159 // CHECK2-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 1160 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1161 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1162 // CHECK2-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 1163 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1164 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8 1165 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1166 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 1167 // CHECK2-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 1168 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1169 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 1170 // CHECK2-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 1171 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1172 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8 1173 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1174 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1175 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 1176 // CHECK2-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1177 // CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 1178 // CHECK2-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1179 // CHECK2: omp_offload.failed: 1180 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 1181 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1182 // CHECK2: omp_offload.cont: 1183 // CHECK2-NEXT: ret void 1184 // 1185 // 1186 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 1187 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 1188 // CHECK2-NEXT: entry: 1189 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1190 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1191 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1192 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1193 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1194 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1195 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1196 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1197 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1198 // CHECK2-NEXT: ret void 1199 // 1200 // 1201 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 1202 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1203 // CHECK2-NEXT: entry: 1204 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1205 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1206 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1207 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1208 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1209 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1210 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1211 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1212 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1213 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1214 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1215 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1216 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1217 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1218 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1219 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1220 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1221 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1222 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1223 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1224 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1225 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1226 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1227 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1228 // CHECK2-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1229 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1230 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1231 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1232 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1233 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1234 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1235 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1236 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1237 // CHECK2: cond.true: 1238 // CHECK2-NEXT: br label [[COND_END:%.*]] 1239 // CHECK2: cond.false: 1240 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1241 // CHECK2-NEXT: br label [[COND_END]] 1242 // CHECK2: cond.end: 1243 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1244 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1245 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1246 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1247 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1248 // CHECK2: omp.inner.for.cond: 1249 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1250 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1251 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1252 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1253 // CHECK2: omp.inner.for.body: 1254 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1255 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1256 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1257 // CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4 1258 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 1259 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1260 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 1261 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 1262 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1263 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 1264 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1265 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 1266 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 1267 // CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 1268 // CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 1269 // CHECK2-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 1270 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1271 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 1272 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 1273 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 1274 // CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 1275 // CHECK2-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 1276 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1277 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 1278 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 1279 // CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 1280 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1281 // CHECK2: omp.body.continue: 1282 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1283 // CHECK2: omp.inner.for.inc: 1284 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1285 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 1286 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1287 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1288 // CHECK2: omp.inner.for.end: 1289 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1290 // CHECK2: omp.loop.exit: 1291 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1292 // CHECK2-NEXT: ret void 1293 // 1294 // 1295 // CHECK2-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 1296 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1297 // CHECK2-NEXT: entry: 1298 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1299 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1300 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1301 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1302 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1303 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1304 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1305 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1306 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1307 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1308 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1309 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1310 // CHECK2-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 1311 // CHECK2-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 1312 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 1313 // CHECK2-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 1314 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1315 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 1316 // CHECK2-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 1317 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1318 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 1319 // CHECK2-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 1320 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1321 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8 1322 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1323 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 1324 // CHECK2-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 1325 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1326 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 1327 // CHECK2-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 1328 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1329 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8 1330 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1331 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 1332 // CHECK2-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 1333 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1334 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1335 // CHECK2-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 1336 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1337 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8 1338 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1339 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 1340 // CHECK2-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 1341 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1342 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 1343 // CHECK2-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 1344 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1345 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8 1346 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1347 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1348 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 1349 // CHECK2-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1350 // CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 1351 // CHECK2-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1352 // CHECK2: omp_offload.failed: 1353 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 1354 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1355 // CHECK2: omp_offload.cont: 1356 // CHECK2-NEXT: ret void 1357 // 1358 // 1359 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 1360 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 1361 // CHECK2-NEXT: entry: 1362 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1363 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1364 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1365 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1366 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1367 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1368 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1369 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1370 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1371 // CHECK2-NEXT: ret void 1372 // 1373 // 1374 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 1375 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1376 // CHECK2-NEXT: entry: 1377 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1378 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1379 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1380 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1381 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1382 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1383 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1384 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1385 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1386 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1387 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1388 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1389 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1390 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1391 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1392 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1393 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1394 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1395 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1396 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1397 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1398 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1399 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1400 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1401 // CHECK2-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 1402 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1403 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1404 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1405 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1406 // CHECK2-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 1407 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1408 // CHECK2: omp.dispatch.cond: 1409 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1410 // CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 1411 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1412 // CHECK2: cond.true: 1413 // CHECK2-NEXT: br label [[COND_END:%.*]] 1414 // CHECK2: cond.false: 1415 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1416 // CHECK2-NEXT: br label [[COND_END]] 1417 // CHECK2: cond.end: 1418 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1419 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1420 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1421 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1422 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1423 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1424 // CHECK2-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 1425 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1426 // CHECK2: omp.dispatch.body: 1427 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1428 // CHECK2: omp.inner.for.cond: 1429 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 1430 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 1431 // CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 1432 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1433 // CHECK2: omp.inner.for.body: 1434 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 1435 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 1436 // CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 1437 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 1438 // CHECK2-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 1439 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 1440 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 1441 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 1442 // CHECK2-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 1443 // CHECK2-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 1444 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 1445 // CHECK2-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 1446 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 1447 // CHECK2-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9 1448 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 1449 // CHECK2-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 1450 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 1451 // CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 1452 // CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 1453 // CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !9 1454 // CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 1455 // CHECK2-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 1456 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 1457 // CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 1458 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 1459 // CHECK2-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 1460 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1461 // CHECK2: omp.body.continue: 1462 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1463 // CHECK2: omp.inner.for.inc: 1464 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 1465 // CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 1466 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 1467 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 1468 // CHECK2: omp.inner.for.end: 1469 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1470 // CHECK2: omp.dispatch.inc: 1471 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1472 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1473 // CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 1474 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 1475 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1476 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1477 // CHECK2-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 1478 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 1479 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1480 // CHECK2: omp.dispatch.end: 1481 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1482 // CHECK2-NEXT: ret void 1483 // 1484 // 1485 // CHECK2-LABEL: define {{[^@]+}}@_Z12test_precondv 1486 // CHECK2-SAME: () #[[ATTR0]] { 1487 // CHECK2-NEXT: entry: 1488 // CHECK2-NEXT: [[A:%.*]] = alloca i8, align 1 1489 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1490 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1491 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1492 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1493 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 1494 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1495 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1496 // CHECK2-NEXT: store i8 0, i8* [[A]], align 1 1497 // CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 1498 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* 1499 // CHECK2-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 1500 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1501 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1502 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 1503 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 1504 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1505 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 1506 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 1507 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1508 // CHECK2-NEXT: store i8* null, i8** [[TMP6]], align 8 1509 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1510 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1511 // CHECK2-NEXT: [[TMP9:%.*]] = load i8, i8* [[A]], align 1 1512 // CHECK2-NEXT: store i8 [[TMP9]], i8* [[DOTCAPTURE_EXPR_]], align 1 1513 // CHECK2-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1514 // CHECK2-NEXT: [[CONV2:%.*]] = sext i8 [[TMP10]] to i32 1515 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV2]] 1516 // CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 1517 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 1518 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1519 // CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 1520 // CHECK2-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1521 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1522 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 1523 // CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[ADD5]] to i64 1524 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP12]]) 1525 // CHECK2-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1526 // CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1527 // CHECK2-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1528 // CHECK2: omp_offload.failed: 1529 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i64 [[TMP1]]) #[[ATTR2]] 1530 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1531 // CHECK2: omp_offload.cont: 1532 // CHECK2-NEXT: ret void 1533 // 1534 // 1535 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 1536 // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { 1537 // CHECK2-NEXT: entry: 1538 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1539 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1540 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* 1541 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]]) 1542 // CHECK2-NEXT: ret void 1543 // 1544 // 1545 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 1546 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 1547 // CHECK2-NEXT: entry: 1548 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1549 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1550 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 1551 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1552 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 1553 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1554 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1555 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1 1556 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1557 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1558 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1559 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1560 // CHECK2-NEXT: [[I5:%.*]] = alloca i8, align 1 1561 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1562 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1563 // CHECK2-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 1564 // CHECK2-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 1565 // CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 1566 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 1567 // CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1568 // CHECK2-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 1569 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 1570 // CHECK2-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 1571 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 1572 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1573 // CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 1574 // CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1575 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1576 // CHECK2-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 1577 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1578 // CHECK2-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 1579 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 1580 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1581 // CHECK2: omp.precond.then: 1582 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1583 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1584 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 1585 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1586 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1587 // CHECK2-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1588 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 1589 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1590 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1591 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1592 // CHECK2-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 1593 // CHECK2-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1594 // CHECK2: cond.true: 1595 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1596 // CHECK2-NEXT: br label [[COND_END:%.*]] 1597 // CHECK2: cond.false: 1598 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1599 // CHECK2-NEXT: br label [[COND_END]] 1600 // CHECK2: cond.end: 1601 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 1602 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1603 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1604 // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 1605 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1606 // CHECK2: omp.inner.for.cond: 1607 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1608 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1609 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 1610 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1611 // CHECK2: omp.inner.for.body: 1612 // CHECK2-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1613 // CHECK2-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 1614 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1615 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 1616 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 1617 // CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 1618 // CHECK2-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 1619 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1620 // CHECK2: omp.body.continue: 1621 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1622 // CHECK2: omp.inner.for.inc: 1623 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1624 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 1625 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 1626 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1627 // CHECK2: omp.inner.for.end: 1628 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1629 // CHECK2: omp.loop.exit: 1630 // CHECK2-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1631 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 1632 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 1633 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 1634 // CHECK2: omp.precond.end: 1635 // CHECK2-NEXT: ret void 1636 // 1637 // 1638 // CHECK2-LABEL: define {{[^@]+}}@_Z4fintv 1639 // CHECK2-SAME: () #[[ATTR0]] { 1640 // CHECK2-NEXT: entry: 1641 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() 1642 // CHECK2-NEXT: ret i32 [[CALL]] 1643 // 1644 // 1645 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 1646 // CHECK2-SAME: () #[[ATTR0]] comdat { 1647 // CHECK2-NEXT: entry: 1648 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 1649 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1650 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1651 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1652 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1653 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1654 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 1655 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 1656 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1657 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 1658 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1659 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1660 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 1661 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 1662 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1663 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 1664 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 1665 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1666 // CHECK2-NEXT: store i8* null, i8** [[TMP6]], align 8 1667 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1668 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1669 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 1670 // CHECK2-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1671 // CHECK2-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 1672 // CHECK2-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1673 // CHECK2: omp_offload.failed: 1674 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i64 [[TMP1]]) #[[ATTR2]] 1675 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1676 // CHECK2: omp_offload.cont: 1677 // CHECK2-NEXT: ret i32 0 1678 // 1679 // 1680 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 1681 // CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] { 1682 // CHECK2-NEXT: entry: 1683 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1684 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1685 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1686 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 1687 // CHECK2-NEXT: ret void 1688 // 1689 // 1690 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 1691 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 1692 // CHECK2-NEXT: entry: 1693 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1694 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1695 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 1696 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1697 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1698 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1699 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1700 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1701 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1702 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1703 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1704 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1705 // CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 1706 // CHECK2-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 1707 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1708 // CHECK2-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 1709 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1710 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1711 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 1712 // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 1713 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1714 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1715 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 1716 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1717 // CHECK2: omp.dispatch.cond: 1718 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1719 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1720 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1721 // CHECK2: cond.true: 1722 // CHECK2-NEXT: br label [[COND_END:%.*]] 1723 // CHECK2: cond.false: 1724 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1725 // CHECK2-NEXT: br label [[COND_END]] 1726 // CHECK2: cond.end: 1727 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1728 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1729 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1730 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 1731 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1732 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1733 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1734 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1735 // CHECK2: omp.dispatch.body: 1736 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1737 // CHECK2: omp.inner.for.cond: 1738 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1739 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 1740 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1741 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1742 // CHECK2: omp.inner.for.body: 1743 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1744 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1745 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1746 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 1747 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1748 // CHECK2: omp.body.continue: 1749 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1750 // CHECK2: omp.inner.for.inc: 1751 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1752 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 1753 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1754 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 1755 // CHECK2: omp.inner.for.end: 1756 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1757 // CHECK2: omp.dispatch.inc: 1758 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1759 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1760 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 1761 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 1762 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1763 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1764 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 1765 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 1766 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1767 // CHECK2: omp.dispatch.end: 1768 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 1769 // CHECK2-NEXT: ret void 1770 // 1771 // 1772 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1773 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 1774 // CHECK2-NEXT: entry: 1775 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 1776 // CHECK2-NEXT: ret void 1777 // 1778 // 1779 // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 1780 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 1781 // CHECK3-NEXT: entry: 1782 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1783 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1784 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1785 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1786 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1787 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1788 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1789 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1790 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1791 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1792 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1793 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1794 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 1795 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 1796 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 1797 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 1798 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1799 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 1800 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 1801 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1802 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 1803 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 1804 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1805 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1806 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1807 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 1808 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 1809 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1810 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 1811 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 1812 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1813 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1814 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1815 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 1816 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 1817 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1818 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1819 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 1820 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1821 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1822 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1823 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 1824 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 1825 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1826 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 1827 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 1828 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1829 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1830 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1831 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1832 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 1833 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1834 // CHECK3-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 1835 // CHECK3-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1836 // CHECK3: omp_offload.failed: 1837 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2:[0-9]+]] 1838 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1839 // CHECK3: omp_offload.cont: 1840 // CHECK3-NEXT: ret void 1841 // 1842 // 1843 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 1844 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { 1845 // CHECK3-NEXT: entry: 1846 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1847 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1848 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1849 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1850 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1851 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1852 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1853 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1854 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1855 // CHECK3-NEXT: ret void 1856 // 1857 // 1858 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1859 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 1860 // CHECK3-NEXT: entry: 1861 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1862 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1863 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 1864 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 1865 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 1866 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 1867 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1868 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1869 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1870 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1871 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1872 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1873 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1874 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1875 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1876 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 1877 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 1878 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 1879 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 1880 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 1881 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 1882 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 1883 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 1884 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1885 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1886 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1887 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1888 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1889 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1890 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1891 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1892 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1893 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1894 // CHECK3: cond.true: 1895 // CHECK3-NEXT: br label [[COND_END:%.*]] 1896 // CHECK3: cond.false: 1897 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1898 // CHECK3-NEXT: br label [[COND_END]] 1899 // CHECK3: cond.end: 1900 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1901 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1902 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1903 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1904 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1905 // CHECK3: omp.inner.for.cond: 1906 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1907 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1908 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1909 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1910 // CHECK3: omp.inner.for.body: 1911 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1912 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1913 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 1914 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1915 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 1916 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1917 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 1918 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1919 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 1920 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1921 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 1922 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 1923 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 1924 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 1925 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1926 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 1927 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 1928 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 1929 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 1930 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1931 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 1932 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 1933 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1934 // CHECK3: omp.body.continue: 1935 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1936 // CHECK3: omp.inner.for.inc: 1937 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1938 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 1939 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 1940 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1941 // CHECK3: omp.inner.for.end: 1942 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1943 // CHECK3: omp.loop.exit: 1944 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1945 // CHECK3-NEXT: ret void 1946 // 1947 // 1948 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1949 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1950 // CHECK3-NEXT: entry: 1951 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1952 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1953 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1954 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1955 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1956 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1957 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1958 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1959 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1960 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1961 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1962 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1963 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 1964 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 1965 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 1966 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 1967 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1968 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 1969 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 1970 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1971 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 1972 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 1973 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1974 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1975 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1976 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 1977 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 1978 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1979 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 1980 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 1981 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1982 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1983 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1984 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 1985 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 1986 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1987 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1988 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 1989 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1990 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1991 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1992 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 1993 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 1994 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1995 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 1996 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 1997 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1998 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1999 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2000 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2001 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 2002 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2003 // CHECK3-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 2004 // CHECK3-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2005 // CHECK3: omp_offload.failed: 2006 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 2007 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2008 // CHECK3: omp_offload.cont: 2009 // CHECK3-NEXT: ret void 2010 // 2011 // 2012 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 2013 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 2014 // CHECK3-NEXT: entry: 2015 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2016 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2017 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2018 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2019 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2020 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2021 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2022 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2023 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2024 // CHECK3-NEXT: ret void 2025 // 2026 // 2027 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 2028 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 2029 // CHECK3-NEXT: entry: 2030 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2031 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2032 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 2033 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 2034 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 2035 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 2036 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2037 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2038 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2039 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2040 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2041 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2042 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2043 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2044 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2045 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 2046 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 2047 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 2048 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 2049 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 2050 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 2051 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 2052 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 2053 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2054 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2055 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2056 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2057 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2058 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2059 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2060 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2061 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 2062 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2063 // CHECK3: cond.true: 2064 // CHECK3-NEXT: br label [[COND_END:%.*]] 2065 // CHECK3: cond.false: 2066 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2067 // CHECK3-NEXT: br label [[COND_END]] 2068 // CHECK3: cond.end: 2069 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2070 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2071 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2072 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2073 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2074 // CHECK3: omp.inner.for.cond: 2075 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2076 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2077 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2078 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2079 // CHECK3: omp.inner.for.body: 2080 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2081 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 2082 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 2083 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4 2084 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 2085 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2086 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 2087 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2088 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 2089 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2090 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 2091 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2092 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 2093 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 2094 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2095 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 2096 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2097 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 2098 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 2099 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2100 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 2101 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 2102 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2103 // CHECK3: omp.body.continue: 2104 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2105 // CHECK3: omp.inner.for.inc: 2106 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2107 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 2108 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2109 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2110 // CHECK3: omp.inner.for.end: 2111 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2112 // CHECK3: omp.loop.exit: 2113 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2114 // CHECK3-NEXT: ret void 2115 // 2116 // 2117 // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 2118 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2119 // CHECK3-NEXT: entry: 2120 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2121 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2122 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2123 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2124 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2125 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2126 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2127 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2128 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2129 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2130 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2131 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2132 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 2133 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 2134 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 2135 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 2136 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2137 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 2138 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 2139 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2140 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 2141 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 2142 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2143 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 2144 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2145 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 2146 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 2147 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2148 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 2149 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 2150 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2151 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 2152 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2153 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 2154 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 2155 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2156 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 2157 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 2158 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2159 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 2160 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2161 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 2162 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 2163 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2164 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 2165 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 2166 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2167 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 2168 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2169 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2170 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 2171 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2172 // CHECK3-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 2173 // CHECK3-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2174 // CHECK3: omp_offload.failed: 2175 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 2176 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2177 // CHECK3: omp_offload.cont: 2178 // CHECK3-NEXT: ret void 2179 // 2180 // 2181 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 2182 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 2183 // CHECK3-NEXT: entry: 2184 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2185 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2186 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2187 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2188 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2189 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2190 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2191 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2192 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2193 // CHECK3-NEXT: ret void 2194 // 2195 // 2196 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 2197 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 2198 // CHECK3-NEXT: entry: 2199 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2200 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2201 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 2202 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 2203 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 2204 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 2205 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2206 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2207 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2208 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2209 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2210 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2211 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2212 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2213 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2214 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 2215 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 2216 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 2217 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 2218 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 2219 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 2220 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 2221 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 2222 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2223 // CHECK3-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 2224 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2225 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2226 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2227 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2228 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 2229 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2230 // CHECK3: omp.dispatch.cond: 2231 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2232 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 2233 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2234 // CHECK3: cond.true: 2235 // CHECK3-NEXT: br label [[COND_END:%.*]] 2236 // CHECK3: cond.false: 2237 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2238 // CHECK3-NEXT: br label [[COND_END]] 2239 // CHECK3: cond.end: 2240 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2241 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2242 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2243 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2244 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2245 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2246 // CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 2247 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2248 // CHECK3: omp.dispatch.body: 2249 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2250 // CHECK3: omp.inner.for.cond: 2251 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 2252 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 2253 // CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 2254 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2255 // CHECK3: omp.inner.for.body: 2256 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 2257 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 2258 // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 2259 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 2260 // CHECK3-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 2261 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 2262 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 2263 // CHECK3-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 2264 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 2265 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 2266 // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 2267 // CHECK3-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10 2268 // CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 2269 // CHECK3-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 2270 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 2271 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 2272 // CHECK3-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 2273 // CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 2274 // CHECK3-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 2275 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 2276 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 2277 // CHECK3-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10 2278 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2279 // CHECK3: omp.body.continue: 2280 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2281 // CHECK3: omp.inner.for.inc: 2282 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 2283 // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 2284 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 2285 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 2286 // CHECK3: omp.inner.for.end: 2287 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2288 // CHECK3: omp.dispatch.inc: 2289 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2290 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2291 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 2292 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 2293 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2294 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2295 // CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 2296 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 2297 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2298 // CHECK3: omp.dispatch.end: 2299 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2300 // CHECK3-NEXT: ret void 2301 // 2302 // 2303 // CHECK3-LABEL: define {{[^@]+}}@_Z12test_precondv 2304 // CHECK3-SAME: () #[[ATTR0]] { 2305 // CHECK3-NEXT: entry: 2306 // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 2307 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2308 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2309 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2310 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2311 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 2312 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2313 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2314 // CHECK3-NEXT: store i8 0, i8* [[A]], align 1 2315 // CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 2316 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[A_CASTED]] to i8* 2317 // CHECK3-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 2318 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2319 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2320 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 2321 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 2322 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2323 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 2324 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 2325 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2326 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4 2327 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2328 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2329 // CHECK3-NEXT: [[TMP9:%.*]] = load i8, i8* [[A]], align 1 2330 // CHECK3-NEXT: store i8 [[TMP9]], i8* [[DOTCAPTURE_EXPR_]], align 1 2331 // CHECK3-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2332 // CHECK3-NEXT: [[CONV2:%.*]] = sext i8 [[TMP10]] to i32 2333 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV2]] 2334 // CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 2335 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 2336 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2337 // CHECK3-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 2338 // CHECK3-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2339 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2340 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 2341 // CHECK3-NEXT: [[TMP12:%.*]] = zext i32 [[ADD5]] to i64 2342 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP12]]) 2343 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2344 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2345 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2346 // CHECK3: omp_offload.failed: 2347 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i32 [[TMP1]]) #[[ATTR2]] 2348 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2349 // CHECK3: omp_offload.cont: 2350 // CHECK3-NEXT: ret void 2351 // 2352 // 2353 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 2354 // CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { 2355 // CHECK3-NEXT: entry: 2356 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2357 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2358 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* 2359 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]]) 2360 // CHECK3-NEXT: ret void 2361 // 2362 // 2363 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 2364 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 2365 // CHECK3-NEXT: entry: 2366 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2367 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2368 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 2369 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2370 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 2371 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2372 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2373 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 2374 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2375 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2376 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2377 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2378 // CHECK3-NEXT: [[I5:%.*]] = alloca i8, align 1 2379 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2380 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2381 // CHECK3-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 2382 // CHECK3-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 2383 // CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 2384 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 2385 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2386 // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 2387 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 2388 // CHECK3-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 2389 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 2390 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2391 // CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 2392 // CHECK3-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2393 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2394 // CHECK3-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 2395 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2396 // CHECK3-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 2397 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 2398 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2399 // CHECK3: omp.precond.then: 2400 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2401 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2402 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 2403 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2404 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2405 // CHECK3-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2406 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 2407 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2408 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2409 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2410 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 2411 // CHECK3-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2412 // CHECK3: cond.true: 2413 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2414 // CHECK3-NEXT: br label [[COND_END:%.*]] 2415 // CHECK3: cond.false: 2416 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2417 // CHECK3-NEXT: br label [[COND_END]] 2418 // CHECK3: cond.end: 2419 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 2420 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2421 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2422 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 2423 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2424 // CHECK3: omp.inner.for.cond: 2425 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2426 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2427 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 2428 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2429 // CHECK3: omp.inner.for.body: 2430 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2431 // CHECK3-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 2432 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2433 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 2434 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 2435 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 2436 // CHECK3-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 2437 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2438 // CHECK3: omp.body.continue: 2439 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2440 // CHECK3: omp.inner.for.inc: 2441 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2442 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 2443 // CHECK3-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 2444 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2445 // CHECK3: omp.inner.for.end: 2446 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2447 // CHECK3: omp.loop.exit: 2448 // CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2449 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 2450 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 2451 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 2452 // CHECK3: omp.precond.end: 2453 // CHECK3-NEXT: ret void 2454 // 2455 // 2456 // CHECK3-LABEL: define {{[^@]+}}@_Z4fintv 2457 // CHECK3-SAME: () #[[ATTR0]] { 2458 // CHECK3-NEXT: entry: 2459 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() 2460 // CHECK3-NEXT: ret i32 [[CALL]] 2461 // 2462 // 2463 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 2464 // CHECK3-SAME: () #[[ATTR0]] comdat { 2465 // CHECK3-NEXT: entry: 2466 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2467 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2468 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2469 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2470 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2471 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2472 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 2473 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 2474 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2475 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 2476 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2477 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2478 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 2479 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 2480 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2481 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 2482 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 2483 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2484 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4 2485 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2486 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2487 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 2488 // CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2489 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 2490 // CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2491 // CHECK3: omp_offload.failed: 2492 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i32 [[TMP1]]) #[[ATTR2]] 2493 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2494 // CHECK3: omp_offload.cont: 2495 // CHECK3-NEXT: ret i32 0 2496 // 2497 // 2498 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 2499 // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] { 2500 // CHECK3-NEXT: entry: 2501 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2502 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2503 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2504 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 2505 // CHECK3-NEXT: ret void 2506 // 2507 // 2508 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 2509 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 2510 // CHECK3-NEXT: entry: 2511 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2512 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2513 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 2514 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2515 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2516 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2517 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2518 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2519 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2520 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2521 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2522 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2523 // CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 2524 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 2525 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2526 // CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 2527 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2528 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2529 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 2530 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2531 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2532 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2533 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 2534 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2535 // CHECK3: omp.dispatch.cond: 2536 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2537 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2538 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2539 // CHECK3: cond.true: 2540 // CHECK3-NEXT: br label [[COND_END:%.*]] 2541 // CHECK3: cond.false: 2542 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2543 // CHECK3-NEXT: br label [[COND_END]] 2544 // CHECK3: cond.end: 2545 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2546 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2547 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2548 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 2549 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2550 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2551 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2552 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2553 // CHECK3: omp.dispatch.body: 2554 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2555 // CHECK3: omp.inner.for.cond: 2556 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2557 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 2558 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2559 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2560 // CHECK3: omp.inner.for.body: 2561 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2562 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 2563 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2564 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 2565 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2566 // CHECK3: omp.body.continue: 2567 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2568 // CHECK3: omp.inner.for.inc: 2569 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2570 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 2571 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2572 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 2573 // CHECK3: omp.inner.for.end: 2574 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2575 // CHECK3: omp.dispatch.inc: 2576 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2577 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2578 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 2579 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 2580 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2581 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2582 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 2583 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 2584 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2585 // CHECK3: omp.dispatch.end: 2586 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 2587 // CHECK3-NEXT: ret void 2588 // 2589 // 2590 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2591 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 2592 // CHECK3-NEXT: entry: 2593 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 2594 // CHECK3-NEXT: ret void 2595 // 2596 // 2597 // CHECK4-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 2598 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 2599 // CHECK4-NEXT: entry: 2600 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2601 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2602 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2603 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2604 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2605 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2606 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2607 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2608 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2609 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2610 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2611 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2612 // CHECK4-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 2613 // CHECK4-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 2614 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 2615 // CHECK4-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 2616 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2617 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 2618 // CHECK4-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 2619 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2620 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 2621 // CHECK4-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 2622 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2623 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4 2624 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2625 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 2626 // CHECK4-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 2627 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2628 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 2629 // CHECK4-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 2630 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2631 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4 2632 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2633 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 2634 // CHECK4-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 2635 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2636 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 2637 // CHECK4-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 2638 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2639 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4 2640 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2641 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 2642 // CHECK4-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 2643 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2644 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 2645 // CHECK4-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 2646 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2647 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4 2648 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2649 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2650 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 2651 // CHECK4-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2652 // CHECK4-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 2653 // CHECK4-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2654 // CHECK4: omp_offload.failed: 2655 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2:[0-9]+]] 2656 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 2657 // CHECK4: omp_offload.cont: 2658 // CHECK4-NEXT: ret void 2659 // 2660 // 2661 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 2662 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { 2663 // CHECK4-NEXT: entry: 2664 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2665 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2666 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2667 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2668 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2669 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2670 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2671 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2672 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2673 // CHECK4-NEXT: ret void 2674 // 2675 // 2676 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 2677 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 2678 // CHECK4-NEXT: entry: 2679 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2680 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2681 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 2682 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 2683 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 2684 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 2685 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2686 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2687 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2688 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2689 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2690 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2691 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 2692 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2693 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2694 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 2695 // CHECK4-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 2696 // CHECK4-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 2697 // CHECK4-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 2698 // CHECK4-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 2699 // CHECK4-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 2700 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 2701 // CHECK4-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 2702 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2703 // CHECK4-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2704 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2705 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2706 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2707 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2708 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2709 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2710 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 2711 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2712 // CHECK4: cond.true: 2713 // CHECK4-NEXT: br label [[COND_END:%.*]] 2714 // CHECK4: cond.false: 2715 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2716 // CHECK4-NEXT: br label [[COND_END]] 2717 // CHECK4: cond.end: 2718 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2719 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2720 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2721 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2722 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2723 // CHECK4: omp.inner.for.cond: 2724 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2725 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2726 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2727 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2728 // CHECK4: omp.inner.for.body: 2729 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2730 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 2731 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 2732 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2733 // CHECK4-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 2734 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2735 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 2736 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2737 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 2738 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2739 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 2740 // CHECK4-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2741 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 2742 // CHECK4-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 2743 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2744 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 2745 // CHECK4-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2746 // CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 2747 // CHECK4-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 2748 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2749 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 2750 // CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 2751 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2752 // CHECK4: omp.body.continue: 2753 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2754 // CHECK4: omp.inner.for.inc: 2755 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2756 // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 2757 // CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 2758 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2759 // CHECK4: omp.inner.for.end: 2760 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2761 // CHECK4: omp.loop.exit: 2762 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2763 // CHECK4-NEXT: ret void 2764 // 2765 // 2766 // CHECK4-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 2767 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2768 // CHECK4-NEXT: entry: 2769 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2770 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2771 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2772 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2773 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2774 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2775 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2776 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2777 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2778 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2779 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2780 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2781 // CHECK4-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 2782 // CHECK4-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 2783 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 2784 // CHECK4-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 2785 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2786 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 2787 // CHECK4-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 2788 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2789 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 2790 // CHECK4-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 2791 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2792 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4 2793 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2794 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 2795 // CHECK4-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 2796 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2797 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 2798 // CHECK4-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 2799 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2800 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4 2801 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2802 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 2803 // CHECK4-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 2804 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2805 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 2806 // CHECK4-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 2807 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2808 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4 2809 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2810 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 2811 // CHECK4-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 2812 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2813 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 2814 // CHECK4-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 2815 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2816 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4 2817 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2818 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2819 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 2820 // CHECK4-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2821 // CHECK4-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 2822 // CHECK4-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2823 // CHECK4: omp_offload.failed: 2824 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 2825 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 2826 // CHECK4: omp_offload.cont: 2827 // CHECK4-NEXT: ret void 2828 // 2829 // 2830 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 2831 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 2832 // CHECK4-NEXT: entry: 2833 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2834 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2835 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2836 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2837 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2838 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2839 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2840 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2841 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2842 // CHECK4-NEXT: ret void 2843 // 2844 // 2845 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 2846 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 2847 // CHECK4-NEXT: entry: 2848 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2849 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2850 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 2851 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 2852 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 2853 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 2854 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2855 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2856 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2857 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2858 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2859 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2860 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 2861 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2862 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2863 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 2864 // CHECK4-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 2865 // CHECK4-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 2866 // CHECK4-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 2867 // CHECK4-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 2868 // CHECK4-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 2869 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 2870 // CHECK4-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 2871 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2872 // CHECK4-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2873 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2874 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2875 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2876 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2877 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2878 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2879 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 2880 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2881 // CHECK4: cond.true: 2882 // CHECK4-NEXT: br label [[COND_END:%.*]] 2883 // CHECK4: cond.false: 2884 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2885 // CHECK4-NEXT: br label [[COND_END]] 2886 // CHECK4: cond.end: 2887 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2888 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2889 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2890 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2891 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2892 // CHECK4: omp.inner.for.cond: 2893 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2894 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2895 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2896 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2897 // CHECK4: omp.inner.for.body: 2898 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2899 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 2900 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 2901 // CHECK4-NEXT: store i32 [[SUB]], i32* [[I]], align 4 2902 // CHECK4-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 2903 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2904 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 2905 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2906 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 2907 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2908 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 2909 // CHECK4-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2910 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 2911 // CHECK4-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 2912 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2913 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 2914 // CHECK4-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2915 // CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 2916 // CHECK4-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 2917 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2918 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 2919 // CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 2920 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2921 // CHECK4: omp.body.continue: 2922 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2923 // CHECK4: omp.inner.for.inc: 2924 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2925 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 2926 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2927 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2928 // CHECK4: omp.inner.for.end: 2929 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2930 // CHECK4: omp.loop.exit: 2931 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2932 // CHECK4-NEXT: ret void 2933 // 2934 // 2935 // CHECK4-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 2936 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2937 // CHECK4-NEXT: entry: 2938 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2939 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2940 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2941 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2942 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2943 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2944 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2945 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2946 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2947 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2948 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2949 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2950 // CHECK4-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 2951 // CHECK4-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 2952 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 2953 // CHECK4-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 2954 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2955 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 2956 // CHECK4-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 2957 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2958 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 2959 // CHECK4-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 2960 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2961 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4 2962 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2963 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 2964 // CHECK4-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 2965 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2966 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 2967 // CHECK4-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 2968 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2969 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4 2970 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2971 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 2972 // CHECK4-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 2973 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2974 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 2975 // CHECK4-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 2976 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2977 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4 2978 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2979 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 2980 // CHECK4-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 2981 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2982 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 2983 // CHECK4-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 2984 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2985 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4 2986 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2987 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2988 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 2989 // CHECK4-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2990 // CHECK4-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 2991 // CHECK4-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2992 // CHECK4: omp_offload.failed: 2993 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 2994 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 2995 // CHECK4: omp_offload.cont: 2996 // CHECK4-NEXT: ret void 2997 // 2998 // 2999 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 3000 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 3001 // CHECK4-NEXT: entry: 3002 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 3003 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 3004 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 3005 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 3006 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 3007 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 3008 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 3009 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 3010 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3011 // CHECK4-NEXT: ret void 3012 // 3013 // 3014 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 3015 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 3016 // CHECK4-NEXT: entry: 3017 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3018 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3019 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 3020 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 3021 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 3022 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 3023 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3024 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 3025 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3026 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3027 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3028 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3029 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 3030 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3031 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3032 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 3033 // CHECK4-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 3034 // CHECK4-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 3035 // CHECK4-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 3036 // CHECK4-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 3037 // CHECK4-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 3038 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 3039 // CHECK4-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 3040 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3041 // CHECK4-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 3042 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3043 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3044 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3045 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3046 // CHECK4-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 3047 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3048 // CHECK4: omp.dispatch.cond: 3049 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3050 // CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 3051 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3052 // CHECK4: cond.true: 3053 // CHECK4-NEXT: br label [[COND_END:%.*]] 3054 // CHECK4: cond.false: 3055 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3056 // CHECK4-NEXT: br label [[COND_END]] 3057 // CHECK4: cond.end: 3058 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3059 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3060 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3061 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3062 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3063 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3064 // CHECK4-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 3065 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3066 // CHECK4: omp.dispatch.body: 3067 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3068 // CHECK4: omp.inner.for.cond: 3069 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 3070 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 3071 // CHECK4-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 3072 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3073 // CHECK4: omp.inner.for.body: 3074 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 3075 // CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 3076 // CHECK4-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 3077 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 3078 // CHECK4-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 3079 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 3080 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 3081 // CHECK4-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 3082 // CHECK4-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 3083 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 3084 // CHECK4-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 3085 // CHECK4-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10 3086 // CHECK4-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 3087 // CHECK4-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 3088 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 3089 // CHECK4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 3090 // CHECK4-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 3091 // CHECK4-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 3092 // CHECK4-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 3093 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 3094 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 3095 // CHECK4-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10 3096 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3097 // CHECK4: omp.body.continue: 3098 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3099 // CHECK4: omp.inner.for.inc: 3100 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 3101 // CHECK4-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 3102 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 3103 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 3104 // CHECK4: omp.inner.for.end: 3105 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3106 // CHECK4: omp.dispatch.inc: 3107 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3108 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3109 // CHECK4-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 3110 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 3111 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3112 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3113 // CHECK4-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 3114 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 3115 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 3116 // CHECK4: omp.dispatch.end: 3117 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3118 // CHECK4-NEXT: ret void 3119 // 3120 // 3121 // CHECK4-LABEL: define {{[^@]+}}@_Z12test_precondv 3122 // CHECK4-SAME: () #[[ATTR0]] { 3123 // CHECK4-NEXT: entry: 3124 // CHECK4-NEXT: [[A:%.*]] = alloca i8, align 1 3125 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3126 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 3127 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 3128 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 3129 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 3130 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3131 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3132 // CHECK4-NEXT: store i8 0, i8* [[A]], align 1 3133 // CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 3134 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[A_CASTED]] to i8* 3135 // CHECK4-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 3136 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3137 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3138 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 3139 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 3140 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3141 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 3142 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 3143 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3144 // CHECK4-NEXT: store i8* null, i8** [[TMP6]], align 4 3145 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3146 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3147 // CHECK4-NEXT: [[TMP9:%.*]] = load i8, i8* [[A]], align 1 3148 // CHECK4-NEXT: store i8 [[TMP9]], i8* [[DOTCAPTURE_EXPR_]], align 1 3149 // CHECK4-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3150 // CHECK4-NEXT: [[CONV2:%.*]] = sext i8 [[TMP10]] to i32 3151 // CHECK4-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV2]] 3152 // CHECK4-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 3153 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 3154 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3155 // CHECK4-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 3156 // CHECK4-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3157 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3158 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 3159 // CHECK4-NEXT: [[TMP12:%.*]] = zext i32 [[ADD5]] to i64 3160 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP12]]) 3161 // CHECK4-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3162 // CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 3163 // CHECK4-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3164 // CHECK4: omp_offload.failed: 3165 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i32 [[TMP1]]) #[[ATTR2]] 3166 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 3167 // CHECK4: omp_offload.cont: 3168 // CHECK4-NEXT: ret void 3169 // 3170 // 3171 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 3172 // CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { 3173 // CHECK4-NEXT: entry: 3174 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3175 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3176 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* 3177 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]]) 3178 // CHECK4-NEXT: ret void 3179 // 3180 // 3181 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 3182 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 3183 // CHECK4-NEXT: entry: 3184 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3185 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3186 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 3187 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3188 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 3189 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3190 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3191 // CHECK4-NEXT: [[I:%.*]] = alloca i8, align 1 3192 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3193 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3194 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3195 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3196 // CHECK4-NEXT: [[I5:%.*]] = alloca i8, align 1 3197 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3198 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3199 // CHECK4-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 3200 // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 3201 // CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 3202 // CHECK4-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 3203 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3204 // CHECK4-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 3205 // CHECK4-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 3206 // CHECK4-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 3207 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 3208 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3209 // CHECK4-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 3210 // CHECK4-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3211 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3212 // CHECK4-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 3213 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3214 // CHECK4-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 3215 // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 3216 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3217 // CHECK4: omp.precond.then: 3218 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3219 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3220 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 3221 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3222 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3223 // CHECK4-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3224 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 3225 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3226 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3227 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3228 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 3229 // CHECK4-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3230 // CHECK4: cond.true: 3231 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3232 // CHECK4-NEXT: br label [[COND_END:%.*]] 3233 // CHECK4: cond.false: 3234 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3235 // CHECK4-NEXT: br label [[COND_END]] 3236 // CHECK4: cond.end: 3237 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 3238 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3239 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3240 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 3241 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3242 // CHECK4: omp.inner.for.cond: 3243 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3244 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3245 // CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 3246 // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3247 // CHECK4: omp.inner.for.body: 3248 // CHECK4-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3249 // CHECK4-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 3250 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3251 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 3252 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 3253 // CHECK4-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 3254 // CHECK4-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 3255 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3256 // CHECK4: omp.body.continue: 3257 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3258 // CHECK4: omp.inner.for.inc: 3259 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3260 // CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 3261 // CHECK4-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 3262 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 3263 // CHECK4: omp.inner.for.end: 3264 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3265 // CHECK4: omp.loop.exit: 3266 // CHECK4-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3267 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 3268 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 3269 // CHECK4-NEXT: br label [[OMP_PRECOND_END]] 3270 // CHECK4: omp.precond.end: 3271 // CHECK4-NEXT: ret void 3272 // 3273 // 3274 // CHECK4-LABEL: define {{[^@]+}}@_Z4fintv 3275 // CHECK4-SAME: () #[[ATTR0]] { 3276 // CHECK4-NEXT: entry: 3277 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() 3278 // CHECK4-NEXT: ret i32 [[CALL]] 3279 // 3280 // 3281 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 3282 // CHECK4-SAME: () #[[ATTR0]] comdat { 3283 // CHECK4-NEXT: entry: 3284 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 3285 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3286 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 3287 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 3288 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 3289 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 3290 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 3291 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 3292 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3293 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 3294 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3295 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3296 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 3297 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 3298 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3299 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 3300 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 3301 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3302 // CHECK4-NEXT: store i8* null, i8** [[TMP6]], align 4 3303 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3304 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3305 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 3306 // CHECK4-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3307 // CHECK4-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 3308 // CHECK4-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3309 // CHECK4: omp_offload.failed: 3310 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i32 [[TMP1]]) #[[ATTR2]] 3311 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 3312 // CHECK4: omp_offload.cont: 3313 // CHECK4-NEXT: ret i32 0 3314 // 3315 // 3316 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 3317 // CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] { 3318 // CHECK4-NEXT: entry: 3319 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3320 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3321 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3322 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 3323 // CHECK4-NEXT: ret void 3324 // 3325 // 3326 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 3327 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 3328 // CHECK4-NEXT: entry: 3329 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3330 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3331 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 3332 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3333 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 3334 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3335 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3336 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3337 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3338 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 3339 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3340 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3341 // CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 3342 // CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 3343 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3344 // CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 3345 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3346 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3347 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 3348 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3349 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3350 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 3351 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 3352 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3353 // CHECK4: omp.dispatch.cond: 3354 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3355 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 3356 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3357 // CHECK4: cond.true: 3358 // CHECK4-NEXT: br label [[COND_END:%.*]] 3359 // CHECK4: cond.false: 3360 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3361 // CHECK4-NEXT: br label [[COND_END]] 3362 // CHECK4: cond.end: 3363 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 3364 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3365 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3366 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 3367 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3368 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3369 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 3370 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3371 // CHECK4: omp.dispatch.body: 3372 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3373 // CHECK4: omp.inner.for.cond: 3374 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 3375 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 3376 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3377 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3378 // CHECK4: omp.inner.for.body: 3379 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 3380 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 3381 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3382 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 3383 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3384 // CHECK4: omp.body.continue: 3385 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3386 // CHECK4: omp.inner.for.inc: 3387 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 3388 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 3389 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 3390 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 3391 // CHECK4: omp.inner.for.end: 3392 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3393 // CHECK4: omp.dispatch.inc: 3394 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3395 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3396 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 3397 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 3398 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3399 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3400 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 3401 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 3402 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 3403 // CHECK4: omp.dispatch.end: 3404 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 3405 // CHECK4-NEXT: ret void 3406 // 3407 // 3408 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3409 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 3410 // CHECK4-NEXT: entry: 3411 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 3412 // CHECK4-NEXT: ret void 3413 // 3414 // 3415 // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 3416 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 3417 // CHECK5-NEXT: entry: 3418 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3419 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3420 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3421 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3422 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 3423 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 3424 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 3425 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3426 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3427 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3428 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3429 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3430 // CHECK5-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 3431 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 3432 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 3433 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 3434 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3435 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 3436 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 3437 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3438 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 3439 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 3440 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3441 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8 3442 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3443 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 3444 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 3445 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3446 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 3447 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 3448 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3449 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 3450 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3451 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 3452 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 3453 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3454 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 3455 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 3456 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3457 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 3458 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3459 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 3460 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 3461 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3462 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 3463 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 3464 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 3465 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 3466 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3467 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3468 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 3469 // CHECK5-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3470 // CHECK5-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 3471 // CHECK5-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3472 // CHECK5: omp_offload.failed: 3473 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2:[0-9]+]] 3474 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 3475 // CHECK5: omp_offload.cont: 3476 // CHECK5-NEXT: ret void 3477 // 3478 // 3479 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 3480 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { 3481 // CHECK5-NEXT: entry: 3482 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3483 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3484 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3485 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3486 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3487 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3488 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3489 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3490 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3491 // CHECK5-NEXT: ret void 3492 // 3493 // 3494 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. 3495 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 3496 // CHECK5-NEXT: entry: 3497 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3498 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3499 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3500 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3501 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3502 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3503 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3504 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3505 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3506 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3507 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3508 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3509 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3510 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3511 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3512 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3513 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3514 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3515 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3516 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 3517 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 3518 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 3519 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 3520 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3521 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 3522 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3523 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3524 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3525 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3526 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3527 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3528 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 3529 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3530 // CHECK5: cond.true: 3531 // CHECK5-NEXT: br label [[COND_END:%.*]] 3532 // CHECK5: cond.false: 3533 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3534 // CHECK5-NEXT: br label [[COND_END]] 3535 // CHECK5: cond.end: 3536 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3537 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3538 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3539 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3540 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3541 // CHECK5: omp.inner.for.cond: 3542 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3543 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3544 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3545 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3546 // CHECK5: omp.inner.for.body: 3547 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3548 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 3549 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 3550 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3551 // CHECK5-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 3552 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 3553 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 3554 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 3555 // CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 3556 // CHECK5-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 3557 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 3558 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 3559 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 3560 // CHECK5-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 3561 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 3562 // CHECK5-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 3563 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 3564 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 3565 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 3566 // CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 3567 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 3568 // CHECK5-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 3569 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 3570 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 3571 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 3572 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 3573 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3574 // CHECK5: omp.body.continue: 3575 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3576 // CHECK5: omp.inner.for.inc: 3577 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3578 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 3579 // CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 3580 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 3581 // CHECK5: omp.inner.for.end: 3582 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3583 // CHECK5: omp.loop.exit: 3584 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3585 // CHECK5-NEXT: ret void 3586 // 3587 // 3588 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 3589 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3590 // CHECK5-NEXT: entry: 3591 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3592 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3593 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3594 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3595 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 3596 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 3597 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 3598 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3599 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3600 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3601 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3602 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3603 // CHECK5-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 3604 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 3605 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 3606 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 3607 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3608 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 3609 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 3610 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3611 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 3612 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 3613 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3614 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8 3615 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3616 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 3617 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 3618 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3619 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 3620 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 3621 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3622 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 3623 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3624 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 3625 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 3626 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3627 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 3628 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 3629 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3630 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 3631 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3632 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 3633 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 3634 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3635 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 3636 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 3637 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 3638 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 3639 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3640 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3641 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 3642 // CHECK5-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3643 // CHECK5-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 3644 // CHECK5-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3645 // CHECK5: omp_offload.failed: 3646 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 3647 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 3648 // CHECK5: omp_offload.cont: 3649 // CHECK5-NEXT: ret void 3650 // 3651 // 3652 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 3653 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 3654 // CHECK5-NEXT: entry: 3655 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3656 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3657 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3658 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3659 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3660 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3661 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3662 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3663 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3664 // CHECK5-NEXT: ret void 3665 // 3666 // 3667 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 3668 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 3669 // CHECK5-NEXT: entry: 3670 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3671 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3672 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3673 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3674 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3675 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3676 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3677 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3678 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3679 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3680 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3681 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3682 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3683 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3684 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3685 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3686 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3687 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3688 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3689 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 3690 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 3691 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 3692 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 3693 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3694 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 3695 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3696 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3697 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3698 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3699 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3700 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3701 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 3702 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3703 // CHECK5: cond.true: 3704 // CHECK5-NEXT: br label [[COND_END:%.*]] 3705 // CHECK5: cond.false: 3706 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3707 // CHECK5-NEXT: br label [[COND_END]] 3708 // CHECK5: cond.end: 3709 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3710 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3711 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3712 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3713 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3714 // CHECK5: omp.inner.for.cond: 3715 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3716 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3717 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3718 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3719 // CHECK5: omp.inner.for.body: 3720 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3721 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 3722 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 3723 // CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4 3724 // CHECK5-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 3725 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 3726 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 3727 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 3728 // CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 3729 // CHECK5-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 3730 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 3731 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 3732 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 3733 // CHECK5-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 3734 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 3735 // CHECK5-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 3736 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 3737 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 3738 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 3739 // CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 3740 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 3741 // CHECK5-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 3742 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 3743 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 3744 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 3745 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 3746 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3747 // CHECK5: omp.body.continue: 3748 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3749 // CHECK5: omp.inner.for.inc: 3750 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3751 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 3752 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 3753 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 3754 // CHECK5: omp.inner.for.end: 3755 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3756 // CHECK5: omp.loop.exit: 3757 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3758 // CHECK5-NEXT: ret void 3759 // 3760 // 3761 // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 3762 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3763 // CHECK5-NEXT: entry: 3764 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3765 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3766 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3767 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3768 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 3769 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 3770 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 3771 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3772 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3773 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3774 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3775 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3776 // CHECK5-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 3777 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 3778 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 3779 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 3780 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3781 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 3782 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 3783 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3784 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 3785 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 3786 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3787 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8 3788 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3789 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 3790 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 3791 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3792 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 3793 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 3794 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3795 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 3796 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3797 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 3798 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 3799 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3800 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 3801 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 3802 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3803 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 3804 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3805 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 3806 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 3807 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3808 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 3809 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 3810 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 3811 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 3812 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3813 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3814 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 3815 // CHECK5-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3816 // CHECK5-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 3817 // CHECK5-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3818 // CHECK5: omp_offload.failed: 3819 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 3820 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 3821 // CHECK5: omp_offload.cont: 3822 // CHECK5-NEXT: ret void 3823 // 3824 // 3825 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 3826 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 3827 // CHECK5-NEXT: entry: 3828 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3829 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3830 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3831 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3832 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3833 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3834 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3835 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3836 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3837 // CHECK5-NEXT: ret void 3838 // 3839 // 3840 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 3841 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 3842 // CHECK5-NEXT: entry: 3843 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3844 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3845 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3846 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3847 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3848 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3849 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3850 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3851 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3852 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3853 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3854 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3855 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3856 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3857 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3858 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3859 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3860 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3861 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3862 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 3863 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 3864 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 3865 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 3866 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3867 // CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 3868 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3869 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3870 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3871 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3872 // CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 3873 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3874 // CHECK5: omp.dispatch.cond: 3875 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3876 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 3877 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3878 // CHECK5: cond.true: 3879 // CHECK5-NEXT: br label [[COND_END:%.*]] 3880 // CHECK5: cond.false: 3881 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3882 // CHECK5-NEXT: br label [[COND_END]] 3883 // CHECK5: cond.end: 3884 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3885 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3886 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3887 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3888 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3889 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3890 // CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 3891 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3892 // CHECK5: omp.dispatch.body: 3893 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3894 // CHECK5: omp.inner.for.cond: 3895 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3896 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 3897 // CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 3898 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3899 // CHECK5: omp.inner.for.body: 3900 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3901 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 3902 // CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 3903 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 3904 // CHECK5-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 3905 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 3906 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 3907 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 3908 // CHECK5-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 3909 // CHECK5-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 3910 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 3911 // CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 3912 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 3913 // CHECK5-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9 3914 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 3915 // CHECK5-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 3916 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 3917 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 3918 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 3919 // CHECK5-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !9 3920 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 3921 // CHECK5-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 3922 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 3923 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 3924 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 3925 // CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 3926 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3927 // CHECK5: omp.body.continue: 3928 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3929 // CHECK5: omp.inner.for.inc: 3930 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3931 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 3932 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3933 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 3934 // CHECK5: omp.inner.for.end: 3935 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3936 // CHECK5: omp.dispatch.inc: 3937 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3938 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3939 // CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 3940 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 3941 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3942 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3943 // CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 3944 // CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 3945 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 3946 // CHECK5: omp.dispatch.end: 3947 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3948 // CHECK5-NEXT: ret void 3949 // 3950 // 3951 // CHECK5-LABEL: define {{[^@]+}}@_Z12test_precondv 3952 // CHECK5-SAME: () #[[ATTR0]] { 3953 // CHECK5-NEXT: entry: 3954 // CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1 3955 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3956 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 3957 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 3958 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 3959 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 3960 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3961 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3962 // CHECK5-NEXT: store i8 0, i8* [[A]], align 1 3963 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 3964 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* 3965 // CHECK5-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 3966 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 3967 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3968 // CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 3969 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 3970 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3971 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 3972 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 3973 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3974 // CHECK5-NEXT: store i8* null, i8** [[TMP6]], align 8 3975 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3976 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3977 // CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[A]], align 1 3978 // CHECK5-NEXT: store i8 [[TMP9]], i8* [[DOTCAPTURE_EXPR_]], align 1 3979 // CHECK5-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3980 // CHECK5-NEXT: [[CONV2:%.*]] = sext i8 [[TMP10]] to i32 3981 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV2]] 3982 // CHECK5-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 3983 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 3984 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3985 // CHECK5-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 3986 // CHECK5-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3987 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3988 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 3989 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[ADD5]] to i64 3990 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP12]]) 3991 // CHECK5-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3992 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 3993 // CHECK5-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3994 // CHECK5: omp_offload.failed: 3995 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i64 [[TMP1]]) #[[ATTR2]] 3996 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 3997 // CHECK5: omp_offload.cont: 3998 // CHECK5-NEXT: ret void 3999 // 4000 // 4001 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 4002 // CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { 4003 // CHECK5-NEXT: entry: 4004 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4005 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4006 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* 4007 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]]) 4008 // CHECK5-NEXT: ret void 4009 // 4010 // 4011 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 4012 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 4013 // CHECK5-NEXT: entry: 4014 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4015 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4016 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 4017 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4018 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 4019 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4020 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4021 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 4022 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4023 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4024 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4025 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4026 // CHECK5-NEXT: [[I5:%.*]] = alloca i8, align 1 4027 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4028 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4029 // CHECK5-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 4030 // CHECK5-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 4031 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 4032 // CHECK5-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 4033 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4034 // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 4035 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 4036 // CHECK5-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 4037 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 4038 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4039 // CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 4040 // CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4041 // CHECK5-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4042 // CHECK5-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 4043 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4044 // CHECK5-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 4045 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 4046 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 4047 // CHECK5: omp.precond.then: 4048 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4049 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4050 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 4051 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4052 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4053 // CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4054 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 4055 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4056 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4057 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4058 // CHECK5-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 4059 // CHECK5-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4060 // CHECK5: cond.true: 4061 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4062 // CHECK5-NEXT: br label [[COND_END:%.*]] 4063 // CHECK5: cond.false: 4064 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4065 // CHECK5-NEXT: br label [[COND_END]] 4066 // CHECK5: cond.end: 4067 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 4068 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4069 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4070 // CHECK5-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 4071 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4072 // CHECK5: omp.inner.for.cond: 4073 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4074 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4075 // CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 4076 // CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4077 // CHECK5: omp.inner.for.body: 4078 // CHECK5-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4079 // CHECK5-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 4080 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4081 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 4082 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 4083 // CHECK5-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 4084 // CHECK5-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 4085 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4086 // CHECK5: omp.body.continue: 4087 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4088 // CHECK5: omp.inner.for.inc: 4089 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4090 // CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 4091 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 4092 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 4093 // CHECK5: omp.inner.for.end: 4094 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4095 // CHECK5: omp.loop.exit: 4096 // CHECK5-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4097 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 4098 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 4099 // CHECK5-NEXT: br label [[OMP_PRECOND_END]] 4100 // CHECK5: omp.precond.end: 4101 // CHECK5-NEXT: ret void 4102 // 4103 // 4104 // CHECK5-LABEL: define {{[^@]+}}@_Z4fintv 4105 // CHECK5-SAME: () #[[ATTR0]] { 4106 // CHECK5-NEXT: entry: 4107 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() 4108 // CHECK5-NEXT: ret i32 [[CALL]] 4109 // 4110 // 4111 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 4112 // CHECK5-SAME: () #[[ATTR0]] comdat { 4113 // CHECK5-NEXT: entry: 4114 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 4115 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4116 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 4117 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 4118 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 4119 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4120 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 4121 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 4122 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4123 // CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 4124 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4125 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4126 // CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 4127 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 4128 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4129 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 4130 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 4131 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4132 // CHECK5-NEXT: store i8* null, i8** [[TMP6]], align 8 4133 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4134 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4135 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 4136 // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4137 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 4138 // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4139 // CHECK5: omp_offload.failed: 4140 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i64 [[TMP1]]) #[[ATTR2]] 4141 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4142 // CHECK5: omp_offload.cont: 4143 // CHECK5-NEXT: ret i32 0 4144 // 4145 // 4146 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 4147 // CHECK5-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] { 4148 // CHECK5-NEXT: entry: 4149 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4150 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4151 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4152 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 4153 // CHECK5-NEXT: ret void 4154 // 4155 // 4156 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 4157 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 4158 // CHECK5-NEXT: entry: 4159 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4160 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4161 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 4162 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4163 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4164 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4165 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4166 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4167 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4168 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 4169 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4170 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4171 // CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 4172 // CHECK5-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 4173 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4174 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 4175 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4176 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4177 // CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 4178 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 4179 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4180 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 4181 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 4182 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4183 // CHECK5: omp.dispatch.cond: 4184 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4185 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 4186 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4187 // CHECK5: cond.true: 4188 // CHECK5-NEXT: br label [[COND_END:%.*]] 4189 // CHECK5: cond.false: 4190 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4191 // CHECK5-NEXT: br label [[COND_END]] 4192 // CHECK5: cond.end: 4193 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 4194 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4195 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4196 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 4197 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4198 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4199 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 4200 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4201 // CHECK5: omp.dispatch.body: 4202 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4203 // CHECK5: omp.inner.for.cond: 4204 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 4205 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 4206 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 4207 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4208 // CHECK5: omp.inner.for.body: 4209 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 4210 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 4211 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4212 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 4213 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4214 // CHECK5: omp.body.continue: 4215 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4216 // CHECK5: omp.inner.for.inc: 4217 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 4218 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 4219 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 4220 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 4221 // CHECK5: omp.inner.for.end: 4222 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4223 // CHECK5: omp.dispatch.inc: 4224 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4225 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4226 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 4227 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 4228 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4229 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4230 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 4231 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 4232 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 4233 // CHECK5: omp.dispatch.end: 4234 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 4235 // CHECK5-NEXT: ret void 4236 // 4237 // 4238 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4239 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 4240 // CHECK5-NEXT: entry: 4241 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1) 4242 // CHECK5-NEXT: ret void 4243 // 4244 // 4245 // CHECK6-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 4246 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 4247 // CHECK6-NEXT: entry: 4248 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4249 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4250 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4251 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4252 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 4253 // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 4254 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 4255 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 4256 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4257 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4258 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4259 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4260 // CHECK6-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 4261 // CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 4262 // CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 4263 // CHECK6-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 4264 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4265 // CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 4266 // CHECK6-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 4267 // CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4268 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 4269 // CHECK6-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 4270 // CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4271 // CHECK6-NEXT: store i8* null, i8** [[TMP8]], align 8 4272 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4273 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 4274 // CHECK6-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 4275 // CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4276 // CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 4277 // CHECK6-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 4278 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4279 // CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8 4280 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4281 // CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 4282 // CHECK6-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 4283 // CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4284 // CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 4285 // CHECK6-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 4286 // CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4287 // CHECK6-NEXT: store i8* null, i8** [[TMP18]], align 8 4288 // CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4289 // CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 4290 // CHECK6-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 4291 // CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4292 // CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 4293 // CHECK6-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 4294 // CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4295 // CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 4296 // CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4297 // CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4298 // CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 4299 // CHECK6-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4300 // CHECK6-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 4301 // CHECK6-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4302 // CHECK6: omp_offload.failed: 4303 // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2:[0-9]+]] 4304 // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] 4305 // CHECK6: omp_offload.cont: 4306 // CHECK6-NEXT: ret void 4307 // 4308 // 4309 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 4310 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { 4311 // CHECK6-NEXT: entry: 4312 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4313 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4314 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4315 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4316 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4317 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4318 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4319 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4320 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 4321 // CHECK6-NEXT: ret void 4322 // 4323 // 4324 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. 4325 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 4326 // CHECK6-NEXT: entry: 4327 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4328 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4329 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4330 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 4331 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 4332 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 4333 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4334 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 4335 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4336 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4337 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4338 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4339 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 4340 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4341 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4342 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4343 // CHECK6-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 4344 // CHECK6-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 4345 // CHECK6-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 4346 // CHECK6-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 4347 // CHECK6-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 4348 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 4349 // CHECK6-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 4350 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4351 // CHECK6-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 4352 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4353 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4354 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4355 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4356 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4357 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4358 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 4359 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4360 // CHECK6: cond.true: 4361 // CHECK6-NEXT: br label [[COND_END:%.*]] 4362 // CHECK6: cond.false: 4363 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4364 // CHECK6-NEXT: br label [[COND_END]] 4365 // CHECK6: cond.end: 4366 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 4367 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4368 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4369 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 4370 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4371 // CHECK6: omp.inner.for.cond: 4372 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4373 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4374 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 4375 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4376 // CHECK6: omp.inner.for.body: 4377 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4378 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 4379 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 4380 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4381 // CHECK6-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 4382 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 4383 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 4384 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 4385 // CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 4386 // CHECK6-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 4387 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 4388 // CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 4389 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 4390 // CHECK6-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 4391 // CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 4392 // CHECK6-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 4393 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 4394 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 4395 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 4396 // CHECK6-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 4397 // CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 4398 // CHECK6-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 4399 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 4400 // CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 4401 // CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 4402 // CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 4403 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4404 // CHECK6: omp.body.continue: 4405 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4406 // CHECK6: omp.inner.for.inc: 4407 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4408 // CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 4409 // CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 4410 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 4411 // CHECK6: omp.inner.for.end: 4412 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4413 // CHECK6: omp.loop.exit: 4414 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 4415 // CHECK6-NEXT: ret void 4416 // 4417 // 4418 // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 4419 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 4420 // CHECK6-NEXT: entry: 4421 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4422 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4423 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4424 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4425 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 4426 // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 4427 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 4428 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 4429 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4430 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4431 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4432 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4433 // CHECK6-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 4434 // CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 4435 // CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 4436 // CHECK6-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 4437 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4438 // CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 4439 // CHECK6-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 4440 // CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4441 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 4442 // CHECK6-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 4443 // CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4444 // CHECK6-NEXT: store i8* null, i8** [[TMP8]], align 8 4445 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4446 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 4447 // CHECK6-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 4448 // CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4449 // CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 4450 // CHECK6-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 4451 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4452 // CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8 4453 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4454 // CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 4455 // CHECK6-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 4456 // CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4457 // CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 4458 // CHECK6-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 4459 // CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4460 // CHECK6-NEXT: store i8* null, i8** [[TMP18]], align 8 4461 // CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4462 // CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 4463 // CHECK6-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 4464 // CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4465 // CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 4466 // CHECK6-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 4467 // CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4468 // CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 4469 // CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4470 // CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4471 // CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 4472 // CHECK6-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4473 // CHECK6-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 4474 // CHECK6-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4475 // CHECK6: omp_offload.failed: 4476 // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 4477 // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] 4478 // CHECK6: omp_offload.cont: 4479 // CHECK6-NEXT: ret void 4480 // 4481 // 4482 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 4483 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 4484 // CHECK6-NEXT: entry: 4485 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4486 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4487 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4488 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4489 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4490 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4491 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4492 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4493 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 4494 // CHECK6-NEXT: ret void 4495 // 4496 // 4497 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 4498 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 4499 // CHECK6-NEXT: entry: 4500 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4501 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4502 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4503 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 4504 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 4505 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 4506 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4507 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 4508 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4509 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4510 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4511 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4512 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 4513 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4514 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4515 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4516 // CHECK6-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 4517 // CHECK6-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 4518 // CHECK6-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 4519 // CHECK6-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 4520 // CHECK6-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 4521 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 4522 // CHECK6-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 4523 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4524 // CHECK6-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 4525 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4526 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4527 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4528 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4529 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4530 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4531 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 4532 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4533 // CHECK6: cond.true: 4534 // CHECK6-NEXT: br label [[COND_END:%.*]] 4535 // CHECK6: cond.false: 4536 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4537 // CHECK6-NEXT: br label [[COND_END]] 4538 // CHECK6: cond.end: 4539 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 4540 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4541 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4542 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 4543 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4544 // CHECK6: omp.inner.for.cond: 4545 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4546 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4547 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 4548 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4549 // CHECK6: omp.inner.for.body: 4550 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4551 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 4552 // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 4553 // CHECK6-NEXT: store i32 [[SUB]], i32* [[I]], align 4 4554 // CHECK6-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 4555 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 4556 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 4557 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 4558 // CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 4559 // CHECK6-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 4560 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 4561 // CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 4562 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 4563 // CHECK6-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 4564 // CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 4565 // CHECK6-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 4566 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 4567 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 4568 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 4569 // CHECK6-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 4570 // CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 4571 // CHECK6-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 4572 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 4573 // CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 4574 // CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 4575 // CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 4576 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4577 // CHECK6: omp.body.continue: 4578 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4579 // CHECK6: omp.inner.for.inc: 4580 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4581 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 4582 // CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 4583 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 4584 // CHECK6: omp.inner.for.end: 4585 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4586 // CHECK6: omp.loop.exit: 4587 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 4588 // CHECK6-NEXT: ret void 4589 // 4590 // 4591 // CHECK6-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 4592 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 4593 // CHECK6-NEXT: entry: 4594 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4595 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4596 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4597 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4598 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 4599 // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 4600 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 4601 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 4602 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4603 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4604 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4605 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4606 // CHECK6-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 4607 // CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 4608 // CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 4609 // CHECK6-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 4610 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4611 // CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 4612 // CHECK6-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 4613 // CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4614 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 4615 // CHECK6-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 4616 // CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4617 // CHECK6-NEXT: store i8* null, i8** [[TMP8]], align 8 4618 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4619 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 4620 // CHECK6-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 4621 // CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4622 // CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 4623 // CHECK6-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 4624 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4625 // CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8 4626 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4627 // CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 4628 // CHECK6-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 4629 // CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4630 // CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 4631 // CHECK6-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 4632 // CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4633 // CHECK6-NEXT: store i8* null, i8** [[TMP18]], align 8 4634 // CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4635 // CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 4636 // CHECK6-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 4637 // CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4638 // CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 4639 // CHECK6-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 4640 // CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4641 // CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8 4642 // CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4643 // CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4644 // CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 4645 // CHECK6-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4646 // CHECK6-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 4647 // CHECK6-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4648 // CHECK6: omp_offload.failed: 4649 // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 4650 // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] 4651 // CHECK6: omp_offload.cont: 4652 // CHECK6-NEXT: ret void 4653 // 4654 // 4655 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 4656 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 4657 // CHECK6-NEXT: entry: 4658 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4659 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4660 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4661 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4662 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4663 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4664 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4665 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4666 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 4667 // CHECK6-NEXT: ret void 4668 // 4669 // 4670 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 4671 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 4672 // CHECK6-NEXT: entry: 4673 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4674 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4675 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4676 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 4677 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 4678 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 4679 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4680 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 4681 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4682 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4683 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4684 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4685 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 4686 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4687 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4688 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4689 // CHECK6-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 4690 // CHECK6-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 4691 // CHECK6-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 4692 // CHECK6-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 4693 // CHECK6-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 4694 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 4695 // CHECK6-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 4696 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4697 // CHECK6-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 4698 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4699 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4700 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4701 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4702 // CHECK6-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 4703 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4704 // CHECK6: omp.dispatch.cond: 4705 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4706 // CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 4707 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4708 // CHECK6: cond.true: 4709 // CHECK6-NEXT: br label [[COND_END:%.*]] 4710 // CHECK6: cond.false: 4711 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4712 // CHECK6-NEXT: br label [[COND_END]] 4713 // CHECK6: cond.end: 4714 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 4715 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4716 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4717 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 4718 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4719 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4720 // CHECK6-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 4721 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4722 // CHECK6: omp.dispatch.body: 4723 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4724 // CHECK6: omp.inner.for.cond: 4725 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 4726 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 4727 // CHECK6-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 4728 // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4729 // CHECK6: omp.inner.for.body: 4730 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 4731 // CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 4732 // CHECK6-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 4733 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 4734 // CHECK6-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 4735 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 4736 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 4737 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 4738 // CHECK6-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 4739 // CHECK6-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 4740 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 4741 // CHECK6-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 4742 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 4743 // CHECK6-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9 4744 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 4745 // CHECK6-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 4746 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 4747 // CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 4748 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 4749 // CHECK6-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !9 4750 // CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 4751 // CHECK6-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 4752 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 4753 // CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 4754 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 4755 // CHECK6-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 4756 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4757 // CHECK6: omp.body.continue: 4758 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4759 // CHECK6: omp.inner.for.inc: 4760 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 4761 // CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 4762 // CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 4763 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 4764 // CHECK6: omp.inner.for.end: 4765 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4766 // CHECK6: omp.dispatch.inc: 4767 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4768 // CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4769 // CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 4770 // CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 4771 // CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4772 // CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4773 // CHECK6-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 4774 // CHECK6-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 4775 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 4776 // CHECK6: omp.dispatch.end: 4777 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 4778 // CHECK6-NEXT: ret void 4779 // 4780 // 4781 // CHECK6-LABEL: define {{[^@]+}}@_Z12test_precondv 4782 // CHECK6-SAME: () #[[ATTR0]] { 4783 // CHECK6-NEXT: entry: 4784 // CHECK6-NEXT: [[A:%.*]] = alloca i8, align 1 4785 // CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4786 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 4787 // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 4788 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 4789 // CHECK6-NEXT: [[TMP:%.*]] = alloca i8, align 1 4790 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4791 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4792 // CHECK6-NEXT: store i8 0, i8* [[A]], align 1 4793 // CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 4794 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* 4795 // CHECK6-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 4796 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4797 // CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4798 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 4799 // CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 4800 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4801 // CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 4802 // CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 4803 // CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4804 // CHECK6-NEXT: store i8* null, i8** [[TMP6]], align 8 4805 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4806 // CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4807 // CHECK6-NEXT: [[TMP9:%.*]] = load i8, i8* [[A]], align 1 4808 // CHECK6-NEXT: store i8 [[TMP9]], i8* [[DOTCAPTURE_EXPR_]], align 1 4809 // CHECK6-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4810 // CHECK6-NEXT: [[CONV2:%.*]] = sext i8 [[TMP10]] to i32 4811 // CHECK6-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV2]] 4812 // CHECK6-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 4813 // CHECK6-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 4814 // CHECK6-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4815 // CHECK6-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 4816 // CHECK6-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4817 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4818 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 4819 // CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[ADD5]] to i64 4820 // CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP12]]) 4821 // CHECK6-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4822 // CHECK6-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 4823 // CHECK6-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4824 // CHECK6: omp_offload.failed: 4825 // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i64 [[TMP1]]) #[[ATTR2]] 4826 // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] 4827 // CHECK6: omp_offload.cont: 4828 // CHECK6-NEXT: ret void 4829 // 4830 // 4831 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 4832 // CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { 4833 // CHECK6-NEXT: entry: 4834 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4835 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4836 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* 4837 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]]) 4838 // CHECK6-NEXT: ret void 4839 // 4840 // 4841 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 4842 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 4843 // CHECK6-NEXT: entry: 4844 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4845 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4846 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 4847 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4848 // CHECK6-NEXT: [[TMP:%.*]] = alloca i8, align 1 4849 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4850 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4851 // CHECK6-NEXT: [[I:%.*]] = alloca i8, align 1 4852 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4853 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4854 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4855 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4856 // CHECK6-NEXT: [[I5:%.*]] = alloca i8, align 1 4857 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4858 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4859 // CHECK6-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 4860 // CHECK6-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 4861 // CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 4862 // CHECK6-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 4863 // CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4864 // CHECK6-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 4865 // CHECK6-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 4866 // CHECK6-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 4867 // CHECK6-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 4868 // CHECK6-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4869 // CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 4870 // CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4871 // CHECK6-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4872 // CHECK6-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 4873 // CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4874 // CHECK6-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 4875 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 4876 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 4877 // CHECK6: omp.precond.then: 4878 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4879 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4880 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 4881 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4882 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4883 // CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4884 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 4885 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4886 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4887 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4888 // CHECK6-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 4889 // CHECK6-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4890 // CHECK6: cond.true: 4891 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4892 // CHECK6-NEXT: br label [[COND_END:%.*]] 4893 // CHECK6: cond.false: 4894 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4895 // CHECK6-NEXT: br label [[COND_END]] 4896 // CHECK6: cond.end: 4897 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 4898 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4899 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4900 // CHECK6-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 4901 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4902 // CHECK6: omp.inner.for.cond: 4903 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4904 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4905 // CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 4906 // CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4907 // CHECK6: omp.inner.for.body: 4908 // CHECK6-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4909 // CHECK6-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 4910 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4911 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 4912 // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 4913 // CHECK6-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 4914 // CHECK6-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 4915 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4916 // CHECK6: omp.body.continue: 4917 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4918 // CHECK6: omp.inner.for.inc: 4919 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4920 // CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 4921 // CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 4922 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 4923 // CHECK6: omp.inner.for.end: 4924 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4925 // CHECK6: omp.loop.exit: 4926 // CHECK6-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4927 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 4928 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 4929 // CHECK6-NEXT: br label [[OMP_PRECOND_END]] 4930 // CHECK6: omp.precond.end: 4931 // CHECK6-NEXT: ret void 4932 // 4933 // 4934 // CHECK6-LABEL: define {{[^@]+}}@_Z4fintv 4935 // CHECK6-SAME: () #[[ATTR0]] { 4936 // CHECK6-NEXT: entry: 4937 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() 4938 // CHECK6-NEXT: ret i32 [[CALL]] 4939 // 4940 // 4941 // CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 4942 // CHECK6-SAME: () #[[ATTR0]] comdat { 4943 // CHECK6-NEXT: entry: 4944 // CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 4945 // CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4946 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 4947 // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 4948 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 4949 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 4950 // CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 4951 // CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 4952 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4953 // CHECK6-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 4954 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4955 // CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4956 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 4957 // CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 4958 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4959 // CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 4960 // CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 4961 // CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4962 // CHECK6-NEXT: store i8* null, i8** [[TMP6]], align 8 4963 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4964 // CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4965 // CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 4966 // CHECK6-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4967 // CHECK6-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 4968 // CHECK6-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4969 // CHECK6: omp_offload.failed: 4970 // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i64 [[TMP1]]) #[[ATTR2]] 4971 // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] 4972 // CHECK6: omp_offload.cont: 4973 // CHECK6-NEXT: ret i32 0 4974 // 4975 // 4976 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 4977 // CHECK6-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] { 4978 // CHECK6-NEXT: entry: 4979 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4980 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4981 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4982 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 4983 // CHECK6-NEXT: ret void 4984 // 4985 // 4986 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 4987 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 4988 // CHECK6-NEXT: entry: 4989 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4990 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4991 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 4992 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4993 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 4994 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4995 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4996 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4997 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4998 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 4999 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5000 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5001 // CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 5002 // CHECK6-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 5003 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5004 // CHECK6-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 5005 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5006 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5007 // CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 5008 // CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5009 // CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5010 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 5011 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 5012 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5013 // CHECK6: omp.dispatch.cond: 5014 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5015 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 5016 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5017 // CHECK6: cond.true: 5018 // CHECK6-NEXT: br label [[COND_END:%.*]] 5019 // CHECK6: cond.false: 5020 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5021 // CHECK6-NEXT: br label [[COND_END]] 5022 // CHECK6: cond.end: 5023 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 5024 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5025 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5026 // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 5027 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5028 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5029 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 5030 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5031 // CHECK6: omp.dispatch.body: 5032 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5033 // CHECK6: omp.inner.for.cond: 5034 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 5035 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 5036 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 5037 // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5038 // CHECK6: omp.inner.for.body: 5039 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 5040 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 5041 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5042 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 5043 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5044 // CHECK6: omp.body.continue: 5045 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5046 // CHECK6: omp.inner.for.inc: 5047 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 5048 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 5049 // CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 5050 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 5051 // CHECK6: omp.inner.for.end: 5052 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5053 // CHECK6: omp.dispatch.inc: 5054 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5055 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 5056 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 5057 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 5058 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5059 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 5060 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 5061 // CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 5062 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 5063 // CHECK6: omp.dispatch.end: 5064 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 5065 // CHECK6-NEXT: ret void 5066 // 5067 // 5068 // CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5069 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] { 5070 // CHECK6-NEXT: entry: 5071 // CHECK6-NEXT: call void @__tgt_register_requires(i64 1) 5072 // CHECK6-NEXT: ret void 5073 // 5074 // 5075 // CHECK7-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 5076 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 5077 // CHECK7-NEXT: entry: 5078 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5079 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 5080 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 5081 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 5082 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 5083 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 5084 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 5085 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5086 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5087 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 5088 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 5089 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 5090 // CHECK7-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 5091 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 5092 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 5093 // CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 5094 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5095 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 5096 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 5097 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5098 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 5099 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 5100 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5101 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4 5102 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5103 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 5104 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 5105 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5106 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 5107 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 5108 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5109 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 5110 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5111 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 5112 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 5113 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5114 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 5115 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 5116 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5117 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 5118 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 5119 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 5120 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 5121 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 5122 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 5123 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 5124 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 5125 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 5126 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5127 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5128 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 5129 // CHECK7-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5130 // CHECK7-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 5131 // CHECK7-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5132 // CHECK7: omp_offload.failed: 5133 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2:[0-9]+]] 5134 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 5135 // CHECK7: omp_offload.cont: 5136 // CHECK7-NEXT: ret void 5137 // 5138 // 5139 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 5140 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { 5141 // CHECK7-NEXT: entry: 5142 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5143 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 5144 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 5145 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 5146 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5147 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 5148 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 5149 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 5150 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 5151 // CHECK7-NEXT: ret void 5152 // 5153 // 5154 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. 5155 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 5156 // CHECK7-NEXT: entry: 5157 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5158 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5159 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 5160 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 5161 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 5162 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 5163 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5164 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5165 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5166 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5167 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5168 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5169 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5170 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5171 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5172 // CHECK7-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 5173 // CHECK7-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 5174 // CHECK7-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 5175 // CHECK7-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 5176 // CHECK7-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 5177 // CHECK7-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 5178 // CHECK7-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 5179 // CHECK7-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 5180 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5181 // CHECK7-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 5182 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5183 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5184 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5185 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 5186 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5187 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5188 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 5189 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5190 // CHECK7: cond.true: 5191 // CHECK7-NEXT: br label [[COND_END:%.*]] 5192 // CHECK7: cond.false: 5193 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5194 // CHECK7-NEXT: br label [[COND_END]] 5195 // CHECK7: cond.end: 5196 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 5197 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5198 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5199 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 5200 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5201 // CHECK7: omp.inner.for.cond: 5202 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5203 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5204 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 5205 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5206 // CHECK7: omp.inner.for.body: 5207 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5208 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 5209 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 5210 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 5211 // CHECK7-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 5212 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 5213 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 5214 // CHECK7-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 5215 // CHECK7-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 5216 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 5217 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 5218 // CHECK7-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 5219 // CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 5220 // CHECK7-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 5221 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 5222 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 5223 // CHECK7-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 5224 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 5225 // CHECK7-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 5226 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 5227 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 5228 // CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 5229 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5230 // CHECK7: omp.body.continue: 5231 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5232 // CHECK7: omp.inner.for.inc: 5233 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5234 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 5235 // CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 5236 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] 5237 // CHECK7: omp.inner.for.end: 5238 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5239 // CHECK7: omp.loop.exit: 5240 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 5241 // CHECK7-NEXT: ret void 5242 // 5243 // 5244 // CHECK7-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 5245 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 5246 // CHECK7-NEXT: entry: 5247 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5248 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 5249 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 5250 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 5251 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 5252 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 5253 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 5254 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5255 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5256 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 5257 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 5258 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 5259 // CHECK7-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 5260 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 5261 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 5262 // CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 5263 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5264 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 5265 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 5266 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5267 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 5268 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 5269 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5270 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4 5271 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5272 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 5273 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 5274 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5275 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 5276 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 5277 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5278 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 5279 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5280 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 5281 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 5282 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5283 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 5284 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 5285 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5286 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 5287 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 5288 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 5289 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 5290 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 5291 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 5292 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 5293 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 5294 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 5295 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5296 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5297 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 5298 // CHECK7-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5299 // CHECK7-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 5300 // CHECK7-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5301 // CHECK7: omp_offload.failed: 5302 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 5303 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 5304 // CHECK7: omp_offload.cont: 5305 // CHECK7-NEXT: ret void 5306 // 5307 // 5308 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 5309 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 5310 // CHECK7-NEXT: entry: 5311 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5312 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 5313 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 5314 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 5315 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5316 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 5317 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 5318 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 5319 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 5320 // CHECK7-NEXT: ret void 5321 // 5322 // 5323 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 5324 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 5325 // CHECK7-NEXT: entry: 5326 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5327 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5328 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 5329 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 5330 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 5331 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 5332 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5333 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5334 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5335 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5336 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5337 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5338 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5339 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5340 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5341 // CHECK7-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 5342 // CHECK7-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 5343 // CHECK7-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 5344 // CHECK7-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 5345 // CHECK7-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 5346 // CHECK7-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 5347 // CHECK7-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 5348 // CHECK7-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 5349 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5350 // CHECK7-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 5351 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5352 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5353 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5354 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 5355 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5356 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5357 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 5358 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5359 // CHECK7: cond.true: 5360 // CHECK7-NEXT: br label [[COND_END:%.*]] 5361 // CHECK7: cond.false: 5362 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5363 // CHECK7-NEXT: br label [[COND_END]] 5364 // CHECK7: cond.end: 5365 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 5366 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5367 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5368 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 5369 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5370 // CHECK7: omp.inner.for.cond: 5371 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5372 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5373 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 5374 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5375 // CHECK7: omp.inner.for.body: 5376 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5377 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 5378 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 5379 // CHECK7-NEXT: store i32 [[SUB]], i32* [[I]], align 4 5380 // CHECK7-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 5381 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 5382 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 5383 // CHECK7-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 5384 // CHECK7-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 5385 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 5386 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 5387 // CHECK7-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 5388 // CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 5389 // CHECK7-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 5390 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 5391 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 5392 // CHECK7-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 5393 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 5394 // CHECK7-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 5395 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 5396 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 5397 // CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 5398 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5399 // CHECK7: omp.body.continue: 5400 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5401 // CHECK7: omp.inner.for.inc: 5402 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5403 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 5404 // CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 5405 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] 5406 // CHECK7: omp.inner.for.end: 5407 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5408 // CHECK7: omp.loop.exit: 5409 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 5410 // CHECK7-NEXT: ret void 5411 // 5412 // 5413 // CHECK7-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 5414 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 5415 // CHECK7-NEXT: entry: 5416 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5417 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 5418 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 5419 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 5420 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 5421 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 5422 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 5423 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5424 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5425 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 5426 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 5427 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 5428 // CHECK7-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 5429 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 5430 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 5431 // CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 5432 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5433 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 5434 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 5435 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5436 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 5437 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 5438 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5439 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4 5440 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5441 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 5442 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 5443 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5444 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 5445 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 5446 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5447 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 5448 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5449 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 5450 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 5451 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5452 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 5453 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 5454 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5455 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 5456 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 5457 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 5458 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 5459 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 5460 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 5461 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 5462 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 5463 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 5464 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5465 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5466 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 5467 // CHECK7-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5468 // CHECK7-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 5469 // CHECK7-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5470 // CHECK7: omp_offload.failed: 5471 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 5472 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 5473 // CHECK7: omp_offload.cont: 5474 // CHECK7-NEXT: ret void 5475 // 5476 // 5477 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 5478 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 5479 // CHECK7-NEXT: entry: 5480 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5481 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 5482 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 5483 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 5484 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5485 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 5486 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 5487 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 5488 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 5489 // CHECK7-NEXT: ret void 5490 // 5491 // 5492 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 5493 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 5494 // CHECK7-NEXT: entry: 5495 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5496 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5497 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 5498 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 5499 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 5500 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 5501 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5502 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5503 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5504 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5505 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5506 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5507 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5508 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5509 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5510 // CHECK7-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 5511 // CHECK7-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 5512 // CHECK7-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 5513 // CHECK7-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 5514 // CHECK7-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 5515 // CHECK7-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 5516 // CHECK7-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 5517 // CHECK7-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 5518 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5519 // CHECK7-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 5520 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5521 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5522 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5523 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 5524 // CHECK7-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 5525 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5526 // CHECK7: omp.dispatch.cond: 5527 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5528 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 5529 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5530 // CHECK7: cond.true: 5531 // CHECK7-NEXT: br label [[COND_END:%.*]] 5532 // CHECK7: cond.false: 5533 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5534 // CHECK7-NEXT: br label [[COND_END]] 5535 // CHECK7: cond.end: 5536 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 5537 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5538 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5539 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 5540 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5541 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5542 // CHECK7-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 5543 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5544 // CHECK7: omp.dispatch.body: 5545 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5546 // CHECK7: omp.inner.for.cond: 5547 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 5548 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 5549 // CHECK7-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 5550 // CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5551 // CHECK7: omp.inner.for.body: 5552 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 5553 // CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 5554 // CHECK7-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 5555 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 5556 // CHECK7-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 5557 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 5558 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 5559 // CHECK7-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 5560 // CHECK7-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 5561 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 5562 // CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 5563 // CHECK7-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10 5564 // CHECK7-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 5565 // CHECK7-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 5566 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 5567 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 5568 // CHECK7-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 5569 // CHECK7-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 5570 // CHECK7-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 5571 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 5572 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 5573 // CHECK7-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10 5574 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5575 // CHECK7: omp.body.continue: 5576 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5577 // CHECK7: omp.inner.for.inc: 5578 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 5579 // CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 5580 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 5581 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 5582 // CHECK7: omp.inner.for.end: 5583 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5584 // CHECK7: omp.dispatch.inc: 5585 // CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5586 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 5587 // CHECK7-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 5588 // CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 5589 // CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5590 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 5591 // CHECK7-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 5592 // CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 5593 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 5594 // CHECK7: omp.dispatch.end: 5595 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 5596 // CHECK7-NEXT: ret void 5597 // 5598 // 5599 // CHECK7-LABEL: define {{[^@]+}}@_Z12test_precondv 5600 // CHECK7-SAME: () #[[ATTR0]] { 5601 // CHECK7-NEXT: entry: 5602 // CHECK7-NEXT: [[A:%.*]] = alloca i8, align 1 5603 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5604 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 5605 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 5606 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 5607 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1 5608 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 5609 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5610 // CHECK7-NEXT: store i8 0, i8* [[A]], align 1 5611 // CHECK7-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 5612 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[A_CASTED]] to i8* 5613 // CHECK7-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 5614 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 5615 // CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5616 // CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 5617 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 5618 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5619 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 5620 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 5621 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5622 // CHECK7-NEXT: store i8* null, i8** [[TMP6]], align 4 5623 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5624 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5625 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[A]], align 1 5626 // CHECK7-NEXT: store i8 [[TMP9]], i8* [[DOTCAPTURE_EXPR_]], align 1 5627 // CHECK7-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 5628 // CHECK7-NEXT: [[CONV2:%.*]] = sext i8 [[TMP10]] to i32 5629 // CHECK7-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV2]] 5630 // CHECK7-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 5631 // CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 5632 // CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 5633 // CHECK7-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 5634 // CHECK7-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 5635 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 5636 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 5637 // CHECK7-NEXT: [[TMP12:%.*]] = zext i32 [[ADD5]] to i64 5638 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP12]]) 5639 // CHECK7-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5640 // CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5641 // CHECK7-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5642 // CHECK7: omp_offload.failed: 5643 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i32 [[TMP1]]) #[[ATTR2]] 5644 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 5645 // CHECK7: omp_offload.cont: 5646 // CHECK7-NEXT: ret void 5647 // 5648 // 5649 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 5650 // CHECK7-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { 5651 // CHECK7-NEXT: entry: 5652 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5653 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5654 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* 5655 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]]) 5656 // CHECK7-NEXT: ret void 5657 // 5658 // 5659 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 5660 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 5661 // CHECK7-NEXT: entry: 5662 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5663 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5664 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 5665 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5666 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1 5667 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 5668 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5669 // CHECK7-NEXT: [[I:%.*]] = alloca i8, align 1 5670 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5671 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5672 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5673 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5674 // CHECK7-NEXT: [[I5:%.*]] = alloca i8, align 1 5675 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5676 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5677 // CHECK7-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 5678 // CHECK7-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 5679 // CHECK7-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 5680 // CHECK7-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 5681 // CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 5682 // CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 5683 // CHECK7-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 5684 // CHECK7-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 5685 // CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 5686 // CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 5687 // CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 5688 // CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 5689 // CHECK7-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 5690 // CHECK7-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 5691 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 5692 // CHECK7-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 5693 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 5694 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 5695 // CHECK7: omp.precond.then: 5696 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5697 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 5698 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 5699 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5700 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5701 // CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5702 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 5703 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5704 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5705 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 5706 // CHECK7-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 5707 // CHECK7-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5708 // CHECK7: cond.true: 5709 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 5710 // CHECK7-NEXT: br label [[COND_END:%.*]] 5711 // CHECK7: cond.false: 5712 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5713 // CHECK7-NEXT: br label [[COND_END]] 5714 // CHECK7: cond.end: 5715 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 5716 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5717 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5718 // CHECK7-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 5719 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5720 // CHECK7: omp.inner.for.cond: 5721 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5722 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5723 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 5724 // CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5725 // CHECK7: omp.inner.for.body: 5726 // CHECK7-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 5727 // CHECK7-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 5728 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5729 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 5730 // CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 5731 // CHECK7-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 5732 // CHECK7-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 5733 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5734 // CHECK7: omp.body.continue: 5735 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5736 // CHECK7: omp.inner.for.inc: 5737 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5738 // CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 5739 // CHECK7-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 5740 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]] 5741 // CHECK7: omp.inner.for.end: 5742 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5743 // CHECK7: omp.loop.exit: 5744 // CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5745 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 5746 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 5747 // CHECK7-NEXT: br label [[OMP_PRECOND_END]] 5748 // CHECK7: omp.precond.end: 5749 // CHECK7-NEXT: ret void 5750 // 5751 // 5752 // CHECK7-LABEL: define {{[^@]+}}@_Z4fintv 5753 // CHECK7-SAME: () #[[ATTR0]] { 5754 // CHECK7-NEXT: entry: 5755 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() 5756 // CHECK7-NEXT: ret i32 [[CALL]] 5757 // 5758 // 5759 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 5760 // CHECK7-SAME: () #[[ATTR0]] comdat { 5761 // CHECK7-NEXT: entry: 5762 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 5763 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5764 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 5765 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 5766 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 5767 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5768 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 5769 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 5770 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5771 // CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 5772 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5773 // CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5774 // CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 5775 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 5776 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5777 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 5778 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 5779 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5780 // CHECK7-NEXT: store i8* null, i8** [[TMP6]], align 4 5781 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5782 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5783 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 5784 // CHECK7-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5785 // CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 5786 // CHECK7-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5787 // CHECK7: omp_offload.failed: 5788 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i32 [[TMP1]]) #[[ATTR2]] 5789 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 5790 // CHECK7: omp_offload.cont: 5791 // CHECK7-NEXT: ret i32 0 5792 // 5793 // 5794 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 5795 // CHECK7-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] { 5796 // CHECK7-NEXT: entry: 5797 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5798 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5799 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5800 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 5801 // CHECK7-NEXT: ret void 5802 // 5803 // 5804 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 5805 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 5806 // CHECK7-NEXT: entry: 5807 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5808 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5809 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 5810 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5811 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5812 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5813 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5814 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5815 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5816 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5817 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5818 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5819 // CHECK7-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 5820 // CHECK7-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 5821 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5822 // CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 5823 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5824 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5825 // CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 5826 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5827 // CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5828 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 5829 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 5830 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5831 // CHECK7: omp.dispatch.cond: 5832 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5833 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 5834 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5835 // CHECK7: cond.true: 5836 // CHECK7-NEXT: br label [[COND_END:%.*]] 5837 // CHECK7: cond.false: 5838 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5839 // CHECK7-NEXT: br label [[COND_END]] 5840 // CHECK7: cond.end: 5841 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 5842 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5843 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5844 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 5845 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5846 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5847 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 5848 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5849 // CHECK7: omp.dispatch.body: 5850 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5851 // CHECK7: omp.inner.for.cond: 5852 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5853 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 5854 // CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 5855 // CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5856 // CHECK7: omp.inner.for.body: 5857 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5858 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 5859 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5860 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 5861 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5862 // CHECK7: omp.body.continue: 5863 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5864 // CHECK7: omp.inner.for.inc: 5865 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5866 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 5867 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5868 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 5869 // CHECK7: omp.inner.for.end: 5870 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5871 // CHECK7: omp.dispatch.inc: 5872 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5873 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 5874 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 5875 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 5876 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5877 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 5878 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 5879 // CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 5880 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 5881 // CHECK7: omp.dispatch.end: 5882 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 5883 // CHECK7-NEXT: ret void 5884 // 5885 // 5886 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5887 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 5888 // CHECK7-NEXT: entry: 5889 // CHECK7-NEXT: call void @__tgt_register_requires(i64 1) 5890 // CHECK7-NEXT: ret void 5891 // 5892 // 5893 // CHECK8-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 5894 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 5895 // CHECK8-NEXT: entry: 5896 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5897 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 5898 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 5899 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 5900 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 5901 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 5902 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 5903 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 5904 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5905 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 5906 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 5907 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 5908 // CHECK8-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 5909 // CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 5910 // CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 5911 // CHECK8-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 5912 // CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5913 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 5914 // CHECK8-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 5915 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5916 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 5917 // CHECK8-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 5918 // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5919 // CHECK8-NEXT: store i8* null, i8** [[TMP8]], align 4 5920 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5921 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 5922 // CHECK8-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 5923 // CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5924 // CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 5925 // CHECK8-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 5926 // CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5927 // CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4 5928 // CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5929 // CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 5930 // CHECK8-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 5931 // CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5932 // CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 5933 // CHECK8-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 5934 // CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5935 // CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 4 5936 // CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 5937 // CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 5938 // CHECK8-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 5939 // CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 5940 // CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 5941 // CHECK8-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 5942 // CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 5943 // CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 5944 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5945 // CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5946 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 5947 // CHECK8-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5948 // CHECK8-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 5949 // CHECK8-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5950 // CHECK8: omp_offload.failed: 5951 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2:[0-9]+]] 5952 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] 5953 // CHECK8: omp_offload.cont: 5954 // CHECK8-NEXT: ret void 5955 // 5956 // 5957 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 5958 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { 5959 // CHECK8-NEXT: entry: 5960 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5961 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 5962 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 5963 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 5964 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5965 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 5966 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 5967 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 5968 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 5969 // CHECK8-NEXT: ret void 5970 // 5971 // 5972 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. 5973 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 5974 // CHECK8-NEXT: entry: 5975 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5976 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5977 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 5978 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 5979 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 5980 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 5981 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5982 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 5983 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5984 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5985 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5986 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5987 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 5988 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5989 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5990 // CHECK8-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 5991 // CHECK8-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 5992 // CHECK8-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 5993 // CHECK8-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 5994 // CHECK8-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 5995 // CHECK8-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 5996 // CHECK8-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 5997 // CHECK8-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 5998 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5999 // CHECK8-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 6000 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6001 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6002 // CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6003 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 6004 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6005 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6006 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 6007 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6008 // CHECK8: cond.true: 6009 // CHECK8-NEXT: br label [[COND_END:%.*]] 6010 // CHECK8: cond.false: 6011 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6012 // CHECK8-NEXT: br label [[COND_END]] 6013 // CHECK8: cond.end: 6014 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 6015 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6016 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6017 // CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 6018 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6019 // CHECK8: omp.inner.for.cond: 6020 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6021 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6022 // CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 6023 // CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6024 // CHECK8: omp.inner.for.body: 6025 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6026 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 6027 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 6028 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 6029 // CHECK8-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 6030 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 6031 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 6032 // CHECK8-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 6033 // CHECK8-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 6034 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 6035 // CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 6036 // CHECK8-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 6037 // CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 6038 // CHECK8-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 6039 // CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 6040 // CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 6041 // CHECK8-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 6042 // CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 6043 // CHECK8-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 6044 // CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 6045 // CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 6046 // CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 6047 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6048 // CHECK8: omp.body.continue: 6049 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6050 // CHECK8: omp.inner.for.inc: 6051 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6052 // CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 6053 // CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 6054 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] 6055 // CHECK8: omp.inner.for.end: 6056 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6057 // CHECK8: omp.loop.exit: 6058 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 6059 // CHECK8-NEXT: ret void 6060 // 6061 // 6062 // CHECK8-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 6063 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6064 // CHECK8-NEXT: entry: 6065 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 6066 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 6067 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 6068 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 6069 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 6070 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 6071 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 6072 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 6073 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 6074 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 6075 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 6076 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 6077 // CHECK8-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 6078 // CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 6079 // CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 6080 // CHECK8-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 6081 // CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6082 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 6083 // CHECK8-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 6084 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6085 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 6086 // CHECK8-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 6087 // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6088 // CHECK8-NEXT: store i8* null, i8** [[TMP8]], align 4 6089 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6090 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 6091 // CHECK8-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 6092 // CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6093 // CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 6094 // CHECK8-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 6095 // CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6096 // CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4 6097 // CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6098 // CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 6099 // CHECK8-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 6100 // CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6101 // CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 6102 // CHECK8-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 6103 // CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6104 // CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 4 6105 // CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6106 // CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 6107 // CHECK8-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 6108 // CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6109 // CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 6110 // CHECK8-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 6111 // CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6112 // CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 6113 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6114 // CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6115 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 6116 // CHECK8-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 6117 // CHECK8-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 6118 // CHECK8-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6119 // CHECK8: omp_offload.failed: 6120 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 6121 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] 6122 // CHECK8: omp_offload.cont: 6123 // CHECK8-NEXT: ret void 6124 // 6125 // 6126 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 6127 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 6128 // CHECK8-NEXT: entry: 6129 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 6130 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 6131 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 6132 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 6133 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 6134 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 6135 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 6136 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 6137 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 6138 // CHECK8-NEXT: ret void 6139 // 6140 // 6141 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 6142 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 6143 // CHECK8-NEXT: entry: 6144 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6145 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6146 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 6147 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 6148 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 6149 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 6150 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6151 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 6152 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6153 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6154 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6155 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6156 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 6157 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6158 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6159 // CHECK8-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 6160 // CHECK8-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 6161 // CHECK8-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 6162 // CHECK8-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 6163 // CHECK8-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 6164 // CHECK8-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 6165 // CHECK8-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 6166 // CHECK8-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 6167 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6168 // CHECK8-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 6169 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6170 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6171 // CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6172 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 6173 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6174 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6175 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 6176 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6177 // CHECK8: cond.true: 6178 // CHECK8-NEXT: br label [[COND_END:%.*]] 6179 // CHECK8: cond.false: 6180 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6181 // CHECK8-NEXT: br label [[COND_END]] 6182 // CHECK8: cond.end: 6183 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 6184 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6185 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6186 // CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 6187 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6188 // CHECK8: omp.inner.for.cond: 6189 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6190 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6191 // CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 6192 // CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6193 // CHECK8: omp.inner.for.body: 6194 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6195 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 6196 // CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 6197 // CHECK8-NEXT: store i32 [[SUB]], i32* [[I]], align 4 6198 // CHECK8-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 6199 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 6200 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 6201 // CHECK8-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 6202 // CHECK8-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 6203 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 6204 // CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 6205 // CHECK8-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 6206 // CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 6207 // CHECK8-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 6208 // CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 6209 // CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 6210 // CHECK8-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 6211 // CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 6212 // CHECK8-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 6213 // CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 6214 // CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 6215 // CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 6216 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6217 // CHECK8: omp.body.continue: 6218 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6219 // CHECK8: omp.inner.for.inc: 6220 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6221 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 6222 // CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 6223 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] 6224 // CHECK8: omp.inner.for.end: 6225 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6226 // CHECK8: omp.loop.exit: 6227 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 6228 // CHECK8-NEXT: ret void 6229 // 6230 // 6231 // CHECK8-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 6232 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6233 // CHECK8-NEXT: entry: 6234 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 6235 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 6236 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 6237 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 6238 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 6239 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 6240 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 6241 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 6242 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 6243 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 6244 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 6245 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 6246 // CHECK8-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 6247 // CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 6248 // CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 6249 // CHECK8-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 6250 // CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6251 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 6252 // CHECK8-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 6253 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6254 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 6255 // CHECK8-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 6256 // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6257 // CHECK8-NEXT: store i8* null, i8** [[TMP8]], align 4 6258 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6259 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 6260 // CHECK8-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 6261 // CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6262 // CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 6263 // CHECK8-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 6264 // CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6265 // CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4 6266 // CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6267 // CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 6268 // CHECK8-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 6269 // CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6270 // CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 6271 // CHECK8-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 6272 // CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6273 // CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 4 6274 // CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6275 // CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 6276 // CHECK8-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 6277 // CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6278 // CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 6279 // CHECK8-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 6280 // CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6281 // CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4 6282 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6283 // CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6284 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 6285 // CHECK8-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 6286 // CHECK8-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 6287 // CHECK8-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6288 // CHECK8: omp_offload.failed: 6289 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 6290 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] 6291 // CHECK8: omp_offload.cont: 6292 // CHECK8-NEXT: ret void 6293 // 6294 // 6295 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 6296 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { 6297 // CHECK8-NEXT: entry: 6298 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 6299 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 6300 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 6301 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 6302 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 6303 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 6304 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 6305 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 6306 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 6307 // CHECK8-NEXT: ret void 6308 // 6309 // 6310 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 6311 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 6312 // CHECK8-NEXT: entry: 6313 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6314 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6315 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 6316 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 6317 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 6318 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 6319 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6320 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 6321 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6322 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6323 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6324 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6325 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 6326 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6327 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6328 // CHECK8-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 6329 // CHECK8-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 6330 // CHECK8-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 6331 // CHECK8-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 6332 // CHECK8-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 6333 // CHECK8-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 6334 // CHECK8-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 6335 // CHECK8-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 6336 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6337 // CHECK8-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 6338 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6339 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6340 // CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6341 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 6342 // CHECK8-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 6343 // CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6344 // CHECK8: omp.dispatch.cond: 6345 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6346 // CHECK8-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 6347 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6348 // CHECK8: cond.true: 6349 // CHECK8-NEXT: br label [[COND_END:%.*]] 6350 // CHECK8: cond.false: 6351 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6352 // CHECK8-NEXT: br label [[COND_END]] 6353 // CHECK8: cond.end: 6354 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 6355 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6356 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6357 // CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 6358 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6359 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6360 // CHECK8-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 6361 // CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6362 // CHECK8: omp.dispatch.body: 6363 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6364 // CHECK8: omp.inner.for.cond: 6365 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 6366 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 6367 // CHECK8-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 6368 // CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6369 // CHECK8: omp.inner.for.body: 6370 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 6371 // CHECK8-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 6372 // CHECK8-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 6373 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 6374 // CHECK8-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 6375 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 6376 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 6377 // CHECK8-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 6378 // CHECK8-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 6379 // CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 6380 // CHECK8-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 6381 // CHECK8-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10 6382 // CHECK8-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 6383 // CHECK8-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 6384 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 6385 // CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 6386 // CHECK8-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 6387 // CHECK8-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 6388 // CHECK8-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 6389 // CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 6390 // CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 6391 // CHECK8-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10 6392 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6393 // CHECK8: omp.body.continue: 6394 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6395 // CHECK8: omp.inner.for.inc: 6396 // CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 6397 // CHECK8-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 6398 // CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 6399 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 6400 // CHECK8: omp.inner.for.end: 6401 // CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6402 // CHECK8: omp.dispatch.inc: 6403 // CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6404 // CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6405 // CHECK8-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 6406 // CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 6407 // CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6408 // CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6409 // CHECK8-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 6410 // CHECK8-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 6411 // CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] 6412 // CHECK8: omp.dispatch.end: 6413 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 6414 // CHECK8-NEXT: ret void 6415 // 6416 // 6417 // CHECK8-LABEL: define {{[^@]+}}@_Z12test_precondv 6418 // CHECK8-SAME: () #[[ATTR0]] { 6419 // CHECK8-NEXT: entry: 6420 // CHECK8-NEXT: [[A:%.*]] = alloca i8, align 1 6421 // CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6422 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 6423 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 6424 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 6425 // CHECK8-NEXT: [[TMP:%.*]] = alloca i8, align 1 6426 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6427 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 6428 // CHECK8-NEXT: store i8 0, i8* [[A]], align 1 6429 // CHECK8-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 6430 // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[A_CASTED]] to i8* 6431 // CHECK8-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 6432 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6433 // CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6434 // CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 6435 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 6436 // CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6437 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 6438 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 6439 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6440 // CHECK8-NEXT: store i8* null, i8** [[TMP6]], align 4 6441 // CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6442 // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6443 // CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[A]], align 1 6444 // CHECK8-NEXT: store i8 [[TMP9]], i8* [[DOTCAPTURE_EXPR_]], align 1 6445 // CHECK8-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6446 // CHECK8-NEXT: [[CONV2:%.*]] = sext i8 [[TMP10]] to i32 6447 // CHECK8-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV2]] 6448 // CHECK8-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 6449 // CHECK8-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 6450 // CHECK8-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 6451 // CHECK8-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 6452 // CHECK8-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 6453 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 6454 // CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 6455 // CHECK8-NEXT: [[TMP12:%.*]] = zext i32 [[ADD5]] to i64 6456 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP12]]) 6457 // CHECK8-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 6458 // CHECK8-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 6459 // CHECK8-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6460 // CHECK8: omp_offload.failed: 6461 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i32 [[TMP1]]) #[[ATTR2]] 6462 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] 6463 // CHECK8: omp_offload.cont: 6464 // CHECK8-NEXT: ret void 6465 // 6466 // 6467 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 6468 // CHECK8-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { 6469 // CHECK8-NEXT: entry: 6470 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6471 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6472 // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* 6473 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]]) 6474 // CHECK8-NEXT: ret void 6475 // 6476 // 6477 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 6478 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 6479 // CHECK8-NEXT: entry: 6480 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6481 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6482 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 6483 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6484 // CHECK8-NEXT: [[TMP:%.*]] = alloca i8, align 1 6485 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6486 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 6487 // CHECK8-NEXT: [[I:%.*]] = alloca i8, align 1 6488 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6489 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6490 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6491 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6492 // CHECK8-NEXT: [[I5:%.*]] = alloca i8, align 1 6493 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6494 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6495 // CHECK8-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 6496 // CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 6497 // CHECK8-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 6498 // CHECK8-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 6499 // CHECK8-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6500 // CHECK8-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 6501 // CHECK8-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 6502 // CHECK8-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 6503 // CHECK8-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 6504 // CHECK8-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 6505 // CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 6506 // CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 6507 // CHECK8-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6508 // CHECK8-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 6509 // CHECK8-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6510 // CHECK8-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 6511 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 6512 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 6513 // CHECK8: omp.precond.then: 6514 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6515 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 6516 // CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 6517 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6518 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6519 // CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6520 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 6521 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6522 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6523 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 6524 // CHECK8-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 6525 // CHECK8-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6526 // CHECK8: cond.true: 6527 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 6528 // CHECK8-NEXT: br label [[COND_END:%.*]] 6529 // CHECK8: cond.false: 6530 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6531 // CHECK8-NEXT: br label [[COND_END]] 6532 // CHECK8: cond.end: 6533 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 6534 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6535 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6536 // CHECK8-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 6537 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6538 // CHECK8: omp.inner.for.cond: 6539 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6540 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6541 // CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 6542 // CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6543 // CHECK8: omp.inner.for.body: 6544 // CHECK8-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6545 // CHECK8-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 6546 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6547 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 6548 // CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 6549 // CHECK8-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 6550 // CHECK8-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 6551 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6552 // CHECK8: omp.body.continue: 6553 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6554 // CHECK8: omp.inner.for.inc: 6555 // CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6556 // CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 6557 // CHECK8-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 6558 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] 6559 // CHECK8: omp.inner.for.end: 6560 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6561 // CHECK8: omp.loop.exit: 6562 // CHECK8-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6563 // CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 6564 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 6565 // CHECK8-NEXT: br label [[OMP_PRECOND_END]] 6566 // CHECK8: omp.precond.end: 6567 // CHECK8-NEXT: ret void 6568 // 6569 // 6570 // CHECK8-LABEL: define {{[^@]+}}@_Z4fintv 6571 // CHECK8-SAME: () #[[ATTR0]] { 6572 // CHECK8-NEXT: entry: 6573 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() 6574 // CHECK8-NEXT: ret i32 [[CALL]] 6575 // 6576 // 6577 // CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 6578 // CHECK8-SAME: () #[[ATTR0]] comdat { 6579 // CHECK8-NEXT: entry: 6580 // CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 6581 // CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6582 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 6583 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 6584 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 6585 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 6586 // CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 6587 // CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 6588 // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6589 // CHECK8-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 6590 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6591 // CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6592 // CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 6593 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 6594 // CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6595 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 6596 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 6597 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6598 // CHECK8-NEXT: store i8* null, i8** [[TMP6]], align 4 6599 // CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6600 // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6601 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 6602 // CHECK8-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 6603 // CHECK8-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 6604 // CHECK8-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6605 // CHECK8: omp_offload.failed: 6606 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i32 [[TMP1]]) #[[ATTR2]] 6607 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] 6608 // CHECK8: omp_offload.cont: 6609 // CHECK8-NEXT: ret i32 0 6610 // 6611 // 6612 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 6613 // CHECK8-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] { 6614 // CHECK8-NEXT: entry: 6615 // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6616 // CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6617 // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6618 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 6619 // CHECK8-NEXT: ret void 6620 // 6621 // 6622 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 6623 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 6624 // CHECK8-NEXT: entry: 6625 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6626 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6627 // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 6628 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6629 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 6630 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6631 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6632 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6633 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6634 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 6635 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6636 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6637 // CHECK8-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 6638 // CHECK8-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 6639 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6640 // CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 6641 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6642 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6643 // CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 6644 // CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6645 // CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6646 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 6647 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 6648 // CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6649 // CHECK8: omp.dispatch.cond: 6650 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6651 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 6652 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6653 // CHECK8: cond.true: 6654 // CHECK8-NEXT: br label [[COND_END:%.*]] 6655 // CHECK8: cond.false: 6656 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6657 // CHECK8-NEXT: br label [[COND_END]] 6658 // CHECK8: cond.end: 6659 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 6660 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6661 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6662 // CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 6663 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6664 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6665 // CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 6666 // CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6667 // CHECK8: omp.dispatch.body: 6668 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6669 // CHECK8: omp.inner.for.cond: 6670 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 6671 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 6672 // CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 6673 // CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6674 // CHECK8: omp.inner.for.body: 6675 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 6676 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 6677 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 6678 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 6679 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6680 // CHECK8: omp.body.continue: 6681 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6682 // CHECK8: omp.inner.for.inc: 6683 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 6684 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 6685 // CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 6686 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 6687 // CHECK8: omp.inner.for.end: 6688 // CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6689 // CHECK8: omp.dispatch.inc: 6690 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6691 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6692 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 6693 // CHECK8-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 6694 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6695 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6696 // CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 6697 // CHECK8-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 6698 // CHECK8-NEXT: br label [[OMP_DISPATCH_COND]] 6699 // CHECK8: omp.dispatch.end: 6700 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 6701 // CHECK8-NEXT: ret void 6702 // 6703 // 6704 // CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 6705 // CHECK8-SAME: () #[[ATTR3:[0-9]+]] { 6706 // CHECK8-NEXT: entry: 6707 // CHECK8-NEXT: call void @__tgt_register_requires(i64 1) 6708 // CHECK8-NEXT: ret void 6709 // 6710 // 6711 // CHECK9-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 6712 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 6713 // CHECK9-NEXT: entry: 6714 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6715 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6716 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6717 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6718 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 6719 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6720 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6721 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6722 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6723 // CHECK9-NEXT: store i32 33, i32* [[I]], align 4 6724 // CHECK9-NEXT: br label [[FOR_COND:%.*]] 6725 // CHECK9: for.cond: 6726 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 6727 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 6728 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6729 // CHECK9: for.body: 6730 // CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 6731 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 6732 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 6733 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 6734 // CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 6735 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 6736 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 6737 // CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 6738 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 6739 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 6740 // CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 6741 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 6742 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 6743 // CHECK9-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 6744 // CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 6745 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 6746 // CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 6747 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 6748 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 6749 // CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 6750 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 6751 // CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 6752 // CHECK9-NEXT: br label [[FOR_INC:%.*]] 6753 // CHECK9: for.inc: 6754 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 6755 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 6756 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 6757 // CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 6758 // CHECK9: for.end: 6759 // CHECK9-NEXT: ret void 6760 // 6761 // 6762 // CHECK9-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 6763 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6764 // CHECK9-NEXT: entry: 6765 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6766 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6767 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6768 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6769 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 6770 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6771 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6772 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6773 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6774 // CHECK9-NEXT: store i32 32000000, i32* [[I]], align 4 6775 // CHECK9-NEXT: br label [[FOR_COND:%.*]] 6776 // CHECK9: for.cond: 6777 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 6778 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 6779 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6780 // CHECK9: for.body: 6781 // CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 6782 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 6783 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 6784 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 6785 // CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 6786 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 6787 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 6788 // CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 6789 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 6790 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 6791 // CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 6792 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 6793 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 6794 // CHECK9-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 6795 // CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 6796 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 6797 // CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 6798 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 6799 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 6800 // CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 6801 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 6802 // CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 6803 // CHECK9-NEXT: br label [[FOR_INC:%.*]] 6804 // CHECK9: for.inc: 6805 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 6806 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 6807 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 6808 // CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 6809 // CHECK9: for.end: 6810 // CHECK9-NEXT: ret void 6811 // 6812 // 6813 // CHECK9-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 6814 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6815 // CHECK9-NEXT: entry: 6816 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6817 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6818 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6819 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6820 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 6821 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6822 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6823 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6824 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6825 // CHECK9-NEXT: store i32 131071, i32* [[I]], align 4 6826 // CHECK9-NEXT: br label [[FOR_COND:%.*]] 6827 // CHECK9: for.cond: 6828 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 6829 // CHECK9-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 6830 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6831 // CHECK9: for.body: 6832 // CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 6833 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 6834 // CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 6835 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 6836 // CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 6837 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 6838 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 6839 // CHECK9-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 6840 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 6841 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 6842 // CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 6843 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 6844 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 6845 // CHECK9-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 6846 // CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 6847 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 6848 // CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 6849 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 6850 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 6851 // CHECK9-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 6852 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 6853 // CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 6854 // CHECK9-NEXT: br label [[FOR_INC:%.*]] 6855 // CHECK9: for.inc: 6856 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 6857 // CHECK9-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 6858 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 6859 // CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 6860 // CHECK9: for.end: 6861 // CHECK9-NEXT: ret void 6862 // 6863 // 6864 // CHECK9-LABEL: define {{[^@]+}}@_Z12test_precondv 6865 // CHECK9-SAME: () #[[ATTR0]] { 6866 // CHECK9-NEXT: entry: 6867 // CHECK9-NEXT: [[A:%.*]] = alloca i8, align 1 6868 // CHECK9-NEXT: [[I:%.*]] = alloca i8, align 1 6869 // CHECK9-NEXT: store i8 0, i8* [[A]], align 1 6870 // CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 6871 // CHECK9-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 6872 // CHECK9-NEXT: br label [[FOR_COND:%.*]] 6873 // CHECK9: for.cond: 6874 // CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 6875 // CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 6876 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 6877 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6878 // CHECK9: for.body: 6879 // CHECK9-NEXT: br label [[FOR_INC:%.*]] 6880 // CHECK9: for.inc: 6881 // CHECK9-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 6882 // CHECK9-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 6883 // CHECK9-NEXT: store i8 [[INC]], i8* [[I]], align 1 6884 // CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 6885 // CHECK9: for.end: 6886 // CHECK9-NEXT: ret void 6887 // 6888 // 6889 // CHECK9-LABEL: define {{[^@]+}}@_Z4fintv 6890 // CHECK9-SAME: () #[[ATTR0]] { 6891 // CHECK9-NEXT: entry: 6892 // CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() 6893 // CHECK9-NEXT: ret i32 [[CALL]] 6894 // 6895 // 6896 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 6897 // CHECK9-SAME: () #[[ATTR0]] comdat { 6898 // CHECK9-NEXT: entry: 6899 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 6900 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 6901 // CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 6902 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4 6903 // CHECK9-NEXT: br label [[FOR_COND:%.*]] 6904 // CHECK9: for.cond: 6905 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 6906 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 6907 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6908 // CHECK9: for.body: 6909 // CHECK9-NEXT: br label [[FOR_INC:%.*]] 6910 // CHECK9: for.inc: 6911 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 6912 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 6913 // CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 6914 // CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 6915 // CHECK9: for.end: 6916 // CHECK9-NEXT: ret i32 0 6917 // 6918 // 6919 // CHECK10-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 6920 // CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 6921 // CHECK10-NEXT: entry: 6922 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6923 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6924 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6925 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6926 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 6927 // CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6928 // CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6929 // CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6930 // CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6931 // CHECK10-NEXT: store i32 33, i32* [[I]], align 4 6932 // CHECK10-NEXT: br label [[FOR_COND:%.*]] 6933 // CHECK10: for.cond: 6934 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 6935 // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 6936 // CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6937 // CHECK10: for.body: 6938 // CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 6939 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 6940 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 6941 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 6942 // CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 6943 // CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 6944 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 6945 // CHECK10-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 6946 // CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 6947 // CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 6948 // CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 6949 // CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 6950 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 6951 // CHECK10-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 6952 // CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 6953 // CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 6954 // CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 6955 // CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 6956 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 6957 // CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 6958 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 6959 // CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 6960 // CHECK10-NEXT: br label [[FOR_INC:%.*]] 6961 // CHECK10: for.inc: 6962 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 6963 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 6964 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 6965 // CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 6966 // CHECK10: for.end: 6967 // CHECK10-NEXT: ret void 6968 // 6969 // 6970 // CHECK10-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 6971 // CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6972 // CHECK10-NEXT: entry: 6973 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6974 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6975 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6976 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6977 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 6978 // CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6979 // CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6980 // CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6981 // CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6982 // CHECK10-NEXT: store i32 32000000, i32* [[I]], align 4 6983 // CHECK10-NEXT: br label [[FOR_COND:%.*]] 6984 // CHECK10: for.cond: 6985 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 6986 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 6987 // CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6988 // CHECK10: for.body: 6989 // CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 6990 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 6991 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 6992 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 6993 // CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 6994 // CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 6995 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 6996 // CHECK10-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 6997 // CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 6998 // CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 6999 // CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7000 // CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 7001 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7002 // CHECK10-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 7003 // CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 7004 // CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 7005 // CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 7006 // CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 7007 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7008 // CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 7009 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 7010 // CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 7011 // CHECK10-NEXT: br label [[FOR_INC:%.*]] 7012 // CHECK10: for.inc: 7013 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7014 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 7015 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7016 // CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 7017 // CHECK10: for.end: 7018 // CHECK10-NEXT: ret void 7019 // 7020 // 7021 // CHECK10-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 7022 // CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7023 // CHECK10-NEXT: entry: 7024 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7025 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7026 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7027 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7028 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 7029 // CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7030 // CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7031 // CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7032 // CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7033 // CHECK10-NEXT: store i32 131071, i32* [[I]], align 4 7034 // CHECK10-NEXT: br label [[FOR_COND:%.*]] 7035 // CHECK10: for.cond: 7036 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7037 // CHECK10-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 7038 // CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7039 // CHECK10: for.body: 7040 // CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 7041 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7042 // CHECK10-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 7043 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 7044 // CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7045 // CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 7046 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7047 // CHECK10-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 7048 // CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 7049 // CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7050 // CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7051 // CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 7052 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7053 // CHECK10-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 7054 // CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 7055 // CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 7056 // CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 7057 // CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 7058 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7059 // CHECK10-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 7060 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 7061 // CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 7062 // CHECK10-NEXT: br label [[FOR_INC:%.*]] 7063 // CHECK10: for.inc: 7064 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7065 // CHECK10-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 7066 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7067 // CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 7068 // CHECK10: for.end: 7069 // CHECK10-NEXT: ret void 7070 // 7071 // 7072 // CHECK10-LABEL: define {{[^@]+}}@_Z12test_precondv 7073 // CHECK10-SAME: () #[[ATTR0]] { 7074 // CHECK10-NEXT: entry: 7075 // CHECK10-NEXT: [[A:%.*]] = alloca i8, align 1 7076 // CHECK10-NEXT: [[I:%.*]] = alloca i8, align 1 7077 // CHECK10-NEXT: store i8 0, i8* [[A]], align 1 7078 // CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 7079 // CHECK10-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 7080 // CHECK10-NEXT: br label [[FOR_COND:%.*]] 7081 // CHECK10: for.cond: 7082 // CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 7083 // CHECK10-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 7084 // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 7085 // CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7086 // CHECK10: for.body: 7087 // CHECK10-NEXT: br label [[FOR_INC:%.*]] 7088 // CHECK10: for.inc: 7089 // CHECK10-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 7090 // CHECK10-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 7091 // CHECK10-NEXT: store i8 [[INC]], i8* [[I]], align 1 7092 // CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 7093 // CHECK10: for.end: 7094 // CHECK10-NEXT: ret void 7095 // 7096 // 7097 // CHECK10-LABEL: define {{[^@]+}}@_Z4fintv 7098 // CHECK10-SAME: () #[[ATTR0]] { 7099 // CHECK10-NEXT: entry: 7100 // CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() 7101 // CHECK10-NEXT: ret i32 [[CALL]] 7102 // 7103 // 7104 // CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 7105 // CHECK10-SAME: () #[[ATTR0]] comdat { 7106 // CHECK10-NEXT: entry: 7107 // CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 7108 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 7109 // CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 7110 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4 7111 // CHECK10-NEXT: br label [[FOR_COND:%.*]] 7112 // CHECK10: for.cond: 7113 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7114 // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 7115 // CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7116 // CHECK10: for.body: 7117 // CHECK10-NEXT: br label [[FOR_INC:%.*]] 7118 // CHECK10: for.inc: 7119 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 7120 // CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 7121 // CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 7122 // CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 7123 // CHECK10: for.end: 7124 // CHECK10-NEXT: ret i32 0 7125 // 7126 // 7127 // CHECK11-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 7128 // CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 7129 // CHECK11-NEXT: entry: 7130 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 7131 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 7132 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 7133 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 7134 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 7135 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 7136 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 7137 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 7138 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 7139 // CHECK11-NEXT: store i32 33, i32* [[I]], align 4 7140 // CHECK11-NEXT: br label [[FOR_COND:%.*]] 7141 // CHECK11: for.cond: 7142 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7143 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 7144 // CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7145 // CHECK11: for.body: 7146 // CHECK11-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 7147 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7148 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 7149 // CHECK11-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7150 // CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 7151 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7152 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 7153 // CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 7154 // CHECK11-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7155 // CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 7156 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7157 // CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 7158 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7159 // CHECK11-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 7160 // CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 7161 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7162 // CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 7163 // CHECK11-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 7164 // CHECK11-NEXT: br label [[FOR_INC:%.*]] 7165 // CHECK11: for.inc: 7166 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7167 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 7168 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7169 // CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 7170 // CHECK11: for.end: 7171 // CHECK11-NEXT: ret void 7172 // 7173 // 7174 // CHECK11-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 7175 // CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7176 // CHECK11-NEXT: entry: 7177 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 7178 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 7179 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 7180 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 7181 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 7182 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 7183 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 7184 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 7185 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 7186 // CHECK11-NEXT: store i32 32000000, i32* [[I]], align 4 7187 // CHECK11-NEXT: br label [[FOR_COND:%.*]] 7188 // CHECK11: for.cond: 7189 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7190 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 7191 // CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7192 // CHECK11: for.body: 7193 // CHECK11-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 7194 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7195 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 7196 // CHECK11-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7197 // CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 7198 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7199 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 7200 // CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 7201 // CHECK11-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7202 // CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 7203 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7204 // CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 7205 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7206 // CHECK11-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 7207 // CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 7208 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7209 // CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 7210 // CHECK11-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 7211 // CHECK11-NEXT: br label [[FOR_INC:%.*]] 7212 // CHECK11: for.inc: 7213 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7214 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 7215 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7216 // CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 7217 // CHECK11: for.end: 7218 // CHECK11-NEXT: ret void 7219 // 7220 // 7221 // CHECK11-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 7222 // CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7223 // CHECK11-NEXT: entry: 7224 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 7225 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 7226 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 7227 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 7228 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 7229 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 7230 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 7231 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 7232 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 7233 // CHECK11-NEXT: store i32 131071, i32* [[I]], align 4 7234 // CHECK11-NEXT: br label [[FOR_COND:%.*]] 7235 // CHECK11: for.cond: 7236 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7237 // CHECK11-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 7238 // CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7239 // CHECK11: for.body: 7240 // CHECK11-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 7241 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7242 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 7243 // CHECK11-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7244 // CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 7245 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7246 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 7247 // CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 7248 // CHECK11-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7249 // CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 7250 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7251 // CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 7252 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7253 // CHECK11-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 7254 // CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 7255 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7256 // CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 7257 // CHECK11-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 7258 // CHECK11-NEXT: br label [[FOR_INC:%.*]] 7259 // CHECK11: for.inc: 7260 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7261 // CHECK11-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 7262 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7263 // CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 7264 // CHECK11: for.end: 7265 // CHECK11-NEXT: ret void 7266 // 7267 // 7268 // CHECK11-LABEL: define {{[^@]+}}@_Z12test_precondv 7269 // CHECK11-SAME: () #[[ATTR0]] { 7270 // CHECK11-NEXT: entry: 7271 // CHECK11-NEXT: [[A:%.*]] = alloca i8, align 1 7272 // CHECK11-NEXT: [[I:%.*]] = alloca i8, align 1 7273 // CHECK11-NEXT: store i8 0, i8* [[A]], align 1 7274 // CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 7275 // CHECK11-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 7276 // CHECK11-NEXT: br label [[FOR_COND:%.*]] 7277 // CHECK11: for.cond: 7278 // CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 7279 // CHECK11-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 7280 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 7281 // CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7282 // CHECK11: for.body: 7283 // CHECK11-NEXT: br label [[FOR_INC:%.*]] 7284 // CHECK11: for.inc: 7285 // CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 7286 // CHECK11-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 7287 // CHECK11-NEXT: store i8 [[INC]], i8* [[I]], align 1 7288 // CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 7289 // CHECK11: for.end: 7290 // CHECK11-NEXT: ret void 7291 // 7292 // 7293 // CHECK11-LABEL: define {{[^@]+}}@_Z4fintv 7294 // CHECK11-SAME: () #[[ATTR0]] { 7295 // CHECK11-NEXT: entry: 7296 // CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() 7297 // CHECK11-NEXT: ret i32 [[CALL]] 7298 // 7299 // 7300 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 7301 // CHECK11-SAME: () #[[ATTR0]] comdat { 7302 // CHECK11-NEXT: entry: 7303 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7304 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 7305 // CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 7306 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4 7307 // CHECK11-NEXT: br label [[FOR_COND:%.*]] 7308 // CHECK11: for.cond: 7309 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7310 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 7311 // CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7312 // CHECK11: for.body: 7313 // CHECK11-NEXT: br label [[FOR_INC:%.*]] 7314 // CHECK11: for.inc: 7315 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 7316 // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 7317 // CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 7318 // CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 7319 // CHECK11: for.end: 7320 // CHECK11-NEXT: ret i32 0 7321 // 7322 // 7323 // CHECK12-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 7324 // CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 7325 // CHECK12-NEXT: entry: 7326 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 7327 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 7328 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 7329 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 7330 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 7331 // CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 7332 // CHECK12-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 7333 // CHECK12-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 7334 // CHECK12-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 7335 // CHECK12-NEXT: store i32 33, i32* [[I]], align 4 7336 // CHECK12-NEXT: br label [[FOR_COND:%.*]] 7337 // CHECK12: for.cond: 7338 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7339 // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 7340 // CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7341 // CHECK12: for.body: 7342 // CHECK12-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 7343 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7344 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 7345 // CHECK12-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7346 // CHECK12-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 7347 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7348 // CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 7349 // CHECK12-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 7350 // CHECK12-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7351 // CHECK12-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 7352 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7353 // CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 7354 // CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7355 // CHECK12-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 7356 // CHECK12-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 7357 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7358 // CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 7359 // CHECK12-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 7360 // CHECK12-NEXT: br label [[FOR_INC:%.*]] 7361 // CHECK12: for.inc: 7362 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7363 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 7364 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7365 // CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 7366 // CHECK12: for.end: 7367 // CHECK12-NEXT: ret void 7368 // 7369 // 7370 // CHECK12-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 7371 // CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7372 // CHECK12-NEXT: entry: 7373 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 7374 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 7375 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 7376 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 7377 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 7378 // CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 7379 // CHECK12-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 7380 // CHECK12-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 7381 // CHECK12-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 7382 // CHECK12-NEXT: store i32 32000000, i32* [[I]], align 4 7383 // CHECK12-NEXT: br label [[FOR_COND:%.*]] 7384 // CHECK12: for.cond: 7385 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7386 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 7387 // CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7388 // CHECK12: for.body: 7389 // CHECK12-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 7390 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7391 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 7392 // CHECK12-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7393 // CHECK12-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 7394 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7395 // CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 7396 // CHECK12-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 7397 // CHECK12-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7398 // CHECK12-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 7399 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7400 // CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 7401 // CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7402 // CHECK12-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 7403 // CHECK12-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 7404 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7405 // CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 7406 // CHECK12-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 7407 // CHECK12-NEXT: br label [[FOR_INC:%.*]] 7408 // CHECK12: for.inc: 7409 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7410 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 7411 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7412 // CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 7413 // CHECK12: for.end: 7414 // CHECK12-NEXT: ret void 7415 // 7416 // 7417 // CHECK12-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 7418 // CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7419 // CHECK12-NEXT: entry: 7420 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 7421 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 7422 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 7423 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 7424 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 7425 // CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 7426 // CHECK12-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 7427 // CHECK12-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 7428 // CHECK12-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 7429 // CHECK12-NEXT: store i32 131071, i32* [[I]], align 4 7430 // CHECK12-NEXT: br label [[FOR_COND:%.*]] 7431 // CHECK12: for.cond: 7432 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7433 // CHECK12-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 7434 // CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7435 // CHECK12: for.body: 7436 // CHECK12-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 7437 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7438 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 7439 // CHECK12-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7440 // CHECK12-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 7441 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7442 // CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 7443 // CHECK12-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 7444 // CHECK12-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7445 // CHECK12-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 7446 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7447 // CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 7448 // CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7449 // CHECK12-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 7450 // CHECK12-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 7451 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7452 // CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 7453 // CHECK12-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 7454 // CHECK12-NEXT: br label [[FOR_INC:%.*]] 7455 // CHECK12: for.inc: 7456 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7457 // CHECK12-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 7458 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7459 // CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 7460 // CHECK12: for.end: 7461 // CHECK12-NEXT: ret void 7462 // 7463 // 7464 // CHECK12-LABEL: define {{[^@]+}}@_Z12test_precondv 7465 // CHECK12-SAME: () #[[ATTR0]] { 7466 // CHECK12-NEXT: entry: 7467 // CHECK12-NEXT: [[A:%.*]] = alloca i8, align 1 7468 // CHECK12-NEXT: [[I:%.*]] = alloca i8, align 1 7469 // CHECK12-NEXT: store i8 0, i8* [[A]], align 1 7470 // CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 7471 // CHECK12-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 7472 // CHECK12-NEXT: br label [[FOR_COND:%.*]] 7473 // CHECK12: for.cond: 7474 // CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 7475 // CHECK12-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 7476 // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 7477 // CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7478 // CHECK12: for.body: 7479 // CHECK12-NEXT: br label [[FOR_INC:%.*]] 7480 // CHECK12: for.inc: 7481 // CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 7482 // CHECK12-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 7483 // CHECK12-NEXT: store i8 [[INC]], i8* [[I]], align 1 7484 // CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 7485 // CHECK12: for.end: 7486 // CHECK12-NEXT: ret void 7487 // 7488 // 7489 // CHECK12-LABEL: define {{[^@]+}}@_Z4fintv 7490 // CHECK12-SAME: () #[[ATTR0]] { 7491 // CHECK12-NEXT: entry: 7492 // CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() 7493 // CHECK12-NEXT: ret i32 [[CALL]] 7494 // 7495 // 7496 // CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 7497 // CHECK12-SAME: () #[[ATTR0]] comdat { 7498 // CHECK12-NEXT: entry: 7499 // CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 7500 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 7501 // CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 7502 // CHECK12-NEXT: store i32 0, i32* [[I]], align 4 7503 // CHECK12-NEXT: br label [[FOR_COND:%.*]] 7504 // CHECK12: for.cond: 7505 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7506 // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 7507 // CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7508 // CHECK12: for.body: 7509 // CHECK12-NEXT: br label [[FOR_INC:%.*]] 7510 // CHECK12: for.inc: 7511 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 7512 // CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 7513 // CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 7514 // CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 7515 // CHECK12: for.end: 7516 // CHECK12-NEXT: ret i32 0 7517 // 7518 // 7519 // CHECK13-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 7520 // CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 7521 // CHECK13-NEXT: entry: 7522 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7523 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7524 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7525 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7526 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 7527 // CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7528 // CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7529 // CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7530 // CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7531 // CHECK13-NEXT: store i32 33, i32* [[I]], align 4 7532 // CHECK13-NEXT: br label [[FOR_COND:%.*]] 7533 // CHECK13: for.cond: 7534 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7535 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 7536 // CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7537 // CHECK13: for.body: 7538 // CHECK13-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 7539 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7540 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 7541 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 7542 // CHECK13-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7543 // CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 7544 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7545 // CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 7546 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 7547 // CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7548 // CHECK13-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7549 // CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 7550 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7551 // CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 7552 // CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 7553 // CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 7554 // CHECK13-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 7555 // CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 7556 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7557 // CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 7558 // CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 7559 // CHECK13-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 7560 // CHECK13-NEXT: br label [[FOR_INC:%.*]] 7561 // CHECK13: for.inc: 7562 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7563 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 7564 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7565 // CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 7566 // CHECK13: for.end: 7567 // CHECK13-NEXT: ret void 7568 // 7569 // 7570 // CHECK13-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 7571 // CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7572 // CHECK13-NEXT: entry: 7573 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7574 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7575 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7576 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7577 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 7578 // CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7579 // CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7580 // CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7581 // CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7582 // CHECK13-NEXT: store i32 32000000, i32* [[I]], align 4 7583 // CHECK13-NEXT: br label [[FOR_COND:%.*]] 7584 // CHECK13: for.cond: 7585 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7586 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 7587 // CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7588 // CHECK13: for.body: 7589 // CHECK13-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 7590 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7591 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 7592 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 7593 // CHECK13-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7594 // CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 7595 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7596 // CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 7597 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 7598 // CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7599 // CHECK13-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7600 // CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 7601 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7602 // CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 7603 // CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 7604 // CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 7605 // CHECK13-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 7606 // CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 7607 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7608 // CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 7609 // CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 7610 // CHECK13-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 7611 // CHECK13-NEXT: br label [[FOR_INC:%.*]] 7612 // CHECK13: for.inc: 7613 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7614 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 7615 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7616 // CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 7617 // CHECK13: for.end: 7618 // CHECK13-NEXT: ret void 7619 // 7620 // 7621 // CHECK13-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 7622 // CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7623 // CHECK13-NEXT: entry: 7624 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7625 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7626 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7627 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7628 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 7629 // CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7630 // CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7631 // CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7632 // CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7633 // CHECK13-NEXT: store i32 131071, i32* [[I]], align 4 7634 // CHECK13-NEXT: br label [[FOR_COND:%.*]] 7635 // CHECK13: for.cond: 7636 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7637 // CHECK13-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 7638 // CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7639 // CHECK13: for.body: 7640 // CHECK13-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 7641 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7642 // CHECK13-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 7643 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 7644 // CHECK13-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7645 // CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 7646 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7647 // CHECK13-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 7648 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 7649 // CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7650 // CHECK13-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7651 // CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 7652 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7653 // CHECK13-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 7654 // CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 7655 // CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 7656 // CHECK13-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 7657 // CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 7658 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7659 // CHECK13-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 7660 // CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 7661 // CHECK13-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 7662 // CHECK13-NEXT: br label [[FOR_INC:%.*]] 7663 // CHECK13: for.inc: 7664 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7665 // CHECK13-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 7666 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7667 // CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 7668 // CHECK13: for.end: 7669 // CHECK13-NEXT: ret void 7670 // 7671 // 7672 // CHECK13-LABEL: define {{[^@]+}}@_Z12test_precondv 7673 // CHECK13-SAME: () #[[ATTR0]] { 7674 // CHECK13-NEXT: entry: 7675 // CHECK13-NEXT: [[A:%.*]] = alloca i8, align 1 7676 // CHECK13-NEXT: [[I:%.*]] = alloca i8, align 1 7677 // CHECK13-NEXT: store i8 0, i8* [[A]], align 1 7678 // CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 7679 // CHECK13-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 7680 // CHECK13-NEXT: br label [[FOR_COND:%.*]] 7681 // CHECK13: for.cond: 7682 // CHECK13-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 7683 // CHECK13-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 7684 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 7685 // CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7686 // CHECK13: for.body: 7687 // CHECK13-NEXT: br label [[FOR_INC:%.*]] 7688 // CHECK13: for.inc: 7689 // CHECK13-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 7690 // CHECK13-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 7691 // CHECK13-NEXT: store i8 [[INC]], i8* [[I]], align 1 7692 // CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 7693 // CHECK13: for.end: 7694 // CHECK13-NEXT: ret void 7695 // 7696 // 7697 // CHECK13-LABEL: define {{[^@]+}}@_Z4fintv 7698 // CHECK13-SAME: () #[[ATTR0]] { 7699 // CHECK13-NEXT: entry: 7700 // CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() 7701 // CHECK13-NEXT: ret i32 [[CALL]] 7702 // 7703 // 7704 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 7705 // CHECK13-SAME: () #[[ATTR0]] comdat { 7706 // CHECK13-NEXT: entry: 7707 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 7708 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 7709 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 7710 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 7711 // CHECK13-NEXT: br label [[FOR_COND:%.*]] 7712 // CHECK13: for.cond: 7713 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7714 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 7715 // CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7716 // CHECK13: for.body: 7717 // CHECK13-NEXT: br label [[FOR_INC:%.*]] 7718 // CHECK13: for.inc: 7719 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 7720 // CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 7721 // CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 7722 // CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 7723 // CHECK13: for.end: 7724 // CHECK13-NEXT: ret i32 0 7725 // 7726 // 7727 // CHECK14-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 7728 // CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 7729 // CHECK14-NEXT: entry: 7730 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7731 // CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7732 // CHECK14-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7733 // CHECK14-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7734 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 7735 // CHECK14-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7736 // CHECK14-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7737 // CHECK14-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7738 // CHECK14-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7739 // CHECK14-NEXT: store i32 33, i32* [[I]], align 4 7740 // CHECK14-NEXT: br label [[FOR_COND:%.*]] 7741 // CHECK14: for.cond: 7742 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7743 // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 7744 // CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7745 // CHECK14: for.body: 7746 // CHECK14-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 7747 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7748 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 7749 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 7750 // CHECK14-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7751 // CHECK14-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 7752 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7753 // CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 7754 // CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 7755 // CHECK14-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7756 // CHECK14-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7757 // CHECK14-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 7758 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7759 // CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 7760 // CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 7761 // CHECK14-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 7762 // CHECK14-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 7763 // CHECK14-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 7764 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7765 // CHECK14-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 7766 // CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 7767 // CHECK14-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 7768 // CHECK14-NEXT: br label [[FOR_INC:%.*]] 7769 // CHECK14: for.inc: 7770 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7771 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 7772 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7773 // CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 7774 // CHECK14: for.end: 7775 // CHECK14-NEXT: ret void 7776 // 7777 // 7778 // CHECK14-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 7779 // CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7780 // CHECK14-NEXT: entry: 7781 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7782 // CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7783 // CHECK14-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7784 // CHECK14-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7785 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 7786 // CHECK14-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7787 // CHECK14-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7788 // CHECK14-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7789 // CHECK14-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7790 // CHECK14-NEXT: store i32 32000000, i32* [[I]], align 4 7791 // CHECK14-NEXT: br label [[FOR_COND:%.*]] 7792 // CHECK14: for.cond: 7793 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7794 // CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 7795 // CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7796 // CHECK14: for.body: 7797 // CHECK14-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 7798 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7799 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 7800 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 7801 // CHECK14-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7802 // CHECK14-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 7803 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7804 // CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 7805 // CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 7806 // CHECK14-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7807 // CHECK14-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7808 // CHECK14-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 7809 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7810 // CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 7811 // CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 7812 // CHECK14-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 7813 // CHECK14-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 7814 // CHECK14-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 7815 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7816 // CHECK14-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 7817 // CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 7818 // CHECK14-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 7819 // CHECK14-NEXT: br label [[FOR_INC:%.*]] 7820 // CHECK14: for.inc: 7821 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7822 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 7823 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7824 // CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 7825 // CHECK14: for.end: 7826 // CHECK14-NEXT: ret void 7827 // 7828 // 7829 // CHECK14-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 7830 // CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7831 // CHECK14-NEXT: entry: 7832 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7833 // CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7834 // CHECK14-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7835 // CHECK14-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7836 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 7837 // CHECK14-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7838 // CHECK14-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7839 // CHECK14-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7840 // CHECK14-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7841 // CHECK14-NEXT: store i32 131071, i32* [[I]], align 4 7842 // CHECK14-NEXT: br label [[FOR_COND:%.*]] 7843 // CHECK14: for.cond: 7844 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7845 // CHECK14-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 7846 // CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7847 // CHECK14: for.body: 7848 // CHECK14-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 7849 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7850 // CHECK14-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 7851 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 7852 // CHECK14-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7853 // CHECK14-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 7854 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7855 // CHECK14-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 7856 // CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 7857 // CHECK14-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7858 // CHECK14-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7859 // CHECK14-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 7860 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7861 // CHECK14-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 7862 // CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 7863 // CHECK14-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 7864 // CHECK14-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 7865 // CHECK14-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 7866 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7867 // CHECK14-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 7868 // CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 7869 // CHECK14-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 7870 // CHECK14-NEXT: br label [[FOR_INC:%.*]] 7871 // CHECK14: for.inc: 7872 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7873 // CHECK14-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 7874 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7875 // CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 7876 // CHECK14: for.end: 7877 // CHECK14-NEXT: ret void 7878 // 7879 // 7880 // CHECK14-LABEL: define {{[^@]+}}@_Z12test_precondv 7881 // CHECK14-SAME: () #[[ATTR0]] { 7882 // CHECK14-NEXT: entry: 7883 // CHECK14-NEXT: [[A:%.*]] = alloca i8, align 1 7884 // CHECK14-NEXT: [[I:%.*]] = alloca i8, align 1 7885 // CHECK14-NEXT: store i8 0, i8* [[A]], align 1 7886 // CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 7887 // CHECK14-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 7888 // CHECK14-NEXT: br label [[FOR_COND:%.*]] 7889 // CHECK14: for.cond: 7890 // CHECK14-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 7891 // CHECK14-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 7892 // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 7893 // CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7894 // CHECK14: for.body: 7895 // CHECK14-NEXT: br label [[FOR_INC:%.*]] 7896 // CHECK14: for.inc: 7897 // CHECK14-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 7898 // CHECK14-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 7899 // CHECK14-NEXT: store i8 [[INC]], i8* [[I]], align 1 7900 // CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 7901 // CHECK14: for.end: 7902 // CHECK14-NEXT: ret void 7903 // 7904 // 7905 // CHECK14-LABEL: define {{[^@]+}}@_Z4fintv 7906 // CHECK14-SAME: () #[[ATTR0]] { 7907 // CHECK14-NEXT: entry: 7908 // CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() 7909 // CHECK14-NEXT: ret i32 [[CALL]] 7910 // 7911 // 7912 // CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 7913 // CHECK14-SAME: () #[[ATTR0]] comdat { 7914 // CHECK14-NEXT: entry: 7915 // CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 7916 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 7917 // CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 7918 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4 7919 // CHECK14-NEXT: br label [[FOR_COND:%.*]] 7920 // CHECK14: for.cond: 7921 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7922 // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 7923 // CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7924 // CHECK14: for.body: 7925 // CHECK14-NEXT: br label [[FOR_INC:%.*]] 7926 // CHECK14: for.inc: 7927 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 7928 // CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 7929 // CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 7930 // CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 7931 // CHECK14: for.end: 7932 // CHECK14-NEXT: ret i32 0 7933 // 7934 // 7935 // CHECK15-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 7936 // CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 7937 // CHECK15-NEXT: entry: 7938 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 7939 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 7940 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 7941 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 7942 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 7943 // CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 7944 // CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 7945 // CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 7946 // CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 7947 // CHECK15-NEXT: store i32 33, i32* [[I]], align 4 7948 // CHECK15-NEXT: br label [[FOR_COND:%.*]] 7949 // CHECK15: for.cond: 7950 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7951 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 7952 // CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7953 // CHECK15: for.body: 7954 // CHECK15-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 7955 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7956 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 7957 // CHECK15-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7958 // CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 7959 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7960 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 7961 // CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 7962 // CHECK15-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7963 // CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 7964 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7965 // CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 7966 // CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7967 // CHECK15-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 7968 // CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 7969 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7970 // CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 7971 // CHECK15-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 7972 // CHECK15-NEXT: br label [[FOR_INC:%.*]] 7973 // CHECK15: for.inc: 7974 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7975 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 7976 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7977 // CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 7978 // CHECK15: for.end: 7979 // CHECK15-NEXT: ret void 7980 // 7981 // 7982 // CHECK15-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 7983 // CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7984 // CHECK15-NEXT: entry: 7985 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 7986 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 7987 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 7988 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 7989 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 7990 // CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 7991 // CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 7992 // CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 7993 // CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 7994 // CHECK15-NEXT: store i32 32000000, i32* [[I]], align 4 7995 // CHECK15-NEXT: br label [[FOR_COND:%.*]] 7996 // CHECK15: for.cond: 7997 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7998 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 7999 // CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 8000 // CHECK15: for.body: 8001 // CHECK15-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 8002 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 8003 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 8004 // CHECK15-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 8005 // CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 8006 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 8007 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 8008 // CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 8009 // CHECK15-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 8010 // CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 8011 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 8012 // CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 8013 // CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 8014 // CHECK15-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 8015 // CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 8016 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 8017 // CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 8018 // CHECK15-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 8019 // CHECK15-NEXT: br label [[FOR_INC:%.*]] 8020 // CHECK15: for.inc: 8021 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 8022 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 8023 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 8024 // CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 8025 // CHECK15: for.end: 8026 // CHECK15-NEXT: ret void 8027 // 8028 // 8029 // CHECK15-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 8030 // CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 8031 // CHECK15-NEXT: entry: 8032 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 8033 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 8034 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 8035 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 8036 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 8037 // CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 8038 // CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 8039 // CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 8040 // CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 8041 // CHECK15-NEXT: store i32 131071, i32* [[I]], align 4 8042 // CHECK15-NEXT: br label [[FOR_COND:%.*]] 8043 // CHECK15: for.cond: 8044 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 8045 // CHECK15-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 8046 // CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 8047 // CHECK15: for.body: 8048 // CHECK15-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 8049 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 8050 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 8051 // CHECK15-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 8052 // CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 8053 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 8054 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 8055 // CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 8056 // CHECK15-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 8057 // CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 8058 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 8059 // CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 8060 // CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 8061 // CHECK15-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 8062 // CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 8063 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 8064 // CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 8065 // CHECK15-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 8066 // CHECK15-NEXT: br label [[FOR_INC:%.*]] 8067 // CHECK15: for.inc: 8068 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 8069 // CHECK15-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 8070 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 8071 // CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 8072 // CHECK15: for.end: 8073 // CHECK15-NEXT: ret void 8074 // 8075 // 8076 // CHECK15-LABEL: define {{[^@]+}}@_Z12test_precondv 8077 // CHECK15-SAME: () #[[ATTR0]] { 8078 // CHECK15-NEXT: entry: 8079 // CHECK15-NEXT: [[A:%.*]] = alloca i8, align 1 8080 // CHECK15-NEXT: [[I:%.*]] = alloca i8, align 1 8081 // CHECK15-NEXT: store i8 0, i8* [[A]], align 1 8082 // CHECK15-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 8083 // CHECK15-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 8084 // CHECK15-NEXT: br label [[FOR_COND:%.*]] 8085 // CHECK15: for.cond: 8086 // CHECK15-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 8087 // CHECK15-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 8088 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 8089 // CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 8090 // CHECK15: for.body: 8091 // CHECK15-NEXT: br label [[FOR_INC:%.*]] 8092 // CHECK15: for.inc: 8093 // CHECK15-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 8094 // CHECK15-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 8095 // CHECK15-NEXT: store i8 [[INC]], i8* [[I]], align 1 8096 // CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 8097 // CHECK15: for.end: 8098 // CHECK15-NEXT: ret void 8099 // 8100 // 8101 // CHECK15-LABEL: define {{[^@]+}}@_Z4fintv 8102 // CHECK15-SAME: () #[[ATTR0]] { 8103 // CHECK15-NEXT: entry: 8104 // CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() 8105 // CHECK15-NEXT: ret i32 [[CALL]] 8106 // 8107 // 8108 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 8109 // CHECK15-SAME: () #[[ATTR0]] comdat { 8110 // CHECK15-NEXT: entry: 8111 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8112 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 8113 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 8114 // CHECK15-NEXT: store i32 0, i32* [[I]], align 4 8115 // CHECK15-NEXT: br label [[FOR_COND:%.*]] 8116 // CHECK15: for.cond: 8117 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 8118 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 8119 // CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 8120 // CHECK15: for.body: 8121 // CHECK15-NEXT: br label [[FOR_INC:%.*]] 8122 // CHECK15: for.inc: 8123 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 8124 // CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 8125 // CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 8126 // CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 8127 // CHECK15: for.end: 8128 // CHECK15-NEXT: ret i32 0 8129 // 8130 // 8131 // CHECK16-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 8132 // CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 8133 // CHECK16-NEXT: entry: 8134 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 8135 // CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 8136 // CHECK16-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 8137 // CHECK16-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 8138 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 8139 // CHECK16-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 8140 // CHECK16-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 8141 // CHECK16-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 8142 // CHECK16-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 8143 // CHECK16-NEXT: store i32 33, i32* [[I]], align 4 8144 // CHECK16-NEXT: br label [[FOR_COND:%.*]] 8145 // CHECK16: for.cond: 8146 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 8147 // CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 8148 // CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 8149 // CHECK16: for.body: 8150 // CHECK16-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 8151 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 8152 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 8153 // CHECK16-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 8154 // CHECK16-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 8155 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 8156 // CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 8157 // CHECK16-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 8158 // CHECK16-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 8159 // CHECK16-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 8160 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 8161 // CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 8162 // CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 8163 // CHECK16-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 8164 // CHECK16-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 8165 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 8166 // CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 8167 // CHECK16-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 8168 // CHECK16-NEXT: br label [[FOR_INC:%.*]] 8169 // CHECK16: for.inc: 8170 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 8171 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 8172 // CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 8173 // CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 8174 // CHECK16: for.end: 8175 // CHECK16-NEXT: ret void 8176 // 8177 // 8178 // CHECK16-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 8179 // CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 8180 // CHECK16-NEXT: entry: 8181 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 8182 // CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 8183 // CHECK16-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 8184 // CHECK16-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 8185 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 8186 // CHECK16-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 8187 // CHECK16-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 8188 // CHECK16-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 8189 // CHECK16-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 8190 // CHECK16-NEXT: store i32 32000000, i32* [[I]], align 4 8191 // CHECK16-NEXT: br label [[FOR_COND:%.*]] 8192 // CHECK16: for.cond: 8193 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 8194 // CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 8195 // CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 8196 // CHECK16: for.body: 8197 // CHECK16-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 8198 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 8199 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 8200 // CHECK16-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 8201 // CHECK16-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 8202 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 8203 // CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 8204 // CHECK16-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 8205 // CHECK16-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 8206 // CHECK16-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 8207 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 8208 // CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 8209 // CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 8210 // CHECK16-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 8211 // CHECK16-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 8212 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 8213 // CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 8214 // CHECK16-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 8215 // CHECK16-NEXT: br label [[FOR_INC:%.*]] 8216 // CHECK16: for.inc: 8217 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 8218 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 8219 // CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 8220 // CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 8221 // CHECK16: for.end: 8222 // CHECK16-NEXT: ret void 8223 // 8224 // 8225 // CHECK16-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 8226 // CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 8227 // CHECK16-NEXT: entry: 8228 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 8229 // CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 8230 // CHECK16-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 8231 // CHECK16-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 8232 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 8233 // CHECK16-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 8234 // CHECK16-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 8235 // CHECK16-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 8236 // CHECK16-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 8237 // CHECK16-NEXT: store i32 131071, i32* [[I]], align 4 8238 // CHECK16-NEXT: br label [[FOR_COND:%.*]] 8239 // CHECK16: for.cond: 8240 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 8241 // CHECK16-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 8242 // CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 8243 // CHECK16: for.body: 8244 // CHECK16-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 8245 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 8246 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 8247 // CHECK16-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 8248 // CHECK16-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 8249 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 8250 // CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 8251 // CHECK16-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 8252 // CHECK16-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 8253 // CHECK16-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 8254 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 8255 // CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 8256 // CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 8257 // CHECK16-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 8258 // CHECK16-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 8259 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 8260 // CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 8261 // CHECK16-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 8262 // CHECK16-NEXT: br label [[FOR_INC:%.*]] 8263 // CHECK16: for.inc: 8264 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 8265 // CHECK16-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 8266 // CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 8267 // CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 8268 // CHECK16: for.end: 8269 // CHECK16-NEXT: ret void 8270 // 8271 // 8272 // CHECK16-LABEL: define {{[^@]+}}@_Z12test_precondv 8273 // CHECK16-SAME: () #[[ATTR0]] { 8274 // CHECK16-NEXT: entry: 8275 // CHECK16-NEXT: [[A:%.*]] = alloca i8, align 1 8276 // CHECK16-NEXT: [[I:%.*]] = alloca i8, align 1 8277 // CHECK16-NEXT: store i8 0, i8* [[A]], align 1 8278 // CHECK16-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 8279 // CHECK16-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 8280 // CHECK16-NEXT: br label [[FOR_COND:%.*]] 8281 // CHECK16: for.cond: 8282 // CHECK16-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 8283 // CHECK16-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 8284 // CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 8285 // CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 8286 // CHECK16: for.body: 8287 // CHECK16-NEXT: br label [[FOR_INC:%.*]] 8288 // CHECK16: for.inc: 8289 // CHECK16-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 8290 // CHECK16-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 8291 // CHECK16-NEXT: store i8 [[INC]], i8* [[I]], align 1 8292 // CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 8293 // CHECK16: for.end: 8294 // CHECK16-NEXT: ret void 8295 // 8296 // 8297 // CHECK16-LABEL: define {{[^@]+}}@_Z4fintv 8298 // CHECK16-SAME: () #[[ATTR0]] { 8299 // CHECK16-NEXT: entry: 8300 // CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() 8301 // CHECK16-NEXT: ret i32 [[CALL]] 8302 // 8303 // 8304 // CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 8305 // CHECK16-SAME: () #[[ATTR0]] comdat { 8306 // CHECK16-NEXT: entry: 8307 // CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 8308 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 8309 // CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 8310 // CHECK16-NEXT: store i32 0, i32* [[I]], align 4 8311 // CHECK16-NEXT: br label [[FOR_COND:%.*]] 8312 // CHECK16: for.cond: 8313 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 8314 // CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 8315 // CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 8316 // CHECK16: for.body: 8317 // CHECK16-NEXT: br label [[FOR_INC:%.*]] 8318 // CHECK16: for.inc: 8319 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 8320 // CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 8321 // CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 8322 // CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 8323 // CHECK16: for.end: 8324 // CHECK16-NEXT: ret i32 0 8325 // 8326 // 8327 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 8328 // CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 8329 // CHECK17-NEXT: entry: 8330 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 8331 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 8332 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 8333 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 8334 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 8335 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 8336 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 8337 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 8338 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 8339 // CHECK17-NEXT: ret void 8340 // 8341 // 8342 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 8343 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 8344 // CHECK17-NEXT: entry: 8345 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8346 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8347 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 8348 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 8349 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 8350 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 8351 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8352 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 8353 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8354 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8355 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8356 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8357 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 8358 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8359 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8360 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 8361 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 8362 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 8363 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 8364 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 8365 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 8366 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 8367 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 8368 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8369 // CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 8370 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8371 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8372 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8373 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 8374 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8375 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8376 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 8377 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8378 // CHECK17: cond.true: 8379 // CHECK17-NEXT: br label [[COND_END:%.*]] 8380 // CHECK17: cond.false: 8381 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8382 // CHECK17-NEXT: br label [[COND_END]] 8383 // CHECK17: cond.end: 8384 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 8385 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8386 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8387 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 8388 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8389 // CHECK17: omp.inner.for.cond: 8390 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8391 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8392 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 8393 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8394 // CHECK17: omp.inner.for.body: 8395 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8396 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 8397 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 8398 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 8399 // CHECK17-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 8400 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 8401 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 8402 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 8403 // CHECK17-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 8404 // CHECK17-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 8405 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 8406 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 8407 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 8408 // CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 8409 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 8410 // CHECK17-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 8411 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 8412 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 8413 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 8414 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 8415 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 8416 // CHECK17-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 8417 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 8418 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 8419 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 8420 // CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 8421 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8422 // CHECK17: omp.body.continue: 8423 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8424 // CHECK17: omp.inner.for.inc: 8425 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8426 // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 8427 // CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 8428 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 8429 // CHECK17: omp.inner.for.end: 8430 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8431 // CHECK17: omp.loop.exit: 8432 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 8433 // CHECK17-NEXT: ret void 8434 // 8435 // 8436 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 8437 // CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 8438 // CHECK17-NEXT: entry: 8439 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 8440 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 8441 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 8442 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 8443 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 8444 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 8445 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 8446 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 8447 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 8448 // CHECK17-NEXT: ret void 8449 // 8450 // 8451 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 8452 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 8453 // CHECK17-NEXT: entry: 8454 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8455 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8456 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 8457 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 8458 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 8459 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 8460 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8461 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 8462 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8463 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8464 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8465 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8466 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 8467 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8468 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8469 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 8470 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 8471 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 8472 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 8473 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 8474 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 8475 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 8476 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 8477 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8478 // CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 8479 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8480 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8481 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8482 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 8483 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8484 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8485 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 8486 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8487 // CHECK17: cond.true: 8488 // CHECK17-NEXT: br label [[COND_END:%.*]] 8489 // CHECK17: cond.false: 8490 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8491 // CHECK17-NEXT: br label [[COND_END]] 8492 // CHECK17: cond.end: 8493 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 8494 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8495 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8496 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 8497 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8498 // CHECK17: omp.inner.for.cond: 8499 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8500 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8501 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 8502 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8503 // CHECK17: omp.inner.for.body: 8504 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8505 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 8506 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 8507 // CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4 8508 // CHECK17-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 8509 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 8510 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 8511 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 8512 // CHECK17-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 8513 // CHECK17-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 8514 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 8515 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 8516 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 8517 // CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 8518 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 8519 // CHECK17-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 8520 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 8521 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 8522 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 8523 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 8524 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 8525 // CHECK17-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 8526 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 8527 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 8528 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 8529 // CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 8530 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8531 // CHECK17: omp.body.continue: 8532 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8533 // CHECK17: omp.inner.for.inc: 8534 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8535 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 8536 // CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 8537 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 8538 // CHECK17: omp.inner.for.end: 8539 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8540 // CHECK17: omp.loop.exit: 8541 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 8542 // CHECK17-NEXT: ret void 8543 // 8544 // 8545 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 8546 // CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 8547 // CHECK17-NEXT: entry: 8548 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 8549 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 8550 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 8551 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 8552 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 8553 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 8554 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 8555 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 8556 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 8557 // CHECK17-NEXT: ret void 8558 // 8559 // 8560 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 8561 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 8562 // CHECK17-NEXT: entry: 8563 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8564 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8565 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 8566 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 8567 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 8568 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 8569 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8570 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 8571 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8572 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8573 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8574 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8575 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 8576 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8577 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8578 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 8579 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 8580 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 8581 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 8582 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 8583 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 8584 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 8585 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 8586 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8587 // CHECK17-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 8588 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8589 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8590 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8591 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 8592 // CHECK17-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 8593 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 8594 // CHECK17: omp.dispatch.cond: 8595 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8596 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 8597 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8598 // CHECK17: cond.true: 8599 // CHECK17-NEXT: br label [[COND_END:%.*]] 8600 // CHECK17: cond.false: 8601 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8602 // CHECK17-NEXT: br label [[COND_END]] 8603 // CHECK17: cond.end: 8604 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 8605 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8606 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8607 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 8608 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8609 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8610 // CHECK17-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 8611 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 8612 // CHECK17: omp.dispatch.body: 8613 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8614 // CHECK17: omp.inner.for.cond: 8615 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 8616 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 8617 // CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 8618 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8619 // CHECK17: omp.inner.for.body: 8620 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 8621 // CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 8622 // CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 8623 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 8624 // CHECK17-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 8625 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 8626 // CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 8627 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 8628 // CHECK17-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 8629 // CHECK17-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 8630 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 8631 // CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 8632 // CHECK17-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 8633 // CHECK17-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9 8634 // CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 8635 // CHECK17-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 8636 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 8637 // CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 8638 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 8639 // CHECK17-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !9 8640 // CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 8641 // CHECK17-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 8642 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 8643 // CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 8644 // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 8645 // CHECK17-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 8646 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8647 // CHECK17: omp.body.continue: 8648 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8649 // CHECK17: omp.inner.for.inc: 8650 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 8651 // CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 8652 // CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 8653 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 8654 // CHECK17: omp.inner.for.end: 8655 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 8656 // CHECK17: omp.dispatch.inc: 8657 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8658 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 8659 // CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 8660 // CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 8661 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8662 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 8663 // CHECK17-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 8664 // CHECK17-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 8665 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 8666 // CHECK17: omp.dispatch.end: 8667 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 8668 // CHECK17-NEXT: ret void 8669 // 8670 // 8671 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 8672 // CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { 8673 // CHECK17-NEXT: entry: 8674 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8675 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8676 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* 8677 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) 8678 // CHECK17-NEXT: ret void 8679 // 8680 // 8681 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 8682 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 8683 // CHECK17-NEXT: entry: 8684 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8685 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8686 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 8687 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8688 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 8689 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 8690 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 8691 // CHECK17-NEXT: [[I:%.*]] = alloca i8, align 1 8692 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8693 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8694 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8695 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8696 // CHECK17-NEXT: [[I5:%.*]] = alloca i8, align 1 8697 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8698 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8699 // CHECK17-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 8700 // CHECK17-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 8701 // CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 8702 // CHECK17-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 8703 // CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 8704 // CHECK17-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 8705 // CHECK17-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 8706 // CHECK17-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 8707 // CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 8708 // CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 8709 // CHECK17-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 8710 // CHECK17-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 8711 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 8712 // CHECK17-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 8713 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 8714 // CHECK17-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 8715 // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 8716 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 8717 // CHECK17: omp.precond.then: 8718 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8719 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 8720 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 8721 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8722 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8723 // CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8724 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 8725 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8726 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8727 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 8728 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 8729 // CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8730 // CHECK17: cond.true: 8731 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 8732 // CHECK17-NEXT: br label [[COND_END:%.*]] 8733 // CHECK17: cond.false: 8734 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8735 // CHECK17-NEXT: br label [[COND_END]] 8736 // CHECK17: cond.end: 8737 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 8738 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8739 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8740 // CHECK17-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 8741 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8742 // CHECK17: omp.inner.for.cond: 8743 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8744 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8745 // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 8746 // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8747 // CHECK17: omp.inner.for.body: 8748 // CHECK17-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 8749 // CHECK17-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 8750 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8751 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 8752 // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 8753 // CHECK17-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 8754 // CHECK17-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 8755 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8756 // CHECK17: omp.body.continue: 8757 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8758 // CHECK17: omp.inner.for.inc: 8759 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8760 // CHECK17-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 8761 // CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 8762 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 8763 // CHECK17: omp.inner.for.end: 8764 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8765 // CHECK17: omp.loop.exit: 8766 // CHECK17-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8767 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 8768 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 8769 // CHECK17-NEXT: br label [[OMP_PRECOND_END]] 8770 // CHECK17: omp.precond.end: 8771 // CHECK17-NEXT: ret void 8772 // 8773 // 8774 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 8775 // CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { 8776 // CHECK17-NEXT: entry: 8777 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8778 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8779 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8780 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) 8781 // CHECK17-NEXT: ret void 8782 // 8783 // 8784 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 8785 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 8786 // CHECK17-NEXT: entry: 8787 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8788 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8789 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 8790 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8791 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 8792 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8793 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8794 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8795 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8796 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 8797 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8798 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8799 // CHECK17-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 8800 // CHECK17-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 8801 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8802 // CHECK17-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 8803 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8804 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8805 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 8806 // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 8807 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8808 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 8809 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 8810 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 8811 // CHECK17: omp.dispatch.cond: 8812 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8813 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 8814 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8815 // CHECK17: cond.true: 8816 // CHECK17-NEXT: br label [[COND_END:%.*]] 8817 // CHECK17: cond.false: 8818 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8819 // CHECK17-NEXT: br label [[COND_END]] 8820 // CHECK17: cond.end: 8821 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 8822 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8823 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8824 // CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 8825 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8826 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8827 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 8828 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 8829 // CHECK17: omp.dispatch.body: 8830 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8831 // CHECK17: omp.inner.for.cond: 8832 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 8833 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 8834 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 8835 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8836 // CHECK17: omp.inner.for.body: 8837 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 8838 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 8839 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 8840 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 8841 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8842 // CHECK17: omp.body.continue: 8843 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8844 // CHECK17: omp.inner.for.inc: 8845 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 8846 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 8847 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 8848 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 8849 // CHECK17: omp.inner.for.end: 8850 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 8851 // CHECK17: omp.dispatch.inc: 8852 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8853 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 8854 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 8855 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 8856 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8857 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 8858 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 8859 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 8860 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 8861 // CHECK17: omp.dispatch.end: 8862 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 8863 // CHECK17-NEXT: ret void 8864 // 8865 // 8866 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 8867 // CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 8868 // CHECK18-NEXT: entry: 8869 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 8870 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 8871 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 8872 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 8873 // CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 8874 // CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 8875 // CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 8876 // CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 8877 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 8878 // CHECK18-NEXT: ret void 8879 // 8880 // 8881 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. 8882 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 8883 // CHECK18-NEXT: entry: 8884 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8885 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8886 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 8887 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 8888 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 8889 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 8890 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8891 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 8892 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8893 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8894 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8895 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8896 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 8897 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8898 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8899 // CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 8900 // CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 8901 // CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 8902 // CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 8903 // CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 8904 // CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 8905 // CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 8906 // CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 8907 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8908 // CHECK18-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 8909 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8910 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8911 // CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8912 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 8913 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8914 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8915 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 8916 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8917 // CHECK18: cond.true: 8918 // CHECK18-NEXT: br label [[COND_END:%.*]] 8919 // CHECK18: cond.false: 8920 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8921 // CHECK18-NEXT: br label [[COND_END]] 8922 // CHECK18: cond.end: 8923 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 8924 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8925 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8926 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 8927 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8928 // CHECK18: omp.inner.for.cond: 8929 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8930 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8931 // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 8932 // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8933 // CHECK18: omp.inner.for.body: 8934 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8935 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 8936 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 8937 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 8938 // CHECK18-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 8939 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 8940 // CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 8941 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 8942 // CHECK18-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 8943 // CHECK18-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 8944 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 8945 // CHECK18-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 8946 // CHECK18-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 8947 // CHECK18-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 8948 // CHECK18-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 8949 // CHECK18-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 8950 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 8951 // CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 8952 // CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 8953 // CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 8954 // CHECK18-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 8955 // CHECK18-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 8956 // CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 8957 // CHECK18-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 8958 // CHECK18-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 8959 // CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 8960 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8961 // CHECK18: omp.body.continue: 8962 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8963 // CHECK18: omp.inner.for.inc: 8964 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8965 // CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 8966 // CHECK18-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 8967 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 8968 // CHECK18: omp.inner.for.end: 8969 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8970 // CHECK18: omp.loop.exit: 8971 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 8972 // CHECK18-NEXT: ret void 8973 // 8974 // 8975 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 8976 // CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 8977 // CHECK18-NEXT: entry: 8978 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 8979 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 8980 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 8981 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 8982 // CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 8983 // CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 8984 // CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 8985 // CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 8986 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 8987 // CHECK18-NEXT: ret void 8988 // 8989 // 8990 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 8991 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 8992 // CHECK18-NEXT: entry: 8993 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8994 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8995 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 8996 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 8997 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 8998 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 8999 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9000 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 9001 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9002 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9003 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9004 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9005 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 9006 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9007 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9008 // CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 9009 // CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 9010 // CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 9011 // CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 9012 // CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 9013 // CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 9014 // CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 9015 // CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 9016 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9017 // CHECK18-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 9018 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9019 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9020 // CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9021 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 9022 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9023 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9024 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 9025 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9026 // CHECK18: cond.true: 9027 // CHECK18-NEXT: br label [[COND_END:%.*]] 9028 // CHECK18: cond.false: 9029 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9030 // CHECK18-NEXT: br label [[COND_END]] 9031 // CHECK18: cond.end: 9032 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9033 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9034 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9035 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 9036 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9037 // CHECK18: omp.inner.for.cond: 9038 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9039 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9040 // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 9041 // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9042 // CHECK18: omp.inner.for.body: 9043 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9044 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 9045 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 9046 // CHECK18-NEXT: store i32 [[SUB]], i32* [[I]], align 4 9047 // CHECK18-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 9048 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 9049 // CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 9050 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 9051 // CHECK18-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 9052 // CHECK18-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 9053 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 9054 // CHECK18-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 9055 // CHECK18-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 9056 // CHECK18-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 9057 // CHECK18-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 9058 // CHECK18-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 9059 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 9060 // CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 9061 // CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 9062 // CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 9063 // CHECK18-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 9064 // CHECK18-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 9065 // CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 9066 // CHECK18-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 9067 // CHECK18-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 9068 // CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 9069 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9070 // CHECK18: omp.body.continue: 9071 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9072 // CHECK18: omp.inner.for.inc: 9073 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9074 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 9075 // CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 9076 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 9077 // CHECK18: omp.inner.for.end: 9078 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9079 // CHECK18: omp.loop.exit: 9080 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 9081 // CHECK18-NEXT: ret void 9082 // 9083 // 9084 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 9085 // CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 9086 // CHECK18-NEXT: entry: 9087 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 9088 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 9089 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 9090 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 9091 // CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 9092 // CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 9093 // CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 9094 // CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 9095 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 9096 // CHECK18-NEXT: ret void 9097 // 9098 // 9099 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 9100 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 9101 // CHECK18-NEXT: entry: 9102 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9103 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9104 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 9105 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 9106 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 9107 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 9108 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9109 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 9110 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9111 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9112 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9113 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9114 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 9115 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9116 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9117 // CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 9118 // CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 9119 // CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 9120 // CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 9121 // CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 9122 // CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 9123 // CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 9124 // CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 9125 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9126 // CHECK18-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 9127 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9128 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9129 // CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9130 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 9131 // CHECK18-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 9132 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 9133 // CHECK18: omp.dispatch.cond: 9134 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9135 // CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 9136 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9137 // CHECK18: cond.true: 9138 // CHECK18-NEXT: br label [[COND_END:%.*]] 9139 // CHECK18: cond.false: 9140 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9141 // CHECK18-NEXT: br label [[COND_END]] 9142 // CHECK18: cond.end: 9143 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9144 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9145 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9146 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 9147 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9148 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9149 // CHECK18-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 9150 // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 9151 // CHECK18: omp.dispatch.body: 9152 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9153 // CHECK18: omp.inner.for.cond: 9154 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 9155 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 9156 // CHECK18-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 9157 // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9158 // CHECK18: omp.inner.for.body: 9159 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 9160 // CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 9161 // CHECK18-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 9162 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 9163 // CHECK18-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 9164 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 9165 // CHECK18-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 9166 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 9167 // CHECK18-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 9168 // CHECK18-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 9169 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 9170 // CHECK18-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 9171 // CHECK18-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 9172 // CHECK18-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9 9173 // CHECK18-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 9174 // CHECK18-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 9175 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 9176 // CHECK18-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 9177 // CHECK18-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 9178 // CHECK18-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !9 9179 // CHECK18-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 9180 // CHECK18-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 9181 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 9182 // CHECK18-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 9183 // CHECK18-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 9184 // CHECK18-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 9185 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9186 // CHECK18: omp.body.continue: 9187 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9188 // CHECK18: omp.inner.for.inc: 9189 // CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 9190 // CHECK18-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 9191 // CHECK18-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 9192 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 9193 // CHECK18: omp.inner.for.end: 9194 // CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 9195 // CHECK18: omp.dispatch.inc: 9196 // CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9197 // CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9198 // CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 9199 // CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 9200 // CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9201 // CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9202 // CHECK18-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 9203 // CHECK18-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 9204 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] 9205 // CHECK18: omp.dispatch.end: 9206 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 9207 // CHECK18-NEXT: ret void 9208 // 9209 // 9210 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 9211 // CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { 9212 // CHECK18-NEXT: entry: 9213 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9214 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9215 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* 9216 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) 9217 // CHECK18-NEXT: ret void 9218 // 9219 // 9220 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 9221 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 9222 // CHECK18-NEXT: entry: 9223 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9224 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9225 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 9226 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9227 // CHECK18-NEXT: [[TMP:%.*]] = alloca i8, align 1 9228 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 9229 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 9230 // CHECK18-NEXT: [[I:%.*]] = alloca i8, align 1 9231 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9232 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9233 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9234 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9235 // CHECK18-NEXT: [[I5:%.*]] = alloca i8, align 1 9236 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9237 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9238 // CHECK18-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 9239 // CHECK18-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 9240 // CHECK18-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 9241 // CHECK18-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 9242 // CHECK18-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 9243 // CHECK18-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 9244 // CHECK18-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 9245 // CHECK18-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 9246 // CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 9247 // CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 9248 // CHECK18-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 9249 // CHECK18-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 9250 // CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 9251 // CHECK18-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 9252 // CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 9253 // CHECK18-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 9254 // CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 9255 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 9256 // CHECK18: omp.precond.then: 9257 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9258 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 9259 // CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 9260 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9261 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9262 // CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9263 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 9264 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9265 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9266 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 9267 // CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 9268 // CHECK18-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9269 // CHECK18: cond.true: 9270 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 9271 // CHECK18-NEXT: br label [[COND_END:%.*]] 9272 // CHECK18: cond.false: 9273 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9274 // CHECK18-NEXT: br label [[COND_END]] 9275 // CHECK18: cond.end: 9276 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 9277 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9278 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9279 // CHECK18-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 9280 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9281 // CHECK18: omp.inner.for.cond: 9282 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9283 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9284 // CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 9285 // CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9286 // CHECK18: omp.inner.for.body: 9287 // CHECK18-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 9288 // CHECK18-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 9289 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9290 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 9291 // CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 9292 // CHECK18-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 9293 // CHECK18-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 9294 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9295 // CHECK18: omp.body.continue: 9296 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9297 // CHECK18: omp.inner.for.inc: 9298 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9299 // CHECK18-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 9300 // CHECK18-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 9301 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 9302 // CHECK18: omp.inner.for.end: 9303 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9304 // CHECK18: omp.loop.exit: 9305 // CHECK18-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9306 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 9307 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 9308 // CHECK18-NEXT: br label [[OMP_PRECOND_END]] 9309 // CHECK18: omp.precond.end: 9310 // CHECK18-NEXT: ret void 9311 // 9312 // 9313 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 9314 // CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { 9315 // CHECK18-NEXT: entry: 9316 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9317 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9318 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9319 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) 9320 // CHECK18-NEXT: ret void 9321 // 9322 // 9323 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 9324 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 9325 // CHECK18-NEXT: entry: 9326 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9327 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9328 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 9329 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9330 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 9331 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9332 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9333 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9334 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9335 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 9336 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9337 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9338 // CHECK18-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 9339 // CHECK18-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 9340 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9341 // CHECK18-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 9342 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9343 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9344 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 9345 // CHECK18-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 9346 // CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9347 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 9348 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 9349 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 9350 // CHECK18: omp.dispatch.cond: 9351 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9352 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 9353 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9354 // CHECK18: cond.true: 9355 // CHECK18-NEXT: br label [[COND_END:%.*]] 9356 // CHECK18: cond.false: 9357 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9358 // CHECK18-NEXT: br label [[COND_END]] 9359 // CHECK18: cond.end: 9360 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 9361 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9362 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9363 // CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 9364 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9365 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9366 // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 9367 // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 9368 // CHECK18: omp.dispatch.body: 9369 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9370 // CHECK18: omp.inner.for.cond: 9371 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 9372 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 9373 // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 9374 // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9375 // CHECK18: omp.inner.for.body: 9376 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 9377 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 9378 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 9379 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 9380 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9381 // CHECK18: omp.body.continue: 9382 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9383 // CHECK18: omp.inner.for.inc: 9384 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 9385 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 9386 // CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 9387 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 9388 // CHECK18: omp.inner.for.end: 9389 // CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 9390 // CHECK18: omp.dispatch.inc: 9391 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9392 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9393 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 9394 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 9395 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9396 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9397 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 9398 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 9399 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] 9400 // CHECK18: omp.dispatch.end: 9401 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 9402 // CHECK18-NEXT: ret void 9403 // 9404 // 9405 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 9406 // CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 9407 // CHECK19-NEXT: entry: 9408 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 9409 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 9410 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 9411 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 9412 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 9413 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 9414 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 9415 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 9416 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 9417 // CHECK19-NEXT: ret void 9418 // 9419 // 9420 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 9421 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 9422 // CHECK19-NEXT: entry: 9423 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9424 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9425 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 9426 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 9427 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 9428 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 9429 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9430 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 9431 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9432 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9433 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9434 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9435 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 9436 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9437 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9438 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 9439 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 9440 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 9441 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 9442 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 9443 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 9444 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 9445 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 9446 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9447 // CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 9448 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9449 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9450 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9451 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 9452 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9453 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9454 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 9455 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9456 // CHECK19: cond.true: 9457 // CHECK19-NEXT: br label [[COND_END:%.*]] 9458 // CHECK19: cond.false: 9459 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9460 // CHECK19-NEXT: br label [[COND_END]] 9461 // CHECK19: cond.end: 9462 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9463 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9464 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9465 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 9466 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9467 // CHECK19: omp.inner.for.cond: 9468 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9469 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9470 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 9471 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9472 // CHECK19: omp.inner.for.body: 9473 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9474 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 9475 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 9476 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 9477 // CHECK19-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 9478 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 9479 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 9480 // CHECK19-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 9481 // CHECK19-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 9482 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 9483 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 9484 // CHECK19-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 9485 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 9486 // CHECK19-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 9487 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 9488 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 9489 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 9490 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 9491 // CHECK19-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 9492 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 9493 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 9494 // CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 9495 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9496 // CHECK19: omp.body.continue: 9497 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9498 // CHECK19: omp.inner.for.inc: 9499 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9500 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 9501 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 9502 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 9503 // CHECK19: omp.inner.for.end: 9504 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9505 // CHECK19: omp.loop.exit: 9506 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 9507 // CHECK19-NEXT: ret void 9508 // 9509 // 9510 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 9511 // CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 9512 // CHECK19-NEXT: entry: 9513 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 9514 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 9515 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 9516 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 9517 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 9518 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 9519 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 9520 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 9521 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 9522 // CHECK19-NEXT: ret void 9523 // 9524 // 9525 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 9526 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 9527 // CHECK19-NEXT: entry: 9528 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9529 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9530 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 9531 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 9532 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 9533 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 9534 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9535 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 9536 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9537 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9538 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9539 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9540 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 9541 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9542 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9543 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 9544 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 9545 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 9546 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 9547 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 9548 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 9549 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 9550 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 9551 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9552 // CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 9553 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9554 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9555 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9556 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 9557 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9558 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9559 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 9560 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9561 // CHECK19: cond.true: 9562 // CHECK19-NEXT: br label [[COND_END:%.*]] 9563 // CHECK19: cond.false: 9564 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9565 // CHECK19-NEXT: br label [[COND_END]] 9566 // CHECK19: cond.end: 9567 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9568 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9569 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9570 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 9571 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9572 // CHECK19: omp.inner.for.cond: 9573 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9574 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9575 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 9576 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9577 // CHECK19: omp.inner.for.body: 9578 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9579 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 9580 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 9581 // CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4 9582 // CHECK19-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 9583 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 9584 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 9585 // CHECK19-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 9586 // CHECK19-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 9587 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 9588 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 9589 // CHECK19-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 9590 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 9591 // CHECK19-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 9592 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 9593 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 9594 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 9595 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 9596 // CHECK19-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 9597 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 9598 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 9599 // CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 9600 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9601 // CHECK19: omp.body.continue: 9602 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9603 // CHECK19: omp.inner.for.inc: 9604 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9605 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 9606 // CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 9607 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 9608 // CHECK19: omp.inner.for.end: 9609 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9610 // CHECK19: omp.loop.exit: 9611 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 9612 // CHECK19-NEXT: ret void 9613 // 9614 // 9615 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 9616 // CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 9617 // CHECK19-NEXT: entry: 9618 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 9619 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 9620 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 9621 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 9622 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 9623 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 9624 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 9625 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 9626 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 9627 // CHECK19-NEXT: ret void 9628 // 9629 // 9630 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 9631 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 9632 // CHECK19-NEXT: entry: 9633 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9634 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9635 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 9636 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 9637 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 9638 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 9639 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9640 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 9641 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9642 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9643 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9644 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9645 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 9646 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9647 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9648 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 9649 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 9650 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 9651 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 9652 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 9653 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 9654 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 9655 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 9656 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9657 // CHECK19-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 9658 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9659 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9660 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9661 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 9662 // CHECK19-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 9663 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 9664 // CHECK19: omp.dispatch.cond: 9665 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9666 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 9667 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9668 // CHECK19: cond.true: 9669 // CHECK19-NEXT: br label [[COND_END:%.*]] 9670 // CHECK19: cond.false: 9671 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9672 // CHECK19-NEXT: br label [[COND_END]] 9673 // CHECK19: cond.end: 9674 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9675 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9676 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9677 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 9678 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9679 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9680 // CHECK19-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 9681 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 9682 // CHECK19: omp.dispatch.body: 9683 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9684 // CHECK19: omp.inner.for.cond: 9685 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 9686 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 9687 // CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 9688 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9689 // CHECK19: omp.inner.for.body: 9690 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 9691 // CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 9692 // CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 9693 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 9694 // CHECK19-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 9695 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 9696 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 9697 // CHECK19-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 9698 // CHECK19-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 9699 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 9700 // CHECK19-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 9701 // CHECK19-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10 9702 // CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 9703 // CHECK19-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 9704 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 9705 // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 9706 // CHECK19-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 9707 // CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 9708 // CHECK19-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 9709 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 9710 // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 9711 // CHECK19-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10 9712 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9713 // CHECK19: omp.body.continue: 9714 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9715 // CHECK19: omp.inner.for.inc: 9716 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 9717 // CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 9718 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 9719 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 9720 // CHECK19: omp.inner.for.end: 9721 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 9722 // CHECK19: omp.dispatch.inc: 9723 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9724 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9725 // CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 9726 // CHECK19-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 9727 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9728 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9729 // CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 9730 // CHECK19-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 9731 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 9732 // CHECK19: omp.dispatch.end: 9733 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 9734 // CHECK19-NEXT: ret void 9735 // 9736 // 9737 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 9738 // CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { 9739 // CHECK19-NEXT: entry: 9740 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9741 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9742 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* 9743 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) 9744 // CHECK19-NEXT: ret void 9745 // 9746 // 9747 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 9748 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 9749 // CHECK19-NEXT: entry: 9750 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9751 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9752 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 9753 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9754 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 9755 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 9756 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 9757 // CHECK19-NEXT: [[I:%.*]] = alloca i8, align 1 9758 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9759 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9760 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9761 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9762 // CHECK19-NEXT: [[I5:%.*]] = alloca i8, align 1 9763 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9764 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9765 // CHECK19-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 9766 // CHECK19-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 9767 // CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 9768 // CHECK19-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 9769 // CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 9770 // CHECK19-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 9771 // CHECK19-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 9772 // CHECK19-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 9773 // CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 9774 // CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 9775 // CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 9776 // CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 9777 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 9778 // CHECK19-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 9779 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 9780 // CHECK19-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 9781 // CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 9782 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 9783 // CHECK19: omp.precond.then: 9784 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9785 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 9786 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 9787 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9788 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9789 // CHECK19-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9790 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 9791 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9792 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9793 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 9794 // CHECK19-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 9795 // CHECK19-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9796 // CHECK19: cond.true: 9797 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 9798 // CHECK19-NEXT: br label [[COND_END:%.*]] 9799 // CHECK19: cond.false: 9800 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9801 // CHECK19-NEXT: br label [[COND_END]] 9802 // CHECK19: cond.end: 9803 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 9804 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9805 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9806 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 9807 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9808 // CHECK19: omp.inner.for.cond: 9809 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9810 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9811 // CHECK19-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 9812 // CHECK19-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9813 // CHECK19: omp.inner.for.body: 9814 // CHECK19-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 9815 // CHECK19-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 9816 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9817 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 9818 // CHECK19-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 9819 // CHECK19-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 9820 // CHECK19-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 9821 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9822 // CHECK19: omp.body.continue: 9823 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9824 // CHECK19: omp.inner.for.inc: 9825 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9826 // CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 9827 // CHECK19-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 9828 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 9829 // CHECK19: omp.inner.for.end: 9830 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9831 // CHECK19: omp.loop.exit: 9832 // CHECK19-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9833 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 9834 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 9835 // CHECK19-NEXT: br label [[OMP_PRECOND_END]] 9836 // CHECK19: omp.precond.end: 9837 // CHECK19-NEXT: ret void 9838 // 9839 // 9840 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 9841 // CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { 9842 // CHECK19-NEXT: entry: 9843 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9844 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9845 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9846 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) 9847 // CHECK19-NEXT: ret void 9848 // 9849 // 9850 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 9851 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 9852 // CHECK19-NEXT: entry: 9853 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9854 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9855 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 9856 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9857 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 9858 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9859 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9860 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9861 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9862 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 9863 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9864 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9865 // CHECK19-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 9866 // CHECK19-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 9867 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9868 // CHECK19-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 9869 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9870 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9871 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 9872 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 9873 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9874 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 9875 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 9876 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 9877 // CHECK19: omp.dispatch.cond: 9878 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9879 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 9880 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9881 // CHECK19: cond.true: 9882 // CHECK19-NEXT: br label [[COND_END:%.*]] 9883 // CHECK19: cond.false: 9884 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9885 // CHECK19-NEXT: br label [[COND_END]] 9886 // CHECK19: cond.end: 9887 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 9888 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9889 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9890 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 9891 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9892 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9893 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 9894 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 9895 // CHECK19: omp.dispatch.body: 9896 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9897 // CHECK19: omp.inner.for.cond: 9898 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 9899 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 9900 // CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 9901 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9902 // CHECK19: omp.inner.for.body: 9903 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 9904 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 9905 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 9906 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 9907 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9908 // CHECK19: omp.body.continue: 9909 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9910 // CHECK19: omp.inner.for.inc: 9911 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 9912 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 9913 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 9914 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 9915 // CHECK19: omp.inner.for.end: 9916 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 9917 // CHECK19: omp.dispatch.inc: 9918 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9919 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9920 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 9921 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 9922 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9923 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9924 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 9925 // CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 9926 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 9927 // CHECK19: omp.dispatch.end: 9928 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 9929 // CHECK19-NEXT: ret void 9930 // 9931 // 9932 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 9933 // CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 9934 // CHECK20-NEXT: entry: 9935 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 9936 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 9937 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 9938 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 9939 // CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 9940 // CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 9941 // CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 9942 // CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 9943 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 9944 // CHECK20-NEXT: ret void 9945 // 9946 // 9947 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. 9948 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 9949 // CHECK20-NEXT: entry: 9950 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9951 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9952 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 9953 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 9954 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 9955 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 9956 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9957 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 9958 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9959 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9960 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9961 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9962 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 9963 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9964 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9965 // CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 9966 // CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 9967 // CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 9968 // CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 9969 // CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 9970 // CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 9971 // CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 9972 // CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 9973 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9974 // CHECK20-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 9975 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9976 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9977 // CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9978 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 9979 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9980 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9981 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 9982 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9983 // CHECK20: cond.true: 9984 // CHECK20-NEXT: br label [[COND_END:%.*]] 9985 // CHECK20: cond.false: 9986 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9987 // CHECK20-NEXT: br label [[COND_END]] 9988 // CHECK20: cond.end: 9989 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9990 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9991 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9992 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 9993 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9994 // CHECK20: omp.inner.for.cond: 9995 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9996 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9997 // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 9998 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9999 // CHECK20: omp.inner.for.body: 10000 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10001 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 10002 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 10003 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 10004 // CHECK20-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 10005 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 10006 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 10007 // CHECK20-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 10008 // CHECK20-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 10009 // CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 10010 // CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 10011 // CHECK20-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 10012 // CHECK20-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 10013 // CHECK20-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 10014 // CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 10015 // CHECK20-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 10016 // CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 10017 // CHECK20-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 10018 // CHECK20-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 10019 // CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 10020 // CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 10021 // CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 10022 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10023 // CHECK20: omp.body.continue: 10024 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10025 // CHECK20: omp.inner.for.inc: 10026 // CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10027 // CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 10028 // CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 10029 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 10030 // CHECK20: omp.inner.for.end: 10031 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10032 // CHECK20: omp.loop.exit: 10033 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 10034 // CHECK20-NEXT: ret void 10035 // 10036 // 10037 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 10038 // CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 10039 // CHECK20-NEXT: entry: 10040 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 10041 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 10042 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 10043 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 10044 // CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 10045 // CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 10046 // CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 10047 // CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 10048 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 10049 // CHECK20-NEXT: ret void 10050 // 10051 // 10052 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 10053 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 10054 // CHECK20-NEXT: entry: 10055 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10056 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10057 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 10058 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 10059 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 10060 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 10061 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10062 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 10063 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10064 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10065 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10066 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10067 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 10068 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10069 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10070 // CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 10071 // CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 10072 // CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 10073 // CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 10074 // CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 10075 // CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 10076 // CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 10077 // CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 10078 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10079 // CHECK20-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 10080 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10081 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10082 // CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10083 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 10084 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10085 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10086 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 10087 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10088 // CHECK20: cond.true: 10089 // CHECK20-NEXT: br label [[COND_END:%.*]] 10090 // CHECK20: cond.false: 10091 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10092 // CHECK20-NEXT: br label [[COND_END]] 10093 // CHECK20: cond.end: 10094 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 10095 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10096 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10097 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 10098 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10099 // CHECK20: omp.inner.for.cond: 10100 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10101 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10102 // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 10103 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10104 // CHECK20: omp.inner.for.body: 10105 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10106 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 10107 // CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 10108 // CHECK20-NEXT: store i32 [[SUB]], i32* [[I]], align 4 10109 // CHECK20-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 10110 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 10111 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 10112 // CHECK20-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 10113 // CHECK20-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 10114 // CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 10115 // CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 10116 // CHECK20-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 10117 // CHECK20-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 10118 // CHECK20-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 10119 // CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 10120 // CHECK20-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 10121 // CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 10122 // CHECK20-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 10123 // CHECK20-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 10124 // CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 10125 // CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 10126 // CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 10127 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10128 // CHECK20: omp.body.continue: 10129 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10130 // CHECK20: omp.inner.for.inc: 10131 // CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10132 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 10133 // CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 10134 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 10135 // CHECK20: omp.inner.for.end: 10136 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10137 // CHECK20: omp.loop.exit: 10138 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 10139 // CHECK20-NEXT: ret void 10140 // 10141 // 10142 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 10143 // CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 10144 // CHECK20-NEXT: entry: 10145 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 10146 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 10147 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 10148 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 10149 // CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 10150 // CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 10151 // CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 10152 // CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 10153 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 10154 // CHECK20-NEXT: ret void 10155 // 10156 // 10157 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 10158 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 10159 // CHECK20-NEXT: entry: 10160 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10161 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10162 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 10163 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 10164 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 10165 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 10166 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10167 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 10168 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10169 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10170 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10171 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10172 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 10173 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10174 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10175 // CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 10176 // CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 10177 // CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 10178 // CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 10179 // CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 10180 // CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 10181 // CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 10182 // CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 10183 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10184 // CHECK20-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 10185 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10186 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10187 // CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10188 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 10189 // CHECK20-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 10190 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 10191 // CHECK20: omp.dispatch.cond: 10192 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10193 // CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 10194 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10195 // CHECK20: cond.true: 10196 // CHECK20-NEXT: br label [[COND_END:%.*]] 10197 // CHECK20: cond.false: 10198 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10199 // CHECK20-NEXT: br label [[COND_END]] 10200 // CHECK20: cond.end: 10201 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 10202 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10203 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10204 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 10205 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10206 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10207 // CHECK20-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 10208 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 10209 // CHECK20: omp.dispatch.body: 10210 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10211 // CHECK20: omp.inner.for.cond: 10212 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 10213 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 10214 // CHECK20-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 10215 // CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10216 // CHECK20: omp.inner.for.body: 10217 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 10218 // CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 10219 // CHECK20-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 10220 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 10221 // CHECK20-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 10222 // CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 10223 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 10224 // CHECK20-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 10225 // CHECK20-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 10226 // CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 10227 // CHECK20-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 10228 // CHECK20-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10 10229 // CHECK20-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 10230 // CHECK20-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 10231 // CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 10232 // CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 10233 // CHECK20-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 10234 // CHECK20-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 10235 // CHECK20-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 10236 // CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 10237 // CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 10238 // CHECK20-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10 10239 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10240 // CHECK20: omp.body.continue: 10241 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10242 // CHECK20: omp.inner.for.inc: 10243 // CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 10244 // CHECK20-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 10245 // CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 10246 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 10247 // CHECK20: omp.inner.for.end: 10248 // CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 10249 // CHECK20: omp.dispatch.inc: 10250 // CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10251 // CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10252 // CHECK20-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 10253 // CHECK20-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 10254 // CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10255 // CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10256 // CHECK20-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 10257 // CHECK20-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 10258 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] 10259 // CHECK20: omp.dispatch.end: 10260 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 10261 // CHECK20-NEXT: ret void 10262 // 10263 // 10264 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 10265 // CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { 10266 // CHECK20-NEXT: entry: 10267 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10268 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10269 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* 10270 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) 10271 // CHECK20-NEXT: ret void 10272 // 10273 // 10274 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 10275 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 10276 // CHECK20-NEXT: entry: 10277 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10278 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10279 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 10280 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10281 // CHECK20-NEXT: [[TMP:%.*]] = alloca i8, align 1 10282 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 10283 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 10284 // CHECK20-NEXT: [[I:%.*]] = alloca i8, align 1 10285 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10286 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10287 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10288 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10289 // CHECK20-NEXT: [[I5:%.*]] = alloca i8, align 1 10290 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10291 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10292 // CHECK20-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 10293 // CHECK20-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 10294 // CHECK20-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 10295 // CHECK20-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 10296 // CHECK20-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 10297 // CHECK20-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 10298 // CHECK20-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 10299 // CHECK20-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 10300 // CHECK20-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 10301 // CHECK20-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 10302 // CHECK20-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 10303 // CHECK20-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 10304 // CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 10305 // CHECK20-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 10306 // CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 10307 // CHECK20-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 10308 // CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 10309 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 10310 // CHECK20: omp.precond.then: 10311 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10312 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 10313 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 10314 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10315 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10316 // CHECK20-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10317 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 10318 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10319 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10320 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 10321 // CHECK20-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 10322 // CHECK20-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10323 // CHECK20: cond.true: 10324 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 10325 // CHECK20-NEXT: br label [[COND_END:%.*]] 10326 // CHECK20: cond.false: 10327 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10328 // CHECK20-NEXT: br label [[COND_END]] 10329 // CHECK20: cond.end: 10330 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 10331 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10332 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10333 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 10334 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10335 // CHECK20: omp.inner.for.cond: 10336 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10337 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10338 // CHECK20-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 10339 // CHECK20-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10340 // CHECK20: omp.inner.for.body: 10341 // CHECK20-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 10342 // CHECK20-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 10343 // CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10344 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 10345 // CHECK20-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 10346 // CHECK20-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 10347 // CHECK20-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 10348 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10349 // CHECK20: omp.body.continue: 10350 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10351 // CHECK20: omp.inner.for.inc: 10352 // CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10353 // CHECK20-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 10354 // CHECK20-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 10355 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 10356 // CHECK20: omp.inner.for.end: 10357 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10358 // CHECK20: omp.loop.exit: 10359 // CHECK20-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10360 // CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 10361 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 10362 // CHECK20-NEXT: br label [[OMP_PRECOND_END]] 10363 // CHECK20: omp.precond.end: 10364 // CHECK20-NEXT: ret void 10365 // 10366 // 10367 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 10368 // CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { 10369 // CHECK20-NEXT: entry: 10370 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10371 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10372 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10373 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) 10374 // CHECK20-NEXT: ret void 10375 // 10376 // 10377 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 10378 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 10379 // CHECK20-NEXT: entry: 10380 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10381 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10382 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 10383 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10384 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 10385 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10386 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10387 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10388 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10389 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 10390 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10391 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10392 // CHECK20-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 10393 // CHECK20-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 10394 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10395 // CHECK20-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 10396 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10397 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10398 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 10399 // CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 10400 // CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10401 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 10402 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 10403 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 10404 // CHECK20: omp.dispatch.cond: 10405 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10406 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 10407 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10408 // CHECK20: cond.true: 10409 // CHECK20-NEXT: br label [[COND_END:%.*]] 10410 // CHECK20: cond.false: 10411 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10412 // CHECK20-NEXT: br label [[COND_END]] 10413 // CHECK20: cond.end: 10414 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 10415 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10416 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10417 // CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 10418 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10419 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10420 // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 10421 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 10422 // CHECK20: omp.dispatch.body: 10423 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10424 // CHECK20: omp.inner.for.cond: 10425 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 10426 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 10427 // CHECK20-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 10428 // CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10429 // CHECK20: omp.inner.for.body: 10430 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 10431 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 10432 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 10433 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 10434 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10435 // CHECK20: omp.body.continue: 10436 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10437 // CHECK20: omp.inner.for.inc: 10438 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 10439 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 10440 // CHECK20-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 10441 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 10442 // CHECK20: omp.inner.for.end: 10443 // CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 10444 // CHECK20: omp.dispatch.inc: 10445 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10446 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10447 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 10448 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 10449 // CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10450 // CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10451 // CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 10452 // CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 10453 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] 10454 // CHECK20: omp.dispatch.end: 10455 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 10456 // CHECK20-NEXT: ret void 10457 // 10458 // 10459 // CHECK21-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 10460 // CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 10461 // CHECK21-NEXT: entry: 10462 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 10463 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 10464 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 10465 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 10466 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 10467 // CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 10468 // CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 10469 // CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 10470 // CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 10471 // CHECK21-NEXT: store i32 33, i32* [[I]], align 4 10472 // CHECK21-NEXT: br label [[FOR_COND:%.*]] 10473 // CHECK21: for.cond: 10474 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 10475 // CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 10476 // CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 10477 // CHECK21: for.body: 10478 // CHECK21-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 10479 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 10480 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 10481 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 10482 // CHECK21-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 10483 // CHECK21-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 10484 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 10485 // CHECK21-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 10486 // CHECK21-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 10487 // CHECK21-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 10488 // CHECK21-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 10489 // CHECK21-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 10490 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 10491 // CHECK21-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 10492 // CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 10493 // CHECK21-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 10494 // CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 10495 // CHECK21-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 10496 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 10497 // CHECK21-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 10498 // CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 10499 // CHECK21-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 10500 // CHECK21-NEXT: br label [[FOR_INC:%.*]] 10501 // CHECK21: for.inc: 10502 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 10503 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 10504 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4 10505 // CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 10506 // CHECK21: for.end: 10507 // CHECK21-NEXT: ret void 10508 // 10509 // 10510 // CHECK21-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 10511 // CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 10512 // CHECK21-NEXT: entry: 10513 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 10514 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 10515 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 10516 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 10517 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 10518 // CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 10519 // CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 10520 // CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 10521 // CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 10522 // CHECK21-NEXT: store i32 32000000, i32* [[I]], align 4 10523 // CHECK21-NEXT: br label [[FOR_COND:%.*]] 10524 // CHECK21: for.cond: 10525 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 10526 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 10527 // CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 10528 // CHECK21: for.body: 10529 // CHECK21-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 10530 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 10531 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 10532 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 10533 // CHECK21-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 10534 // CHECK21-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 10535 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 10536 // CHECK21-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 10537 // CHECK21-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 10538 // CHECK21-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 10539 // CHECK21-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 10540 // CHECK21-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 10541 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 10542 // CHECK21-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 10543 // CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 10544 // CHECK21-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 10545 // CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 10546 // CHECK21-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 10547 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 10548 // CHECK21-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 10549 // CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 10550 // CHECK21-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 10551 // CHECK21-NEXT: br label [[FOR_INC:%.*]] 10552 // CHECK21: for.inc: 10553 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 10554 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 10555 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4 10556 // CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 10557 // CHECK21: for.end: 10558 // CHECK21-NEXT: ret void 10559 // 10560 // 10561 // CHECK21-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 10562 // CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 10563 // CHECK21-NEXT: entry: 10564 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 10565 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 10566 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 10567 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 10568 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 10569 // CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 10570 // CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 10571 // CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 10572 // CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 10573 // CHECK21-NEXT: store i32 131071, i32* [[I]], align 4 10574 // CHECK21-NEXT: br label [[FOR_COND:%.*]] 10575 // CHECK21: for.cond: 10576 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 10577 // CHECK21-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 10578 // CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 10579 // CHECK21: for.body: 10580 // CHECK21-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 10581 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 10582 // CHECK21-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 10583 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 10584 // CHECK21-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 10585 // CHECK21-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 10586 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 10587 // CHECK21-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 10588 // CHECK21-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 10589 // CHECK21-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 10590 // CHECK21-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 10591 // CHECK21-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 10592 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 10593 // CHECK21-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 10594 // CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 10595 // CHECK21-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 10596 // CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 10597 // CHECK21-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 10598 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 10599 // CHECK21-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 10600 // CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 10601 // CHECK21-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 10602 // CHECK21-NEXT: br label [[FOR_INC:%.*]] 10603 // CHECK21: for.inc: 10604 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 10605 // CHECK21-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 10606 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4 10607 // CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 10608 // CHECK21: for.end: 10609 // CHECK21-NEXT: ret void 10610 // 10611 // 10612 // CHECK21-LABEL: define {{[^@]+}}@_Z12test_precondv 10613 // CHECK21-SAME: () #[[ATTR0]] { 10614 // CHECK21-NEXT: entry: 10615 // CHECK21-NEXT: [[A:%.*]] = alloca i8, align 1 10616 // CHECK21-NEXT: [[I:%.*]] = alloca i8, align 1 10617 // CHECK21-NEXT: store i8 0, i8* [[A]], align 1 10618 // CHECK21-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 10619 // CHECK21-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 10620 // CHECK21-NEXT: br label [[FOR_COND:%.*]] 10621 // CHECK21: for.cond: 10622 // CHECK21-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 10623 // CHECK21-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 10624 // CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 10625 // CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 10626 // CHECK21: for.body: 10627 // CHECK21-NEXT: br label [[FOR_INC:%.*]] 10628 // CHECK21: for.inc: 10629 // CHECK21-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 10630 // CHECK21-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 10631 // CHECK21-NEXT: store i8 [[INC]], i8* [[I]], align 1 10632 // CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 10633 // CHECK21: for.end: 10634 // CHECK21-NEXT: ret void 10635 // 10636 // 10637 // CHECK21-LABEL: define {{[^@]+}}@_Z4fintv 10638 // CHECK21-SAME: () #[[ATTR0]] { 10639 // CHECK21-NEXT: entry: 10640 // CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() 10641 // CHECK21-NEXT: ret i32 [[CALL]] 10642 // 10643 // 10644 // CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 10645 // CHECK21-SAME: () #[[ATTR0]] comdat { 10646 // CHECK21-NEXT: entry: 10647 // CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 10648 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 10649 // CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 10650 // CHECK21-NEXT: store i32 0, i32* [[I]], align 4 10651 // CHECK21-NEXT: br label [[FOR_COND:%.*]] 10652 // CHECK21: for.cond: 10653 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 10654 // CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 10655 // CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 10656 // CHECK21: for.body: 10657 // CHECK21-NEXT: br label [[FOR_INC:%.*]] 10658 // CHECK21: for.inc: 10659 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 10660 // CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 10661 // CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 10662 // CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 10663 // CHECK21: for.end: 10664 // CHECK21-NEXT: ret i32 0 10665 // 10666 // 10667 // CHECK22-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 10668 // CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 10669 // CHECK22-NEXT: entry: 10670 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 10671 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 10672 // CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 10673 // CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 10674 // CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 10675 // CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 10676 // CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 10677 // CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 10678 // CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 10679 // CHECK22-NEXT: store i32 33, i32* [[I]], align 4 10680 // CHECK22-NEXT: br label [[FOR_COND:%.*]] 10681 // CHECK22: for.cond: 10682 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 10683 // CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 10684 // CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 10685 // CHECK22: for.body: 10686 // CHECK22-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 10687 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 10688 // CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 10689 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 10690 // CHECK22-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 10691 // CHECK22-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 10692 // CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 10693 // CHECK22-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 10694 // CHECK22-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 10695 // CHECK22-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 10696 // CHECK22-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 10697 // CHECK22-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 10698 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 10699 // CHECK22-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 10700 // CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 10701 // CHECK22-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 10702 // CHECK22-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 10703 // CHECK22-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 10704 // CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 10705 // CHECK22-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 10706 // CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 10707 // CHECK22-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 10708 // CHECK22-NEXT: br label [[FOR_INC:%.*]] 10709 // CHECK22: for.inc: 10710 // CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 10711 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 10712 // CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4 10713 // CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 10714 // CHECK22: for.end: 10715 // CHECK22-NEXT: ret void 10716 // 10717 // 10718 // CHECK22-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 10719 // CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 10720 // CHECK22-NEXT: entry: 10721 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 10722 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 10723 // CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 10724 // CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 10725 // CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 10726 // CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 10727 // CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 10728 // CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 10729 // CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 10730 // CHECK22-NEXT: store i32 32000000, i32* [[I]], align 4 10731 // CHECK22-NEXT: br label [[FOR_COND:%.*]] 10732 // CHECK22: for.cond: 10733 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 10734 // CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 10735 // CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 10736 // CHECK22: for.body: 10737 // CHECK22-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 10738 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 10739 // CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 10740 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 10741 // CHECK22-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 10742 // CHECK22-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 10743 // CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 10744 // CHECK22-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 10745 // CHECK22-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 10746 // CHECK22-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 10747 // CHECK22-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 10748 // CHECK22-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 10749 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 10750 // CHECK22-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 10751 // CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 10752 // CHECK22-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 10753 // CHECK22-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 10754 // CHECK22-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 10755 // CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 10756 // CHECK22-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 10757 // CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 10758 // CHECK22-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 10759 // CHECK22-NEXT: br label [[FOR_INC:%.*]] 10760 // CHECK22: for.inc: 10761 // CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 10762 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 10763 // CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4 10764 // CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 10765 // CHECK22: for.end: 10766 // CHECK22-NEXT: ret void 10767 // 10768 // 10769 // CHECK22-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 10770 // CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 10771 // CHECK22-NEXT: entry: 10772 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 10773 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 10774 // CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 10775 // CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 10776 // CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 10777 // CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 10778 // CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 10779 // CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 10780 // CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 10781 // CHECK22-NEXT: store i32 131071, i32* [[I]], align 4 10782 // CHECK22-NEXT: br label [[FOR_COND:%.*]] 10783 // CHECK22: for.cond: 10784 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 10785 // CHECK22-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 10786 // CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 10787 // CHECK22: for.body: 10788 // CHECK22-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 10789 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 10790 // CHECK22-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 10791 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 10792 // CHECK22-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 10793 // CHECK22-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 10794 // CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 10795 // CHECK22-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 10796 // CHECK22-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 10797 // CHECK22-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 10798 // CHECK22-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 10799 // CHECK22-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 10800 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 10801 // CHECK22-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 10802 // CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 10803 // CHECK22-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 10804 // CHECK22-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 10805 // CHECK22-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 10806 // CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 10807 // CHECK22-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 10808 // CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 10809 // CHECK22-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 10810 // CHECK22-NEXT: br label [[FOR_INC:%.*]] 10811 // CHECK22: for.inc: 10812 // CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 10813 // CHECK22-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 10814 // CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4 10815 // CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 10816 // CHECK22: for.end: 10817 // CHECK22-NEXT: ret void 10818 // 10819 // 10820 // CHECK22-LABEL: define {{[^@]+}}@_Z12test_precondv 10821 // CHECK22-SAME: () #[[ATTR0]] { 10822 // CHECK22-NEXT: entry: 10823 // CHECK22-NEXT: [[A:%.*]] = alloca i8, align 1 10824 // CHECK22-NEXT: [[I:%.*]] = alloca i8, align 1 10825 // CHECK22-NEXT: store i8 0, i8* [[A]], align 1 10826 // CHECK22-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 10827 // CHECK22-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 10828 // CHECK22-NEXT: br label [[FOR_COND:%.*]] 10829 // CHECK22: for.cond: 10830 // CHECK22-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 10831 // CHECK22-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 10832 // CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 10833 // CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 10834 // CHECK22: for.body: 10835 // CHECK22-NEXT: br label [[FOR_INC:%.*]] 10836 // CHECK22: for.inc: 10837 // CHECK22-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 10838 // CHECK22-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 10839 // CHECK22-NEXT: store i8 [[INC]], i8* [[I]], align 1 10840 // CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 10841 // CHECK22: for.end: 10842 // CHECK22-NEXT: ret void 10843 // 10844 // 10845 // CHECK22-LABEL: define {{[^@]+}}@_Z4fintv 10846 // CHECK22-SAME: () #[[ATTR0]] { 10847 // CHECK22-NEXT: entry: 10848 // CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() 10849 // CHECK22-NEXT: ret i32 [[CALL]] 10850 // 10851 // 10852 // CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 10853 // CHECK22-SAME: () #[[ATTR0]] comdat { 10854 // CHECK22-NEXT: entry: 10855 // CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 10856 // CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 10857 // CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 10858 // CHECK22-NEXT: store i32 0, i32* [[I]], align 4 10859 // CHECK22-NEXT: br label [[FOR_COND:%.*]] 10860 // CHECK22: for.cond: 10861 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 10862 // CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 10863 // CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 10864 // CHECK22: for.body: 10865 // CHECK22-NEXT: br label [[FOR_INC:%.*]] 10866 // CHECK22: for.inc: 10867 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 10868 // CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 10869 // CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 10870 // CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 10871 // CHECK22: for.end: 10872 // CHECK22-NEXT: ret i32 0 10873 // 10874 // 10875 // CHECK23-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 10876 // CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 10877 // CHECK23-NEXT: entry: 10878 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 10879 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 10880 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 10881 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 10882 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 10883 // CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 10884 // CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 10885 // CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 10886 // CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 10887 // CHECK23-NEXT: store i32 33, i32* [[I]], align 4 10888 // CHECK23-NEXT: br label [[FOR_COND:%.*]] 10889 // CHECK23: for.cond: 10890 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 10891 // CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 10892 // CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 10893 // CHECK23: for.body: 10894 // CHECK23-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 10895 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 10896 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 10897 // CHECK23-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 10898 // CHECK23-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 10899 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 10900 // CHECK23-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 10901 // CHECK23-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 10902 // CHECK23-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 10903 // CHECK23-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 10904 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 10905 // CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 10906 // CHECK23-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 10907 // CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 10908 // CHECK23-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 10909 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 10910 // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 10911 // CHECK23-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 10912 // CHECK23-NEXT: br label [[FOR_INC:%.*]] 10913 // CHECK23: for.inc: 10914 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 10915 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 10916 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4 10917 // CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 10918 // CHECK23: for.end: 10919 // CHECK23-NEXT: ret void 10920 // 10921 // 10922 // CHECK23-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 10923 // CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 10924 // CHECK23-NEXT: entry: 10925 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 10926 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 10927 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 10928 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 10929 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 10930 // CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 10931 // CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 10932 // CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 10933 // CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 10934 // CHECK23-NEXT: store i32 32000000, i32* [[I]], align 4 10935 // CHECK23-NEXT: br label [[FOR_COND:%.*]] 10936 // CHECK23: for.cond: 10937 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 10938 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 10939 // CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 10940 // CHECK23: for.body: 10941 // CHECK23-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 10942 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 10943 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 10944 // CHECK23-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 10945 // CHECK23-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 10946 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 10947 // CHECK23-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 10948 // CHECK23-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 10949 // CHECK23-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 10950 // CHECK23-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 10951 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 10952 // CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 10953 // CHECK23-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 10954 // CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 10955 // CHECK23-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 10956 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 10957 // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 10958 // CHECK23-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 10959 // CHECK23-NEXT: br label [[FOR_INC:%.*]] 10960 // CHECK23: for.inc: 10961 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 10962 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 10963 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4 10964 // CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 10965 // CHECK23: for.end: 10966 // CHECK23-NEXT: ret void 10967 // 10968 // 10969 // CHECK23-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 10970 // CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 10971 // CHECK23-NEXT: entry: 10972 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 10973 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 10974 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 10975 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 10976 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 10977 // CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 10978 // CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 10979 // CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 10980 // CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 10981 // CHECK23-NEXT: store i32 131071, i32* [[I]], align 4 10982 // CHECK23-NEXT: br label [[FOR_COND:%.*]] 10983 // CHECK23: for.cond: 10984 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 10985 // CHECK23-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 10986 // CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 10987 // CHECK23: for.body: 10988 // CHECK23-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 10989 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 10990 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 10991 // CHECK23-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 10992 // CHECK23-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 10993 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 10994 // CHECK23-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 10995 // CHECK23-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 10996 // CHECK23-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 10997 // CHECK23-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 10998 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 10999 // CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 11000 // CHECK23-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 11001 // CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 11002 // CHECK23-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 11003 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 11004 // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 11005 // CHECK23-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 11006 // CHECK23-NEXT: br label [[FOR_INC:%.*]] 11007 // CHECK23: for.inc: 11008 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 11009 // CHECK23-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 11010 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4 11011 // CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 11012 // CHECK23: for.end: 11013 // CHECK23-NEXT: ret void 11014 // 11015 // 11016 // CHECK23-LABEL: define {{[^@]+}}@_Z12test_precondv 11017 // CHECK23-SAME: () #[[ATTR0]] { 11018 // CHECK23-NEXT: entry: 11019 // CHECK23-NEXT: [[A:%.*]] = alloca i8, align 1 11020 // CHECK23-NEXT: [[I:%.*]] = alloca i8, align 1 11021 // CHECK23-NEXT: store i8 0, i8* [[A]], align 1 11022 // CHECK23-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 11023 // CHECK23-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 11024 // CHECK23-NEXT: br label [[FOR_COND:%.*]] 11025 // CHECK23: for.cond: 11026 // CHECK23-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 11027 // CHECK23-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 11028 // CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 11029 // CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 11030 // CHECK23: for.body: 11031 // CHECK23-NEXT: br label [[FOR_INC:%.*]] 11032 // CHECK23: for.inc: 11033 // CHECK23-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 11034 // CHECK23-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 11035 // CHECK23-NEXT: store i8 [[INC]], i8* [[I]], align 1 11036 // CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 11037 // CHECK23: for.end: 11038 // CHECK23-NEXT: ret void 11039 // 11040 // 11041 // CHECK23-LABEL: define {{[^@]+}}@_Z4fintv 11042 // CHECK23-SAME: () #[[ATTR0]] { 11043 // CHECK23-NEXT: entry: 11044 // CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() 11045 // CHECK23-NEXT: ret i32 [[CALL]] 11046 // 11047 // 11048 // CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 11049 // CHECK23-SAME: () #[[ATTR0]] comdat { 11050 // CHECK23-NEXT: entry: 11051 // CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 11052 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 11053 // CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 11054 // CHECK23-NEXT: store i32 0, i32* [[I]], align 4 11055 // CHECK23-NEXT: br label [[FOR_COND:%.*]] 11056 // CHECK23: for.cond: 11057 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 11058 // CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 11059 // CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 11060 // CHECK23: for.body: 11061 // CHECK23-NEXT: br label [[FOR_INC:%.*]] 11062 // CHECK23: for.inc: 11063 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 11064 // CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 11065 // CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 11066 // CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 11067 // CHECK23: for.end: 11068 // CHECK23-NEXT: ret i32 0 11069 // 11070 // 11071 // CHECK24-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 11072 // CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 11073 // CHECK24-NEXT: entry: 11074 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 11075 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 11076 // CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 11077 // CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 11078 // CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 11079 // CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 11080 // CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 11081 // CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 11082 // CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 11083 // CHECK24-NEXT: store i32 33, i32* [[I]], align 4 11084 // CHECK24-NEXT: br label [[FOR_COND:%.*]] 11085 // CHECK24: for.cond: 11086 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 11087 // CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 11088 // CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 11089 // CHECK24: for.body: 11090 // CHECK24-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 11091 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 11092 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 11093 // CHECK24-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 11094 // CHECK24-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 11095 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 11096 // CHECK24-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 11097 // CHECK24-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 11098 // CHECK24-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 11099 // CHECK24-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 11100 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 11101 // CHECK24-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 11102 // CHECK24-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 11103 // CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 11104 // CHECK24-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 11105 // CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 11106 // CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 11107 // CHECK24-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 11108 // CHECK24-NEXT: br label [[FOR_INC:%.*]] 11109 // CHECK24: for.inc: 11110 // CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 11111 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 11112 // CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4 11113 // CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 11114 // CHECK24: for.end: 11115 // CHECK24-NEXT: ret void 11116 // 11117 // 11118 // CHECK24-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 11119 // CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 11120 // CHECK24-NEXT: entry: 11121 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 11122 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 11123 // CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 11124 // CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 11125 // CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 11126 // CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 11127 // CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 11128 // CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 11129 // CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 11130 // CHECK24-NEXT: store i32 32000000, i32* [[I]], align 4 11131 // CHECK24-NEXT: br label [[FOR_COND:%.*]] 11132 // CHECK24: for.cond: 11133 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 11134 // CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 11135 // CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 11136 // CHECK24: for.body: 11137 // CHECK24-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 11138 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 11139 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 11140 // CHECK24-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 11141 // CHECK24-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 11142 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 11143 // CHECK24-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 11144 // CHECK24-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 11145 // CHECK24-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 11146 // CHECK24-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 11147 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 11148 // CHECK24-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 11149 // CHECK24-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 11150 // CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 11151 // CHECK24-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 11152 // CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 11153 // CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 11154 // CHECK24-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 11155 // CHECK24-NEXT: br label [[FOR_INC:%.*]] 11156 // CHECK24: for.inc: 11157 // CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 11158 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 11159 // CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4 11160 // CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 11161 // CHECK24: for.end: 11162 // CHECK24-NEXT: ret void 11163 // 11164 // 11165 // CHECK24-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 11166 // CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 11167 // CHECK24-NEXT: entry: 11168 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 11169 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 11170 // CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 11171 // CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 11172 // CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 11173 // CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 11174 // CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 11175 // CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 11176 // CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 11177 // CHECK24-NEXT: store i32 131071, i32* [[I]], align 4 11178 // CHECK24-NEXT: br label [[FOR_COND:%.*]] 11179 // CHECK24: for.cond: 11180 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 11181 // CHECK24-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 11182 // CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 11183 // CHECK24: for.body: 11184 // CHECK24-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 11185 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 11186 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] 11187 // CHECK24-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 11188 // CHECK24-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 11189 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 11190 // CHECK24-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 11191 // CHECK24-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 11192 // CHECK24-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 11193 // CHECK24-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 11194 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 11195 // CHECK24-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 11196 // CHECK24-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 11197 // CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 11198 // CHECK24-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 11199 // CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 11200 // CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 11201 // CHECK24-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 11202 // CHECK24-NEXT: br label [[FOR_INC:%.*]] 11203 // CHECK24: for.inc: 11204 // CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 11205 // CHECK24-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 11206 // CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4 11207 // CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 11208 // CHECK24: for.end: 11209 // CHECK24-NEXT: ret void 11210 // 11211 // 11212 // CHECK24-LABEL: define {{[^@]+}}@_Z12test_precondv 11213 // CHECK24-SAME: () #[[ATTR0]] { 11214 // CHECK24-NEXT: entry: 11215 // CHECK24-NEXT: [[A:%.*]] = alloca i8, align 1 11216 // CHECK24-NEXT: [[I:%.*]] = alloca i8, align 1 11217 // CHECK24-NEXT: store i8 0, i8* [[A]], align 1 11218 // CHECK24-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 11219 // CHECK24-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 11220 // CHECK24-NEXT: br label [[FOR_COND:%.*]] 11221 // CHECK24: for.cond: 11222 // CHECK24-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 11223 // CHECK24-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 11224 // CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 11225 // CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 11226 // CHECK24: for.body: 11227 // CHECK24-NEXT: br label [[FOR_INC:%.*]] 11228 // CHECK24: for.inc: 11229 // CHECK24-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 11230 // CHECK24-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 11231 // CHECK24-NEXT: store i8 [[INC]], i8* [[I]], align 1 11232 // CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 11233 // CHECK24: for.end: 11234 // CHECK24-NEXT: ret void 11235 // 11236 // 11237 // CHECK24-LABEL: define {{[^@]+}}@_Z4fintv 11238 // CHECK24-SAME: () #[[ATTR0]] { 11239 // CHECK24-NEXT: entry: 11240 // CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() 11241 // CHECK24-NEXT: ret i32 [[CALL]] 11242 // 11243 // 11244 // CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 11245 // CHECK24-SAME: () #[[ATTR0]] comdat { 11246 // CHECK24-NEXT: entry: 11247 // CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 11248 // CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 11249 // CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 11250 // CHECK24-NEXT: store i32 0, i32* [[I]], align 4 11251 // CHECK24-NEXT: br label [[FOR_COND:%.*]] 11252 // CHECK24: for.cond: 11253 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 11254 // CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 11255 // CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 11256 // CHECK24: for.body: 11257 // CHECK24-NEXT: br label [[FOR_INC:%.*]] 11258 // CHECK24: for.inc: 11259 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 11260 // CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 11261 // CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 11262 // CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 11263 // CHECK24: for.end: 11264 // CHECK24-NEXT: ret i32 0 11265 // 11266