1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-version=45 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 9 // Test host codegen. 10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 16 17 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 18 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 19 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 20 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 24 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 26 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 27 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 28 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 29 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 30 31 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) 32 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 33 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 35 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 36 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 37 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19 38 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 39 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 40 41 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 42 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 43 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 44 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 45 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 46 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 48 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 49 50 // expected-no-diagnostics 51 #ifndef HEADER 52 #define HEADER 53 54 55 void without_schedule_clause(float *a, float *b, float *c, float *d) { 56 #pragma omp target 57 #pragma omp teams 58 #pragma omp distribute 59 for (int i = 33; i < 32000000; i += 7) { 60 a[i] = b[i] * c[i] * d[i]; 61 } 62 } 63 64 // ... loop body ... 65 66 67 void static_not_chunked(float *a, float *b, float *c, float *d) { 68 #pragma omp target 69 #pragma omp teams 70 #pragma omp distribute dist_schedule(static) 71 for (int i = 32000000; i > 33; i += -7) { 72 a[i] = b[i] * c[i] * d[i]; 73 } 74 } 75 76 // ... loop body ... 77 78 79 void static_chunked(float *a, float *b, float *c, float *d) { 80 #pragma omp target 81 #pragma omp teams 82 #pragma omp distribute dist_schedule(static, 5) 83 for (unsigned i = 131071; i <= 2147483647; i += 127) { 84 a[i] = b[i] * c[i] * d[i]; 85 } 86 } 87 88 // ... loop body ... 89 90 void test_precond() { 91 char a = 0; 92 #pragma omp target 93 #pragma omp teams 94 #pragma omp distribute 95 for(char i = a; i < 10; ++i); 96 } 97 98 // a is passed as a parameter to the outlined functions 99 // ..many loads of %0.. 100 101 // no templates for now, as these require special handling in target regions and/or declare target 102 103 104 template <typename T> 105 T ftemplate() { 106 short aa = 0; 107 108 #pragma omp target 109 #pragma omp teams 110 #pragma omp distribute dist_schedule(static, aa) 111 for (int i = 0; i < 100; i++) { 112 } 113 return T(); 114 } 115 116 int fint(void) { return ftemplate<int>(); } 117 118 #endif 119 // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 120 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 121 // CHECK1-NEXT: entry: 122 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 123 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 124 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 125 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 126 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 127 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 128 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 129 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 130 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 131 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 132 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 133 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 134 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 135 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 136 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 137 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 138 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 139 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 140 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 141 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 142 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 143 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 144 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 145 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 146 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 147 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 148 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 149 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 150 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 151 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 152 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 153 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 154 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 155 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 156 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 157 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 158 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 159 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 160 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 161 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 162 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 163 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 164 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 165 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 166 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 167 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 168 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 169 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 170 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 171 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 172 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 173 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 174 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 175 // CHECK1-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 176 // CHECK1: omp_offload.failed: 177 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2:[0-9]+]] 178 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 179 // CHECK1: omp_offload.cont: 180 // CHECK1-NEXT: ret void 181 // 182 // 183 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 184 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { 185 // CHECK1-NEXT: entry: 186 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 187 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 188 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 189 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 190 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 191 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 192 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 193 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 194 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 195 // CHECK1-NEXT: ret void 196 // 197 // 198 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 199 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 200 // CHECK1-NEXT: entry: 201 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 202 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 203 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 204 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 205 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 206 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 207 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 208 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 209 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 210 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 211 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 212 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 213 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 214 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 215 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 216 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 217 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 218 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 219 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 220 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 221 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 222 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 223 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 224 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 225 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 226 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 227 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 228 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 229 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 230 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 231 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 232 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 233 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 234 // CHECK1: cond.true: 235 // CHECK1-NEXT: br label [[COND_END:%.*]] 236 // CHECK1: cond.false: 237 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 238 // CHECK1-NEXT: br label [[COND_END]] 239 // CHECK1: cond.end: 240 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 241 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 242 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 243 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 244 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 245 // CHECK1: omp.inner.for.cond: 246 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 247 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 248 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 249 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 250 // CHECK1: omp.inner.for.body: 251 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 252 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 253 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 254 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 255 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 256 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 257 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 258 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 259 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 260 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 261 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 262 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 263 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 264 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 265 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 266 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 267 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 268 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 269 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 270 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 271 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 272 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 273 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 274 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 275 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 276 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 277 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 278 // CHECK1: omp.body.continue: 279 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 280 // CHECK1: omp.inner.for.inc: 281 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 282 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 283 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 284 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 285 // CHECK1: omp.inner.for.end: 286 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 287 // CHECK1: omp.loop.exit: 288 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 289 // CHECK1-NEXT: ret void 290 // 291 // 292 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 293 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 294 // CHECK1-NEXT: entry: 295 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 296 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 297 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 298 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 299 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 300 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 301 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 302 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 303 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 304 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 305 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 306 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 307 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 308 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 309 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 310 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 311 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 312 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 313 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 314 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 315 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 316 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 317 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 318 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 319 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 320 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 321 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 322 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 323 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 324 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 325 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 326 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 327 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 328 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 329 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 330 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 331 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 332 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 333 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 334 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 335 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 336 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 337 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 338 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 339 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 340 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 341 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 342 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 343 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 344 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 345 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 346 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 347 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 348 // CHECK1-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 349 // CHECK1: omp_offload.failed: 350 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 351 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 352 // CHECK1: omp_offload.cont: 353 // CHECK1-NEXT: ret void 354 // 355 // 356 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 357 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 358 // CHECK1-NEXT: entry: 359 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 360 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 361 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 362 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 363 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 364 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 365 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 366 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 367 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 368 // CHECK1-NEXT: ret void 369 // 370 // 371 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 372 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 373 // CHECK1-NEXT: entry: 374 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 375 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 376 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 377 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 378 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 379 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 380 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 381 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 382 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 383 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 384 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 385 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 386 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 387 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 388 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 389 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 390 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 391 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 392 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 393 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 394 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 395 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 396 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 397 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 398 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 399 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 400 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 401 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 402 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 403 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 404 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 405 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 406 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 407 // CHECK1: cond.true: 408 // CHECK1-NEXT: br label [[COND_END:%.*]] 409 // CHECK1: cond.false: 410 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 411 // CHECK1-NEXT: br label [[COND_END]] 412 // CHECK1: cond.end: 413 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 414 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 415 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 416 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 417 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 418 // CHECK1: omp.inner.for.cond: 419 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 420 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 421 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 422 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 423 // CHECK1: omp.inner.for.body: 424 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 425 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 426 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 427 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4 428 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 429 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 430 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 431 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 432 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 433 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 434 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 435 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 436 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 437 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 438 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 439 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 440 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 441 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 442 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 443 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 444 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 445 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 446 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 447 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 448 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 449 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 450 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 451 // CHECK1: omp.body.continue: 452 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 453 // CHECK1: omp.inner.for.inc: 454 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 455 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 456 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 457 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 458 // CHECK1: omp.inner.for.end: 459 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 460 // CHECK1: omp.loop.exit: 461 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 462 // CHECK1-NEXT: ret void 463 // 464 // 465 // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 466 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 467 // CHECK1-NEXT: entry: 468 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 469 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 470 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 471 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 472 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 473 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 474 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 475 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 476 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 477 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 478 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 479 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 480 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 481 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 482 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 483 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 484 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 485 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 486 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 487 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 488 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 489 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 490 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 491 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 492 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 493 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 494 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 495 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 496 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 497 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 498 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 499 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 500 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 501 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 502 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 503 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 504 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 505 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 506 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 507 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 508 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 509 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 510 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 511 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 512 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 513 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 514 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 515 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 516 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 517 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 518 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 519 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 520 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 521 // CHECK1-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 522 // CHECK1: omp_offload.failed: 523 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 524 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 525 // CHECK1: omp_offload.cont: 526 // CHECK1-NEXT: ret void 527 // 528 // 529 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 530 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 531 // CHECK1-NEXT: entry: 532 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 533 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 534 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 535 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 536 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 537 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 538 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 539 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 540 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 541 // CHECK1-NEXT: ret void 542 // 543 // 544 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 545 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 546 // CHECK1-NEXT: entry: 547 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 548 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 549 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 550 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 551 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 552 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 553 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 554 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 555 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 556 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 557 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 558 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 559 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 560 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 561 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 562 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 563 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 564 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 565 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 566 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 567 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 568 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 569 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 570 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 571 // CHECK1-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 572 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 573 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 574 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 575 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 576 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 577 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 578 // CHECK1: omp.dispatch.cond: 579 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 580 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 581 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 582 // CHECK1: cond.true: 583 // CHECK1-NEXT: br label [[COND_END:%.*]] 584 // CHECK1: cond.false: 585 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 586 // CHECK1-NEXT: br label [[COND_END]] 587 // CHECK1: cond.end: 588 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 589 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 590 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 591 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 592 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 593 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 594 // CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 595 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 596 // CHECK1: omp.dispatch.body: 597 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 598 // CHECK1: omp.inner.for.cond: 599 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 600 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 601 // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 602 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 603 // CHECK1: omp.inner.for.body: 604 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 605 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 606 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 607 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 608 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !10 609 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 610 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 611 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 612 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 613 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !10 614 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 615 // CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 616 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 617 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !10 618 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 619 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !10 620 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 621 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 622 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 623 // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !10 624 // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 625 // CHECK1-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !10 626 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 627 // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 628 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 629 // CHECK1-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !10 630 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 631 // CHECK1: omp.body.continue: 632 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 633 // CHECK1: omp.inner.for.inc: 634 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 635 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 636 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 637 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 638 // CHECK1: omp.inner.for.end: 639 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 640 // CHECK1: omp.dispatch.inc: 641 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 642 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 643 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 644 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 645 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 646 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 647 // CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 648 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 649 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 650 // CHECK1: omp.dispatch.end: 651 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 652 // CHECK1-NEXT: ret void 653 // 654 // 655 // CHECK1-LABEL: define {{[^@]+}}@_Z12test_precondv 656 // CHECK1-SAME: () #[[ATTR0]] { 657 // CHECK1-NEXT: entry: 658 // CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1 659 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 660 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 661 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 662 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 663 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 664 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 665 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 666 // CHECK1-NEXT: store i8 0, i8* [[A]], align 1 667 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 668 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8* 669 // CHECK1-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 670 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 671 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 672 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 673 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 674 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 675 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 676 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 677 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 678 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 679 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 680 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 681 // CHECK1-NEXT: [[TMP9:%.*]] = load i8, i8* [[A]], align 1 682 // CHECK1-NEXT: store i8 [[TMP9]], i8* [[DOTCAPTURE_EXPR_]], align 1 683 // CHECK1-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 684 // CHECK1-NEXT: [[CONV2:%.*]] = sext i8 [[TMP10]] to i32 685 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV2]] 686 // CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 687 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 688 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 689 // CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 690 // CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 691 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 692 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 693 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[ADD5]] to i64 694 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP12]]) 695 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 696 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 697 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 698 // CHECK1: omp_offload.failed: 699 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i64 [[TMP1]]) #[[ATTR2]] 700 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 701 // CHECK1: omp_offload.cont: 702 // CHECK1-NEXT: ret void 703 // 704 // 705 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 706 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { 707 // CHECK1-NEXT: entry: 708 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 709 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 710 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* 711 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]]) 712 // CHECK1-NEXT: ret void 713 // 714 // 715 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 716 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 717 // CHECK1-NEXT: entry: 718 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 719 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 720 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 721 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 722 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 723 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 724 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 725 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 726 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 727 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 728 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 729 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 730 // CHECK1-NEXT: [[I5:%.*]] = alloca i8, align 1 731 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 732 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 733 // CHECK1-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 734 // CHECK1-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 735 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 736 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 737 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 738 // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 739 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 740 // CHECK1-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 741 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 742 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 743 // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 744 // CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 745 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 746 // CHECK1-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 747 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 748 // CHECK1-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 749 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 750 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 751 // CHECK1: omp.precond.then: 752 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 753 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 754 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 755 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 756 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 757 // CHECK1-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 758 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 759 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 760 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 761 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 762 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 763 // CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 764 // CHECK1: cond.true: 765 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 766 // CHECK1-NEXT: br label [[COND_END:%.*]] 767 // CHECK1: cond.false: 768 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 769 // CHECK1-NEXT: br label [[COND_END]] 770 // CHECK1: cond.end: 771 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 772 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 773 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 774 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 775 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 776 // CHECK1: omp.inner.for.cond: 777 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 778 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 779 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 780 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 781 // CHECK1: omp.inner.for.body: 782 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 783 // CHECK1-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 784 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 785 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 786 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 787 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 788 // CHECK1-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 789 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 790 // CHECK1: omp.body.continue: 791 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 792 // CHECK1: omp.inner.for.inc: 793 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 794 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 795 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 796 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 797 // CHECK1: omp.inner.for.end: 798 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 799 // CHECK1: omp.loop.exit: 800 // CHECK1-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 801 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 802 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 803 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 804 // CHECK1: omp.precond.end: 805 // CHECK1-NEXT: ret void 806 // 807 // 808 // CHECK1-LABEL: define {{[^@]+}}@_Z4fintv 809 // CHECK1-SAME: () #[[ATTR0]] { 810 // CHECK1-NEXT: entry: 811 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() 812 // CHECK1-NEXT: ret i32 [[CALL]] 813 // 814 // 815 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 816 // CHECK1-SAME: () #[[ATTR0]] comdat { 817 // CHECK1-NEXT: entry: 818 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 819 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 820 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 821 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 822 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 823 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 824 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 825 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 826 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 827 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 828 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 829 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 830 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 831 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 832 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 833 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 834 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 835 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 836 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 837 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 838 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 839 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 840 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 841 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 842 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 843 // CHECK1: omp_offload.failed: 844 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i64 [[TMP1]]) #[[ATTR2]] 845 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 846 // CHECK1: omp_offload.cont: 847 // CHECK1-NEXT: ret i32 0 848 // 849 // 850 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 851 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { 852 // CHECK1-NEXT: entry: 853 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 854 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 855 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 856 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 857 // CHECK1-NEXT: ret void 858 // 859 // 860 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 861 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 862 // CHECK1-NEXT: entry: 863 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 864 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 865 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 866 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 867 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 868 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 869 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 870 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 871 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 872 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 873 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 874 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 875 // CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 876 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 877 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 878 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 879 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 880 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 881 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 882 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 883 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 884 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 885 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 886 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 887 // CHECK1: omp.dispatch.cond: 888 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 889 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 890 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 891 // CHECK1: cond.true: 892 // CHECK1-NEXT: br label [[COND_END:%.*]] 893 // CHECK1: cond.false: 894 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 895 // CHECK1-NEXT: br label [[COND_END]] 896 // CHECK1: cond.end: 897 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 898 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 899 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 900 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 901 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 902 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 903 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 904 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 905 // CHECK1: omp.dispatch.body: 906 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 907 // CHECK1: omp.inner.for.cond: 908 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 909 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 910 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 911 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 912 // CHECK1: omp.inner.for.body: 913 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 914 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 915 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 916 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 917 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 918 // CHECK1: omp.body.continue: 919 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 920 // CHECK1: omp.inner.for.inc: 921 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 922 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 923 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 924 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 925 // CHECK1: omp.inner.for.end: 926 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 927 // CHECK1: omp.dispatch.inc: 928 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 929 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 930 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 931 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 932 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 933 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 934 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 935 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 936 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 937 // CHECK1: omp.dispatch.end: 938 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 939 // CHECK1-NEXT: ret void 940 // 941 // 942 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 943 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 944 // CHECK1-NEXT: entry: 945 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 946 // CHECK1-NEXT: ret void 947 // 948 // 949 // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 950 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 951 // CHECK3-NEXT: entry: 952 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 953 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 954 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 955 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 956 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 957 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 958 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 959 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 960 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 961 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 962 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 963 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 964 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 965 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 966 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 967 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 968 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 969 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 970 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 971 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 972 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 973 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 974 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 975 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 976 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 977 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 978 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 979 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 980 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 981 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 982 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 983 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 984 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 985 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 986 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 987 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 988 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 989 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 990 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 991 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 992 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 993 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 994 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 995 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 996 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 997 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 998 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 999 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1000 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1001 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1002 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 1003 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1004 // CHECK3-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 1005 // CHECK3-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1006 // CHECK3: omp_offload.failed: 1007 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2:[0-9]+]] 1008 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1009 // CHECK3: omp_offload.cont: 1010 // CHECK3-NEXT: ret void 1011 // 1012 // 1013 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 1014 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { 1015 // CHECK3-NEXT: entry: 1016 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1017 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1018 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1019 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1020 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1021 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1022 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1023 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1024 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1025 // CHECK3-NEXT: ret void 1026 // 1027 // 1028 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1029 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 1030 // CHECK3-NEXT: entry: 1031 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1032 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1033 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 1034 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 1035 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 1036 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 1037 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1038 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1039 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1040 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1041 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1042 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1043 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1044 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1045 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1046 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 1047 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 1048 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 1049 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 1050 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 1051 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 1052 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 1053 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 1054 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1055 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1056 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1057 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1058 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1059 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1060 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1061 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1062 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1063 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1064 // CHECK3: cond.true: 1065 // CHECK3-NEXT: br label [[COND_END:%.*]] 1066 // CHECK3: cond.false: 1067 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1068 // CHECK3-NEXT: br label [[COND_END]] 1069 // CHECK3: cond.end: 1070 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1071 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1072 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1073 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1074 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1075 // CHECK3: omp.inner.for.cond: 1076 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1077 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1078 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1079 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1080 // CHECK3: omp.inner.for.body: 1081 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1082 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1083 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 1084 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1085 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 1086 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1087 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 1088 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1089 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 1090 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1091 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 1092 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 1093 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 1094 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 1095 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1096 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 1097 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 1098 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 1099 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 1100 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1101 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 1102 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 1103 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1104 // CHECK3: omp.body.continue: 1105 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1106 // CHECK3: omp.inner.for.inc: 1107 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1108 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 1109 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 1110 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1111 // CHECK3: omp.inner.for.end: 1112 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1113 // CHECK3: omp.loop.exit: 1114 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1115 // CHECK3-NEXT: ret void 1116 // 1117 // 1118 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1119 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1120 // CHECK3-NEXT: entry: 1121 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1122 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1123 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1124 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1125 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1126 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1127 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1128 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1129 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1130 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1131 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1132 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1133 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 1134 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 1135 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 1136 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 1137 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1138 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 1139 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 1140 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1141 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 1142 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 1143 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1144 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1145 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1146 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 1147 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 1148 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1149 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 1150 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 1151 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1152 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1153 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1154 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 1155 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 1156 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1157 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1158 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 1159 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1160 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1161 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1162 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 1163 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 1164 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1165 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 1166 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 1167 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1168 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1169 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1170 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1171 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 1172 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1173 // CHECK3-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 1174 // CHECK3-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1175 // CHECK3: omp_offload.failed: 1176 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 1177 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1178 // CHECK3: omp_offload.cont: 1179 // CHECK3-NEXT: ret void 1180 // 1181 // 1182 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 1183 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 1184 // CHECK3-NEXT: entry: 1185 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1186 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1187 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1188 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1189 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1190 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1191 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1192 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1193 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1194 // CHECK3-NEXT: ret void 1195 // 1196 // 1197 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 1198 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 1199 // CHECK3-NEXT: entry: 1200 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1201 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1202 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 1203 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 1204 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 1205 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 1206 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1207 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1208 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1209 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1210 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1211 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1212 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1213 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1214 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1215 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 1216 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 1217 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 1218 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 1219 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 1220 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 1221 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 1222 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 1223 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1224 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1225 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1226 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1227 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1228 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1229 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1230 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1231 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1232 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1233 // CHECK3: cond.true: 1234 // CHECK3-NEXT: br label [[COND_END:%.*]] 1235 // CHECK3: cond.false: 1236 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1237 // CHECK3-NEXT: br label [[COND_END]] 1238 // CHECK3: cond.end: 1239 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1240 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1241 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1242 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1243 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1244 // CHECK3: omp.inner.for.cond: 1245 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1246 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1247 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1248 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1249 // CHECK3: omp.inner.for.body: 1250 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1251 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1252 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1253 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4 1254 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 1255 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1256 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 1257 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1258 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 1259 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1260 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 1261 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 1262 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 1263 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 1264 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1265 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 1266 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 1267 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 1268 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 1269 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1270 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 1271 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 1272 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1273 // CHECK3: omp.body.continue: 1274 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1275 // CHECK3: omp.inner.for.inc: 1276 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1277 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 1278 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1279 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1280 // CHECK3: omp.inner.for.end: 1281 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1282 // CHECK3: omp.loop.exit: 1283 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1284 // CHECK3-NEXT: ret void 1285 // 1286 // 1287 // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 1288 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1289 // CHECK3-NEXT: entry: 1290 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1291 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1292 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1293 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1294 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1295 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1296 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1297 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1298 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1299 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1300 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1301 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1302 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 1303 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 1304 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 1305 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 1306 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1307 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 1308 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 1309 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1310 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 1311 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 1312 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1313 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1314 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1315 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 1316 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 1317 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1318 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 1319 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 1320 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1321 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1322 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1323 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 1324 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 1325 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1326 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1327 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 1328 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1329 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1330 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1331 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 1332 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 1333 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1334 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 1335 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 1336 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1337 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1338 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1339 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1340 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 1341 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1342 // CHECK3-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 1343 // CHECK3-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1344 // CHECK3: omp_offload.failed: 1345 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR2]] 1346 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1347 // CHECK3: omp_offload.cont: 1348 // CHECK3-NEXT: ret void 1349 // 1350 // 1351 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 1352 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 1353 // CHECK3-NEXT: entry: 1354 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1355 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1356 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1357 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1358 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1359 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1360 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1361 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1362 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1363 // CHECK3-NEXT: ret void 1364 // 1365 // 1366 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 1367 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 1368 // CHECK3-NEXT: entry: 1369 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1370 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1371 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 1372 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 1373 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 1374 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 1375 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1376 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1377 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1378 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1379 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1380 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1381 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1382 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1383 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1384 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 1385 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 1386 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 1387 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 1388 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 1389 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 1390 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 1391 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 1392 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1393 // CHECK3-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 1394 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1395 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1396 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1397 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1398 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 1399 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1400 // CHECK3: omp.dispatch.cond: 1401 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1402 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 1403 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1404 // CHECK3: cond.true: 1405 // CHECK3-NEXT: br label [[COND_END:%.*]] 1406 // CHECK3: cond.false: 1407 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1408 // CHECK3-NEXT: br label [[COND_END]] 1409 // CHECK3: cond.end: 1410 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1411 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1412 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1413 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1414 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1415 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1416 // CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 1417 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1418 // CHECK3: omp.dispatch.body: 1419 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1420 // CHECK3: omp.inner.for.cond: 1421 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1422 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 1423 // CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 1424 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1425 // CHECK3: omp.inner.for.body: 1426 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1427 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 1428 // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 1429 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 1430 // CHECK3-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !11 1431 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1432 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 1433 // CHECK3-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 1434 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !11 1435 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1436 // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 1437 // CHECK3-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !11 1438 // CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 1439 // CHECK3-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !11 1440 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1441 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 1442 // CHECK3-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !11 1443 // CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 1444 // CHECK3-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !11 1445 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1446 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 1447 // CHECK3-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !11 1448 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1449 // CHECK3: omp.body.continue: 1450 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1451 // CHECK3: omp.inner.for.inc: 1452 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1453 // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 1454 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1455 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 1456 // CHECK3: omp.inner.for.end: 1457 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1458 // CHECK3: omp.dispatch.inc: 1459 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1460 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1461 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 1462 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 1463 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1464 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1465 // CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 1466 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 1467 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1468 // CHECK3: omp.dispatch.end: 1469 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1470 // CHECK3-NEXT: ret void 1471 // 1472 // 1473 // CHECK3-LABEL: define {{[^@]+}}@_Z12test_precondv 1474 // CHECK3-SAME: () #[[ATTR0]] { 1475 // CHECK3-NEXT: entry: 1476 // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 1477 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1478 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1479 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1480 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1481 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 1482 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1483 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1484 // CHECK3-NEXT: store i8 0, i8* [[A]], align 1 1485 // CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 1486 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[A_CASTED]] to i8* 1487 // CHECK3-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 1488 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 1489 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1490 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 1491 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 1492 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1493 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 1494 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 1495 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1496 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4 1497 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1498 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1499 // CHECK3-NEXT: [[TMP9:%.*]] = load i8, i8* [[A]], align 1 1500 // CHECK3-NEXT: store i8 [[TMP9]], i8* [[DOTCAPTURE_EXPR_]], align 1 1501 // CHECK3-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1502 // CHECK3-NEXT: [[CONV2:%.*]] = sext i8 [[TMP10]] to i32 1503 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV2]] 1504 // CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 1505 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 1506 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1507 // CHECK3-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 1508 // CHECK3-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1509 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1510 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 1511 // CHECK3-NEXT: [[TMP12:%.*]] = zext i32 [[ADD5]] to i64 1512 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP12]]) 1513 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1514 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1515 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1516 // CHECK3: omp_offload.failed: 1517 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i32 [[TMP1]]) #[[ATTR2]] 1518 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1519 // CHECK3: omp_offload.cont: 1520 // CHECK3-NEXT: ret void 1521 // 1522 // 1523 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 1524 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { 1525 // CHECK3-NEXT: entry: 1526 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1527 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1528 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* 1529 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]]) 1530 // CHECK3-NEXT: ret void 1531 // 1532 // 1533 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 1534 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 1535 // CHECK3-NEXT: entry: 1536 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1537 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1538 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 1539 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1540 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 1541 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1542 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1543 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 1544 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1545 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1546 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1547 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1548 // CHECK3-NEXT: [[I5:%.*]] = alloca i8, align 1 1549 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1550 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1551 // CHECK3-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 1552 // CHECK3-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 1553 // CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 1554 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 1555 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1556 // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 1557 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 1558 // CHECK3-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 1559 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 1560 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1561 // CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 1562 // CHECK3-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1563 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1564 // CHECK3-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 1565 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1566 // CHECK3-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 1567 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 1568 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1569 // CHECK3: omp.precond.then: 1570 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1571 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1572 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 1573 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1574 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1575 // CHECK3-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1576 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 1577 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1578 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1579 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1580 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 1581 // CHECK3-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1582 // CHECK3: cond.true: 1583 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1584 // CHECK3-NEXT: br label [[COND_END:%.*]] 1585 // CHECK3: cond.false: 1586 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1587 // CHECK3-NEXT: br label [[COND_END]] 1588 // CHECK3: cond.end: 1589 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 1590 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1591 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1592 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 1593 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1594 // CHECK3: omp.inner.for.cond: 1595 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1596 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1597 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 1598 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1599 // CHECK3: omp.inner.for.body: 1600 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1601 // CHECK3-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 1602 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1603 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 1604 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 1605 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 1606 // CHECK3-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 1607 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1608 // CHECK3: omp.body.continue: 1609 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1610 // CHECK3: omp.inner.for.inc: 1611 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1612 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 1613 // CHECK3-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 1614 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1615 // CHECK3: omp.inner.for.end: 1616 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1617 // CHECK3: omp.loop.exit: 1618 // CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1619 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 1620 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 1621 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 1622 // CHECK3: omp.precond.end: 1623 // CHECK3-NEXT: ret void 1624 // 1625 // 1626 // CHECK3-LABEL: define {{[^@]+}}@_Z4fintv 1627 // CHECK3-SAME: () #[[ATTR0]] { 1628 // CHECK3-NEXT: entry: 1629 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() 1630 // CHECK3-NEXT: ret i32 [[CALL]] 1631 // 1632 // 1633 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 1634 // CHECK3-SAME: () #[[ATTR0]] comdat { 1635 // CHECK3-NEXT: entry: 1636 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1637 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1638 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1639 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1640 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1641 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1642 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 1643 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 1644 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 1645 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 1646 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 1647 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1648 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 1649 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 1650 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1651 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 1652 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 1653 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1654 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4 1655 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1656 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1657 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 1658 // CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1659 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 1660 // CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1661 // CHECK3: omp_offload.failed: 1662 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i32 [[TMP1]]) #[[ATTR2]] 1663 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1664 // CHECK3: omp_offload.cont: 1665 // CHECK3-NEXT: ret i32 0 1666 // 1667 // 1668 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 1669 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { 1670 // CHECK3-NEXT: entry: 1671 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1672 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1673 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1674 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 1675 // CHECK3-NEXT: ret void 1676 // 1677 // 1678 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 1679 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 1680 // CHECK3-NEXT: entry: 1681 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1682 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1683 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 1684 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1685 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1686 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1687 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1688 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1689 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1690 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1691 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1692 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1693 // CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 1694 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 1695 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1696 // CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 1697 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1698 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1699 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 1700 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 1701 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1702 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1703 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 1704 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1705 // CHECK3: omp.dispatch.cond: 1706 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1707 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1708 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1709 // CHECK3: cond.true: 1710 // CHECK3-NEXT: br label [[COND_END:%.*]] 1711 // CHECK3: cond.false: 1712 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1713 // CHECK3-NEXT: br label [[COND_END]] 1714 // CHECK3: cond.end: 1715 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1716 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1717 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1718 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 1719 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1720 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1721 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1722 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1723 // CHECK3: omp.dispatch.body: 1724 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1725 // CHECK3: omp.inner.for.cond: 1726 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1727 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 1728 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1729 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1730 // CHECK3: omp.inner.for.body: 1731 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1732 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1733 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1734 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 1735 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1736 // CHECK3: omp.body.continue: 1737 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1738 // CHECK3: omp.inner.for.inc: 1739 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1740 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 1741 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1742 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 1743 // CHECK3: omp.inner.for.end: 1744 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1745 // CHECK3: omp.dispatch.inc: 1746 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1747 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1748 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 1749 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 1750 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1751 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1752 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 1753 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 1754 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1755 // CHECK3: omp.dispatch.end: 1756 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 1757 // CHECK3-NEXT: ret void 1758 // 1759 // 1760 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1761 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1762 // CHECK3-NEXT: entry: 1763 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1764 // CHECK3-NEXT: ret void 1765 // 1766 // 1767 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 1768 // CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 1769 // CHECK17-NEXT: entry: 1770 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1771 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1772 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1773 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1774 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1775 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1776 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1777 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1778 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1779 // CHECK17-NEXT: ret void 1780 // 1781 // 1782 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 1783 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 1784 // CHECK17-NEXT: entry: 1785 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1786 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1787 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1788 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1789 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1790 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1791 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1792 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 1793 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1794 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1795 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1796 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1797 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 1798 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1799 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1800 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1801 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1802 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1803 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1804 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1805 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1806 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1807 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1808 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1809 // CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1810 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1811 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1812 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1813 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1814 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1815 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1816 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1817 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1818 // CHECK17: cond.true: 1819 // CHECK17-NEXT: br label [[COND_END:%.*]] 1820 // CHECK17: cond.false: 1821 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1822 // CHECK17-NEXT: br label [[COND_END]] 1823 // CHECK17: cond.end: 1824 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1825 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1826 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1827 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1828 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1829 // CHECK17: omp.inner.for.cond: 1830 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1831 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1832 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1833 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1834 // CHECK17: omp.inner.for.body: 1835 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1836 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1837 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 1838 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1839 // CHECK17-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 1840 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1841 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 1842 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 1843 // CHECK17-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1844 // CHECK17-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 1845 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1846 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 1847 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 1848 // CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 1849 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 1850 // CHECK17-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 1851 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1852 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 1853 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 1854 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 1855 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 1856 // CHECK17-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 1857 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1858 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 1859 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 1860 // CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 1861 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1862 // CHECK17: omp.body.continue: 1863 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1864 // CHECK17: omp.inner.for.inc: 1865 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1866 // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 1867 // CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 1868 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 1869 // CHECK17: omp.inner.for.end: 1870 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1871 // CHECK17: omp.loop.exit: 1872 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1873 // CHECK17-NEXT: ret void 1874 // 1875 // 1876 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 1877 // CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1878 // CHECK17-NEXT: entry: 1879 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1880 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1881 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1882 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1883 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1884 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1885 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1886 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1887 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1888 // CHECK17-NEXT: ret void 1889 // 1890 // 1891 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 1892 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 1893 // CHECK17-NEXT: entry: 1894 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1895 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1896 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1897 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1898 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1899 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1900 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1901 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 1902 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1903 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1904 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1905 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1906 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 1907 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1908 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1909 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1910 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1911 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1912 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1913 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1914 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1915 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1916 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1917 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1918 // CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1919 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1920 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1921 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1922 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1923 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1924 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1925 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1926 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1927 // CHECK17: cond.true: 1928 // CHECK17-NEXT: br label [[COND_END:%.*]] 1929 // CHECK17: cond.false: 1930 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1931 // CHECK17-NEXT: br label [[COND_END]] 1932 // CHECK17: cond.end: 1933 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1934 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1935 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1936 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1937 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1938 // CHECK17: omp.inner.for.cond: 1939 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1940 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1941 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1942 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1943 // CHECK17: omp.inner.for.body: 1944 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1945 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1946 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1947 // CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4 1948 // CHECK17-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 1949 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1950 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 1951 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 1952 // CHECK17-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1953 // CHECK17-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 1954 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1955 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 1956 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 1957 // CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 1958 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 1959 // CHECK17-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 1960 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1961 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 1962 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 1963 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 1964 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 1965 // CHECK17-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 1966 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1967 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 1968 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 1969 // CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 1970 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1971 // CHECK17: omp.body.continue: 1972 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1973 // CHECK17: omp.inner.for.inc: 1974 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1975 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 1976 // CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1977 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 1978 // CHECK17: omp.inner.for.end: 1979 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1980 // CHECK17: omp.loop.exit: 1981 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1982 // CHECK17-NEXT: ret void 1983 // 1984 // 1985 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 1986 // CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1987 // CHECK17-NEXT: entry: 1988 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1989 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1990 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1991 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1992 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1993 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1994 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1995 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1996 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1997 // CHECK17-NEXT: ret void 1998 // 1999 // 2000 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 2001 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 2002 // CHECK17-NEXT: entry: 2003 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2004 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2005 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2006 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2007 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2008 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2009 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2010 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 2011 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2012 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2013 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2014 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2015 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 2016 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2017 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2018 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2019 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2020 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2021 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2022 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2023 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 2024 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 2025 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 2026 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2027 // CHECK17-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 2028 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2029 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2030 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2031 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2032 // CHECK17-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 2033 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2034 // CHECK17: omp.dispatch.cond: 2035 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2036 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 2037 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2038 // CHECK17: cond.true: 2039 // CHECK17-NEXT: br label [[COND_END:%.*]] 2040 // CHECK17: cond.false: 2041 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2042 // CHECK17-NEXT: br label [[COND_END]] 2043 // CHECK17: cond.end: 2044 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2045 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2046 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2047 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2048 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2049 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2050 // CHECK17-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 2051 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2052 // CHECK17: omp.dispatch.body: 2053 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2054 // CHECK17: omp.inner.for.cond: 2055 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2056 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 2057 // CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 2058 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2059 // CHECK17: omp.inner.for.body: 2060 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2061 // CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 2062 // CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 2063 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 2064 // CHECK17-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !11 2065 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 2066 // CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 2067 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 2068 // CHECK17-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 2069 // CHECK17-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !11 2070 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 2071 // CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 2072 // CHECK17-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 2073 // CHECK17-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !11 2074 // CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 2075 // CHECK17-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !11 2076 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 2077 // CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 2078 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 2079 // CHECK17-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !11 2080 // CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 2081 // CHECK17-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !11 2082 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 2083 // CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 2084 // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 2085 // CHECK17-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !11 2086 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2087 // CHECK17: omp.body.continue: 2088 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2089 // CHECK17: omp.inner.for.inc: 2090 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2091 // CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 2092 // CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2093 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 2094 // CHECK17: omp.inner.for.end: 2095 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2096 // CHECK17: omp.dispatch.inc: 2097 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2098 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2099 // CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 2100 // CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 2101 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2102 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2103 // CHECK17-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 2104 // CHECK17-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 2105 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 2106 // CHECK17: omp.dispatch.end: 2107 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2108 // CHECK17-NEXT: ret void 2109 // 2110 // 2111 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 2112 // CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0]] { 2113 // CHECK17-NEXT: entry: 2114 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2115 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2116 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* 2117 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) 2118 // CHECK17-NEXT: ret void 2119 // 2120 // 2121 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 2122 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 2123 // CHECK17-NEXT: entry: 2124 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2125 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2126 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 2127 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2128 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 2129 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2130 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2131 // CHECK17-NEXT: [[I:%.*]] = alloca i8, align 1 2132 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2133 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2134 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2135 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2136 // CHECK17-NEXT: [[I5:%.*]] = alloca i8, align 1 2137 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2138 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2139 // CHECK17-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 2140 // CHECK17-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 2141 // CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 2142 // CHECK17-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 2143 // CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2144 // CHECK17-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 2145 // CHECK17-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 2146 // CHECK17-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 2147 // CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 2148 // CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2149 // CHECK17-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 2150 // CHECK17-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2151 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2152 // CHECK17-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 2153 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2154 // CHECK17-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 2155 // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 2156 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2157 // CHECK17: omp.precond.then: 2158 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2159 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2160 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 2161 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2162 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2163 // CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2164 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 2165 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2166 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2167 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2168 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 2169 // CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2170 // CHECK17: cond.true: 2171 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2172 // CHECK17-NEXT: br label [[COND_END:%.*]] 2173 // CHECK17: cond.false: 2174 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2175 // CHECK17-NEXT: br label [[COND_END]] 2176 // CHECK17: cond.end: 2177 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 2178 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2179 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2180 // CHECK17-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 2181 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2182 // CHECK17: omp.inner.for.cond: 2183 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2184 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2185 // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 2186 // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2187 // CHECK17: omp.inner.for.body: 2188 // CHECK17-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2189 // CHECK17-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 2190 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2191 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 2192 // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 2193 // CHECK17-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 2194 // CHECK17-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 2195 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2196 // CHECK17: omp.body.continue: 2197 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2198 // CHECK17: omp.inner.for.inc: 2199 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2200 // CHECK17-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 2201 // CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 2202 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 2203 // CHECK17: omp.inner.for.end: 2204 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2205 // CHECK17: omp.loop.exit: 2206 // CHECK17-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2207 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 2208 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 2209 // CHECK17-NEXT: br label [[OMP_PRECOND_END]] 2210 // CHECK17: omp.precond.end: 2211 // CHECK17-NEXT: ret void 2212 // 2213 // 2214 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 2215 // CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 2216 // CHECK17-NEXT: entry: 2217 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2218 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2219 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2220 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) 2221 // CHECK17-NEXT: ret void 2222 // 2223 // 2224 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 2225 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 2226 // CHECK17-NEXT: entry: 2227 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2228 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2229 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 2230 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2231 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 2232 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2233 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2234 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2235 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2236 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 2237 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2238 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2239 // CHECK17-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 2240 // CHECK17-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 2241 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2242 // CHECK17-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 2243 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2244 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2245 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 2246 // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2247 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2248 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2249 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 2250 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2251 // CHECK17: omp.dispatch.cond: 2252 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2253 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2254 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2255 // CHECK17: cond.true: 2256 // CHECK17-NEXT: br label [[COND_END:%.*]] 2257 // CHECK17: cond.false: 2258 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2259 // CHECK17-NEXT: br label [[COND_END]] 2260 // CHECK17: cond.end: 2261 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2262 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2263 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2264 // CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 2265 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2266 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2267 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2268 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2269 // CHECK17: omp.dispatch.body: 2270 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2271 // CHECK17: omp.inner.for.cond: 2272 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2273 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 2274 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2275 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2276 // CHECK17: omp.inner.for.body: 2277 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2278 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 2279 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2280 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 2281 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2282 // CHECK17: omp.body.continue: 2283 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2284 // CHECK17: omp.inner.for.inc: 2285 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2286 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 2287 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2288 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 2289 // CHECK17: omp.inner.for.end: 2290 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2291 // CHECK17: omp.dispatch.inc: 2292 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2293 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2294 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 2295 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 2296 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2297 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2298 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 2299 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 2300 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 2301 // CHECK17: omp.dispatch.end: 2302 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 2303 // CHECK17-NEXT: ret void 2304 // 2305 // 2306 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 2307 // CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 2308 // CHECK19-NEXT: entry: 2309 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2310 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2311 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2312 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2313 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2314 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2315 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2316 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2317 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2318 // CHECK19-NEXT: ret void 2319 // 2320 // 2321 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 2322 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 2323 // CHECK19-NEXT: entry: 2324 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2325 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2326 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 2327 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 2328 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 2329 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 2330 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2331 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 2332 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2333 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2334 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2335 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2336 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 2337 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2338 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2339 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 2340 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 2341 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 2342 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 2343 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 2344 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 2345 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 2346 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 2347 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2348 // CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2349 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2350 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2351 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2352 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2353 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2354 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2355 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 2356 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2357 // CHECK19: cond.true: 2358 // CHECK19-NEXT: br label [[COND_END:%.*]] 2359 // CHECK19: cond.false: 2360 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2361 // CHECK19-NEXT: br label [[COND_END]] 2362 // CHECK19: cond.end: 2363 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2364 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2365 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2366 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2367 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2368 // CHECK19: omp.inner.for.cond: 2369 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2370 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2371 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2372 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2373 // CHECK19: omp.inner.for.body: 2374 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2375 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 2376 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 2377 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2378 // CHECK19-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 2379 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2380 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 2381 // CHECK19-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2382 // CHECK19-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 2383 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2384 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 2385 // CHECK19-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2386 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 2387 // CHECK19-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 2388 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2389 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 2390 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2391 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 2392 // CHECK19-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 2393 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2394 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 2395 // CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 2396 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2397 // CHECK19: omp.body.continue: 2398 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2399 // CHECK19: omp.inner.for.inc: 2400 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2401 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 2402 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 2403 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 2404 // CHECK19: omp.inner.for.end: 2405 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2406 // CHECK19: omp.loop.exit: 2407 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2408 // CHECK19-NEXT: ret void 2409 // 2410 // 2411 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 2412 // CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2413 // CHECK19-NEXT: entry: 2414 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2415 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2416 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2417 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2418 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2419 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2420 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2421 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2422 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2423 // CHECK19-NEXT: ret void 2424 // 2425 // 2426 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 2427 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 2428 // CHECK19-NEXT: entry: 2429 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2430 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2431 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 2432 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 2433 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 2434 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 2435 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2436 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 2437 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2438 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2439 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2440 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2441 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 2442 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2443 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2444 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 2445 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 2446 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 2447 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 2448 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 2449 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 2450 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 2451 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 2452 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2453 // CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2454 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2455 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2456 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2457 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2458 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2459 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2460 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 2461 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2462 // CHECK19: cond.true: 2463 // CHECK19-NEXT: br label [[COND_END:%.*]] 2464 // CHECK19: cond.false: 2465 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2466 // CHECK19-NEXT: br label [[COND_END]] 2467 // CHECK19: cond.end: 2468 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2469 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2470 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2471 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2472 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2473 // CHECK19: omp.inner.for.cond: 2474 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2475 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2476 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2477 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2478 // CHECK19: omp.inner.for.body: 2479 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2480 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 2481 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 2482 // CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4 2483 // CHECK19-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 2484 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2485 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 2486 // CHECK19-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2487 // CHECK19-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 2488 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2489 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 2490 // CHECK19-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2491 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 2492 // CHECK19-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 2493 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2494 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 2495 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2496 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 2497 // CHECK19-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 2498 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2499 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 2500 // CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 2501 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2502 // CHECK19: omp.body.continue: 2503 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2504 // CHECK19: omp.inner.for.inc: 2505 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2506 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 2507 // CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2508 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 2509 // CHECK19: omp.inner.for.end: 2510 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2511 // CHECK19: omp.loop.exit: 2512 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2513 // CHECK19-NEXT: ret void 2514 // 2515 // 2516 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 2517 // CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2518 // CHECK19-NEXT: entry: 2519 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2520 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2521 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2522 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2523 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2524 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2525 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2526 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2527 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2528 // CHECK19-NEXT: ret void 2529 // 2530 // 2531 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 2532 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 2533 // CHECK19-NEXT: entry: 2534 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2535 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2536 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 2537 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 2538 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 2539 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 2540 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2541 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 2542 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2543 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2544 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2545 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2546 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 2547 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2548 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2549 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 2550 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 2551 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 2552 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 2553 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 2554 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 2555 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 2556 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 2557 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2558 // CHECK19-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 2559 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2560 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2561 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2562 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2563 // CHECK19-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 2564 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2565 // CHECK19: omp.dispatch.cond: 2566 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2567 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 2568 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2569 // CHECK19: cond.true: 2570 // CHECK19-NEXT: br label [[COND_END:%.*]] 2571 // CHECK19: cond.false: 2572 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2573 // CHECK19-NEXT: br label [[COND_END]] 2574 // CHECK19: cond.end: 2575 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2576 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2577 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2578 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2579 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2580 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2581 // CHECK19-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 2582 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2583 // CHECK19: omp.dispatch.body: 2584 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2585 // CHECK19: omp.inner.for.cond: 2586 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2587 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 2588 // CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 2589 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2590 // CHECK19: omp.inner.for.body: 2591 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2592 // CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 2593 // CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 2594 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 2595 // CHECK19-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !12 2596 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2597 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 2598 // CHECK19-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12 2599 // CHECK19-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !12 2600 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2601 // CHECK19-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 2602 // CHECK19-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !12 2603 // CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 2604 // CHECK19-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !12 2605 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2606 // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 2607 // CHECK19-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !12 2608 // CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 2609 // CHECK19-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !12 2610 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2611 // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 2612 // CHECK19-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !12 2613 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2614 // CHECK19: omp.body.continue: 2615 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2616 // CHECK19: omp.inner.for.inc: 2617 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2618 // CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 2619 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2620 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 2621 // CHECK19: omp.inner.for.end: 2622 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2623 // CHECK19: omp.dispatch.inc: 2624 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2625 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2626 // CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 2627 // CHECK19-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 2628 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2629 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2630 // CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 2631 // CHECK19-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 2632 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 2633 // CHECK19: omp.dispatch.end: 2634 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2635 // CHECK19-NEXT: ret void 2636 // 2637 // 2638 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 2639 // CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0]] { 2640 // CHECK19-NEXT: entry: 2641 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2642 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2643 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* 2644 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) 2645 // CHECK19-NEXT: ret void 2646 // 2647 // 2648 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 2649 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 2650 // CHECK19-NEXT: entry: 2651 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2652 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2653 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 2654 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2655 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 2656 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2657 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2658 // CHECK19-NEXT: [[I:%.*]] = alloca i8, align 1 2659 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2660 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2661 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2662 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2663 // CHECK19-NEXT: [[I5:%.*]] = alloca i8, align 1 2664 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2665 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2666 // CHECK19-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 2667 // CHECK19-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 2668 // CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 2669 // CHECK19-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 2670 // CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2671 // CHECK19-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 2672 // CHECK19-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 2673 // CHECK19-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 2674 // CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 2675 // CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2676 // CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 2677 // CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2678 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2679 // CHECK19-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 2680 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2681 // CHECK19-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 2682 // CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 2683 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2684 // CHECK19: omp.precond.then: 2685 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2686 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2687 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 2688 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2689 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2690 // CHECK19-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2691 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 2692 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2693 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2694 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2695 // CHECK19-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] 2696 // CHECK19-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2697 // CHECK19: cond.true: 2698 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2699 // CHECK19-NEXT: br label [[COND_END:%.*]] 2700 // CHECK19: cond.false: 2701 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2702 // CHECK19-NEXT: br label [[COND_END]] 2703 // CHECK19: cond.end: 2704 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 2705 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2706 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2707 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 2708 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2709 // CHECK19: omp.inner.for.cond: 2710 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2711 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2712 // CHECK19-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 2713 // CHECK19-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2714 // CHECK19: omp.inner.for.body: 2715 // CHECK19-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2716 // CHECK19-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 2717 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2718 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 2719 // CHECK19-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] 2720 // CHECK19-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 2721 // CHECK19-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 2722 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2723 // CHECK19: omp.body.continue: 2724 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2725 // CHECK19: omp.inner.for.inc: 2726 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2727 // CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 2728 // CHECK19-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 2729 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 2730 // CHECK19: omp.inner.for.end: 2731 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2732 // CHECK19: omp.loop.exit: 2733 // CHECK19-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2734 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 2735 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 2736 // CHECK19-NEXT: br label [[OMP_PRECOND_END]] 2737 // CHECK19: omp.precond.end: 2738 // CHECK19-NEXT: ret void 2739 // 2740 // 2741 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 2742 // CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 2743 // CHECK19-NEXT: entry: 2744 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2745 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2746 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2747 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) 2748 // CHECK19-NEXT: ret void 2749 // 2750 // 2751 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 2752 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 2753 // CHECK19-NEXT: entry: 2754 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2755 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2756 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 2757 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2758 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 2759 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2760 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2761 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2762 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2763 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 2764 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2765 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2766 // CHECK19-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 2767 // CHECK19-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 2768 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2769 // CHECK19-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 2770 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2771 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2772 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 2773 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2774 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2775 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2776 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 2777 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2778 // CHECK19: omp.dispatch.cond: 2779 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2780 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2781 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2782 // CHECK19: cond.true: 2783 // CHECK19-NEXT: br label [[COND_END:%.*]] 2784 // CHECK19: cond.false: 2785 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2786 // CHECK19-NEXT: br label [[COND_END]] 2787 // CHECK19: cond.end: 2788 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2789 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2790 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2791 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 2792 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2793 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2794 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2795 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2796 // CHECK19: omp.dispatch.body: 2797 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2798 // CHECK19: omp.inner.for.cond: 2799 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 2800 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 2801 // CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2802 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2803 // CHECK19: omp.inner.for.body: 2804 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 2805 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 2806 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2807 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 2808 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2809 // CHECK19: omp.body.continue: 2810 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2811 // CHECK19: omp.inner.for.inc: 2812 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 2813 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 2814 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 2815 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 2816 // CHECK19: omp.inner.for.end: 2817 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2818 // CHECK19: omp.dispatch.inc: 2819 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2820 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2821 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 2822 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 2823 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2824 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2825 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 2826 // CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 2827 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 2828 // CHECK19: omp.dispatch.end: 2829 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 2830 // CHECK19-NEXT: ret void 2831 // 2832