1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1
4 // expected-no-diagnostics
5 
6 int foo(int &a) { return a; }
7 
8 int bar() {
9   int a;
10   return foo(a);
11 }
12 
13 
14 int maini1() {
15   int a;
16 #pragma omp target parallel map(from:a)
17   {
18     int b;
19     a = foo(b) + bar();
20   }
21   return a;
22 }
23 
24 // parallel region
25 
26 
27 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6maini1v_l16
28 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0:[0-9]+]] {
29 // CHECK1-NEXT:  entry:
30 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
31 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
32 // CHECK1-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
33 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
34 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
35 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 1)
36 // CHECK1-NEXT:    call void @__kmpc_data_sharing_init_stack_spmd()
37 // CHECK1-NEXT:    br label [[DOTEXECUTE:%.*]]
38 // CHECK1:       .execute:
39 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
40 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
41 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast i32* [[TMP0]] to i8*
42 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[TMP2]], align 8
43 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
44 // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP4]], i64 1)
45 // CHECK1-NEXT:    br label [[DOTOMP_DEINIT:%.*]]
46 // CHECK1:       .omp.deinit:
47 // CHECK1-NEXT:    call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
48 // CHECK1-NEXT:    br label [[DOTEXIT:%.*]]
49 // CHECK1:       .exit:
50 // CHECK1-NEXT:    ret void
51 //
52 //
53 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
54 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] {
55 // CHECK1-NEXT:  entry:
56 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
57 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
58 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
59 // CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 4
60 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
61 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
62 // CHECK1-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
63 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
64 // CHECK1-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooRi(i32* nonnull align 4 dereferenceable(4) [[B]]) #[[ATTR4:[0-9]+]]
65 // CHECK1-NEXT:    [[CALL1:%.*]] = call i32 @_Z3barv() #[[ATTR4]]
66 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
67 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[TMP0]], align 4
68 // CHECK1-NEXT:    ret void
69 //
70 //
71 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooRi
72 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
73 // CHECK1-NEXT:  entry:
74 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
75 // CHECK1-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
76 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
77 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
78 // CHECK1-NEXT:    ret i32 [[TMP1]]
79 //
80 //
81 // CHECK1-LABEL: define {{[^@]+}}@_Z3barv
82 // CHECK1-SAME: () #[[ATTR2]] {
83 // CHECK1-NEXT:  entry:
84 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
85 // CHECK1-NEXT:    [[A2:%.*]] = alloca i32, align 4
86 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
87 // CHECK1-NEXT:    [[TMP1:%.*]] = call i16 @__kmpc_parallel_level(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
88 // CHECK1-NEXT:    [[TMP2:%.*]] = icmp eq i16 [[TMP1]], 0
89 // CHECK1-NEXT:    [[TMP3:%.*]] = call i8 @__kmpc_is_spmd_exec_mode() #[[ATTR3:[0-9]+]]
90 // CHECK1-NEXT:    [[TMP4:%.*]] = icmp ne i8 [[TMP3]], 0
91 // CHECK1-NEXT:    br i1 [[TMP4]], label [[DOTSPMD:%.*]], label [[DOTNON_SPMD:%.*]]
92 // CHECK1:       .spmd:
93 // CHECK1-NEXT:    br label [[DOTEXIT:%.*]]
94 // CHECK1:       .non-spmd:
95 // CHECK1-NEXT:    [[TMP5:%.*]] = select i1 [[TMP2]], i64 4, i64 128
96 // CHECK1-NEXT:    [[TMP6:%.*]] = call i8* @__kmpc_data_sharing_coalesced_push_stack(i64 [[TMP5]], i16 0)
97 // CHECK1-NEXT:    [[TMP7:%.*]] = bitcast i8* [[TMP6]] to %struct._globalized_locals_ty*
98 // CHECK1-NEXT:    br label [[DOTEXIT]]
99 // CHECK1:       .exit:
100 // CHECK1-NEXT:    [[_SELECT_STACK:%.*]] = phi %struct._globalized_locals_ty* [ null, [[DOTSPMD]] ], [ [[TMP7]], [[DOTNON_SPMD]] ]
101 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast %struct._globalized_locals_ty* [[_SELECT_STACK]] to %struct._globalized_locals_ty.0*
102 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[_SELECT_STACK]], i32 0, i32 0
103 // CHECK1-NEXT:    [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
104 // CHECK1-NEXT:    [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID]], 31
105 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [32 x i32], [32 x i32]* [[A]], i32 0, i32 [[NVPTX_LANE_ID]]
106 // CHECK1-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_0:%.*]], %struct._globalized_locals_ty.0* [[TMP8]], i32 0, i32 0
107 // CHECK1-NEXT:    [[TMP10:%.*]] = select i1 [[TMP2]], i32* [[A1]], i32* [[TMP9]]
108 // CHECK1-NEXT:    [[TMP11:%.*]] = select i1 [[TMP4]], i32* [[A2]], i32* [[TMP10]]
109 // CHECK1-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooRi(i32* nonnull align 4 dereferenceable(4) [[TMP11]]) #[[ATTR4]]
110 // CHECK1-NEXT:    store i32 [[CALL]], i32* [[RETVAL]], align 4
111 // CHECK1-NEXT:    br i1 [[TMP4]], label [[DOTEXIT4:%.*]], label [[DOTNON_SPMD3:%.*]]
112 // CHECK1:       .non-spmd3:
113 // CHECK1-NEXT:    [[TMP12:%.*]] = bitcast %struct._globalized_locals_ty* [[_SELECT_STACK]] to i8*
114 // CHECK1-NEXT:    call void @__kmpc_data_sharing_pop_stack(i8* [[TMP12]])
115 // CHECK1-NEXT:    br label [[DOTEXIT4]]
116 // CHECK1:       .exit4:
117 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4
118 // CHECK1-NEXT:    ret i32 [[TMP13]]
119 //
120