1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1 4 // expected-no-diagnostics 5 6 int foo(int &a) { return a; } 7 8 int bar() { 9 int a; 10 return foo(a); 11 } 12 13 14 int maini1() { 15 int a; 16 #pragma omp target parallel map(from:a) 17 { 18 int b; 19 a = foo(b) + bar(); 20 } 21 return a; 22 } 23 24 // parallel region 25 26 27 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6maini1v_l16 28 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0:[0-9]+]] { 29 // CHECK1-NEXT: entry: 30 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 31 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 32 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 33 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 34 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 true, i1 false, i1 true) 35 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 36 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 37 // CHECK1: user_code.entry: 38 // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 39 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 40 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8* 41 // CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8 42 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 43 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i64 1) 44 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) 45 // CHECK1-NEXT: ret void 46 // CHECK1: worker.exit: 47 // CHECK1-NEXT: ret void 48 // 49 // 50 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ 51 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] { 52 // CHECK1-NEXT: entry: 53 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 54 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 55 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 56 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 57 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 58 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 59 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 60 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 61 // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z3fooRi(i32* nonnull align 4 dereferenceable(4) [[B]]) #[[ATTR3:[0-9]+]] 62 // CHECK1-NEXT: [[CALL1:%.*]] = call i32 @_Z3barv() #[[ATTR3]] 63 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] 64 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 65 // CHECK1-NEXT: ret void 66 // 67 // 68 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooRi 69 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { 70 // CHECK1-NEXT: entry: 71 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 72 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 73 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 74 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 75 // CHECK1-NEXT: ret i32 [[TMP1]] 76 // 77 // 78 // CHECK1-LABEL: define {{[^@]+}}@_Z3barv 79 // CHECK1-SAME: () #[[ATTR1]] { 80 // CHECK1-NEXT: entry: 81 // CHECK1-NEXT: [[A:%.*]] = call i8* @__kmpc_alloc_shared(i64 4) 82 // CHECK1-NEXT: [[A_ON_STACK:%.*]] = bitcast i8* [[A]] to i32* 83 // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z3fooRi(i32* nonnull align 4 dereferenceable(4) [[A_ON_STACK]]) #[[ATTR3]] 84 // CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[A]]) 85 // CHECK1-NEXT: ret i32 [[CALL]] 86 // 87