1*7cb25c9bSArtem Belevich; Simple bit of IR to mimic CUDA's libdevice. We want to be
2*7cb25c9bSArtem Belevich; able to link with it and we need to make sure all __nvvm_reflect
3*7cb25c9bSArtem Belevich; calls are eliminated by the time PTX has been produced.
4*7cb25c9bSArtem Belevich
5*7cb25c9bSArtem Belevichtarget triple = "nvptx-unknown-cuda"
6*7cb25c9bSArtem Belevich
7*7cb25c9bSArtem Belevichdeclare i32 @__nvvm_reflect(i8*)
8*7cb25c9bSArtem Belevich
9*7cb25c9bSArtem Belevich@"$str" = private addrspace(1) constant [8 x i8] c"USE_MUL\00"
10*7cb25c9bSArtem Belevich
11*7cb25c9bSArtem Belevichdefine void @unused_subfunc(float %a) {
12*7cb25c9bSArtem Belevich       ret void
13*7cb25c9bSArtem Belevich}
14*7cb25c9bSArtem Belevich
15*7cb25c9bSArtem Belevichdefine void @used_subfunc(float %a) {
16*7cb25c9bSArtem Belevich       ret void
17*7cb25c9bSArtem Belevich}
18*7cb25c9bSArtem Belevich
19*7cb25c9bSArtem Belevichdefine float @_Z17device_mul_or_addff(float %a, float %b) {
20*7cb25c9bSArtem Belevich  %reflect = call i32 @__nvvm_reflect(i8* addrspacecast (i8 addrspace(1)* getelementptr inbounds ([8 x i8], [8 x i8] addrspace(1)* @"$str", i32 0, i32 0) to i8*))
21*7cb25c9bSArtem Belevich  %cmp = icmp ne i32 %reflect, 0
22*7cb25c9bSArtem Belevich  br i1 %cmp, label %use_mul, label %use_add
23*7cb25c9bSArtem Belevich
24*7cb25c9bSArtem Belevichuse_mul:
25*7cb25c9bSArtem Belevich  %ret1 = fmul float %a, %b
26*7cb25c9bSArtem Belevich  br label %exit
27*7cb25c9bSArtem Belevich
28*7cb25c9bSArtem Belevichuse_add:
29*7cb25c9bSArtem Belevich  %ret2 = fadd float %a, %b
30*7cb25c9bSArtem Belevich  br label %exit
31*7cb25c9bSArtem Belevich
32*7cb25c9bSArtem Belevichexit:
33*7cb25c9bSArtem Belevich  %ret = phi float [%ret1, %use_mul], [%ret2, %use_add]
34*7cb25c9bSArtem Belevich
35*7cb25c9bSArtem Belevich  call void @used_subfunc(float %ret)
36*7cb25c9bSArtem Belevich
37*7cb25c9bSArtem Belevich  ret float %ret
38*7cb25c9bSArtem Belevich}
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