1 // REQUIRES: arm-registered-target
2 // RUN: %clang_cc1 -triple arm64-apple-ios9 -emit-llvm -o - -fallow-half-arguments-and-returns %s | FileCheck %s --check-prefix=CHECK
3 // RUN: %clang_cc1 -triple armv7-apple-ios9 -emit-llvm -o - -fallow-half-arguments-and-returns %s | FileCheck %s --check-prefix=CHECK
4 
5 typedef __fp16 half4 __attribute__ ((vector_size (8)));
6 typedef short short4 __attribute__ ((vector_size (8)));
7 
8 half4 hv0, hv1;
9 short4 sv0;
10 
11 // CHECK-LABEL: testFP16Vec0
12 // CHECK: %[[V0:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
13 // CHECK: %[[CONV:.*]] = fpext <4 x half> %[[V0]] to <4 x float>
14 // CHECK: %[[V1:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
15 // CHECK: %[[CONV1:.*]] = fpext <4 x half> %[[V1]] to <4 x float>
16 // CHECK: %[[ADD:.*]] = fadd <4 x float> %[[CONV]], %[[CONV1]]
17 // CHECK: %[[CONV2:.*]] = fptrunc <4 x float> %[[ADD]] to <4 x half>
18 // CHECK: store <4 x half> %[[CONV2]], <4 x half>* @hv0, align 8
19 // CHECK: %[[V2:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
20 // CHECK: %[[CONV3:.*]] = fpext <4 x half> %[[V2]] to <4 x float>
21 // CHECK: %[[V3:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
22 // CHECK: %[[CONV4:.*]] = fpext <4 x half> %[[V3]] to <4 x float>
23 // CHECK: %[[SUB:.*]] = fsub <4 x float> %[[CONV3]], %[[CONV4]]
24 // CHECK: %[[CONV5:.*]] = fptrunc <4 x float> %[[SUB]] to <4 x half>
25 // CHECK: store <4 x half> %[[CONV5]], <4 x half>* @hv0, align 8
26 // CHECK: %[[V4:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
27 // CHECK: %[[CONV6:.*]] = fpext <4 x half> %[[V4]] to <4 x float>
28 // CHECK: %[[V5:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
29 // CHECK: %[[CONV7:.*]] = fpext <4 x half> %[[V5]] to <4 x float>
30 // CHECK: %[[MUL:.*]] = fmul <4 x float> %[[CONV6]], %[[CONV7]]
31 // CHECK: %[[CONV8:.*]] = fptrunc <4 x float> %[[MUL]] to <4 x half>
32 // CHECK: store <4 x half> %[[CONV8]], <4 x half>* @hv0, align 8
33 // CHECK: %[[V6:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
34 // CHECK: %[[CONV9:.*]] = fpext <4 x half> %[[V6]] to <4 x float>
35 // CHECK: %[[V7:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
36 // CHECK: %[[CONV10:.*]] = fpext <4 x half> %[[V7]] to <4 x float>
37 // CHECK: %[[DIV:.*]] = fdiv <4 x float> %[[CONV9]], %[[CONV10]]
38 // CHECK: %[[CONV11:.*]] = fptrunc <4 x float> %[[DIV]] to <4 x half>
39 // CHECK: store <4 x half> %[[CONV11]], <4 x half>* @hv0, align 8
40 
41 void testFP16Vec0() {
42   hv0 = hv0 + hv1;
43   hv0 = hv0 - hv1;
44   hv0 = hv0 * hv1;
45   hv0 = hv0 / hv1;
46 }
47 
48 // CHECK-LABEL: testFP16Vec1
49 // CHECK: %[[V0:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
50 // CHECK: %[[CONV:.*]] = fpext <4 x half> %[[V0]] to <4 x float>
51 // CHECK: %[[V1:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
52 // CHECK: %[[CONV1:.*]] = fpext <4 x half> %[[V1]] to <4 x float>
53 // CHECK: %[[ADD:.*]] = fadd <4 x float> %[[CONV1]], %[[CONV]]
54 // CHECK: %[[CONV2:.*]] = fptrunc <4 x float> %[[ADD]] to <4 x half>
55 // CHECK: store <4 x half> %[[CONV2]], <4 x half>* @hv0, align 8
56 // CHECK: %[[V2:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
57 // CHECK: %[[CONV3:.*]] = fpext <4 x half> %[[V2]] to <4 x float>
58 // CHECK: %[[V3:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
59 // CHECK: %[[CONV4:.*]] = fpext <4 x half> %[[V3]] to <4 x float>
60 // CHECK: %[[SUB:.*]] = fsub <4 x float> %[[CONV4]], %[[CONV3]]
61 // CHECK: %[[CONV5:.*]] = fptrunc <4 x float> %[[SUB]] to <4 x half>
62 // CHECK: store <4 x half> %[[CONV5]], <4 x half>* @hv0, align 8
63 // CHECK: %[[V4:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
64 // CHECK: %[[CONV6:.*]] = fpext <4 x half> %[[V4]] to <4 x float>
65 // CHECK: %[[V5:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
66 // CHECK: %[[CONV7:.*]] = fpext <4 x half> %[[V5]] to <4 x float>
67 // CHECK: %[[MUL:.*]] = fmul <4 x float> %[[CONV7]], %[[CONV6]]
68 // CHECK: %[[CONV8:.*]] = fptrunc <4 x float> %[[MUL]] to <4 x half>
69 // CHECK: store <4 x half> %[[CONV8]], <4 x half>* @hv0, align 8
70 // CHECK: %[[V6:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
71 // CHECK: %[[CONV9:.*]] = fpext <4 x half> %[[V6]] to <4 x float>
72 // CHECK: %[[V7:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
73 // CHECK: %[[CONV10:.*]] = fpext <4 x half> %[[V7]] to <4 x float>
74 // CHECK: %[[DIV:.*]] = fdiv <4 x float> %[[CONV10]], %[[CONV9]]
75 // CHECK: %[[CONV11:.*]] = fptrunc <4 x float> %[[DIV]] to <4 x half>
76 // CHECK: store <4 x half> %[[CONV11]], <4 x half>* @hv0, align 8
77 
78 void testFP16Vec1() {
79   hv0 += hv1;
80   hv0 -= hv1;
81   hv0 *= hv1;
82   hv0 /= hv1;
83 }
84 
85 // CHECK-LABEL: testFP16Vec2
86 // CHECK: %[[CADDR:.*]] = alloca i32, align 4
87 // CHECK: store i32 %[[C:.*]], i32* %[[CADDR]], align 4
88 // CHECK: %[[V0:.*]] = load i32, i32* %[[CADDR]], align 4
89 // CHECK: %[[TOBOOL:.*]] = icmp ne i32 %[[V0]], 0
90 // CHECK: br i1 %[[TOBOOL]], label %{{.*}}, label %{{.*}}
91 //
92 // CHECK: %[[V1:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
93 // CHECK: br label %{{.*}}
94 //
95 // CHECK: %[[V2:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
96 // CHECK: br label %{{.*}}
97 //
98 // CHECK: %[[COND:.*]] = phi <4 x half> [ %[[V1]], %{{.*}} ], [ %[[V2]], %{{.*}} ]
99 // CHECK: store <4 x half> %[[COND]], <4 x half>* @hv0, align 8
100 
101 void testFP16Vec2(int c) {
102   hv0 = c ? hv0 : hv1;
103 }
104 
105 // CHECK-LABEL: testFP16Vec3
106 // CHECK: %[[V0:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
107 // CHECK: %[[CONV:.*]] = fpext <4 x half> %[[V0]] to <4 x float>
108 // CHECK: %[[V1:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
109 // CHECK: %[[CONV1:.*]] = fpext <4 x half> %[[V1]] to <4 x float>
110 // CHECK: %[[CMP:.*]] = fcmp oeq <4 x float> %[[CONV]], %[[CONV1]]
111 // CHECK: %[[SEXT:.*]] = sext <4 x i1> %[[CMP]] to <4 x i32>
112 // CHECK: %[[CONV2:.*]] = trunc <4 x i32> %[[SEXT]] to <4 x i16>
113 // CHECK: store <4 x i16> %[[CONV2]], <4 x i16>* @sv0, align 8
114 // CHECK: %[[V2:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
115 // CHECK: %[[CONV3:.*]] = fpext <4 x half> %[[V2]] to <4 x float>
116 // CHECK: %[[V3:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
117 // CHECK: %[[CONV4:.*]] = fpext <4 x half> %[[V3]] to <4 x float>
118 // CHECK: %[[CMP5:.*]] = fcmp une <4 x float> %[[CONV3]], %[[CONV4]]
119 // CHECK: %[[SEXT6:.*]] = sext <4 x i1> %[[CMP5]] to <4 x i32>
120 // CHECK: %[[CONV7:.*]] = trunc <4 x i32> %[[SEXT6]] to <4 x i16>
121 // CHECK: store <4 x i16> %[[CONV7]], <4 x i16>* @sv0, align 8
122 // CHECK: %[[V4:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
123 // CHECK: %[[CONV8:.*]] = fpext <4 x half> %[[V4]] to <4 x float>
124 // CHECK: %[[V5:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
125 // CHECK: %[[CONV9:.*]] = fpext <4 x half> %[[V5]] to <4 x float>
126 // CHECK: %[[CMP10:.*]] = fcmp olt <4 x float> %[[CONV8]], %[[CONV9]]
127 // CHECK: %[[SEXT11:.*]] = sext <4 x i1> %[[CMP10]] to <4 x i32>
128 // CHECK: %[[CONV12:.*]] = trunc <4 x i32> %[[SEXT11]] to <4 x i16>
129 // CHECK: store <4 x i16> %[[CONV12]], <4 x i16>* @sv0, align 8
130 // CHECK: %[[V6:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
131 // CHECK: %[[CONV13:.*]] = fpext <4 x half> %[[V6]] to <4 x float>
132 // CHECK: %[[V7:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
133 // CHECK: %[[CONV14:.*]] = fpext <4 x half> %[[V7]] to <4 x float>
134 // CHECK: %[[CMP15:.*]] = fcmp ogt <4 x float> %[[CONV13]], %[[CONV14]]
135 // CHECK: %[[SEXT16:.*]] = sext <4 x i1> %[[CMP15]] to <4 x i32>
136 // CHECK: %[[CONV17:.*]] = trunc <4 x i32> %[[SEXT16]] to <4 x i16>
137 // CHECK: store <4 x i16> %[[CONV17]], <4 x i16>* @sv0, align 8
138 // CHECK: %[[V8:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
139 // CHECK: %[[CONV18:.*]] = fpext <4 x half> %[[V8]] to <4 x float>
140 // CHECK: %[[V9:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
141 // CHECK: %[[CONV19:.*]] = fpext <4 x half> %[[V9]] to <4 x float>
142 // CHECK: %[[CMP20:.*]] = fcmp ole <4 x float> %[[CONV18]], %[[CONV19]]
143 // CHECK: %[[SEXT21:.*]] = sext <4 x i1> %[[CMP20]] to <4 x i32>
144 // CHECK: %[[CONV22:.*]] = trunc <4 x i32> %[[SEXT21]] to <4 x i16>
145 // CHECK: store <4 x i16> %[[CONV22]], <4 x i16>* @sv0, align 8
146 // CHECK: %[[V10:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
147 // CHECK: %[[CONV23:.*]] = fpext <4 x half> %[[V10]] to <4 x float>
148 // CHECK: %[[V11:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
149 // CHECK: %[[CONV24:.*]] = fpext <4 x half> %[[V11]] to <4 x float>
150 // CHECK: %[[CMP25:.*]] = fcmp oge <4 x float> %[[CONV23]], %[[CONV24]]
151 // CHECK: %[[SEXT26:.*]] = sext <4 x i1> %[[CMP25]] to <4 x i32>
152 // CHECK: %[[CONV27:.*]] = trunc <4 x i32> %[[SEXT26]] to <4 x i16>
153 // CHECK: store <4 x i16> %[[CONV27]], <4 x i16>* @sv0, align 8
154 
155 void testFP16Vec3() {
156   sv0 = hv0 == hv1;
157   sv0 = hv0 != hv1;
158   sv0 = hv0 < hv1;
159   sv0 = hv0 > hv1;
160   sv0 = hv0 <= hv1;
161   sv0 = hv0 >= hv1;
162 }
163