1 // RUN: %clang_cc1 -Wall -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s 2 3 void *f0() 4 { 5 return __builtin_thread_pointer(); 6 } 7 8 void f1(char *a, char *b) { 9 __clear_cache(a,b); 10 } 11 12 // CHECK: call {{.*}} @__clear_cache 13 14 void test_eh_return_data_regno() 15 { 16 volatile int res; 17 res = __builtin_eh_return_data_regno(0); // CHECK: store volatile i32 0 18 res = __builtin_eh_return_data_regno(1); // CHECK: store volatile i32 1 19 } 20 21 void nop() { 22 __builtin_arm_nop(); 23 } 24 25 // CHECK: call {{.*}} @llvm.arm.hint(i32 0) 26 27 void yield() { 28 __builtin_arm_yield(); 29 } 30 31 // CHECK: call {{.*}} @llvm.arm.hint(i32 1) 32 33 void wfe() { 34 __builtin_arm_wfe(); 35 } 36 37 // CHECK: call {{.*}} @llvm.arm.hint(i32 2) 38 39 void wfi() { 40 __builtin_arm_wfi(); 41 } 42 43 // CHECK: call {{.*}} @llvm.arm.hint(i32 3) 44 45 void sev() { 46 __builtin_arm_sev(); 47 } 48 49 // CHECK: call {{.*}} @llvm.arm.hint(i32 4) 50 51 void sevl() { 52 __builtin_arm_sevl(); 53 } 54 55 // CHECK: call {{.*}} @llvm.arm.hint(i32 5) 56 57 void dbg() { 58 __builtin_arm_dbg(0); 59 } 60 61 // CHECK: call {{.*}} @llvm.arm.dbg(i32 0) 62 63 void test_barrier() { 64 __builtin_arm_dmb(1); //CHECK: call {{.*}} @llvm.arm.dmb(i32 1) 65 __builtin_arm_dsb(2); //CHECK: call {{.*}} @llvm.arm.dsb(i32 2) 66 __builtin_arm_isb(3); //CHECK: call {{.*}} @llvm.arm.isb(i32 3) 67 } 68 69 // CHECK: call {{.*}} @llvm.arm.rbit(i32 %a) 70 71 unsigned rbit(unsigned a) { 72 return __builtin_arm_rbit(a); 73 } 74 75 void prefetch(int i) { 76 __builtin_arm_prefetch(&i, 0, 1); 77 // CHECK: call {{.*}} @llvm.prefetch(i8* %{{.*}}, i32 0, i32 3, i32 1) 78 79 __builtin_arm_prefetch(&i, 1, 1); 80 // CHECK: call {{.*}} @llvm.prefetch(i8* %{{.*}}, i32 1, i32 3, i32 1) 81 82 83 __builtin_arm_prefetch(&i, 1, 0); 84 // CHECK: call {{.*}} @llvm.prefetch(i8* %{{.*}}, i32 1, i32 3, i32 0) 85 } 86 87 unsigned mrc() { 88 // CHECK: define i32 @mrc() 89 // CHECK: [[R:%.*]] = call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3) 90 // CHECK-NEXT: ret i32 [[R]] 91 return __builtin_arm_mrc(15, 0, 13, 0, 3); 92 } 93 94 unsigned mrc2() { 95 // CHECK: define i32 @mrc2() 96 // CHECK: [[R:%.*]] = call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3) 97 // CHECK-NEXT: ret i32 [[R]] 98 return __builtin_arm_mrc2(15, 0, 13, 0, 3); 99 } 100 101 void mcr(unsigned a) { 102 // CHECK: define void @mcr(i32 [[A:%.*]]) 103 // CHECK: call void @llvm.arm.mcr(i32 15, i32 0, i32 [[A]], i32 13, i32 0, i32 3) 104 __builtin_arm_mcr(15, 0, a, 13, 0, 3); 105 } 106 107 void mcr2(unsigned a) { 108 // CHECK: define void @mcr2(i32 [[A:%.*]]) 109 // CHECK: call void @llvm.arm.mcr2(i32 15, i32 0, i32 [[A]], i32 13, i32 0, i32 3) 110 __builtin_arm_mcr2(15, 0, a, 13, 0, 3); 111 } 112 113 void mcrr(unsigned a, unsigned b) { 114 // CHECK: define void @mcrr(i32 [[A:%.*]], i32 [[B:%.*]]) 115 // CHECK: call void @llvm.arm.mcrr(i32 15, i32 0, i32 [[A]], i32 [[B]], i32 0) 116 __builtin_arm_mcrr(15, 0, a, b, 0); 117 } 118 119 void mcrr2(unsigned a, unsigned b) { 120 // CHECK: define void @mcrr2(i32 [[A:%.*]], i32 [[B:%.*]]) 121 // CHECK: call void @llvm.arm.mcrr2(i32 15, i32 0, i32 [[A]], i32 [[B]], i32 0) 122 __builtin_arm_mcrr2(15, 0, a, b, 0); 123 } 124 125 unsigned rsr() { 126 // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_register.i32(metadata ![[M0:.*]]) 127 // CHECK-NEXT: ret i32 [[V0]] 128 return __builtin_arm_rsr("cp1:2:c3:c4:5"); 129 } 130 131 unsigned long long rsr64() { 132 // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_register.i64(metadata ![[M1:.*]]) 133 // CHECK-NEXT: ret i64 [[V0]] 134 return __builtin_arm_rsr64("cp1:2:c3"); 135 } 136 137 void *rsrp() { 138 // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_register.i32(metadata ![[M2:.*]]) 139 // CHECK-NEXT: [[V1:[%A-Za-z0-9.]+]] = inttoptr i32 [[V0]] to i8* 140 // CHECK-NEXT: ret i8* [[V1]] 141 return __builtin_arm_rsrp("sysreg"); 142 } 143 144 void wsr(unsigned v) { 145 // CHECK: call void @llvm.write_register.i32(metadata ![[M0]], i32 %v) 146 __builtin_arm_wsr("cp1:2:c3:c4:5", v); 147 } 148 149 void wsr64(unsigned long long v) { 150 // CHECK: call void @llvm.write_register.i64(metadata ![[M1]], i64 %v) 151 __builtin_arm_wsr64("cp1:2:c3", v); 152 } 153 154 void wsrp(void *v) { 155 // CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint i8* %v to i32 156 // CHECK-NEXT: call void @llvm.write_register.i32(metadata ![[M2]], i32 [[V0]]) 157 __builtin_arm_wsrp("sysreg", v); 158 } 159 160 // CHECK: ![[M0]] = !{!"cp1:2:c3:c4:5"} 161 // CHECK: ![[M1]] = !{!"cp1:2:c3"} 162 // CHECK: ![[M2]] = !{!"sysreg"} 163