1 // REQUIRES: aarch64-registered-target 2 3 // RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm -S \ 4 // RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM 5 6 // RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm \ 7 // RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR 8 9 // From winnt.h 10 #define ARM64_SYSREG(op0, op1, crn, crm, op2) \ 11 ( ((op0 & 1) << 14) | \ 12 ((op1 & 7) << 11) | \ 13 ((crn & 15) << 7) | \ 14 ((crm & 15) << 3) | \ 15 ((op2 & 7) << 0) ) 16 17 #define ARM64_CNTVCT ARM64_SYSREG(3,3,14, 0,2) // Generic Timer counter register 18 #define ARM64_PMCCNTR_EL0 ARM64_SYSREG(3,3, 9,13,0) // Cycle Count Register [CP15_PMCCNTR] 19 #define ARM64_PMSELR_EL0 ARM64_SYSREG(3,3, 9,12,5) // Event Counter Selection Register [CP15_PMSELR] 20 #define ARM64_PMXEVCNTR_EL0 ARM64_SYSREG(3,3, 9,13,2) // Event Count Register [CP15_PMXEVCNTR] 21 #define ARM64_PMXEVCNTRn_EL0(n) ARM64_SYSREG(3,3,14, 8+((n)/8), (n)%8) // Direct Event Count Register [n/a] 22 #define ARM64_TPIDR_EL0 ARM64_SYSREG(3,3,13, 0,2) // Thread ID Register, User Read/Write [CP15_TPIDRURW] 23 #define ARM64_TPIDRRO_EL0 ARM64_SYSREG(3,3,13, 0,3) // Thread ID Register, User Read Only [CP15_TPIDRURO] 24 #define ARM64_TPIDR_EL1 ARM64_SYSREG(3,0,13, 0,4) // Thread ID Register, Privileged Only [CP15_TPIDRPRW] 25 26 void check_ReadWriteStatusReg(int v) { 27 int ret; 28 ret = _ReadStatusReg(ARM64_CNTVCT); 29 // CHECK-ASM: mrs x8, CNTVCT_EL0 30 // CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD2:.*]]) 31 32 ret = _ReadStatusReg(ARM64_PMCCNTR_EL0); 33 // CHECK-ASM: mrs x8, PMCCNTR_EL0 34 // CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD3:.*]]) 35 36 ret = _ReadStatusReg(ARM64_PMSELR_EL0); 37 // CHECK-ASM: mrs x8, PMSELR_EL0 38 // CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD4:.*]]) 39 40 ret = _ReadStatusReg(ARM64_PMXEVCNTR_EL0); 41 // CHECK-ASM: mrs x8, PMXEVCNTR_EL0 42 // CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD5:.*]]) 43 44 ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(0)); 45 // CHECK-ASM: mrs x8, PMEVCNTR0_EL0 46 // CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD6:.*]]) 47 48 ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(1)); 49 // CHECK-ASM: mrs x8, PMEVCNTR1_EL0 50 // CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD7:.*]]) 51 52 ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(30)); 53 // CHECK-ASM: mrs x8, PMEVCNTR30_EL0 54 // CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD8:.*]]) 55 56 ret = _ReadStatusReg(ARM64_TPIDR_EL0); 57 // CHECK-ASM: mrs x8, TPIDR_EL0 58 // CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD9:.*]]) 59 60 ret = _ReadStatusReg(ARM64_TPIDRRO_EL0); 61 // CHECK-ASM: mrs x8, TPIDRRO_EL0 62 // CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD10:.*]]) 63 64 ret = _ReadStatusReg(ARM64_TPIDR_EL1); 65 // CHECK-ASM: mrs x8, TPIDR_EL1 66 // CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD11:.*]]) 67 68 69 _WriteStatusReg(ARM64_CNTVCT, v); 70 // CHECK-ASM: msr S3_3_C14_C0_2, x8 71 // CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 {{%.*}}) 72 73 _WriteStatusReg(ARM64_PMCCNTR_EL0, v); 74 // CHECK-ASM: msr PMCCNTR_EL0, x8 75 // CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 {{%.*}}) 76 77 _WriteStatusReg(ARM64_PMSELR_EL0, v); 78 // CHECK-ASM: msr PMSELR_EL0, x8 79 // CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 {{%.*}}) 80 81 _WriteStatusReg(ARM64_PMXEVCNTR_EL0, v); 82 // CHECK-ASM: msr PMXEVCNTR_EL0, x8 83 // CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 {{%.*}}) 84 85 _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(0), v); 86 // CHECK-ASM: msr PMEVCNTR0_EL0, x8 87 // CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 {{%.*}}) 88 89 _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(1), v); 90 // CHECK-ASM: msr PMEVCNTR1_EL0, x8 91 // CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD7:.*]], i64 {{%.*}}) 92 93 _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(30), v); 94 // CHECK-ASM: msr PMEVCNTR30_EL0, x8 95 // CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD8:.*]], i64 {{%.*}}) 96 97 _WriteStatusReg(ARM64_TPIDR_EL0, v); 98 // CHECK-ASM: msr TPIDR_EL0, x8 99 // CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD9:.*]], i64 {{%.*}}) 100 101 _WriteStatusReg(ARM64_TPIDRRO_EL0, v); 102 // CHECK-ASM: msr TPIDRRO_EL0, x8 103 // CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD10:.*]], i64 {{%.*}}) 104 105 _WriteStatusReg(ARM64_TPIDR_EL1, v); 106 // CHECK-ASM: msr TPIDR_EL1, x8 107 // CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD11:.*]], i64 {{%.*}}) 108 } 109 110 // CHECK-IR: ![[MD2]] = !{!"3:3:14:0:2"} 111 // CHECK-IR: ![[MD3]] = !{!"3:3:9:13:0"} 112 // CHECK-IR: ![[MD4]] = !{!"3:3:9:12:5"} 113 // CHECK-IR: ![[MD5]] = !{!"3:3:9:13:2"} 114 // CHECK-IR: ![[MD6]] = !{!"3:3:14:8:0"} 115 // CHECK-IR: ![[MD7]] = !{!"3:3:14:8:1"} 116 // CHECK-IR: ![[MD8]] = !{!"3:3:14:11:6"} 117 // CHECK-IR: ![[MD9]] = !{!"3:3:13:0:2"} 118 // CHECK-IR: ![[MD10]] = !{!"3:3:13:0:3"} 119 // CHECK-IR: ![[MD11]] = !{!"3:0:13:0:4"} 120