1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
3 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
4 
5 #include <arm_mve.h>
6 
7 // CHECK-LABEL: @_Z16test_vbicq_n_s1617__simd128_int16_t(
8 // CHECK-NEXT:  entry:
9 // CHECK-NEXT:    [[TMP0:%.*]] = and <8 x i16> [[A:%.*]], <i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007>
10 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
11 //
12 int16x8_t test_vbicq_n_s16(int16x8_t a)
13 {
14 #ifdef POLYMORPHIC
15     return vbicq(a, 0xd500);
16 #else /* POLYMORPHIC */
17     return vbicq_n_s16(a, 0xd500);
18 #endif /* POLYMORPHIC */
19 }
20 
21 // CHECK-LABEL: @_Z16test_vbicq_n_u3218__simd128_uint32_t(
22 // CHECK-NEXT:  entry:
23 // CHECK-NEXT:    [[TMP0:%.*]] = and <4 x i32> [[A:%.*]], <i32 -8193, i32 -8193, i32 -8193, i32 -8193>
24 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
25 //
26 uint32x4_t test_vbicq_n_u32(uint32x4_t a)
27 {
28 #ifdef POLYMORPHIC
29     return vbicq(a, 0x2000);
30 #else /* POLYMORPHIC */
31     return vbicq_n_u32(a, 0x2000);
32 #endif /* POLYMORPHIC */
33 }
34 
35 // CHECK-LABEL: @_Z16test_vorrq_n_s3217__simd128_int32_t(
36 // CHECK-NEXT:  entry:
37 // CHECK-NEXT:    [[TMP0:%.*]] = or <4 x i32> [[A:%.*]], <i32 65536, i32 65536, i32 65536, i32 65536>
38 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
39 //
40 int32x4_t test_vorrq_n_s32(int32x4_t a)
41 {
42 #ifdef POLYMORPHIC
43     return vorrq(a, 0x10000);
44 #else /* POLYMORPHIC */
45     return vorrq_n_s32(a, 0x10000);
46 #endif /* POLYMORPHIC */
47 }
48 
49 // CHECK-LABEL: @_Z16test_vorrq_n_u1618__simd128_uint16_t(
50 // CHECK-NEXT:  entry:
51 // CHECK-NEXT:    [[TMP0:%.*]] = or <8 x i16> [[A:%.*]], <i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096>
52 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
53 //
54 uint16x8_t test_vorrq_n_u16(uint16x8_t a)
55 {
56 #ifdef POLYMORPHIC
57     return vorrq(a, 0xf000);
58 #else /* POLYMORPHIC */
59     return vorrq_n_u16(a, 0xf000);
60 #endif /* POLYMORPHIC */
61 }
62 
63 // CHECK-LABEL: @_Z16test_vcmpeqq_f1619__simd128_float16_tS_(
64 // CHECK-NEXT:  entry:
65 // CHECK-NEXT:    [[TMP0:%.*]] = fcmp oeq <8 x half> [[A:%.*]], [[B:%.*]]
66 // CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> [[TMP0]])
67 // CHECK-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
68 // CHECK-NEXT:    ret i16 [[TMP2]]
69 //
70 mve_pred16_t test_vcmpeqq_f16(float16x8_t a, float16x8_t b)
71 {
72 #ifdef POLYMORPHIC
73     return vcmpeqq(a, b);
74 #else /* POLYMORPHIC */
75     return vcmpeqq_f16(a, b);
76 #endif /* POLYMORPHIC */
77 }
78 
79 // CHECK-LABEL: @_Z18test_vcmpeqq_n_f1619__simd128_float16_tDh(
80 // CHECK-NEXT:  entry:
81 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <8 x half> poison, half [[B:%.*]], i32 0
82 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <8 x half> [[DOTSPLATINSERT]], <8 x half> poison, <8 x i32> zeroinitializer
83 // CHECK-NEXT:    [[TMP0:%.*]] = fcmp oeq <8 x half> [[A:%.*]], [[DOTSPLAT]]
84 // CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> [[TMP0]])
85 // CHECK-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
86 // CHECK-NEXT:    ret i16 [[TMP2]]
87 //
88 mve_pred16_t test_vcmpeqq_n_f16(float16x8_t a, float16_t b)
89 {
90 #ifdef POLYMORPHIC
91     return vcmpeqq(a, b);
92 #else /* POLYMORPHIC */
93     return vcmpeqq_n_f16(a, b);
94 #endif /* POLYMORPHIC */
95 }
96 
97 // CHECK-LABEL: @_Z14test_vld1q_u16PKt(
98 // CHECK-NEXT:  entry:
99 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <8 x i16>*
100 // CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[TMP0]], align 2
101 // CHECK-NEXT:    ret <8 x i16> [[TMP1]]
102 //
103 uint16x8_t test_vld1q_u16(const uint16_t *base)
104 {
105 #ifdef POLYMORPHIC
106     return vld1q(base);
107 #else /* POLYMORPHIC */
108     return vld1q_u16(base);
109 #endif /* POLYMORPHIC */
110 }
111 
112 // CHECK-LABEL: @_Z16test_vst1q_p_s32Pi17__simd128_int32_tt(
113 // CHECK-NEXT:  entry:
114 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <4 x i32>*
115 // CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
116 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]])
117 // CHECK-NEXT:    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[VALUE:%.*]], <4 x i32>* [[TMP0]], i32 4, <4 x i1> [[TMP2]])
118 // CHECK-NEXT:    ret void
119 //
120 void test_vst1q_p_s32(int32_t *base, int32x4_t value, mve_pred16_t p)
121 {
122 #ifdef POLYMORPHIC
123     vst1q_p(base, value, p);
124 #else /* POLYMORPHIC */
125     vst1q_p_s32(base, value, p);
126 #endif /* POLYMORPHIC */
127 }
128 
129 // CHECK-LABEL: @_Z30test_vldrdq_gather_base_wb_s64P18__simd128_uint64_t(
130 // CHECK-NEXT:  entry:
131 // CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[ADDR:%.*]], align 8
132 // CHECK-NEXT:    [[TMP1:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> [[TMP0]], i32 576)
133 // CHECK-NEXT:    [[TMP2:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP1]], 1
134 // CHECK-NEXT:    store <2 x i64> [[TMP2]], <2 x i64>* [[ADDR]], align 8
135 // CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP1]], 0
136 // CHECK-NEXT:    ret <2 x i64> [[TMP3]]
137 //
138 int64x2_t test_vldrdq_gather_base_wb_s64(uint64x2_t *addr)
139 {
140     return vldrdq_gather_base_wb_s64(addr, 0x240);
141 }
142 
143 // CHECK-LABEL: @_Z31test_vstrwq_scatter_base_wb_u32P18__simd128_uint32_tS_(
144 // CHECK-NEXT:  entry:
145 // CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[ADDR:%.*]], align 8
146 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> [[TMP0]], i32 64, <4 x i32> [[VALUE:%.*]])
147 // CHECK-NEXT:    store <4 x i32> [[TMP1]], <4 x i32>* [[ADDR]], align 8
148 // CHECK-NEXT:    ret void
149 //
150 void test_vstrwq_scatter_base_wb_u32(uint32x4_t *addr, uint32x4_t value)
151 {
152 #ifdef POLYMORPHIC
153     vstrwq_scatter_base_wb(addr, 0x40, value);
154 #else /* POLYMORPHIC */
155     vstrwq_scatter_base_wb_u32(addr, 0x40, value);
156 #endif /* POLYMORPHIC */
157 }
158