1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 2 // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s 3 // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s 4 5 #include <arm_mve.h> 6 7 // CHECK-LABEL: @_Z16test_vbicq_n_s1617__simd128_int16_t( 8 // CHECK-NEXT: entry: 9 // CHECK-NEXT: [[TMP0:%.*]] = and <8 x i16> [[A:%.*]], <i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007> 10 // CHECK-NEXT: ret <8 x i16> [[TMP0]] 11 // 12 int16x8_t test_vbicq_n_s16(int16x8_t a) 13 { 14 #ifdef POLYMORPHIC 15 return vbicq(a, 0xd500); 16 #else /* POLYMORPHIC */ 17 return vbicq_n_s16(a, 0xd500); 18 #endif /* POLYMORPHIC */ 19 } 20 21 // CHECK-LABEL: @_Z16test_vbicq_n_u3218__simd128_uint32_t( 22 // CHECK-NEXT: entry: 23 // CHECK-NEXT: [[TMP0:%.*]] = and <4 x i32> [[A:%.*]], <i32 -8193, i32 -8193, i32 -8193, i32 -8193> 24 // CHECK-NEXT: ret <4 x i32> [[TMP0]] 25 // 26 uint32x4_t test_vbicq_n_u32(uint32x4_t a) 27 { 28 #ifdef POLYMORPHIC 29 return vbicq(a, 0x2000); 30 #else /* POLYMORPHIC */ 31 return vbicq_n_u32(a, 0x2000); 32 #endif /* POLYMORPHIC */ 33 } 34 35 // CHECK-LABEL: @_Z16test_vorrq_n_s3217__simd128_int32_t( 36 // CHECK-NEXT: entry: 37 // CHECK-NEXT: [[TMP0:%.*]] = or <4 x i32> [[A:%.*]], <i32 65536, i32 65536, i32 65536, i32 65536> 38 // CHECK-NEXT: ret <4 x i32> [[TMP0]] 39 // 40 int32x4_t test_vorrq_n_s32(int32x4_t a) 41 { 42 #ifdef POLYMORPHIC 43 return vorrq(a, 0x10000); 44 #else /* POLYMORPHIC */ 45 return vorrq_n_s32(a, 0x10000); 46 #endif /* POLYMORPHIC */ 47 } 48 49 // CHECK-LABEL: @_Z16test_vorrq_n_u1618__simd128_uint16_t( 50 // CHECK-NEXT: entry: 51 // CHECK-NEXT: [[TMP0:%.*]] = or <8 x i16> [[A:%.*]], <i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096> 52 // CHECK-NEXT: ret <8 x i16> [[TMP0]] 53 // 54 uint16x8_t test_vorrq_n_u16(uint16x8_t a) 55 { 56 #ifdef POLYMORPHIC 57 return vorrq(a, 0xf000); 58 #else /* POLYMORPHIC */ 59 return vorrq_n_u16(a, 0xf000); 60 #endif /* POLYMORPHIC */ 61 } 62 63 // CHECK-LABEL: @_Z16test_vcmpeqq_f1619__simd128_float16_tS_( 64 // CHECK-NEXT: entry: 65 // CHECK-NEXT: [[TMP0:%.*]] = fcmp oeq <8 x half> [[A:%.*]], [[B:%.*]] 66 // CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> [[TMP0]]), !range !3 67 // CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16 68 // CHECK-NEXT: ret i16 [[TMP2]] 69 // 70 mve_pred16_t test_vcmpeqq_f16(float16x8_t a, float16x8_t b) 71 { 72 #ifdef POLYMORPHIC 73 return vcmpeqq(a, b); 74 #else /* POLYMORPHIC */ 75 return vcmpeqq_f16(a, b); 76 #endif /* POLYMORPHIC */ 77 } 78 79 // CHECK-LABEL: @_Z18test_vcmpeqq_n_f1619__simd128_float16_tDh( 80 // CHECK-NEXT: entry: 81 // CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[B_COERCE:%.*]] to i32 82 // CHECK-NEXT: [[TMP_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[TMP0]] to i16 83 // CHECK-NEXT: [[TMP1:%.*]] = bitcast i16 [[TMP_0_EXTRACT_TRUNC]] to half 84 // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <8 x half> undef, half [[TMP1]], i32 0 85 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <8 x half> [[DOTSPLATINSERT]], <8 x half> undef, <8 x i32> zeroinitializer 86 // CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq <8 x half> [[DOTSPLAT]], [[A:%.*]] 87 // CHECK-NEXT: [[TMP3:%.*]] = tail call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> [[TMP2]]), !range !3 88 // CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16 89 // CHECK-NEXT: ret i16 [[TMP4]] 90 // 91 mve_pred16_t test_vcmpeqq_n_f16(float16x8_t a, float16_t b) 92 { 93 #ifdef POLYMORPHIC 94 return vcmpeqq(a, b); 95 #else /* POLYMORPHIC */ 96 return vcmpeqq_n_f16(a, b); 97 #endif /* POLYMORPHIC */ 98 } 99 100 // CHECK-LABEL: @_Z14test_vld1q_u16PKt( 101 // CHECK-NEXT: entry: 102 // CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <8 x i16>* 103 // CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[TMP0]], align 2 104 // CHECK-NEXT: ret <8 x i16> [[TMP1]] 105 // 106 uint16x8_t test_vld1q_u16(const uint16_t *base) 107 { 108 #ifdef POLYMORPHIC 109 return vld1q(base); 110 #else /* POLYMORPHIC */ 111 return vld1q_u16(base); 112 #endif /* POLYMORPHIC */ 113 } 114 115 // CHECK-LABEL: @_Z16test_vst1q_p_s32Pi17__simd128_int32_tt( 116 // CHECK-NEXT: entry: 117 // CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <4 x i32>* 118 // CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32 119 // CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]]) 120 // CHECK-NEXT: tail call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[VALUE:%.*]], <4 x i32>* [[TMP0]], i32 4, <4 x i1> [[TMP2]]) 121 // CHECK-NEXT: ret void 122 // 123 void test_vst1q_p_s32(int32_t *base, int32x4_t value, mve_pred16_t p) 124 { 125 #ifdef POLYMORPHIC 126 vst1q_p(base, value, p); 127 #else /* POLYMORPHIC */ 128 vst1q_p_s32(base, value, p); 129 #endif /* POLYMORPHIC */ 130 } 131 132 // CHECK-LABEL: @_Z30test_vldrdq_gather_base_wb_s64P18__simd128_uint64_t( 133 // CHECK-NEXT: entry: 134 // CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[ADDR:%.*]], align 8 135 // CHECK-NEXT: [[TMP1:%.*]] = tail call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> [[TMP0]], i32 576) 136 // CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP1]], 1 137 // CHECK-NEXT: store <2 x i64> [[TMP2]], <2 x i64>* [[ADDR]], align 8 138 // CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP1]], 0 139 // CHECK-NEXT: ret <2 x i64> [[TMP3]] 140 // 141 int64x2_t test_vldrdq_gather_base_wb_s64(uint64x2_t *addr) 142 { 143 return vldrdq_gather_base_wb_s64(addr, 0x240); 144 } 145 146 // CHECK-LABEL: @_Z31test_vstrwq_scatter_base_wb_u32P18__simd128_uint32_tS_( 147 // CHECK-NEXT: entry: 148 // CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[ADDR:%.*]], align 8 149 // CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> [[TMP0]], i32 64, <4 x i32> [[VALUE:%.*]]) 150 // CHECK-NEXT: store <4 x i32> [[TMP1]], <4 x i32>* [[ADDR]], align 8 151 // CHECK-NEXT: ret void 152 // 153 void test_vstrwq_scatter_base_wb_u32(uint32x4_t *addr, uint32x4_t value) 154 { 155 #ifdef POLYMORPHIC 156 vstrwq_scatter_base_wb(addr, 0x40, value); 157 #else /* POLYMORPHIC */ 158 vstrwq_scatter_base_wb_u32(addr, 0x40, value); 159 #endif /* POLYMORPHIC */ 160 } 161