1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 2 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi \ 3 // RUN: -target-feature +cdecp0 -target-feature +cdecp1 \ 4 // RUN: -target-feature +mve.fp \ 5 // RUN: -mfloat-abi hard -O0 -disable-O0-optnone \ 6 // RUN: -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s 7 8 #include <arm_cde.h> 9 10 // CHECK-LABEL: @test_vcx1q_u8( 11 // CHECK-NEXT: entry: 12 // CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.cde.vcx1q(i32 0, i32 1111) 13 // CHECK-NEXT: ret <16 x i8> [[TMP0]] 14 // 15 uint8x16_t test_vcx1q_u8(void) { 16 return __arm_vcx1q_u8(0, 1111); 17 } 18 19 // CHECK-LABEL: @test_vcx1qa_1( 20 // CHECK-NEXT: entry: 21 // CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 1, <16 x i8> [[ACC:%.*]], i32 1112) 22 // CHECK-NEXT: ret <16 x i8> [[TMP0]] 23 // 24 uint8x16_t test_vcx1qa_1(uint8x16_t acc) { 25 return __arm_vcx1qa(1, acc, 1112); 26 } 27 28 // CHECK-LABEL: @test_vcx1qa_2( 29 // CHECK-NEXT: entry: 30 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[ACC:%.*]] to <16 x i8> 31 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 0, <16 x i8> [[TMP0]], i32 1113) 32 // CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 33 // CHECK-NEXT: ret <4 x i32> [[TMP2]] 34 // 35 int32x4_t test_vcx1qa_2(int32x4_t acc) { 36 return __arm_vcx1qa(0, acc, 1113); 37 } 38 39 // CHECK-LABEL: @test_vcx2q_u8( 40 // CHECK-NEXT: entry: 41 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[N:%.*]] to <16 x i8> 42 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> [[TMP0]], i32 111) 43 // CHECK-NEXT: ret <16 x i8> [[TMP1]] 44 // 45 uint8x16_t test_vcx2q_u8(float16x8_t n) { 46 return __arm_vcx2q_u8(1, n, 111); 47 } 48 49 // CHECK-LABEL: @test_vcx2q( 50 // CHECK-NEXT: entry: 51 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[N:%.*]] to <16 x i8> 52 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> [[TMP0]], i32 112) 53 // CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 54 // CHECK-NEXT: ret <4 x float> [[TMP2]] 55 // 56 float32x4_t test_vcx2q(float32x4_t n) { 57 return __arm_vcx2q(1, n, 112); 58 } 59 60 // CHECK-LABEL: @test_vcx2qa( 61 // CHECK-NEXT: entry: 62 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[ACC:%.*]] to <16 x i8> 63 // CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[N:%.*]] to <16 x i8> 64 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx2qa(i32 0, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 113) 65 // CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float> 66 // CHECK-NEXT: ret <4 x float> [[TMP3]] 67 // 68 float32x4_t test_vcx2qa(float32x4_t acc, int64x2_t n) { 69 return __arm_vcx2qa(0, acc, n, 113); 70 } 71 72 // CHECK-LABEL: @test_vcx3q_u8( 73 // CHECK-NEXT: entry: 74 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[N:%.*]] to <16 x i8> 75 // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[M:%.*]] to <16 x i8> 76 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx3q(i32 0, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 11) 77 // CHECK-NEXT: ret <16 x i8> [[TMP2]] 78 // 79 uint8x16_t test_vcx3q_u8(uint16x8_t n, int32x4_t m) { 80 return __arm_vcx3q_u8(0, n, m, 11); 81 } 82 83 // CHECK-LABEL: @test_vcx3q( 84 // CHECK-NEXT: entry: 85 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[N:%.*]] to <16 x i8> 86 // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[M:%.*]] to <16 x i8> 87 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx3q(i32 1, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 12) 88 // CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64> 89 // CHECK-NEXT: ret <2 x i64> [[TMP3]] 90 // 91 uint64x2_t test_vcx3q(uint64x2_t n, float32x4_t m) { 92 return __arm_vcx3q(1, n, m, 12); 93 } 94 95 // CHECK-LABEL: @test_vcx3qa( 96 // CHECK-NEXT: entry: 97 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[N:%.*]] to <16 x i8> 98 // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[M:%.*]] to <16 x i8> 99 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx3qa(i32 1, <16 x i8> [[ACC:%.*]], <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 13) 100 // CHECK-NEXT: ret <16 x i8> [[TMP2]] 101 // 102 int8x16_t test_vcx3qa(int8x16_t acc, uint16x8_t n, float32x4_t m) { 103 return __arm_vcx3qa(1, acc, n, m, 13); 104 } 105 106 // CHECK-LABEL: @test_vcx1q_m( 107 // CHECK-NEXT: entry: 108 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 109 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) 110 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 0, <8 x i16> [[INACTIVE:%.*]], i32 1111, <8 x i1> [[TMP1]]) 111 // CHECK-NEXT: ret <8 x i16> [[TMP2]] 112 // 113 uint16x8_t test_vcx1q_m(uint16x8_t inactive, mve_pred16_t p) { 114 return __arm_vcx1q_m(0, inactive, 1111, p); 115 } 116 117 // CHECK-LABEL: @test_vcx1qa_m( 118 // CHECK-NEXT: entry: 119 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 120 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) 121 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 1, <16 x i8> [[ACC:%.*]], i32 1112, <16 x i1> [[TMP1]]) 122 // CHECK-NEXT: ret <16 x i8> [[TMP2]] 123 // 124 uint8x16_t test_vcx1qa_m(uint8x16_t acc, mve_pred16_t p) { 125 return __arm_vcx1qa_m(1, acc, 1112, p); 126 } 127 128 // CHECK-LABEL: @test_vcx2q_m( 129 // CHECK-NEXT: entry: 130 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[N:%.*]] to <16 x i8> 131 // CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32 132 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]]) 133 // CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 0, <4 x i32> [[INACTIVE:%.*]], <16 x i8> [[TMP0]], i32 111, <4 x i1> [[TMP2]]) 134 // CHECK-NEXT: ret <4 x i32> [[TMP3]] 135 // 136 int32x4_t test_vcx2q_m(int32x4_t inactive, float32x4_t n, mve_pred16_t p) { 137 return __arm_vcx2q_m(0, inactive, n, 111, p); 138 } 139 140 // CHECK-LABEL: @test_vcx2qa_m( 141 // CHECK-NEXT: entry: 142 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[N:%.*]] to <16 x i8> 143 // CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32 144 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]]) 145 // CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 0, <4 x float> [[ACC:%.*]], <16 x i8> [[TMP0]], i32 112, <4 x i1> [[TMP2]]) 146 // CHECK-NEXT: ret <4 x float> [[TMP3]] 147 // 148 float32x4_t test_vcx2qa_m(float32x4_t acc, float16x8_t n, mve_pred16_t p) { 149 return __arm_vcx2qa_m(0, acc, n, 112, p); 150 } 151 152 // CHECK-LABEL: @test_vcx3q_m( 153 // CHECK-NEXT: entry: 154 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[N:%.*]] to <16 x i8> 155 // CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32 156 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]]) 157 // CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.arm.cde.vcx3q.predicated.v2i64.v4i1(i32 1, <2 x i64> [[INACTIVE:%.*]], <16 x i8> [[TMP0]], <16 x i8> [[M:%.*]], i32 11, <4 x i1> [[TMP2]]) 158 // CHECK-NEXT: ret <2 x i64> [[TMP3]] 159 // 160 int64x2_t test_vcx3q_m(int64x2_t inactive, float32x4_t n, int8x16_t m, mve_pred16_t p) { 161 return __arm_vcx3q_m(1, inactive, n, m, 11, p); 162 } 163 164 // CHECK-LABEL: @test_vcx3qa_m( 165 // CHECK-NEXT: entry: 166 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[N:%.*]] to <16 x i8> 167 // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[M:%.*]] to <16 x i8> 168 // CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32 169 // CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]]) 170 // CHECK-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.arm.cde.vcx3qa.predicated.v4f32.v4i1(i32 1, <4 x float> [[INACTIVE:%.*]], <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 12, <4 x i1> [[TMP3]]) 171 // CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[TMP4]] to <8 x half> 172 // CHECK-NEXT: ret <8 x half> [[TMP5]] 173 // 174 float16x8_t test_vcx3qa_m(float32x4_t inactive, float16x8_t n, uint32x4_t m, mve_pred16_t p) { 175 return __arm_vcx3qa_m(1, inactive, n, m, 12, p); 176 } 177