1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 2 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi \ 3 // RUN: -target-feature +cdecp0 -target-feature +cdecp1 \ 4 // RUN: -target-feature +mve.fp \ 5 // RUN: -mfloat-abi hard -O0 -disable-O0-optnone \ 6 // RUN: -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s 7 8 // REQUIRES: aarch64-registered-target || arm-registered-target 9 10 #include <arm_cde.h> 11 12 // CHECK-LABEL: @test_vcx1q_u8( 13 // CHECK-NEXT: entry: 14 // CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.cde.vcx1q(i32 0, i32 1111) 15 // CHECK-NEXT: ret <16 x i8> [[TMP0]] 16 // 17 uint8x16_t test_vcx1q_u8(void) { 18 return __arm_vcx1q_u8(0, 1111); 19 } 20 21 // CHECK-LABEL: @test_vcx1qa_1( 22 // CHECK-NEXT: entry: 23 // CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 1, <16 x i8> [[ACC:%.*]], i32 1112) 24 // CHECK-NEXT: ret <16 x i8> [[TMP0]] 25 // 26 uint8x16_t test_vcx1qa_1(uint8x16_t acc) { 27 return __arm_vcx1qa(1, acc, 1112); 28 } 29 30 // CHECK-LABEL: @test_vcx1qa_2( 31 // CHECK-NEXT: entry: 32 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[ACC:%.*]] to <16 x i8> 33 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 0, <16 x i8> [[TMP0]], i32 1113) 34 // CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 35 // CHECK-NEXT: ret <4 x i32> [[TMP2]] 36 // 37 int32x4_t test_vcx1qa_2(int32x4_t acc) { 38 return __arm_vcx1qa(0, acc, 1113); 39 } 40 41 // CHECK-LABEL: @test_vcx2q_u8( 42 // CHECK-NEXT: entry: 43 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[N:%.*]] to <16 x i8> 44 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> [[TMP0]], i32 111) 45 // CHECK-NEXT: ret <16 x i8> [[TMP1]] 46 // 47 uint8x16_t test_vcx2q_u8(float16x8_t n) { 48 return __arm_vcx2q_u8(1, n, 111); 49 } 50 51 // CHECK-LABEL: @test_vcx2q( 52 // CHECK-NEXT: entry: 53 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[N:%.*]] to <16 x i8> 54 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> [[TMP0]], i32 112) 55 // CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> 56 // CHECK-NEXT: ret <4 x float> [[TMP2]] 57 // 58 float32x4_t test_vcx2q(float32x4_t n) { 59 return __arm_vcx2q(1, n, 112); 60 } 61 62 // CHECK-LABEL: @test_vcx2qa( 63 // CHECK-NEXT: entry: 64 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[ACC:%.*]] to <16 x i8> 65 // CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[N:%.*]] to <16 x i8> 66 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx2qa(i32 0, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 113) 67 // CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float> 68 // CHECK-NEXT: ret <4 x float> [[TMP3]] 69 // 70 float32x4_t test_vcx2qa(float32x4_t acc, int64x2_t n) { 71 return __arm_vcx2qa(0, acc, n, 113); 72 } 73 74 // CHECK-LABEL: @test_vcx3q_u8( 75 // CHECK-NEXT: entry: 76 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[N:%.*]] to <16 x i8> 77 // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[M:%.*]] to <16 x i8> 78 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx3q(i32 0, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 11) 79 // CHECK-NEXT: ret <16 x i8> [[TMP2]] 80 // 81 uint8x16_t test_vcx3q_u8(uint16x8_t n, int32x4_t m) { 82 return __arm_vcx3q_u8(0, n, m, 11); 83 } 84 85 // CHECK-LABEL: @test_vcx3q( 86 // CHECK-NEXT: entry: 87 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[N:%.*]] to <16 x i8> 88 // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[M:%.*]] to <16 x i8> 89 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx3q(i32 1, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 12) 90 // CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64> 91 // CHECK-NEXT: ret <2 x i64> [[TMP3]] 92 // 93 uint64x2_t test_vcx3q(uint64x2_t n, float32x4_t m) { 94 return __arm_vcx3q(1, n, m, 12); 95 } 96 97 // CHECK-LABEL: @test_vcx3qa( 98 // CHECK-NEXT: entry: 99 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[N:%.*]] to <16 x i8> 100 // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[M:%.*]] to <16 x i8> 101 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx3qa(i32 1, <16 x i8> [[ACC:%.*]], <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 13) 102 // CHECK-NEXT: ret <16 x i8> [[TMP2]] 103 // 104 int8x16_t test_vcx3qa(int8x16_t acc, uint16x8_t n, float32x4_t m) { 105 return __arm_vcx3qa(1, acc, n, m, 13); 106 } 107 108 // CHECK-LABEL: @test_vcx1q_m( 109 // CHECK-NEXT: entry: 110 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 111 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) 112 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 0, <8 x i16> [[INACTIVE:%.*]], i32 1111, <8 x i1> [[TMP1]]) 113 // CHECK-NEXT: ret <8 x i16> [[TMP2]] 114 // 115 uint16x8_t test_vcx1q_m(uint16x8_t inactive, mve_pred16_t p) { 116 return __arm_vcx1q_m(0, inactive, 1111, p); 117 } 118 119 // CHECK-LABEL: @test_vcx1qa_m( 120 // CHECK-NEXT: entry: 121 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 122 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) 123 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 1, <16 x i8> [[ACC:%.*]], i32 1112, <16 x i1> [[TMP1]]) 124 // CHECK-NEXT: ret <16 x i8> [[TMP2]] 125 // 126 uint8x16_t test_vcx1qa_m(uint8x16_t acc, mve_pred16_t p) { 127 return __arm_vcx1qa_m(1, acc, 1112, p); 128 } 129 130 // CHECK-LABEL: @test_vcx2q_m( 131 // CHECK-NEXT: entry: 132 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[N:%.*]] to <16 x i8> 133 // CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32 134 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]]) 135 // CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 0, <4 x i32> [[INACTIVE:%.*]], <16 x i8> [[TMP0]], i32 111, <4 x i1> [[TMP2]]) 136 // CHECK-NEXT: ret <4 x i32> [[TMP3]] 137 // 138 int32x4_t test_vcx2q_m(int32x4_t inactive, float32x4_t n, mve_pred16_t p) { 139 return __arm_vcx2q_m(0, inactive, n, 111, p); 140 } 141 142 // CHECK-LABEL: @test_vcx2qa_m( 143 // CHECK-NEXT: entry: 144 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[N:%.*]] to <16 x i8> 145 // CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32 146 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]]) 147 // CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 0, <4 x float> [[ACC:%.*]], <16 x i8> [[TMP0]], i32 112, <4 x i1> [[TMP2]]) 148 // CHECK-NEXT: ret <4 x float> [[TMP3]] 149 // 150 float32x4_t test_vcx2qa_m(float32x4_t acc, float16x8_t n, mve_pred16_t p) { 151 return __arm_vcx2qa_m(0, acc, n, 112, p); 152 } 153 154 // CHECK-LABEL: @test_vcx3q_m( 155 // CHECK-NEXT: entry: 156 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[N:%.*]] to <16 x i8> 157 // CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32 158 // CHECK-NEXT: [[TMP2:%.*]] = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 [[TMP1]]) 159 // CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.arm.cde.vcx3q.predicated.v2i64.v2i1(i32 1, <2 x i64> [[INACTIVE:%.*]], <16 x i8> [[TMP0]], <16 x i8> [[M:%.*]], i32 11, <2 x i1> [[TMP2]]) 160 // CHECK-NEXT: ret <2 x i64> [[TMP3]] 161 // 162 int64x2_t test_vcx3q_m(int64x2_t inactive, float32x4_t n, int8x16_t m, mve_pred16_t p) { 163 return __arm_vcx3q_m(1, inactive, n, m, 11, p); 164 } 165 166 // CHECK-LABEL: @test_vcx3qa_m( 167 // CHECK-NEXT: entry: 168 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[N:%.*]] to <16 x i8> 169 // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[M:%.*]] to <16 x i8> 170 // CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32 171 // CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]]) 172 // CHECK-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.arm.cde.vcx3qa.predicated.v4f32.v4i1(i32 1, <4 x float> [[INACTIVE:%.*]], <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 12, <4 x i1> [[TMP3]]) 173 // CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[TMP4]] to <8 x half> 174 // CHECK-NEXT: ret <8 x half> [[TMP5]] 175 // 176 float16x8_t test_vcx3qa_m(float32x4_t inactive, float16x8_t n, uint32x4_t m, mve_pred16_t p) { 177 return __arm_vcx3qa_m(1, inactive, n, m, 12, p); 178 } 179