1 // RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=128 | FileCheck %s -D#VBITS=128 --check-prefixes=CHECK,CHECK128 2 // RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=256 | FileCheck %s -D#VBITS=256 --check-prefixes=CHECK,CHECKWIDE 3 // RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=512 | FileCheck %s -D#VBITS=512 --check-prefixes=CHECK,CHECKWIDE 4 // RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=1024 | FileCheck %s -D#VBITS=1024 --check-prefixes=CHECK,CHECKWIDE 5 // RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=2048 | FileCheck %s -D#VBITS=2048 --check-prefixes=CHECK,CHECKWIDE 6 // REQUIRES: aarch64-registered-target 7 8 // Examples taken from section "3.7.3.3 Behavior specific to SVE 9 // vectors" of the SVE ACLE (Version 00bet6) that can be found at 10 // https://developer.arm.com/documentation/100987/latest 11 // 12 // Example has been expanded to work with mutiple values of 13 // -msve-vector-bits. 14 15 #include <arm_sve.h> 16 17 // Page 26, first paragraph of 3.7.3.3: sizeof and alignof 18 #if __ARM_FEATURE_SVE_BITS 19 #define N __ARM_FEATURE_SVE_BITS 20 typedef svfloat32_t fixed_svfloat __attribute__((arm_sve_vector_bits(N))); 21 void test01() { 22 static_assert(alignof(fixed_svfloat) == 16, 23 "Invalid align of Vector Length Specific Type."); 24 static_assert(sizeof(fixed_svfloat) == N / 8, 25 "Invalid size of Vector Length Specific Type."); 26 } 27 #endif 28 29 // Page 26, items 1 and 2 of 3.7.3.3: how VLST and GNUT are related. 30 #if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS 31 #define N __ARM_FEATURE_SVE_BITS 32 typedef svfloat64_t fixed_svfloat64 __attribute__((arm_sve_vector_bits(N))); 33 typedef float64_t gnufloat64 __attribute__((vector_size(N / 8))); 34 void test02() { 35 static_assert(alignof(fixed_svfloat64) == alignof(gnufloat64), 36 "Align of Vector Length Specific Type and GNU Vector Types " 37 "should be the same."); 38 static_assert(sizeof(fixed_svfloat64) == sizeof(gnufloat64), 39 "Size of Vector Length Specific Type and GNU Vector Types " 40 "should be the same."); 41 } 42 #endif 43 44 // Page 27, item 1. 45 #if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS 46 #define N __ARM_FEATURE_SVE_BITS 47 // CHECK-LABEL: define{{.*}} <vscale x 4 x i32> @_Z1f9__SVE_VLSIu11__SVInt32_tLj 48 // CHECK-SAME: [[#VBITS]] 49 // CHECK-SAME: EES_(<vscale x 4 x i32> %x.coerce, <vscale x 4 x i32> %y.coerce) 50 // CHECK-NEXT: entry: 51 // CHECK-NEXT: [[X:%.*]] = call <[[#div(VBITS, 32)]] x i32> @llvm.experimental.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32(<vscale x 4 x i32> [[X_COERCE:%.*]], i64 0) 52 // CHECK-NEXT: [[Y:%.*]] = call <[[#div(VBITS, 32)]] x i32> @llvm.experimental.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32(<vscale x 4 x i32> [[X_COERCE1:%.*]], i64 0) 53 // CHECK-NEXT: [[ADD:%.*]] = add <[[#div(VBITS, 32)]] x i32> [[Y]], [[X]] 54 // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v[[#div(VBITS, 32)]]i32(<vscale x 4 x i32> undef, <[[#div(VBITS, 32)]] x i32> [[ADD]], i64 0) 55 // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] 56 typedef svint32_t vec __attribute__((arm_sve_vector_bits(N))); 57 auto f(vec x, vec y) { return x + y; } // Returns a vec. 58 #endif 59 60 // Page 27, item 3, adapted for a generic value of __ARM_FEATURE_SVE_BITS 61 #if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS 62 #define N __ARM_FEATURE_SVE_BITS 63 typedef int16_t vec1 __attribute__((vector_size(N / 8))); 64 void f(vec1); 65 typedef svint16_t vec2 __attribute__((arm_sve_vector_bits(N))); 66 // CHECK-LABEL: define{{.*}} void @_Z1g9__SVE_VLSIu11__SVInt16_tLj 67 // CHECK-SAME: [[#VBITS]] 68 // CHECK-SAME: EE(<vscale x 8 x i16> %x.coerce) 69 // CHECK-NEXT: entry: 70 // CHECK128-NEXT: [[X:%.*]] = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> [[X_COERCE:%.*]], i64 0) 71 // CHECK128-NEXT: call void @_Z1fDv8_s(<8 x i16> [[X]]) [[ATTR5:#.*]] 72 // CHECK128-NEXT: ret void 73 // CHECKWIDE-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca <[[#div(VBITS, 16)]] x i16>, align 16 74 // CHECKWIDE-NEXT: [[X:%.*]] = call <[[#div(VBITS, 16)]] x i16> @llvm.experimental.vector.extract.v[[#div(VBITS, 16)]]i16.nxv8i16(<vscale x 8 x i16> [[X_COERCE:%.*]], i64 0) 75 // CHECKWIDE-NEXT: store <[[#div(VBITS, 16)]] x i16> [[X]], <[[#div(VBITS, 16)]] x i16>* [[INDIRECT_ARG_TEMP]], align 16, [[TBAA6:!tbaa !.*]] 76 // CHECKWIDE-NEXT: call void @_Z1fDv[[#div(VBITS, 16)]]_s(<[[#div(VBITS, 16)]] x i16>* nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]] 77 // CHECKWIDE-NEXT: ret void 78 void g(vec2 x) { f(x); } // OK 79 #endif 80