1 // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
2 // RUN:  -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg \
3 // RUN:  | FileCheck %s
4 
5 // Test new aarch64 intrinsics with poly64
6 
7 #include <arm_neon.h>
8 
9 // CHECK-LABEL: define <1 x i64> @test_vceq_p64(<1 x i64> %a, <1 x i64> %b) #0 {
10 // CHECK:   [[CMP_I:%.*]] = icmp eq <1 x i64> %a, %b
11 // CHECK:   [[SEXT_I:%.*]] = sext <1 x i1> [[CMP_I]] to <1 x i64>
12 // CHECK:   ret <1 x i64> [[SEXT_I]]
13 uint64x1_t test_vceq_p64(poly64x1_t a, poly64x1_t b) {
14   return vceq_p64(a, b);
15 }
16 
17 // CHECK-LABEL: define <2 x i64> @test_vceqq_p64(<2 x i64> %a, <2 x i64> %b) #1 {
18 // CHECK:   [[CMP_I:%.*]] = icmp eq <2 x i64> %a, %b
19 // CHECK:   [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i64>
20 // CHECK:   ret <2 x i64> [[SEXT_I]]
21 uint64x2_t test_vceqq_p64(poly64x2_t a, poly64x2_t b) {
22   return vceqq_p64(a, b);
23 }
24 
25 // CHECK-LABEL: define <1 x i64> @test_vtst_p64(<1 x i64> %a, <1 x i64> %b) #0 {
26 // CHECK:   [[TMP4:%.*]] = and <1 x i64> %a, %b
27 // CHECK:   [[TMP5:%.*]] = icmp ne <1 x i64> [[TMP4]], zeroinitializer
28 // CHECK:   [[VTST_I:%.*]] = sext <1 x i1> [[TMP5]] to <1 x i64>
29 // CHECK:   ret <1 x i64> [[VTST_I]]
30 uint64x1_t test_vtst_p64(poly64x1_t a, poly64x1_t b) {
31   return vtst_p64(a, b);
32 }
33 
34 // CHECK-LABEL: define <2 x i64> @test_vtstq_p64(<2 x i64> %a, <2 x i64> %b) #1 {
35 // CHECK:   [[TMP4:%.*]] = and <2 x i64> %a, %b
36 // CHECK:   [[TMP5:%.*]] = icmp ne <2 x i64> [[TMP4]], zeroinitializer
37 // CHECK:   [[VTST_I:%.*]] = sext <2 x i1> [[TMP5]] to <2 x i64>
38 // CHECK:   ret <2 x i64> [[VTST_I]]
39 uint64x2_t test_vtstq_p64(poly64x2_t a, poly64x2_t b) {
40   return vtstq_p64(a, b);
41 }
42 
43 // CHECK-LABEL: define <1 x i64> @test_vbsl_p64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) #0 {
44 // CHECK:   [[VBSL3_I:%.*]] = and <1 x i64> %a, %b
45 // CHECK:   [[TMP3:%.*]] = xor <1 x i64> %a, <i64 -1>
46 // CHECK:   [[VBSL4_I:%.*]] = and <1 x i64> [[TMP3]], %c
47 // CHECK:   [[VBSL5_I:%.*]] = or <1 x i64> [[VBSL3_I]], [[VBSL4_I]]
48 // CHECK:   ret <1 x i64> [[VBSL5_I]]
49 poly64x1_t test_vbsl_p64(poly64x1_t a, poly64x1_t b, poly64x1_t c) {
50   return vbsl_p64(a, b, c);
51 }
52 
53 // CHECK-LABEL: define <2 x i64> @test_vbslq_p64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) #1 {
54 // CHECK:   [[VBSL3_I:%.*]] = and <2 x i64> %a, %b
55 // CHECK:   [[TMP3:%.*]] = xor <2 x i64> %a, <i64 -1, i64 -1>
56 // CHECK:   [[VBSL4_I:%.*]] = and <2 x i64> [[TMP3]], %c
57 // CHECK:   [[VBSL5_I:%.*]] = or <2 x i64> [[VBSL3_I]], [[VBSL4_I]]
58 // CHECK:   ret <2 x i64> [[VBSL5_I]]
59 poly64x2_t test_vbslq_p64(poly64x2_t a, poly64x2_t b, poly64x2_t c) {
60   return vbslq_p64(a, b, c);
61 }
62 
63 // CHECK-LABEL: define i64 @test_vget_lane_p64(<1 x i64> %v) #0 {
64 // CHECK:   [[VGET_LANE:%.*]] = extractelement <1 x i64> %v, i32 0
65 // CHECK:   ret i64 [[VGET_LANE]]
66 poly64_t test_vget_lane_p64(poly64x1_t v) {
67   return vget_lane_p64(v, 0);
68 }
69 
70 // CHECK-LABEL: define i64 @test_vgetq_lane_p64(<2 x i64> %v) #1 {
71 // CHECK:   [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %v, i32 1
72 // CHECK:   ret i64 [[VGETQ_LANE]]
73 poly64_t test_vgetq_lane_p64(poly64x2_t v) {
74   return vgetq_lane_p64(v, 1);
75 }
76 
77 // CHECK-LABEL: define <1 x i64> @test_vset_lane_p64(i64 %a, <1 x i64> %v) #0 {
78 // CHECK:   [[VSET_LANE:%.*]] = insertelement <1 x i64> %v, i64 %a, i32 0
79 // CHECK:   ret <1 x i64> [[VSET_LANE]]
80 poly64x1_t test_vset_lane_p64(poly64_t a, poly64x1_t v) {
81   return vset_lane_p64(a, v, 0);
82 }
83 
84 // CHECK-LABEL: define <2 x i64> @test_vsetq_lane_p64(i64 %a, <2 x i64> %v) #1 {
85 // CHECK:   [[VSET_LANE:%.*]] = insertelement <2 x i64> %v, i64 %a, i32 1
86 // CHECK:   ret <2 x i64> [[VSET_LANE]]
87 poly64x2_t test_vsetq_lane_p64(poly64_t a, poly64x2_t v) {
88   return vsetq_lane_p64(a, v, 1);
89 }
90 
91 // CHECK-LABEL: define <1 x i64> @test_vcopy_lane_p64(<1 x i64> %a, <1 x i64> %b) #0 {
92 // CHECK:   [[VGET_LANE:%.*]] = extractelement <1 x i64> %b, i32 0
93 // CHECK:   [[VSET_LANE:%.*]] = insertelement <1 x i64> %a, i64 [[VGET_LANE]], i32 0
94 // CHECK:   ret <1 x i64> [[VSET_LANE]]
95 poly64x1_t test_vcopy_lane_p64(poly64x1_t a, poly64x1_t b) {
96   return vcopy_lane_p64(a, 0, b, 0);
97 
98 }
99 
100 // CHECK-LABEL: define <2 x i64> @test_vcopyq_lane_p64(<2 x i64> %a, <1 x i64> %b) #1 {
101 // CHECK:   [[VGET_LANE:%.*]] = extractelement <1 x i64> %b, i32 0
102 // CHECK:   [[VSET_LANE:%.*]] = insertelement <2 x i64> %a, i64 [[VGET_LANE]], i32 1
103 // CHECK:   ret <2 x i64> [[VSET_LANE]]
104 poly64x2_t test_vcopyq_lane_p64(poly64x2_t a, poly64x1_t b) {
105   return vcopyq_lane_p64(a, 1, b, 0);
106 }
107 
108 // CHECK-LABEL: define <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> %a, <2 x i64> %b) #1 {
109 // CHECK:   [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %b, i32 1
110 // CHECK:   [[VSET_LANE:%.*]] = insertelement <2 x i64> %a, i64 [[VGETQ_LANE]], i32 1
111 // CHECK:   ret <2 x i64> [[VSET_LANE]]
112 poly64x2_t test_vcopyq_laneq_p64(poly64x2_t a, poly64x2_t b) {
113   return vcopyq_laneq_p64(a, 1, b, 1);
114 }
115 
116 // CHECK-LABEL: define <1 x i64> @test_vcreate_p64(i64 %a) #0 {
117 // CHECK:   [[TMP0:%.*]] = bitcast i64 %a to <1 x i64>
118 // CHECK:   ret <1 x i64> [[TMP0]]
119 poly64x1_t test_vcreate_p64(uint64_t a) {
120   return vcreate_p64(a);
121 }
122 
123 // CHECK-LABEL: define <1 x i64> @test_vdup_n_p64(i64 %a) #0 {
124 // CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x i64> undef, i64 %a, i32 0
125 // CHECK:   ret <1 x i64> [[VECINIT_I]]
126 poly64x1_t test_vdup_n_p64(poly64_t a) {
127   return vdup_n_p64(a);
128 }
129 // CHECK-LABEL: define <2 x i64> @test_vdupq_n_p64(i64 %a) #1 {
130 // CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x i64> undef, i64 %a, i32 0
131 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 %a, i32 1
132 // CHECK:   ret <2 x i64> [[VECINIT1_I]]
133 poly64x2_t test_vdupq_n_p64(poly64_t a) {
134   return vdupq_n_p64(a);
135 }
136 
137 // CHECK-LABEL: define <1 x i64> @test_vmov_n_p64(i64 %a) #0 {
138 // CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x i64> undef, i64 %a, i32 0
139 // CHECK:   ret <1 x i64> [[VECINIT_I]]
140 poly64x1_t test_vmov_n_p64(poly64_t a) {
141   return vmov_n_p64(a);
142 }
143 
144 // CHECK-LABEL: define <2 x i64> @test_vmovq_n_p64(i64 %a) #1 {
145 // CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x i64> undef, i64 %a, i32 0
146 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 %a, i32 1
147 // CHECK:   ret <2 x i64> [[VECINIT1_I]]
148 poly64x2_t test_vmovq_n_p64(poly64_t a) {
149   return vmovq_n_p64(a);
150 }
151 
152 // CHECK-LABEL: define <1 x i64> @test_vdup_lane_p64(<1 x i64> %vec) #0 {
153 // CHECK:   [[SHUFFLE:%.*]] = shufflevector <1 x i64> %vec, <1 x i64> %vec, <1 x i32> zeroinitializer
154 // CHECK:   ret <1 x i64> [[SHUFFLE]]
155 poly64x1_t test_vdup_lane_p64(poly64x1_t vec) {
156   return vdup_lane_p64(vec, 0);
157 }
158 
159 // CHECK-LABEL: define <2 x i64> @test_vdupq_lane_p64(<1 x i64> %vec) #1 {
160 // CHECK:   [[SHUFFLE:%.*]] = shufflevector <1 x i64> %vec, <1 x i64> %vec, <2 x i32> zeroinitializer
161 // CHECK:   ret <2 x i64> [[SHUFFLE]]
162 poly64x2_t test_vdupq_lane_p64(poly64x1_t vec) {
163   return vdupq_lane_p64(vec, 0);
164 }
165 
166 // CHECK-LABEL: define <2 x i64> @test_vdupq_laneq_p64(<2 x i64> %vec) #1 {
167 // CHECK:   [[SHUFFLE:%.*]] = shufflevector <2 x i64> %vec, <2 x i64> %vec, <2 x i32> <i32 1, i32 1>
168 // CHECK:   ret <2 x i64> [[SHUFFLE]]
169 poly64x2_t test_vdupq_laneq_p64(poly64x2_t vec) {
170   return vdupq_laneq_p64(vec, 1);
171 }
172 
173 // CHECK-LABEL: define <2 x i64> @test_vcombine_p64(<1 x i64> %low, <1 x i64> %high) #1 {
174 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <1 x i64> %low, <1 x i64> %high, <2 x i32> <i32 0, i32 1>
175 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
176 poly64x2_t test_vcombine_p64(poly64x1_t low, poly64x1_t high) {
177   return vcombine_p64(low, high);
178 }
179 
180 // CHECK-LABEL: define <1 x i64> @test_vld1_p64(i64* %ptr) #0 {
181 // CHECK:   [[TMP0:%.*]] = bitcast i64* %ptr to i8*
182 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <1 x i64>*
183 // CHECK:   [[TMP2:%.*]] = load <1 x i64>, <1 x i64>* [[TMP1]]
184 // CHECK:   ret <1 x i64> [[TMP2]]
185 poly64x1_t test_vld1_p64(poly64_t const * ptr) {
186   return vld1_p64(ptr);
187 }
188 
189 // CHECK-LABEL: define <2 x i64> @test_vld1q_p64(i64* %ptr) #1 {
190 // CHECK:   [[TMP0:%.*]] = bitcast i64* %ptr to i8*
191 // CHECK:   [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
192 // CHECK:   [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]]
193 // CHECK:   ret <2 x i64> [[TMP2]]
194 poly64x2_t test_vld1q_p64(poly64_t const * ptr) {
195   return vld1q_p64(ptr);
196 }
197 
198 // CHECK-LABEL: define void @test_vst1_p64(i64* %ptr, <1 x i64> %val) #0 {
199 // CHECK:   [[TMP0:%.*]] = bitcast i64* %ptr to i8*
200 // CHECK:   [[TMP1:%.*]] = bitcast <1 x i64> %val to <8 x i8>
201 // CHECK:   [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <1 x i64>*
202 // CHECK:   [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
203 // CHECK:   store <1 x i64> [[TMP3]], <1 x i64>* [[TMP2]]
204 // CHECK:   ret void
205 void test_vst1_p64(poly64_t * ptr, poly64x1_t val) {
206   return vst1_p64(ptr, val);
207 }
208 
209 // CHECK-LABEL: define void @test_vst1q_p64(i64* %ptr, <2 x i64> %val) #1 {
210 // CHECK:   [[TMP0:%.*]] = bitcast i64* %ptr to i8*
211 // CHECK:   [[TMP1:%.*]] = bitcast <2 x i64> %val to <16 x i8>
212 // CHECK:   [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
213 // CHECK:   [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
214 // CHECK:   store <2 x i64> [[TMP3]], <2 x i64>* [[TMP2]]
215 // CHECK:   ret void
216 void test_vst1q_p64(poly64_t * ptr, poly64x2_t val) {
217   return vst1q_p64(ptr, val);
218 }
219 
220 // CHECK-LABEL: define %struct.poly64x1x2_t @test_vld2_p64(i64* %ptr) #2 {
221 // CHECK:   [[RETVAL:%.*]] = alloca %struct.poly64x1x2_t, align 8
222 // CHECK:   [[__RET:%.*]] = alloca %struct.poly64x1x2_t, align 8
223 // CHECK:   [[TMP0:%.*]] = bitcast %struct.poly64x1x2_t* [[__RET]] to i8*
224 // CHECK:   [[TMP1:%.*]] = bitcast i64* %ptr to i8*
225 // CHECK:   [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <1 x i64>*
226 // CHECK:   [[VLD2:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2.v1i64.p0v1i64(<1 x i64>* [[TMP2]])
227 // CHECK:   [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <1 x i64>, <1 x i64> }*
228 // CHECK:   store { <1 x i64>, <1 x i64> } [[VLD2]], { <1 x i64>, <1 x i64> }* [[TMP3]]
229 // CHECK:   [[TMP4:%.*]] = bitcast %struct.poly64x1x2_t* [[RETVAL]] to i8*
230 // CHECK:   [[TMP5:%.*]] = bitcast %struct.poly64x1x2_t* [[__RET]] to i8*
231 // CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP4]], i8* align 8 [[TMP5]], i64 16, i1 false)
232 // CHECK:   [[TMP6:%.*]] = load %struct.poly64x1x2_t, %struct.poly64x1x2_t* [[RETVAL]], align 8
233 // CHECK:   ret %struct.poly64x1x2_t [[TMP6]]
234 poly64x1x2_t test_vld2_p64(poly64_t const * ptr) {
235   return vld2_p64(ptr);
236 }
237 
238 // CHECK-LABEL: define %struct.poly64x2x2_t @test_vld2q_p64(i64* %ptr) #2 {
239 // CHECK:   [[RETVAL:%.*]] = alloca %struct.poly64x2x2_t, align 16
240 // CHECK:   [[__RET:%.*]] = alloca %struct.poly64x2x2_t, align 16
241 // CHECK:   [[TMP0:%.*]] = bitcast %struct.poly64x2x2_t* [[__RET]] to i8*
242 // CHECK:   [[TMP1:%.*]] = bitcast i64* %ptr to i8*
243 // CHECK:   [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <2 x i64>*
244 // CHECK:   [[VLD2:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2.v2i64.p0v2i64(<2 x i64>* [[TMP2]])
245 // CHECK:   [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <2 x i64>, <2 x i64> }*
246 // CHECK:   store { <2 x i64>, <2 x i64> } [[VLD2]], { <2 x i64>, <2 x i64> }* [[TMP3]]
247 // CHECK:   [[TMP4:%.*]] = bitcast %struct.poly64x2x2_t* [[RETVAL]] to i8*
248 // CHECK:   [[TMP5:%.*]] = bitcast %struct.poly64x2x2_t* [[__RET]] to i8*
249 // CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP4]], i8* align 16 [[TMP5]], i64 32, i1 false)
250 // CHECK:   [[TMP6:%.*]] = load %struct.poly64x2x2_t, %struct.poly64x2x2_t* [[RETVAL]], align 16
251 // CHECK:   ret %struct.poly64x2x2_t [[TMP6]]
252 poly64x2x2_t test_vld2q_p64(poly64_t const * ptr) {
253   return vld2q_p64(ptr);
254 }
255 
256 // CHECK-LABEL: define %struct.poly64x1x3_t @test_vld3_p64(i64* %ptr) #2 {
257 // CHECK:   [[RETVAL:%.*]] = alloca %struct.poly64x1x3_t, align 8
258 // CHECK:   [[__RET:%.*]] = alloca %struct.poly64x1x3_t, align 8
259 // CHECK:   [[TMP0:%.*]] = bitcast %struct.poly64x1x3_t* [[__RET]] to i8*
260 // CHECK:   [[TMP1:%.*]] = bitcast i64* %ptr to i8*
261 // CHECK:   [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <1 x i64>*
262 // CHECK:   [[VLD3:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3.v1i64.p0v1i64(<1 x i64>* [[TMP2]])
263 // CHECK:   [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <1 x i64>, <1 x i64>, <1 x i64> }*
264 // CHECK:   store { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD3]], { <1 x i64>, <1 x i64>, <1 x i64> }* [[TMP3]]
265 // CHECK:   [[TMP4:%.*]] = bitcast %struct.poly64x1x3_t* [[RETVAL]] to i8*
266 // CHECK:   [[TMP5:%.*]] = bitcast %struct.poly64x1x3_t* [[__RET]] to i8*
267 // CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP4]], i8* align 8 [[TMP5]], i64 24, i1 false)
268 // CHECK:   [[TMP6:%.*]] = load %struct.poly64x1x3_t, %struct.poly64x1x3_t* [[RETVAL]], align 8
269 // CHECK:   ret %struct.poly64x1x3_t [[TMP6]]
270 poly64x1x3_t test_vld3_p64(poly64_t const * ptr) {
271   return vld3_p64(ptr);
272 }
273 
274 // CHECK-LABEL: define %struct.poly64x2x3_t @test_vld3q_p64(i64* %ptr) #2 {
275 // CHECK:   [[RETVAL:%.*]] = alloca %struct.poly64x2x3_t, align 16
276 // CHECK:   [[__RET:%.*]] = alloca %struct.poly64x2x3_t, align 16
277 // CHECK:   [[TMP0:%.*]] = bitcast %struct.poly64x2x3_t* [[__RET]] to i8*
278 // CHECK:   [[TMP1:%.*]] = bitcast i64* %ptr to i8*
279 // CHECK:   [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <2 x i64>*
280 // CHECK:   [[VLD3:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3.v2i64.p0v2i64(<2 x i64>* [[TMP2]])
281 // CHECK:   [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <2 x i64>, <2 x i64>, <2 x i64> }*
282 // CHECK:   store { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD3]], { <2 x i64>, <2 x i64>, <2 x i64> }* [[TMP3]]
283 // CHECK:   [[TMP4:%.*]] = bitcast %struct.poly64x2x3_t* [[RETVAL]] to i8*
284 // CHECK:   [[TMP5:%.*]] = bitcast %struct.poly64x2x3_t* [[__RET]] to i8*
285 // CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP4]], i8* align 16 [[TMP5]], i64 48, i1 false)
286 // CHECK:   [[TMP6:%.*]] = load %struct.poly64x2x3_t, %struct.poly64x2x3_t* [[RETVAL]], align 16
287 // CHECK:   ret %struct.poly64x2x3_t [[TMP6]]
288 poly64x2x3_t test_vld3q_p64(poly64_t const * ptr) {
289   return vld3q_p64(ptr);
290 }
291 
292 // CHECK-LABEL: define %struct.poly64x1x4_t @test_vld4_p64(i64* %ptr) #2 {
293 // CHECK:   [[RETVAL:%.*]] = alloca %struct.poly64x1x4_t, align 8
294 // CHECK:   [[__RET:%.*]] = alloca %struct.poly64x1x4_t, align 8
295 // CHECK:   [[TMP0:%.*]] = bitcast %struct.poly64x1x4_t* [[__RET]] to i8*
296 // CHECK:   [[TMP1:%.*]] = bitcast i64* %ptr to i8*
297 // CHECK:   [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <1 x i64>*
298 // CHECK:   [[VLD4:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4.v1i64.p0v1i64(<1 x i64>* [[TMP2]])
299 // CHECK:   [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> }*
300 // CHECK:   store { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD4]], { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> }* [[TMP3]]
301 // CHECK:   [[TMP4:%.*]] = bitcast %struct.poly64x1x4_t* [[RETVAL]] to i8*
302 // CHECK:   [[TMP5:%.*]] = bitcast %struct.poly64x1x4_t* [[__RET]] to i8*
303 // CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP4]], i8* align 8 [[TMP5]], i64 32, i1 false)
304 // CHECK:   [[TMP6:%.*]] = load %struct.poly64x1x4_t, %struct.poly64x1x4_t* [[RETVAL]], align 8
305 // CHECK:   ret %struct.poly64x1x4_t [[TMP6]]
306 poly64x1x4_t test_vld4_p64(poly64_t const * ptr) {
307   return vld4_p64(ptr);
308 }
309 
310 // CHECK-LABEL: define %struct.poly64x2x4_t @test_vld4q_p64(i64* %ptr) #2 {
311 // CHECK:   [[RETVAL:%.*]] = alloca %struct.poly64x2x4_t, align 16
312 // CHECK:   [[__RET:%.*]] = alloca %struct.poly64x2x4_t, align 16
313 // CHECK:   [[TMP0:%.*]] = bitcast %struct.poly64x2x4_t* [[__RET]] to i8*
314 // CHECK:   [[TMP1:%.*]] = bitcast i64* %ptr to i8*
315 // CHECK:   [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <2 x i64>*
316 // CHECK:   [[VLD4:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0v2i64(<2 x i64>* [[TMP2]])
317 // CHECK:   [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> }*
318 // CHECK:   store { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD4]], { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> }* [[TMP3]]
319 // CHECK:   [[TMP4:%.*]] = bitcast %struct.poly64x2x4_t* [[RETVAL]] to i8*
320 // CHECK:   [[TMP5:%.*]] = bitcast %struct.poly64x2x4_t* [[__RET]] to i8*
321 // CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP4]], i8* align 16 [[TMP5]], i64 64, i1 false)
322 // CHECK:   [[TMP6:%.*]] = load %struct.poly64x2x4_t, %struct.poly64x2x4_t* [[RETVAL]], align 16
323 // CHECK:   ret %struct.poly64x2x4_t [[TMP6]]
324 poly64x2x4_t test_vld4q_p64(poly64_t const * ptr) {
325   return vld4q_p64(ptr);
326 }
327 
328 // CHECK-LABEL: define void @test_vst2_p64(i64* %ptr, [2 x <1 x i64>] %val.coerce) #2 {
329 // CHECK:   [[VAL:%.*]] = alloca %struct.poly64x1x2_t, align 8
330 // CHECK:   [[__S1:%.*]] = alloca %struct.poly64x1x2_t, align 8
331 // CHECK:   [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x2_t, %struct.poly64x1x2_t* [[VAL]], i32 0, i32 0
332 // CHECK:   store [2 x <1 x i64>] [[VAL]].coerce, [2 x <1 x i64>]* [[COERCE_DIVE]], align 8
333 // CHECK:   [[TMP0:%.*]] = bitcast %struct.poly64x1x2_t* [[__S1]] to i8*
334 // CHECK:   [[TMP1:%.*]] = bitcast %struct.poly64x1x2_t* [[VAL]] to i8*
335 // CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP0]], i8* align 8 [[TMP1]], i64 16, i1 false)
336 // CHECK:   [[TMP2:%.*]] = bitcast i64* %ptr to i8*
337 // CHECK:   [[VAL1:%.*]] = getelementptr inbounds %struct.poly64x1x2_t, %struct.poly64x1x2_t* [[__S1]], i32 0, i32 0
338 // CHECK:   [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x <1 x i64>], [2 x <1 x i64>]* [[VAL1]], i64 0, i64 0
339 // CHECK:   [[TMP3:%.*]] = load <1 x i64>, <1 x i64>* [[ARRAYIDX]], align 8
340 // CHECK:   [[TMP4:%.*]] = bitcast <1 x i64> [[TMP3]] to <8 x i8>
341 // CHECK:   [[VAL2:%.*]] = getelementptr inbounds %struct.poly64x1x2_t, %struct.poly64x1x2_t* [[__S1]], i32 0, i32 0
342 // CHECK:   [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x <1 x i64>], [2 x <1 x i64>]* [[VAL2]], i64 0, i64 1
343 // CHECK:   [[TMP5:%.*]] = load <1 x i64>, <1 x i64>* [[ARRAYIDX3]], align 8
344 // CHECK:   [[TMP6:%.*]] = bitcast <1 x i64> [[TMP5]] to <8 x i8>
345 // CHECK:   [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x i64>
346 // CHECK:   [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <1 x i64>
347 // CHECK:   call void @llvm.aarch64.neon.st2.v1i64.p0i8(<1 x i64> [[TMP7]], <1 x i64> [[TMP8]], i8* [[TMP2]])
348 // CHECK:   ret void
349 void test_vst2_p64(poly64_t * ptr, poly64x1x2_t val) {
350   return vst2_p64(ptr, val);
351 }
352 
353 // CHECK-LABEL: define void @test_vst2q_p64(i64* %ptr, [2 x <2 x i64>] %val.coerce) #2 {
354 // CHECK:   [[VAL:%.*]] = alloca %struct.poly64x2x2_t, align 16
355 // CHECK:   [[__S1:%.*]] = alloca %struct.poly64x2x2_t, align 16
356 // CHECK:   [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x2_t, %struct.poly64x2x2_t* [[VAL]], i32 0, i32 0
357 // CHECK:   store [2 x <2 x i64>] [[VAL]].coerce, [2 x <2 x i64>]* [[COERCE_DIVE]], align 16
358 // CHECK:   [[TMP0:%.*]] = bitcast %struct.poly64x2x2_t* [[__S1]] to i8*
359 // CHECK:   [[TMP1:%.*]] = bitcast %struct.poly64x2x2_t* [[VAL]] to i8*
360 // CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP0]], i8* align 16 [[TMP1]], i64 32, i1 false)
361 // CHECK:   [[TMP2:%.*]] = bitcast i64* %ptr to i8*
362 // CHECK:   [[VAL1:%.*]] = getelementptr inbounds %struct.poly64x2x2_t, %struct.poly64x2x2_t* [[__S1]], i32 0, i32 0
363 // CHECK:   [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>]* [[VAL1]], i64 0, i64 0
364 // CHECK:   [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* [[ARRAYIDX]], align 16
365 // CHECK:   [[TMP4:%.*]] = bitcast <2 x i64> [[TMP3]] to <16 x i8>
366 // CHECK:   [[VAL2:%.*]] = getelementptr inbounds %struct.poly64x2x2_t, %struct.poly64x2x2_t* [[__S1]], i32 0, i32 0
367 // CHECK:   [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>]* [[VAL2]], i64 0, i64 1
368 // CHECK:   [[TMP5:%.*]] = load <2 x i64>, <2 x i64>* [[ARRAYIDX3]], align 16
369 // CHECK:   [[TMP6:%.*]] = bitcast <2 x i64> [[TMP5]] to <16 x i8>
370 // CHECK:   [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x i64>
371 // CHECK:   [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <2 x i64>
372 // CHECK:   call void @llvm.aarch64.neon.st2.v2i64.p0i8(<2 x i64> [[TMP7]], <2 x i64> [[TMP8]], i8* [[TMP2]])
373 // CHECK:   ret void
374 void test_vst2q_p64(poly64_t * ptr, poly64x2x2_t val) {
375   return vst2q_p64(ptr, val);
376 }
377 
378 // CHECK-LABEL: define void @test_vst3_p64(i64* %ptr, [3 x <1 x i64>] %val.coerce) #2 {
379 // CHECK:   [[VAL:%.*]] = alloca %struct.poly64x1x3_t, align 8
380 // CHECK:   [[__S1:%.*]] = alloca %struct.poly64x1x3_t, align 8
381 // CHECK:   [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x3_t, %struct.poly64x1x3_t* [[VAL]], i32 0, i32 0
382 // CHECK:   store [3 x <1 x i64>] [[VAL]].coerce, [3 x <1 x i64>]* [[COERCE_DIVE]], align 8
383 // CHECK:   [[TMP0:%.*]] = bitcast %struct.poly64x1x3_t* [[__S1]] to i8*
384 // CHECK:   [[TMP1:%.*]] = bitcast %struct.poly64x1x3_t* [[VAL]] to i8*
385 // CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP0]], i8* align 8 [[TMP1]], i64 24, i1 false)
386 // CHECK:   [[TMP2:%.*]] = bitcast i64* %ptr to i8*
387 // CHECK:   [[VAL1:%.*]] = getelementptr inbounds %struct.poly64x1x3_t, %struct.poly64x1x3_t* [[__S1]], i32 0, i32 0
388 // CHECK:   [[ARRAYIDX:%.*]] = getelementptr inbounds [3 x <1 x i64>], [3 x <1 x i64>]* [[VAL1]], i64 0, i64 0
389 // CHECK:   [[TMP3:%.*]] = load <1 x i64>, <1 x i64>* [[ARRAYIDX]], align 8
390 // CHECK:   [[TMP4:%.*]] = bitcast <1 x i64> [[TMP3]] to <8 x i8>
391 // CHECK:   [[VAL2:%.*]] = getelementptr inbounds %struct.poly64x1x3_t, %struct.poly64x1x3_t* [[__S1]], i32 0, i32 0
392 // CHECK:   [[ARRAYIDX3:%.*]] = getelementptr inbounds [3 x <1 x i64>], [3 x <1 x i64>]* [[VAL2]], i64 0, i64 1
393 // CHECK:   [[TMP5:%.*]] = load <1 x i64>, <1 x i64>* [[ARRAYIDX3]], align 8
394 // CHECK:   [[TMP6:%.*]] = bitcast <1 x i64> [[TMP5]] to <8 x i8>
395 // CHECK:   [[VAL4:%.*]] = getelementptr inbounds %struct.poly64x1x3_t, %struct.poly64x1x3_t* [[__S1]], i32 0, i32 0
396 // CHECK:   [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x <1 x i64>], [3 x <1 x i64>]* [[VAL4]], i64 0, i64 2
397 // CHECK:   [[TMP7:%.*]] = load <1 x i64>, <1 x i64>* [[ARRAYIDX5]], align 8
398 // CHECK:   [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <8 x i8>
399 // CHECK:   [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x i64>
400 // CHECK:   [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <1 x i64>
401 // CHECK:   [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <1 x i64>
402 // CHECK:   call void @llvm.aarch64.neon.st3.v1i64.p0i8(<1 x i64> [[TMP9]], <1 x i64> [[TMP10]], <1 x i64> [[TMP11]], i8* [[TMP2]])
403 // CHECK:   ret void
404 void test_vst3_p64(poly64_t * ptr, poly64x1x3_t val) {
405   return vst3_p64(ptr, val);
406 }
407 
408 // CHECK-LABEL: define void @test_vst3q_p64(i64* %ptr, [3 x <2 x i64>] %val.coerce) #2 {
409 // CHECK:   [[VAL:%.*]] = alloca %struct.poly64x2x3_t, align 16
410 // CHECK:   [[__S1:%.*]] = alloca %struct.poly64x2x3_t, align 16
411 // CHECK:   [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x3_t, %struct.poly64x2x3_t* [[VAL]], i32 0, i32 0
412 // CHECK:   store [3 x <2 x i64>] [[VAL]].coerce, [3 x <2 x i64>]* [[COERCE_DIVE]], align 16
413 // CHECK:   [[TMP0:%.*]] = bitcast %struct.poly64x2x3_t* [[__S1]] to i8*
414 // CHECK:   [[TMP1:%.*]] = bitcast %struct.poly64x2x3_t* [[VAL]] to i8*
415 // CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP0]], i8* align 16 [[TMP1]], i64 48, i1 false)
416 // CHECK:   [[TMP2:%.*]] = bitcast i64* %ptr to i8*
417 // CHECK:   [[VAL1:%.*]] = getelementptr inbounds %struct.poly64x2x3_t, %struct.poly64x2x3_t* [[__S1]], i32 0, i32 0
418 // CHECK:   [[ARRAYIDX:%.*]] = getelementptr inbounds [3 x <2 x i64>], [3 x <2 x i64>]* [[VAL1]], i64 0, i64 0
419 // CHECK:   [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* [[ARRAYIDX]], align 16
420 // CHECK:   [[TMP4:%.*]] = bitcast <2 x i64> [[TMP3]] to <16 x i8>
421 // CHECK:   [[VAL2:%.*]] = getelementptr inbounds %struct.poly64x2x3_t, %struct.poly64x2x3_t* [[__S1]], i32 0, i32 0
422 // CHECK:   [[ARRAYIDX3:%.*]] = getelementptr inbounds [3 x <2 x i64>], [3 x <2 x i64>]* [[VAL2]], i64 0, i64 1
423 // CHECK:   [[TMP5:%.*]] = load <2 x i64>, <2 x i64>* [[ARRAYIDX3]], align 16
424 // CHECK:   [[TMP6:%.*]] = bitcast <2 x i64> [[TMP5]] to <16 x i8>
425 // CHECK:   [[VAL4:%.*]] = getelementptr inbounds %struct.poly64x2x3_t, %struct.poly64x2x3_t* [[__S1]], i32 0, i32 0
426 // CHECK:   [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x <2 x i64>], [3 x <2 x i64>]* [[VAL4]], i64 0, i64 2
427 // CHECK:   [[TMP7:%.*]] = load <2 x i64>, <2 x i64>* [[ARRAYIDX5]], align 16
428 // CHECK:   [[TMP8:%.*]] = bitcast <2 x i64> [[TMP7]] to <16 x i8>
429 // CHECK:   [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x i64>
430 // CHECK:   [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <2 x i64>
431 // CHECK:   [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <2 x i64>
432 // CHECK:   call void @llvm.aarch64.neon.st3.v2i64.p0i8(<2 x i64> [[TMP9]], <2 x i64> [[TMP10]], <2 x i64> [[TMP11]], i8* [[TMP2]])
433 // CHECK:   ret void
434 void test_vst3q_p64(poly64_t * ptr, poly64x2x3_t val) {
435   return vst3q_p64(ptr, val);
436 }
437 
438 // CHECK-LABEL: define void @test_vst4_p64(i64* %ptr, [4 x <1 x i64>] %val.coerce) #2 {
439 // CHECK:   [[VAL:%.*]] = alloca %struct.poly64x1x4_t, align 8
440 // CHECK:   [[__S1:%.*]] = alloca %struct.poly64x1x4_t, align 8
441 // CHECK:   [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x4_t, %struct.poly64x1x4_t* [[VAL]], i32 0, i32 0
442 // CHECK:   store [4 x <1 x i64>] [[VAL]].coerce, [4 x <1 x i64>]* [[COERCE_DIVE]], align 8
443 // CHECK:   [[TMP0:%.*]] = bitcast %struct.poly64x1x4_t* [[__S1]] to i8*
444 // CHECK:   [[TMP1:%.*]] = bitcast %struct.poly64x1x4_t* [[VAL]] to i8*
445 // CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP0]], i8* align 8 [[TMP1]], i64 32, i1 false)
446 // CHECK:   [[TMP2:%.*]] = bitcast i64* %ptr to i8*
447 // CHECK:   [[VAL1:%.*]] = getelementptr inbounds %struct.poly64x1x4_t, %struct.poly64x1x4_t* [[__S1]], i32 0, i32 0
448 // CHECK:   [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x <1 x i64>], [4 x <1 x i64>]* [[VAL1]], i64 0, i64 0
449 // CHECK:   [[TMP3:%.*]] = load <1 x i64>, <1 x i64>* [[ARRAYIDX]], align 8
450 // CHECK:   [[TMP4:%.*]] = bitcast <1 x i64> [[TMP3]] to <8 x i8>
451 // CHECK:   [[VAL2:%.*]] = getelementptr inbounds %struct.poly64x1x4_t, %struct.poly64x1x4_t* [[__S1]], i32 0, i32 0
452 // CHECK:   [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x <1 x i64>], [4 x <1 x i64>]* [[VAL2]], i64 0, i64 1
453 // CHECK:   [[TMP5:%.*]] = load <1 x i64>, <1 x i64>* [[ARRAYIDX3]], align 8
454 // CHECK:   [[TMP6:%.*]] = bitcast <1 x i64> [[TMP5]] to <8 x i8>
455 // CHECK:   [[VAL4:%.*]] = getelementptr inbounds %struct.poly64x1x4_t, %struct.poly64x1x4_t* [[__S1]], i32 0, i32 0
456 // CHECK:   [[ARRAYIDX5:%.*]] = getelementptr inbounds [4 x <1 x i64>], [4 x <1 x i64>]* [[VAL4]], i64 0, i64 2
457 // CHECK:   [[TMP7:%.*]] = load <1 x i64>, <1 x i64>* [[ARRAYIDX5]], align 8
458 // CHECK:   [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <8 x i8>
459 // CHECK:   [[VAL6:%.*]] = getelementptr inbounds %struct.poly64x1x4_t, %struct.poly64x1x4_t* [[__S1]], i32 0, i32 0
460 // CHECK:   [[ARRAYIDX7:%.*]] = getelementptr inbounds [4 x <1 x i64>], [4 x <1 x i64>]* [[VAL6]], i64 0, i64 3
461 // CHECK:   [[TMP9:%.*]] = load <1 x i64>, <1 x i64>* [[ARRAYIDX7]], align 8
462 // CHECK:   [[TMP10:%.*]] = bitcast <1 x i64> [[TMP9]] to <8 x i8>
463 // CHECK:   [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x i64>
464 // CHECK:   [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <1 x i64>
465 // CHECK:   [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <1 x i64>
466 // CHECK:   [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <1 x i64>
467 // CHECK:   call void @llvm.aarch64.neon.st4.v1i64.p0i8(<1 x i64> [[TMP11]], <1 x i64> [[TMP12]], <1 x i64> [[TMP13]], <1 x i64> [[TMP14]], i8* [[TMP2]])
468 // CHECK:   ret void
469 void test_vst4_p64(poly64_t * ptr, poly64x1x4_t val) {
470   return vst4_p64(ptr, val);
471 }
472 
473 // CHECK-LABEL: define void @test_vst4q_p64(i64* %ptr, [4 x <2 x i64>] %val.coerce) #2 {
474 // CHECK:   [[VAL:%.*]] = alloca %struct.poly64x2x4_t, align 16
475 // CHECK:   [[__S1:%.*]] = alloca %struct.poly64x2x4_t, align 16
476 // CHECK:   [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x4_t, %struct.poly64x2x4_t* [[VAL]], i32 0, i32 0
477 // CHECK:   store [4 x <2 x i64>] [[VAL]].coerce, [4 x <2 x i64>]* [[COERCE_DIVE]], align 16
478 // CHECK:   [[TMP0:%.*]] = bitcast %struct.poly64x2x4_t* [[__S1]] to i8*
479 // CHECK:   [[TMP1:%.*]] = bitcast %struct.poly64x2x4_t* [[VAL]] to i8*
480 // CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP0]], i8* align 16 [[TMP1]], i64 64, i1 false)
481 // CHECK:   [[TMP2:%.*]] = bitcast i64* %ptr to i8*
482 // CHECK:   [[VAL1:%.*]] = getelementptr inbounds %struct.poly64x2x4_t, %struct.poly64x2x4_t* [[__S1]], i32 0, i32 0
483 // CHECK:   [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* [[VAL1]], i64 0, i64 0
484 // CHECK:   [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* [[ARRAYIDX]], align 16
485 // CHECK:   [[TMP4:%.*]] = bitcast <2 x i64> [[TMP3]] to <16 x i8>
486 // CHECK:   [[VAL2:%.*]] = getelementptr inbounds %struct.poly64x2x4_t, %struct.poly64x2x4_t* [[__S1]], i32 0, i32 0
487 // CHECK:   [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* [[VAL2]], i64 0, i64 1
488 // CHECK:   [[TMP5:%.*]] = load <2 x i64>, <2 x i64>* [[ARRAYIDX3]], align 16
489 // CHECK:   [[TMP6:%.*]] = bitcast <2 x i64> [[TMP5]] to <16 x i8>
490 // CHECK:   [[VAL4:%.*]] = getelementptr inbounds %struct.poly64x2x4_t, %struct.poly64x2x4_t* [[__S1]], i32 0, i32 0
491 // CHECK:   [[ARRAYIDX5:%.*]] = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* [[VAL4]], i64 0, i64 2
492 // CHECK:   [[TMP7:%.*]] = load <2 x i64>, <2 x i64>* [[ARRAYIDX5]], align 16
493 // CHECK:   [[TMP8:%.*]] = bitcast <2 x i64> [[TMP7]] to <16 x i8>
494 // CHECK:   [[VAL6:%.*]] = getelementptr inbounds %struct.poly64x2x4_t, %struct.poly64x2x4_t* [[__S1]], i32 0, i32 0
495 // CHECK:   [[ARRAYIDX7:%.*]] = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* [[VAL6]], i64 0, i64 3
496 // CHECK:   [[TMP9:%.*]] = load <2 x i64>, <2 x i64>* [[ARRAYIDX7]], align 16
497 // CHECK:   [[TMP10:%.*]] = bitcast <2 x i64> [[TMP9]] to <16 x i8>
498 // CHECK:   [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x i64>
499 // CHECK:   [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <2 x i64>
500 // CHECK:   [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <2 x i64>
501 // CHECK:   [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <2 x i64>
502 // CHECK:   call void @llvm.aarch64.neon.st4.v2i64.p0i8(<2 x i64> [[TMP11]], <2 x i64> [[TMP12]], <2 x i64> [[TMP13]], <2 x i64> [[TMP14]], i8* [[TMP2]])
503 // CHECK:   ret void
504 void test_vst4q_p64(poly64_t * ptr, poly64x2x4_t val) {
505   return vst4q_p64(ptr, val);
506 }
507 
508 // CHECK-LABEL: define <1 x i64> @test_vext_p64(<1 x i64> %a, <1 x i64> %b) #0 {
509 // CHECK:   [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
510 // CHECK:   [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
511 // CHECK:   [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
512 // CHECK:   [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
513 // CHECK:   [[VEXT:%.*]] = shufflevector <1 x i64> [[TMP2]], <1 x i64> [[TMP3]], <1 x i32> zeroinitializer
514 // CHECK:   ret <1 x i64> [[VEXT]]
515 poly64x1_t test_vext_p64(poly64x1_t a, poly64x1_t b) {
516   return vext_u64(a, b, 0);
517 
518 }
519 
520 // CHECK-LABEL: define <2 x i64> @test_vextq_p64(<2 x i64> %a, <2 x i64> %b) #1 {
521 // CHECK:   [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
522 // CHECK:   [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8>
523 // CHECK:   [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
524 // CHECK:   [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
525 // CHECK:   [[VEXT:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> [[TMP3]], <2 x i32> <i32 1, i32 2>
526 // CHECK:   ret <2 x i64> [[VEXT]]
527 poly64x2_t test_vextq_p64(poly64x2_t a, poly64x2_t b) {
528   return vextq_p64(a, b, 1);
529 }
530 
531 // CHECK-LABEL: define <2 x i64> @test_vzip1q_p64(<2 x i64> %a, <2 x i64> %b) #1 {
532 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>
533 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
534 poly64x2_t test_vzip1q_p64(poly64x2_t a, poly64x2_t b) {
535   return vzip1q_p64(a, b);
536 }
537 
538 // CHECK-LABEL: define <2 x i64> @test_vzip2q_p64(<2 x i64> %a, <2 x i64> %b) #1 {
539 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
540 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
541 poly64x2_t test_vzip2q_p64(poly64x2_t a, poly64x2_t b) {
542   return vzip2q_u64(a, b);
543 }
544 
545 // CHECK-LABEL: define <2 x i64> @test_vuzp1q_p64(<2 x i64> %a, <2 x i64> %b) #1 {
546 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>
547 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
548 poly64x2_t test_vuzp1q_p64(poly64x2_t a, poly64x2_t b) {
549   return vuzp1q_p64(a, b);
550 }
551 
552 // CHECK-LABEL: define <2 x i64> @test_vuzp2q_p64(<2 x i64> %a, <2 x i64> %b) #1 {
553 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
554 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
555 poly64x2_t test_vuzp2q_p64(poly64x2_t a, poly64x2_t b) {
556   return vuzp2q_u64(a, b);
557 }
558 
559 // CHECK-LABEL: define <2 x i64> @test_vtrn1q_p64(<2 x i64> %a, <2 x i64> %b) #1 {
560 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>
561 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
562 poly64x2_t test_vtrn1q_p64(poly64x2_t a, poly64x2_t b) {
563   return vtrn1q_p64(a, b);
564 }
565 
566 // CHECK-LABEL: define <2 x i64> @test_vtrn2q_p64(<2 x i64> %a, <2 x i64> %b) #1 {
567 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
568 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
569 poly64x2_t test_vtrn2q_p64(poly64x2_t a, poly64x2_t b) {
570   return vtrn2q_u64(a, b);
571 }
572 
573 // CHECK-LABEL: define <1 x i64> @test_vsri_n_p64(<1 x i64> %a, <1 x i64> %b) #0 {
574 // CHECK:   [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
575 // CHECK:   [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
576 // CHECK:   [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
577 // CHECK:   [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
578 // CHECK:   [[VSRI_N2:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsri.v1i64(<1 x i64> [[VSRI_N]], <1 x i64> [[VSRI_N1]], i32 33)
579 // CHECK:   ret <1 x i64> [[VSRI_N2]]
580 poly64x1_t test_vsri_n_p64(poly64x1_t a, poly64x1_t b) {
581   return vsri_n_p64(a, b, 33);
582 }
583 
584 // CHECK-LABEL: define <2 x i64> @test_vsriq_n_p64(<2 x i64> %a, <2 x i64> %b) #1 {
585 // CHECK:   [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
586 // CHECK:   [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8>
587 // CHECK:   [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
588 // CHECK:   [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
589 // CHECK:   [[VSRI_N2:%.*]] = call <2 x i64> @llvm.aarch64.neon.vsri.v2i64(<2 x i64> [[VSRI_N]], <2 x i64> [[VSRI_N1]], i32 64)
590 // CHECK:   ret <2 x i64> [[VSRI_N2]]
591 poly64x2_t test_vsriq_n_p64(poly64x2_t a, poly64x2_t b) {
592   return vsriq_n_p64(a, b, 64);
593 }
594 
595 // CHECK: attributes #0 ={{.*}}"min-legal-vector-width"="64"
596 // CHECK: attributes #1 ={{.*}}"min-legal-vector-width"="128"
597 // CHECK: attributes #2 ={{.*}}"min-legal-vector-width"="0"
598