1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 2 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | FileCheck %s 3 4 5 // CHECK-LABEL: @add1( 6 // CHECK-NEXT: entry: 7 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2 8 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 2 9 // CHECK-NEXT: store half [[A:%.*]], ptr [[A_ADDR]], align 2 10 // CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 2 11 // CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2 12 // CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2 13 // CHECK-NEXT: [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]] 14 // CHECK-NEXT: ret half [[ADD]] 15 // 16 _Float16 add1(_Float16 a, _Float16 b) { 17 return a + b; 18 } 19 20 // CHECK-LABEL: @add2( 21 // CHECK-NEXT: entry: 22 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2 23 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 2 24 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca half, align 2 25 // CHECK-NEXT: store half [[A:%.*]], ptr [[A_ADDR]], align 2 26 // CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 2 27 // CHECK-NEXT: store half [[C:%.*]], ptr [[C_ADDR]], align 2 28 // CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2 29 // CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2 30 // CHECK-NEXT: [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]] 31 // CHECK-NEXT: [[TMP2:%.*]] = load half, ptr [[C_ADDR]], align 2 32 // CHECK-NEXT: [[ADD1:%.*]] = fadd half [[ADD]], [[TMP2]] 33 // CHECK-NEXT: ret half [[ADD1]] 34 // 35 _Float16 add2(_Float16 a, _Float16 b, _Float16 c) { 36 return a + b + c; 37 } 38 39 // CHECK-LABEL: @div( 40 // CHECK-NEXT: entry: 41 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2 42 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 2 43 // CHECK-NEXT: store half [[A:%.*]], ptr [[A_ADDR]], align 2 44 // CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 2 45 // CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2 46 // CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2 47 // CHECK-NEXT: [[DIV:%.*]] = fdiv half [[TMP0]], [[TMP1]] 48 // CHECK-NEXT: ret half [[DIV]] 49 // 50 _Float16 div(_Float16 a, _Float16 b) { 51 return a / b; 52 } 53 54 // CHECK-LABEL: @mul( 55 // CHECK-NEXT: entry: 56 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2 57 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 2 58 // CHECK-NEXT: store half [[A:%.*]], ptr [[A_ADDR]], align 2 59 // CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 2 60 // CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2 61 // CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2 62 // CHECK-NEXT: [[MUL:%.*]] = fmul half [[TMP0]], [[TMP1]] 63 // CHECK-NEXT: ret half [[MUL]] 64 // 65 _Float16 mul(_Float16 a, _Float16 b) { 66 return a * b; 67 } 68 69 // CHECK-LABEL: @add_and_mul1( 70 // CHECK-NEXT: entry: 71 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2 72 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 2 73 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca half, align 2 74 // CHECK-NEXT: [[D_ADDR:%.*]] = alloca half, align 2 75 // CHECK-NEXT: store half [[A:%.*]], ptr [[A_ADDR]], align 2 76 // CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 2 77 // CHECK-NEXT: store half [[C:%.*]], ptr [[C_ADDR]], align 2 78 // CHECK-NEXT: store half [[D:%.*]], ptr [[D_ADDR]], align 2 79 // CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2 80 // CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2 81 // CHECK-NEXT: [[MUL:%.*]] = fmul half [[TMP0]], [[TMP1]] 82 // CHECK-NEXT: [[TMP2:%.*]] = load half, ptr [[C_ADDR]], align 2 83 // CHECK-NEXT: [[TMP3:%.*]] = load half, ptr [[D_ADDR]], align 2 84 // CHECK-NEXT: [[MUL1:%.*]] = fmul half [[TMP2]], [[TMP3]] 85 // CHECK-NEXT: [[ADD:%.*]] = fadd half [[MUL]], [[MUL1]] 86 // CHECK-NEXT: ret half [[ADD]] 87 // 88 _Float16 add_and_mul1(_Float16 a, _Float16 b, _Float16 c, _Float16 d) { 89 return a * b + c * d; 90 } 91 92 // CHECK-LABEL: @add_and_mul2( 93 // CHECK-NEXT: entry: 94 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2 95 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 2 96 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca half, align 2 97 // CHECK-NEXT: [[D_ADDR:%.*]] = alloca half, align 2 98 // CHECK-NEXT: store half [[A:%.*]], ptr [[A_ADDR]], align 2 99 // CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 2 100 // CHECK-NEXT: store half [[C:%.*]], ptr [[C_ADDR]], align 2 101 // CHECK-NEXT: store half [[D:%.*]], ptr [[D_ADDR]], align 2 102 // CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2 103 // CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2 104 // CHECK-NEXT: [[MUL:%.*]] = fmul half 0xH4600, [[TMP1]] 105 // CHECK-NEXT: [[SUB:%.*]] = fsub half [[TMP0]], [[MUL]] 106 // CHECK-NEXT: [[TMP2:%.*]] = load half, ptr [[C_ADDR]], align 2 107 // CHECK-NEXT: [[ADD:%.*]] = fadd half [[SUB]], [[TMP2]] 108 // CHECK-NEXT: ret half [[ADD]] 109 // 110 _Float16 add_and_mul2(_Float16 a, _Float16 b, _Float16 c, _Float16 d) { 111 return (a - 6 * b) + c; 112 } 113