1 // REQUIRES: powerpc-registered-target
2 // RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power9-vector \
3 // RUN:   -triple powerpc64-unknown-unknown -emit-llvm %s \
4 // RUN:   -flax-vector-conversions=integer \
5 // RUN:   -o - | FileCheck %s -check-prefix=CHECK-BE
6 
7 // RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power9-vector \
8 // RUN:   -triple powerpc64le-unknown-unknown -emit-llvm %s \
9 // RUN:   -flax-vector-conversions=integer \
10 // RUN:   -o - | FileCheck %s
11 
12 // RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +power9-vector \
13 // RUN:   -triple powerpc64-unknown-unknown -emit-llvm %s \
14 // RUN:   -o - | FileCheck %s -check-prefix=CHECK-BE
15 
16 #include <altivec.h>
17 
18 vector signed char vsca, vscb;
19 vector unsigned char vuca, vucb;
20 vector bool char vbca, vbcb;
21 vector signed short vssa, vssb;
22 vector unsigned short vusa, vusb;
23 vector bool short vbsa, vbsb;
24 vector signed int vsia, vsib;
25 vector unsigned int vuia, vuib;
26 vector bool int vbia, vbib;
27 vector signed long long vsla, vslb;
28 vector unsigned long long vula, vulb;
29 vector bool long long vbla, vblb;
30 vector float vfa, vfb;
31 vector double vda, vdb;
32 vector unsigned __int128 vui128a, vui128b;
33 vector signed __int128 vsi128a, vsi128b;
34 
35 float f[4] = { 23.4f, 56.7f, 89.0f, 12.3f };
36 double d[2] = { 23.4, 56.7 };
37 signed char sc[16] = { -8,  9, -10, 11, -12, 13, -14, 15,
38                         -0,  1,  -2,  3,  -4,  5,  -6,  7 };
39 unsigned char uc[16] = { 8,  9, 10, 11, 12, 13, 14, 15,
40                           0,  1,  2,  3,  4,  5,  6,  7 };
41 signed short ss[8] = { -1, 2, -3, 4, -5, 6, -7, 8 };
42 unsigned short us[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
43 signed int si[4] = { -1, 2, -3, 4 };
44 unsigned int ui[4] = { 0, 1, 2, 3 };
45 signed long sl[2] = { -1L, 2L };
46 unsigned long ul[2] = { 1L, 2L };
47 signed long long sll[2] = { 1LL, 1LL };
48 unsigned long long ull[2] = { -1LL, 1LL };
49 signed __int128 sint128[1] = { -1 };
50 unsigned __int128 uint128[1] = { 1 };
51 
52 unsigned test1(void) {
53 // CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
54 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
55 // CHECK-BE: extractelement <2 x i64>
56 // CHECK-BE: icmp eq i64 {{.*}}, 64
57 // CHECK-BE: extractelement <2 x i64>
58 // CHECK-BE: add i64 {{.*}}, 64
59 // CHECK-BE: lshr i64 {{.*}}, 3
60 // CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
61 // CHECK: @llvm.cttz.v2i64(<2 x i64>
62 // CHECK: extractelement <2 x i64>
63 // CHECK: icmp eq i64 {{.*}}, 64
64 // CHECK: extractelement <2 x i64>
65 // CHECK: add i64 {{.*}}, 64
66 // CHECK: lshr i64 {{.*}}, 3
67   return vec_first_match_index (vsca, vscb);
68 }
69 unsigned test2(void) {
70 // CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
71 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
72 // CHECK-BE: extractelement <2 x i64>
73 // CHECK-BE: icmp eq i64 {{.*}}, 64
74 // CHECK-BE: extractelement <2 x i64>
75 // CHECK-BE: add i64 {{.*}}, 64
76 // CHECK-BE: lshr i64 {{.*}}, 3
77 // CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
78 // CHECK: @llvm.cttz.v2i64(<2 x i64>
79 // CHECK: extractelement <2 x i64>
80 // CHECK: icmp eq i64 {{.*}}, 64
81 // CHECK: extractelement <2 x i64>
82 // CHECK: add i64 {{.*}}, 64
83 // CHECK: lshr i64 {{.*}}, 3
84   return vec_first_match_index (vuca, vucb);
85 }
86 unsigned test3(void) {
87 // CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
88 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
89 // CHECK-BE: extractelement <2 x i64>
90 // CHECK-BE: icmp eq i64 {{.*}}, 64
91 // CHECK-BE: extractelement <2 x i64>
92 // CHECK-BE: add i64 {{.*}}, 64
93 // CHECK-BE: lshr i64 {{.*}}, 5
94 // CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
95 // CHECK: @llvm.cttz.v2i64(<2 x i64>
96 // CHECK: extractelement <2 x i64>
97 // CHECK: icmp eq i64 {{.*}}, 64
98 // CHECK: extractelement <2 x i64>
99 // CHECK: add i64 {{.*}}, 64
100 // CHECK: lshr i64 {{.*}}, 5
101   return vec_first_match_index (vsia, vsib);
102 }
103 unsigned test4(void) {
104 // CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
105 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
106 // CHECK-BE: extractelement <2 x i64>
107 // CHECK-BE: icmp eq i64 {{.*}}, 64
108 // CHECK-BE: extractelement <2 x i64>
109 // CHECK-BE: add i64 {{.*}}, 64
110 // CHECK-BE: lshr i64 {{.*}}, 5
111 // CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
112 // CHECK: @llvm.cttz.v2i64(<2 x i64>
113 // CHECK: extractelement <2 x i64>
114 // CHECK: icmp eq i64 {{.*}}, 64
115 // CHECK: extractelement <2 x i64>
116 // CHECK: add i64 {{.*}}, 64
117 // CHECK: lshr i64 {{.*}}, 5
118   return vec_first_match_index (vuia, vuib);
119 }
120 unsigned test5(void) {
121 // CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
122 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
123 // CHECK-BE: extractelement <2 x i64>
124 // CHECK-BE: icmp eq i64 {{.*}}, 64
125 // CHECK-BE: extractelement <2 x i64>
126 // CHECK-BE: add i64 {{.*}}, 64
127 // CHECK-BE: lshr i64 {{.*}}, 4
128 // CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
129 // CHECK: @llvm.cttz.v2i64(<2 x i64>
130 // CHECK: extractelement <2 x i64>
131 // CHECK: icmp eq i64 {{.*}}, 64
132 // CHECK: extractelement <2 x i64>
133 // CHECK: add i64 {{.*}}, 64
134 // CHECK: lshr i64 {{.*}}, 4
135   return vec_first_match_index (vssa, vssb);
136 }
137 unsigned test6(void) {
138 // CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
139 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
140 // CHECK-BE: extractelement <2 x i64>
141 // CHECK-BE: icmp eq i64 {{.*}}, 64
142 // CHECK-BE: extractelement <2 x i64>
143 // CHECK-BE: add i64 {{.*}}, 64
144 // CHECK-BE: lshr i64 {{.*}}, 4
145 // CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
146 // CHECK: @llvm.cttz.v2i64(<2 x i64>
147 // CHECK: extractelement <2 x i64>
148 // CHECK: icmp eq i64 {{.*}}, 64
149 // CHECK: extractelement <2 x i64>
150 // CHECK: add i64 {{.*}}, 64
151 // CHECK: lshr i64 {{.*}}, 4
152   return vec_first_match_index (vusa, vusb);
153 }
154 unsigned test7(void) {
155 // CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
156 // CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
157 // CHECK-BE: or <16 x i8>
158 // CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
159 // CHECK-BE: or <16 x i8>
160 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
161 // CHECK-BE: extractelement <2 x i64>
162 // CHECK-BE: icmp eq i64 {{.*}}, 64
163 // CHECK-BE: extractelement <2 x i64>
164 // CHECK-BE: add i64 {{.*}}, 64
165 // CHECK-BE: lshr i64 {{.*}}, 3
166 // CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
167 // CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
168 // CHECK: or <16 x i8>
169 // CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
170 // CHECK: or <16 x i8>
171 // CHECK: @llvm.cttz.v2i64(<2 x i64>
172 // CHECK: extractelement <2 x i64>
173 // CHECK: icmp eq i64 {{.*}}, 64
174 // CHECK: extractelement <2 x i64>
175 // CHECK: add i64 {{.*}}, 64
176 // CHECK: lshr i64 {{.*}}, 3
177   return vec_first_match_or_eos_index (vsca, vscb);
178 }
179 unsigned test8(void) {
180 // CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
181 // CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
182 // CHECK-BE: or <16 x i8>
183 // CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
184 // CHECK-BE: or <16 x i8>
185 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
186 // CHECK-BE: extractelement <2 x i64>
187 // CHECK-BE: icmp eq i64 {{.*}}, 64
188 // CHECK-BE: extractelement <2 x i64>
189 // CHECK-BE: add i64 {{.*}}, 64
190 // CHECK-BE: lshr i64 {{.*}}, 3
191 // CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
192 // CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
193 // CHECK: or <16 x i8>
194 // CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
195 // CHECK: or <16 x i8>
196 // CHECK: @llvm.cttz.v2i64(<2 x i64>
197 // CHECK: extractelement <2 x i64>
198 // CHECK: icmp eq i64 {{.*}}, 64
199 // CHECK: extractelement <2 x i64>
200 // CHECK: add i64 {{.*}}, 64
201 // CHECK: lshr i64 {{.*}}, 3
202   return vec_first_match_or_eos_index (vuca, vucb);
203 }
204 unsigned test9(void) {
205 // CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
206 // CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
207 // CHECK-BE: or <4 x i32>
208 // CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
209 // CHECK-BE: or <4 x i32>
210 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
211 // CHECK-BE: extractelement <2 x i64>
212 // CHECK-BE: icmp eq i64 {{.*}}, 64
213 // CHECK-BE: extractelement <2 x i64>
214 // CHECK-BE: add i64 {{.*}}, 64
215 // CHECK-BE: lshr i64 {{.*}}, 5
216 // CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
217 // CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
218 // CHECK: or <4 x i32>
219 // CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
220 // CHECK: or <4 x i32>
221 // CHECK: @llvm.cttz.v2i64(<2 x i64>
222 // CHECK: extractelement <2 x i64>
223 // CHECK: icmp eq i64 {{.*}}, 64
224 // CHECK: extractelement <2 x i64>
225 // CHECK: add i64 {{.*}}, 64
226 // CHECK: lshr i64 {{.*}}, 5
227   return vec_first_match_or_eos_index (vsia, vsib);
228 }
229 unsigned test10(void) {
230 // CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
231 // CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
232 // CHECK-BE: or <4 x i32>
233 // CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
234 // CHECK-BE: or <4 x i32>
235 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
236 // CHECK-BE: extractelement <2 x i64>
237 // CHECK-BE: icmp eq i64 {{.*}}, 64
238 // CHECK-BE: extractelement <2 x i64>
239 // CHECK-BE: add i64 {{.*}}, 64
240 // CHECK-BE: lshr i64 {{.*}}, 5
241 // CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
242 // CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
243 // CHECK: or <4 x i32>
244 // CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
245 // CHECK: or <4 x i32>
246 // CHECK: @llvm.cttz.v2i64(<2 x i64>
247 // CHECK: extractelement <2 x i64>
248 // CHECK: icmp eq i64 {{.*}}, 64
249 // CHECK: extractelement <2 x i64>
250 // CHECK: add i64 {{.*}}, 64
251 // CHECK: lshr i64 {{.*}}, 5
252   return vec_first_match_or_eos_index (vuia, vuib);
253 }
254 unsigned test11(void) {
255 // CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
256 // CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
257 // CHECK-BE: or <8 x i16>
258 // CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
259 // CHECK-BE: or <8 x i16>
260 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
261 // CHECK-BE: extractelement <2 x i64>
262 // CHECK-BE: icmp eq i64 {{.*}}, 64
263 // CHECK-BE: extractelement <2 x i64>
264 // CHECK-BE: add i64 {{.*}}, 64
265 // CHECK-BE: lshr i64 {{.*}}, 4
266 // CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
267 // CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
268 // CHECK: or <8 x i16>
269 // CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
270 // CHECK: or <8 x i16>
271 // CHECK: @llvm.cttz.v2i64(<2 x i64>
272 // CHECK: extractelement <2 x i64>
273 // CHECK: icmp eq i64 {{.*}}, 64
274 // CHECK: extractelement <2 x i64>
275 // CHECK: add i64 {{.*}}, 64
276 // CHECK: lshr i64 {{.*}}, 4
277   return vec_first_match_or_eos_index (vssa, vssb);
278 }
279 unsigned test12(void) {
280 // CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
281 // CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
282 // CHECK-BE: or <8 x i16>
283 // CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
284 // CHECK-BE: or <8 x i16>
285 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
286 // CHECK-BE: extractelement <2 x i64>
287 // CHECK-BE: icmp eq i64 {{.*}}, 64
288 // CHECK-BE: extractelement <2 x i64>
289 // CHECK-BE: add i64 {{.*}}, 64
290 // CHECK-BE: lshr i64 {{.*}}, 4
291 // CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
292 // CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
293 // CHECK: or <8 x i16>
294 // CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
295 // CHECK: or <8 x i16>
296 // CHECK: @llvm.cttz.v2i64(<2 x i64>
297 // CHECK: extractelement <2 x i64>
298 // CHECK: icmp eq i64 {{.*}}, 64
299 // CHECK: extractelement <2 x i64>
300 // CHECK: add i64 {{.*}}, 64
301 // CHECK: lshr i64 {{.*}}, 4
302   return vec_first_match_or_eos_index (vusa, vusb);
303 }
304 unsigned test13(void) {
305 // CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>
306 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
307 // CHECK-BE: extractelement <2 x i64>
308 // CHECK-BE: icmp eq i64 {{.*}}, 64
309 // CHECK-BE: extractelement <2 x i64>
310 // CHECK-BE: add i64 {{.*}}, 64
311 // CHECK-BE: lshr i64 {{.*}}, 3
312 // CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>
313 // CHECK: @llvm.cttz.v2i64(<2 x i64>
314 // CHECK: extractelement <2 x i64>
315 // CHECK: icmp eq i64 {{.*}}, 64
316 // CHECK: extractelement <2 x i64>
317 // CHECK: add i64 {{.*}}, 64
318 // CHECK: lshr i64 {{.*}}, 3
319   return vec_first_mismatch_index (vsca, vscb);
320 }
321 unsigned test14(void) {
322 // CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>
323 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
324 // CHECK-BE: extractelement <2 x i64>
325 // CHECK-BE: icmp eq i64 {{.*}}, 64
326 // CHECK-BE: extractelement <2 x i64>
327 // CHECK-BE: add i64 {{.*}}, 64
328 // CHECK-BE: lshr i64 {{.*}}, 3
329 // CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>
330 // CHECK: @llvm.cttz.v2i64(<2 x i64>
331 // CHECK: extractelement <2 x i64>
332 // CHECK: icmp eq i64 {{.*}}, 64
333 // CHECK: extractelement <2 x i64>
334 // CHECK: add i64 {{.*}}, 64
335 // CHECK: lshr i64 {{.*}}, 3
336   return vec_first_mismatch_index (vuca, vucb);
337 }
338 unsigned test15(void) {
339 // CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>
340 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
341 // CHECK-BE: extractelement <2 x i64>
342 // CHECK-BE: icmp eq i64 {{.*}}, 64
343 // CHECK-BE: extractelement <2 x i64>
344 // CHECK-BE: add i64 {{.*}}, 64
345 // CHECK-BE: lshr i64 {{.*}}, 5
346 // CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>
347 // CHECK: @llvm.cttz.v2i64(<2 x i64>
348 // CHECK: extractelement <2 x i64>
349 // CHECK: icmp eq i64 {{.*}}, 64
350 // CHECK: extractelement <2 x i64>
351 // CHECK: add i64 {{.*}}, 64
352 // CHECK: lshr i64 {{.*}}, 5
353   return vec_first_mismatch_index (vsia, vsib);
354 }
355 unsigned test16(void) {
356 // CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>
357 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
358 // CHECK-BE: extractelement <2 x i64>
359 // CHECK-BE: icmp eq i64 {{.*}}, 64
360 // CHECK-BE: extractelement <2 x i64>
361 // CHECK-BE: add i64 {{.*}}, 64
362 // CHECK-BE: lshr i64 {{.*}}, 5
363 // CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>
364 // CHECK: @llvm.cttz.v2i64(<2 x i64>
365 // CHECK: extractelement <2 x i64>
366 // CHECK: icmp eq i64 {{.*}}, 64
367 // CHECK: extractelement <2 x i64>
368 // CHECK: add i64 {{.*}}, 64
369 // CHECK: lshr i64 {{.*}}, 5
370   return vec_first_mismatch_index (vuia, vuib);
371 }
372 unsigned test17(void) {
373 // CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>
374 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
375 // CHECK-BE: extractelement <2 x i64>
376 // CHECK-BE: icmp eq i64 {{.*}}, 64
377 // CHECK-BE: extractelement <2 x i64>
378 // CHECK-BE: add i64 {{.*}}, 64
379 // CHECK-BE: lshr i64 {{.*}}, 4
380 // CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>
381 // CHECK: @llvm.cttz.v2i64(<2 x i64>
382 // CHECK: extractelement <2 x i64>
383 // CHECK: icmp eq i64 {{.*}}, 64
384 // CHECK: extractelement <2 x i64>
385 // CHECK: add i64 {{.*}}, 64
386 // CHECK: lshr i64 {{.*}}, 4
387   return vec_first_mismatch_index (vssa, vssb);
388 }
389 unsigned test18(void) {
390 // CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>
391 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
392 // CHECK-BE: extractelement <2 x i64>
393 // CHECK-BE: icmp eq i64 {{.*}}, 64
394 // CHECK-BE: extractelement <2 x i64>
395 // CHECK-BE: add i64 {{.*}}, 64
396 // CHECK-BE: lshr i64 {{.*}}, 4
397 // CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>
398 // CHECK: @llvm.cttz.v2i64(<2 x i64>
399 // CHECK: extractelement <2 x i64>
400 // CHECK: icmp eq i64 {{.*}}, 64
401 // CHECK: extractelement <2 x i64>
402 // CHECK: add i64 {{.*}}, 64
403 // CHECK: lshr i64 {{.*}}, 4
404   return vec_first_mismatch_index (vusa, vusb);
405 }
406 unsigned test19(void) {
407 // CHECK-BE: @llvm.ppc.altivec.vcmpnezb(<16 x i8>
408 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
409 // CHECK-BE: extractelement <2 x i64>
410 // CHECK-BE: icmp eq i64 {{.*}}, 64
411 // CHECK-BE: extractelement <2 x i64>
412 // CHECK-BE: add i64 {{.*}}, 64
413 // CHECK-BE: lshr i64 {{.*}}, 3
414 // CHECK: @llvm.ppc.altivec.vcmpnezb(<16 x i8>
415 // CHECK: @llvm.cttz.v2i64(<2 x i64>
416 // CHECK: extractelement <2 x i64>
417 // CHECK: icmp eq i64 {{.*}}, 64
418 // CHECK: extractelement <2 x i64>
419 // CHECK: add i64 {{.*}}, 64
420 // CHECK: lshr i64 {{.*}}, 3
421   return vec_first_mismatch_or_eos_index (vsca, vscb);
422 }
423 unsigned test20(void) {
424 // CHECK-BE: @llvm.ppc.altivec.vcmpnezb(<16 x i8>
425 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
426 // CHECK-BE: extractelement <2 x i64>
427 // CHECK-BE: icmp eq i64 {{.*}}, 64
428 // CHECK-BE: extractelement <2 x i64>
429 // CHECK-BE: add i64 {{.*}}, 64
430 // CHECK-BE: lshr i64 {{.*}}, 3
431 // CHECK: @llvm.ppc.altivec.vcmpnezb(<16 x i8>
432 // CHECK: @llvm.cttz.v2i64(<2 x i64>
433 // CHECK: extractelement <2 x i64>
434 // CHECK: icmp eq i64 {{.*}}, 64
435 // CHECK: extractelement <2 x i64>
436 // CHECK: add i64 {{.*}}, 64
437 // CHECK: lshr i64 {{.*}}, 3
438   return vec_first_mismatch_or_eos_index (vuca, vucb);
439 }
440 unsigned test21(void) {
441 // CHECK-BE: @llvm.ppc.altivec.vcmpnezw(<4 x i32>
442 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
443 // CHECK-BE: extractelement <2 x i64>
444 // CHECK-BE: icmp eq i64 {{.*}}, 64
445 // CHECK-BE: extractelement <2 x i64>
446 // CHECK-BE: add i64 {{.*}}, 64
447 // CHECK-BE: lshr i64 {{.*}}, 5
448 // CHECK: @llvm.ppc.altivec.vcmpnezw(<4 x i32>
449 // CHECK: @llvm.cttz.v2i64(<2 x i64>
450 // CHECK: extractelement <2 x i64>
451 // CHECK: icmp eq i64 {{.*}}, 64
452 // CHECK: extractelement <2 x i64>
453 // CHECK: add i64 {{.*}}, 64
454 // CHECK: lshr i64 {{.*}}, 5
455   return vec_first_mismatch_or_eos_index (vsia, vsib);
456 }
457 unsigned test22(void) {
458 // CHECK-BE: @llvm.ppc.altivec.vcmpnezw(<4 x i32>
459 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
460 // CHECK-BE: extractelement <2 x i64>
461 // CHECK-BE: icmp eq i64 {{.*}}, 64
462 // CHECK-BE: extractelement <2 x i64>
463 // CHECK-BE: add i64 {{.*}}, 64
464 // CHECK-BE: lshr i64 {{.*}}, 5
465 // CHECK: @llvm.ppc.altivec.vcmpnezw(<4 x i32>
466 // CHECK: @llvm.cttz.v2i64(<2 x i64>
467 // CHECK: extractelement <2 x i64>
468 // CHECK: icmp eq i64 {{.*}}, 64
469 // CHECK: extractelement <2 x i64>
470 // CHECK: add i64 {{.*}}, 64
471 // CHECK: lshr i64 {{.*}}, 5
472   return vec_first_mismatch_or_eos_index (vuia, vuib);
473 }
474 unsigned test23(void) {
475 // CHECK-BE: @llvm.ppc.altivec.vcmpnezh(<8 x i16>
476 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
477 // CHECK-BE: extractelement <2 x i64>
478 // CHECK-BE: icmp eq i64 {{.*}}, 64
479 // CHECK-BE: extractelement <2 x i64>
480 // CHECK-BE: add i64 {{.*}}, 64
481 // CHECK-BE: lshr i64 {{.*}}, 4
482 // CHECK: @llvm.ppc.altivec.vcmpnezh(<8 x i16>
483 // CHECK: @llvm.cttz.v2i64(<2 x i64>
484 // CHECK: extractelement <2 x i64>
485 // CHECK: icmp eq i64 {{.*}}, 64
486 // CHECK: extractelement <2 x i64>
487 // CHECK: add i64 {{.*}}, 64
488 // CHECK: lshr i64 {{.*}}, 4
489   return vec_first_mismatch_or_eos_index (vssa, vssb);
490 }
491 unsigned test24(void) {
492 // CHECK-BE: @llvm.ppc.altivec.vcmpnezh(<8 x i16>
493 // CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
494 // CHECK-BE: extractelement <2 x i64>
495 // CHECK-BE: icmp eq i64 {{.*}}, 64
496 // CHECK-BE: extractelement <2 x i64>
497 // CHECK-BE: add i64 {{.*}}, 64
498 // CHECK-BE: lshr i64 {{.*}}, 4
499 // CHECK: @llvm.ppc.altivec.vcmpnezh(<8 x i16>
500 // CHECK: @llvm.cttz.v2i64(<2 x i64>
501 // CHECK: extractelement <2 x i64>
502 // CHECK: icmp eq i64 {{.*}}, 64
503 // CHECK: extractelement <2 x i64>
504 // CHECK: add i64 {{.*}}, 64
505 // CHECK: lshr i64 {{.*}}, 4
506   return vec_first_mismatch_or_eos_index (vusa, vusb);
507 }
508 vector bool char test25(void) {
509 // CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>
510 // CHECK-BE-NEXT: ret <16 x i8>
511 // CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>
512 // CHECK-NEXT: ret <16 x i8>
513   return vec_cmpne (vbca, vbcb);
514 }
515 vector bool char test26(void) {
516 // CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>
517 // CHECK-BE-NEXT: ret <16 x i8>
518 // CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>
519 // CHECK-NEXT: ret <16 x i8>
520   return vec_cmpne (vsca, vscb);
521 }
522 vector bool char test27(void) {
523 // CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>
524 // CHECK-BE-NEXT: ret <16 x i8>
525 // CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>
526 // CHECK-NEXT: ret <16 x i8>
527   return vec_cmpne (vuca, vucb);
528 }
529 vector bool int test28(void) {
530 // CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>
531 // CHECK-BE-NEXT: ret <4 x i32>
532 // CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>
533 // CHECK-NEXT: ret <4 x i32>
534   return vec_cmpne (vbia, vbib);
535 }
536 vector bool int test29(void) {
537 // CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>
538 // CHECK-BE-NEXT: ret <4 x i32>
539 // CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>
540 // CHECK-NEXT: ret <4 x i32>
541   return vec_cmpne (vsia, vsib);
542 }
543 vector bool int test30(void) {
544 // CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>
545 // CHECK-BE-NEXT: ret <4 x i32>
546 // CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>
547 // CHECK-NEXT: ret <4 x i32>
548   return vec_cmpne (vuia, vuib);
549 }
550 vector bool long long test31(void) {
551 // CHECK-BE: @llvm.ppc.altivec.vcmpequd(<2 x i64>
552 // CHECK-BE: xor <2 x i64>
553 // CHECK-BE-NEXT: ret <2 x i64>
554 // CHECK: @llvm.ppc.altivec.vcmpequd(<2 x i64>
555 // CHECK: xor <2 x i64>
556 // CHECK-NEXT: ret <2 x i64>
557   return vec_cmpne (vbla, vblb);
558 }
559 vector bool long long test32(void) {
560 // CHECK-BE: @llvm.ppc.altivec.vcmpequd(<2 x i64>
561 // CHECK-BE: xor <2 x i64>
562 // CHECK-BE-NEXT: ret <2 x i64>
563 // CHECK: @llvm.ppc.altivec.vcmpequd(<2 x i64>
564 // CHECK: xor <2 x i64>
565 // CHECK-NEXT: ret <2 x i64>
566   return vec_cmpne (vsla, vslb);
567 }
568 vector bool long long test33(void) {
569 // CHECK-BE: @llvm.ppc.altivec.vcmpequd(<2 x i64>
570 // CHECK-BE: xor <2 x i64>
571 // CHECK-BE-NEXT: ret <2 x i64>
572 // CHECK: @llvm.ppc.altivec.vcmpequd(<2 x i64>
573 // CHECK: xor <2 x i64>
574 // CHECK-NEXT: ret <2 x i64>
575   return vec_cmpne (vula, vulb);
576 }
577 vector bool short test34(void) {
578 // CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>
579 // CHECK-BE-NEXT: ret <8 x i16>
580 // CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>
581 // CHECK-NEXT: ret <8 x i16>
582   return vec_cmpne (vbsa, vbsb);
583 }
584 vector bool short test35(void) {
585 // CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>
586 // CHECK-BE-NEXT: ret <8 x i16>
587 // CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>
588 // CHECK-NEXT: ret <8 x i16>
589   return vec_cmpne (vssa, vssb);
590 }
591 vector bool short test36(void) {
592 // CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>
593 // CHECK-BE-NEXT: ret <8 x i16>
594 // CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>
595 // CHECK-NEXT: ret <8 x i16>
596   return vec_cmpne (vusa, vusb);
597 }
598 vector bool long long test37(void) {
599 // CHECK-BE: @llvm.ppc.altivec.vcmpequd(<2 x i64>
600 // CHECK-BE: xor <2 x i64>
601 // CHECK-BE-NEXT: ret <2 x i64>
602 // CHECK: @llvm.ppc.altivec.vcmpequd(<2 x i64>
603 // CHECK: xor <2 x i64>
604 // CHECK-NEXT: ret <2 x i64>
605   return vec_cmpne (vda, vdb);
606 }
607 vector bool int test38(void) {
608 // CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>
609 // CHECK-BE-NEXT: ret <4 x i32>
610 // CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>
611 // CHECK-NEXT: ret <4 x i32>
612   return vec_cmpne (vfa, vfb);
613 }
614 vector signed char test39(void) {
615 // CHECK-BE: @llvm.cttz.v16i8(<16 x i8>
616 // CHECK-BE-NEXT: ret <16 x i8>
617 // CHECK: @llvm.cttz.v16i8(<16 x i8>
618 // CHECK-NEXT: ret <16 x i8>
619   return vec_cnttz (vsca);
620 }
621 vector unsigned char test40(void) {
622 // CHECK-BE: @llvm.cttz.v16i8(<16 x i8>
623 // CHECK-BE-NEXT: ret <16 x i8>
624 // CHECK: @llvm.cttz.v16i8(<16 x i8>
625 // CHECK-NEXT: ret <16 x i8>
626   return vec_cnttz (vuca);
627 }
628 vector signed int test41(void) {
629 // CHECK-BE: @llvm.cttz.v4i32(<4 x i32>
630 // CHECK-BE-NEXT: ret <4 x i32>
631 // CHECK: @llvm.cttz.v4i32(<4 x i32>
632 // CHECK-NEXT: ret <4 x i32>
633   return vec_cnttz (vsia);
634 }
635 vector unsigned int test42(void) {
636 // CHECK-BE: @llvm.cttz.v4i32(<4 x i32>
637 // CHECK-BE-NEXT: ret <4 x i32>
638 // CHECK: @llvm.cttz.v4i32(<4 x i32>
639 // CHECK-NEXT: ret <4 x i32>
640   return vec_cnttz (vuia);
641 }
642 vector signed long long test43(void) {
643 // CHECK-BE: @llvm.cttz.v2i64(<2 x i64>
644 // CHECK-BE-NEXT: ret <2 x i64>
645 // CHECK: @llvm.cttz.v2i64(<2 x i64>
646 // CHECK-NEXT: ret <2 x i64>
647   return vec_cnttz (vsla);
648 }
649 vector unsigned long long test44(void) {
650 // CHECK-BE: @llvm.cttz.v2i64(<2 x i64>
651 // CHECK-BE-NEXT: ret <2 x i64>
652 // CHECK: @llvm.cttz.v2i64(<2 x i64>
653 // CHECK-NEXT: ret <2 x i64>
654   return vec_cnttz (vula);
655 }
656 vector signed short test45(void) {
657 // CHECK-BE: @llvm.cttz.v8i16(<8 x i16>
658 // CHECK-BE-NEXT: ret <8 x i16>
659 // CHECK: @llvm.cttz.v8i16(<8 x i16>
660 // CHECK-NEXT: ret <8 x i16>
661   return vec_cnttz (vssa);
662 }
663 vector unsigned short test46(void) {
664 // CHECK-BE: @llvm.cttz.v8i16(<8 x i16>
665 // CHECK-BE-NEXT: ret <8 x i16>
666 // CHECK: @llvm.cttz.v8i16(<8 x i16>
667 // CHECK-NEXT: ret <8 x i16>
668   return vec_cnttz (vusa);
669 }
670 vector unsigned char test47(void) {
671 // CHECK-BE: @llvm.ctpop.v16i8(<16 x i8>
672 // CHECK-BE-NEXT: ret <16 x i8>
673 // CHECK: @llvm.ctpop.v16i8(<16 x i8>
674 // CHECK-NEXT: ret <16 x i8>
675   return vec_popcnt (vsca);
676 }
677 vector unsigned char test48(void) {
678 // CHECK-BE: @llvm.ctpop.v16i8(<16 x i8>
679 // CHECK-BE-NEXT: ret <16 x i8>
680 // CHECK: @llvm.ctpop.v16i8(<16 x i8>
681 // CHECK-NEXT: ret <16 x i8>
682   return vec_popcnt (vuca);
683 }
684 vector unsigned int test49(void) {
685 // CHECK-BE: @llvm.ctpop.v4i32(<4 x i32>
686 // CHECK-BE-NEXT: ret <4 x i32>
687 // CHECK: @llvm.ctpop.v4i32(<4 x i32>
688 // CHECK-NEXT: ret <4 x i32>
689   return vec_popcnt (vsia);
690 }
691 vector unsigned int test50(void) {
692 // CHECK-BE: @llvm.ctpop.v4i32(<4 x i32>
693 // CHECK-BE-NEXT: ret <4 x i32>
694 // CHECK: @llvm.ctpop.v4i32(<4 x i32>
695 // CHECK-NEXT: ret <4 x i32>
696   return vec_popcnt (vuia);
697 }
698 vector unsigned long long test51(void) {
699 // CHECK-BE: @llvm.ctpop.v2i64(<2 x i64>
700 // CHECK-BE-NEXT: ret <2 x i64>
701 // CHECK: @llvm.ctpop.v2i64(<2 x i64>
702 // CHECK-NEXT: ret <2 x i64>
703   return vec_popcnt (vsla);
704 }
705 vector unsigned long long test52(void) {
706 // CHECK-BE: @llvm.ctpop.v2i64(<2 x i64>
707 // CHECK-BE-NEXT: ret <2 x i64>
708 // CHECK: @llvm.ctpop.v2i64(<2 x i64>
709 // CHECK-NEXT: ret <2 x i64>
710   return vec_popcnt (vula);
711 }
712 vector unsigned short test53(void) {
713 // CHECK-BE: @llvm.ctpop.v8i16(<8 x i16>
714 // CHECK-BE-NEXT: ret <8 x i16>
715 // CHECK: @llvm.ctpop.v8i16(<8 x i16>
716 // CHECK-NEXT: ret <8 x i16>
717   return vec_popcnt (vssa);
718 }
719 vector unsigned short test54(void) {
720 // CHECK-BE: @llvm.ctpop.v8i16(<8 x i16>
721 // CHECK-BE-NEXT: ret <8 x i16>
722 // CHECK: @llvm.ctpop.v8i16(<8 x i16>
723 // CHECK-NEXT: ret <8 x i16>
724   return vec_popcnt (vusa);
725 }
726 vector double test55(void) {
727 // CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
728 // CHECK-BE-NEXT: ret <2 x double>
729 // CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
730 // CHECK-NEXT: ret <2 x double>
731   return vec_insert_exp (vda,vulb);
732 }
733 vector double test56(void) {
734 // CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
735 // CHECK-BE-NEXT: ret <2 x double>
736 // CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
737 // CHECK-NEXT: ret <2 x double>
738   return vec_insert_exp (vula, vulb);
739 }
740 vector float test57(void) {
741 // CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
742 // CHECK-BE-NEXT: ret <4 x float>
743 // CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
744 // CHECK-NEXT: ret <4 x float>
745   return vec_insert_exp (vfa,vuib);
746 }
747 vector float test58(void) {
748 // CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
749 // CHECK-BE-NEXT: ret <4 x float>
750 // CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
751 // CHECK-NEXT: ret <4 x float>
752   return vec_insert_exp (vuia,vuib);
753 }
754 signed int test59(void) {
755 // CHECK-BE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>
756 // CHECK-BE-NEXT: ret i32
757 // CHECK-LE: @llvm.ppc.altivec.vctzlsbb(<16 x i8>
758 // CHECK-LE-NEXT: ret i32
759   return vec_cntlz_lsbb (vuca);
760 }
761 signed int test60(void) {
762 // CHECK-BE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>
763 // CHECK-BE-NEXT: ret i32
764 // CHECK-LE: @llvm.ppc.altivec.vctzlsbb(<16 x i8>
765 // CHECK-LE-NEXT: ret i32
766   return vec_cntlz_lsbb (vsca);
767 }
768 signed int test61(void) {
769 // CHECK-BE: @llvm.ppc.altivec.vctzlsbb(<16 x i8>
770 // CHECK-BE-NEXT: ret i32
771 // CHECK-LE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>
772 // CHECK-LE-NEXT: ret i32
773   return vec_cnttz_lsbb (vsca);
774 }
775 signed int test62(void) {
776 // CHECK-BE: @llvm.ppc.altivec.vctzlsbb(<16 x i8>
777 // CHECK-BE-NEXT: ret i32
778 // CHECK-LE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>
779 // CHECK-LE-NEXT: ret i32
780   return vec_cnttz_lsbb (vuca);
781 }
782 vector unsigned int test63(void) {
783 // CHECK-BE: @llvm.ppc.altivec.vprtybw(<4 x i32>
784 // CHECK-BE-NEXT: ret <4 x i32>
785 // CHECK: @llvm.ppc.altivec.vprtybw(<4 x i32>
786 // CHECK-NEXT: ret <4 x i32>
787   return vec_parity_lsbb (vuia);
788 }
789 vector unsigned int test64(void) {
790 // CHECK-BE: @llvm.ppc.altivec.vprtybw(<4 x i32>
791 // CHECK-BE-NEXT: ret <4 x i32>
792 // CHECK: @llvm.ppc.altivec.vprtybw(<4 x i32>
793 // CHECK-NEXT: ret <4 x i32>
794   return vec_parity_lsbb (vsia);
795 }
796 vector unsigned long long test65(void) {
797 // CHECK-BE: @llvm.ppc.altivec.vprtybd(<2 x i64>
798 // CHECK-BE-NEXT: ret <2 x i64>
799 // CHECK: @llvm.ppc.altivec.vprtybd(<2 x i64>
800 // CHECK-NEXT: ret <2 x i64>
801   return vec_parity_lsbb (vula);
802 }
803 vector unsigned long long test66(void) {
804 // CHECK-BE: @llvm.ppc.altivec.vprtybd(<2 x i64>
805 // CHECK-BE-NEXT: ret <2 x i64>
806 // CHECK: @llvm.ppc.altivec.vprtybd(<2 x i64>
807 // CHECK-NEXT: ret <2 x i64>
808   return vec_parity_lsbb (vsla);
809 }
810 vector unsigned __int128 test67(void) {
811 // CHECK-BE: @llvm.ppc.altivec.vprtybq(<1 x i128>
812 // CHECK-BE-NEXT: ret <1 x i128>
813 // CHECK: @llvm.ppc.altivec.vprtybq(<1 x i128>
814 // CHECK-NEXT: ret <1 x i128>
815   return vec_parity_lsbb (vui128a);
816 }
817 vector unsigned __int128 test68(void) {
818 // CHECK-BE: @llvm.ppc.altivec.vprtybq(<1 x i128>
819 // CHECK-BE-NEXT: ret <1 x i128>
820 // CHECK: @llvm.ppc.altivec.vprtybq(<1 x i128>
821 // CHECK-NEXT: ret <1 x i128>
822   return vec_parity_lsbb (vsi128a);
823 }
824 vector unsigned char test69(void) {
825 // CHECK-BE: call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> {{.+}}, <16 x i8> {{.+}})
826 // CHECK: call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> {{.+}}, <16 x i8> {{.+}})
827   return vec_absd(vuca, vucb);
828 }
829 vector unsigned short test70(void) {
830 // CHECK-BE: call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> {{.+}}, <8 x i16> {{.+}})
831 // CHECK: call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> {{.+}}, <8 x i16> {{.+}})
832   return vec_absd(vusa, vusb);
833 }
834 vector unsigned int test71(void) {
835 // CHECK-BE: call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> {{.+}}, <4 x i32> {{.+}})
836 // CHECK: call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> {{.+}}, <4 x i32> {{.+}})
837   return vec_absd(vuia, vuib);
838 }
839 vector unsigned char test72(void) {
840 // CHECK-BE: @llvm.ppc.altivec.vslv(<16 x i8>
841 // CHECK-BE-NEXT: ret <16 x i8>
842 // CHECK: @llvm.ppc.altivec.vslv(<16 x i8>
843 // CHECK-NEXT: ret <16 x i8>
844   return vec_slv (vuca, vucb);
845 }
846 vector unsigned char test73(void) {
847 // CHECK-BE: @llvm.ppc.altivec.vsrv(<16 x i8>
848 // CHECK-BE-NEXT: ret <16 x i8>
849 // CHECK: @llvm.ppc.altivec.vsrv(<16 x i8>
850 // CHECK-NEXT: ret <16 x i8>
851   return vec_srv (vuca, vucb);
852 }
853 vector unsigned short test74(void) {
854 // CHECK-BE: @llvm.ppc.vsx.xvcvsphp(<4 x float>
855 // CHECK-BE: @llvm.ppc.vsx.xvcvsphp(<4 x float>
856 // CHECK-BE: @llvm.ppc.altivec.vperm
857 // CHECK: @llvm.ppc.vsx.xvcvsphp(<4 x float>
858 // CHECK: @llvm.ppc.vsx.xvcvsphp(<4 x float>
859 // CHECK: @llvm.ppc.altivec.vperm
860   return vec_pack_to_short_fp32(vfa, vfb);
861 }
862 vector unsigned int test75(void) {
863 // CHECK-BE: @llvm.ppc.altivec.vrlwmi(<4 x i32
864 // CHECK-BE-NEXT: ret <4 x i32>
865 // CHECK: @llvm.ppc.altivec.vrlwmi(<4 x i32
866 // CHECK-NEXT: ret <4 x i32>
867   return vec_rlmi(vuia, vuia, vuia);
868 }
869 vector unsigned long long test76(void) {
870 // CHECK-BE: @llvm.ppc.altivec.vrldmi(<2 x i64
871 // CHECK-BE-NEXT: ret <2 x i64>
872 // CHECK: @llvm.ppc.altivec.vrldmi(<2 x i64
873 // CHECK-NEXT: ret <2 x i64>
874   return vec_rlmi(vula, vula, vula);
875 }
876 vector unsigned int test77(void) {
877 // CHECK-BE: %[[RES1:.+]] = shl <4 x i32
878 // CHECK-BE: %[[RES2:.+]] = or <4 x i32> %[[RES1]]
879 // CHECK-BE: @llvm.ppc.altivec.vrlwnm(<4 x i32
880 // CHECK-BE: ret <4 x i32>
881 // CHECK: %[[RES1:.+]] = shl <4 x i32
882 // CHECK: %[[RES2:.+]] = or <4 x i32> %[[RES1]]
883 // CHECK: @llvm.ppc.altivec.vrlwnm(<4 x i32
884 // CHECK: ret <4 x i32>
885   return vec_rlnm(vuia, vuia, vuia);
886 }
887 vector unsigned long long test78(void) {
888 // CHECK-BE: %[[RES1:.+]] = shl <2 x i64
889 // CHECK-BE: %[[RES2:.+]] = or <2 x i64> %[[RES1]]
890 // CHECK-BE: @llvm.ppc.altivec.vrldnm(<2 x i64
891 // CHECK-BE-NEXT: ret <2 x i64>
892 // CHECK: %[[RES1:.+]] = shl <2 x i64
893 // CHECK: %[[RES2:.+]] = or <2 x i64> %[[RES1]]
894 // CHECK: @llvm.ppc.altivec.vrldnm(<2 x i64
895 // CHECK-NEXT: ret <2 x i64>
896   return vec_rlnm(vula, vula, vula);
897 }
898 vector double test79(void) {
899 // CHECK-BE: extractelement <4 x float>
900 // CHECK-BE: fpext float
901 // CHECK-BE: insertelement <2 x double>
902 // CHECK-BE: extractelement <4 x float>
903 // CHECK-BE: fpext float
904 // CHECK-BE: insertelement <2 x double>
905 // CHECK: extractelement <4 x float>
906 // CHECK: fpext float
907 // CHECK: insertelement <2 x double>
908 // CHECK: extractelement <4 x float>
909 // CHECK: fpext float
910 // CHECK: insertelement <2 x double>
911   return vec_unpackh(vfa);
912 }
913 vector double test80(void) {
914 // CHECK-BE: extractelement <4 x float>
915 // CHECK-BE: fpext float
916 // CHECK-BE: insertelement <2 x double>
917 // CHECK-BE: extractelement <4 x float>
918 // CHECK-BE: fpext float
919 // CHECK-BE: insertelement <2 x double>
920 // CHECK: extractelement <4 x float>
921 // CHECK: fpext float
922 // CHECK: insertelement <2 x double>
923 // CHECK: extractelement <4 x float>
924 // CHECK: fpext float
925 // CHECK: insertelement <2 x double>
926   return vec_unpackl(vfa);
927 }
928 vector float test81(void) {
929   // CHECK: extractelement <2 x double>
930   // CHECK: fptrunc double
931   // CHECK: insertelement <4 x float>
932   // CHECK: extractelement <2 x double>
933   // CHECK: fptrunc double
934   // CHECK: insertelement <4 x float>
935   // CHECK: extractelement <2 x double>
936   // CHECK: fptrunc double
937   // CHECK: insertelement <4 x float>
938   // CHECK: extractelement <2 x double>
939   // CHECK: fptrunc double
940   // CHECK: insertelement <4 x float>
941   // CHECK-LE: extractelement <2 x double>
942   // CHECK-LE: fptrunc double
943   // CHECK-LE: insertelement <4 x float>
944   // CHECK-LE: extractelement <2 x double>
945   // CHECK-LE: fptrunc double
946   // CHECK-LE: insertelement <4 x float>
947   // CHECK-LE: extractelement <2 x double>
948   // CHECK-LE: fptrunc double
949   // CHECK-LE: insertelement <4 x float>
950   // CHECK-LE: extractelement <2 x double>
951   // CHECK-LE: fptrunc double
952   // CHECK-LE: insertelement <4 x float>
953   return vec_pack(vda, vdb);
954 }
955 vector unsigned int test82(void) {
956 // CHECK-BE: @llvm.ppc.vsx.xvxexpsp(<4 x float> {{.+}})
957 // CHECK-BE-NEXT: ret <4 x i32>
958 // CHECK: @llvm.ppc.vsx.xvxexpsp(<4 x float> {{.+}})
959 // CHECK-NEXT: ret <4 x i32>
960   return vec_extract_exp(vfa);
961 }
962 vector unsigned long long test83(void) {
963 // CHECK-BE: @llvm.ppc.vsx.xvxexpdp(<2 x double> {{.+}})
964 // CHECK-BE-NEXT: ret <2 x i64>
965 // CHECK: @llvm.ppc.vsx.xvxexpdp(<2 x double> {{.+}})
966 // CHECK-NEXT: ret <2 x i64>
967   return vec_extract_exp(vda);
968 }
969 vector unsigned int test84(void) {
970 // CHECK-BE: @llvm.ppc.vsx.xvxsigsp(<4 x float> {{.+}})
971 // CHECK-BE-NEXT: ret <4 x i32>
972 // CHECK: @llvm.ppc.vsx.xvxsigsp(<4 x float> {{.+}})
973 // CHECK-NEXT: ret <4 x i32>
974   return vec_extract_sig(vfa);
975 }
976 vector unsigned long long test85(void) {
977 // CHECK-BE: @llvm.ppc.vsx.xvxsigdp(<2 x double> {{.+}})
978 // CHECK-BE-NEXT: ret <2 x i64>
979 // CHECK: @llvm.ppc.vsx.xvxsigdp(<2 x double> {{.+}})
980 // CHECK-NEXT: ret <2 x i64>
981   return vec_extract_sig(vda);
982 }
983 vector bool int test86(void) {
984 // CHECK-BE: @llvm.ppc.vsx.xvtstdcsp(<4 x float> {{.+}}, i32 127)
985 // CHECK-BE-NEXT: ret <4 x i32>
986 // CHECK: @llvm.ppc.vsx.xvtstdcsp(<4 x float> {{.+}}, i32 127)
987 // CHECK-NEXT: ret <4 x i32>
988    return vec_test_data_class(vfa, __VEC_CLASS_FP_NOT_NORMAL);
989 }
990 vector bool long long test87(void) {
991 // CHECK-BE: @llvm.ppc.vsx.xvtstdcdp(<2 x double> {{.+}}, i32 127)
992 // CHECK-BE-NEXT: ret <2 x i64>
993 // CHECK: @llvm.ppc.vsx.xvtstdcdp(<2 x double> {{.+}}, i32 127)
994 // CHECK-NEXT: ret <2 x i64>
995   return vec_test_data_class(vda, __VEC_CLASS_FP_NOT_NORMAL);
996 }
997 vector unsigned char test88(void) {
998 // CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
999 // CHECK-BE-NEXT-NEXT: ret <16 x i8>
1000 // CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1001 // CHECK-NEXT-NEXT: ret <16 x i8>
1002   return vec_xl_len(uc,0);
1003 }
1004 vector signed char test89(void) {
1005 // CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1006 // CHECK-BE-NEXT-NEXT: ret <16 x i8>
1007 // CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1008 // CHECK-NEXT-NEXT: ret <16 x i8>
1009   return vec_xl_len(sc,0);
1010 }
1011 vector unsigned short test90(void) {
1012 // CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1013 // CHECK-BE-NEXT-NEXT: ret <8 x i16>
1014 // CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1015 // CHECK-NEXT-NEXT: ret <8 x i16>
1016   return vec_xl_len(us,0);
1017 }
1018 vector signed short test91(void) {
1019 // CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1020 // CHECK-BE-NEXT-NEXT: ret <8 x i16>
1021 // CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1022 // CHECK-NEXT-NEXT: ret <8 x i16>
1023   return vec_xl_len(ss,0);
1024 }
1025 vector unsigned int test92(void) {
1026 // CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1027 // CHECK-BE-NEXT: ret <4 x i32>
1028 // CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1029 // CHECK-NEXT: ret <4 x i32>
1030   return vec_xl_len(ui,0);
1031 }
1032 
1033 vector signed int test93(void) {
1034 // CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1035 // CHECK-BE-NEXT: ret <4 x i32>
1036 // CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1037 // CHECK-NEXT: ret <4 x i32>
1038   return vec_xl_len(si,0);
1039 }
1040 
1041 vector float test94(void) {
1042 // CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1043 // CHECK-BE-NEXT-NEXT: ret <4 x i32>
1044 // CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1045 // CHECK-NEXT-NEXT: ret <4 x i32>
1046   return vec_xl_len(f,0);
1047 }
1048 
1049 vector unsigned long long test95(void) {
1050 // CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1051 // CHECK-BE-NEXT-NEXT: ret <2 x i64>
1052 // CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1053 // CHECK-NEXT-NEXT: ret <2 x i64>
1054   return vec_xl_len(ull,0);
1055 }
1056 
1057 vector signed long long test96(void) {
1058 // CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1059 // CHECK-BE-NEXT-NEXT: ret <2 x i64>
1060 // CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1061 // CHECK-NEXT-NEXT: ret <2 x i64>
1062   return vec_xl_len(sll,0);
1063 }
1064 
1065 vector double test97(void) {
1066 // CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1067 // CHECK-BE-NEXT-NEXT: ret <2 x i64>
1068 // CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1069 // CHECK-NEXT-NEXT: ret <2 x i64>
1070   return vec_xl_len(d,0);
1071 }
1072 
1073 vector unsigned __int128 test98(void) {
1074 // CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1075 // CHECK-BE-NEXT-NEXT: ret <1 x i128>
1076 // CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1077 // CHECK-NEXT-NEXT: ret <1 x i128>
1078   return vec_xl_len(uint128,0);
1079 }
1080 
1081 vector signed __int128 test99(void) {
1082 // CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1083 // CHECK-BE-NEXT-NEXT: ret <1 x i128>
1084 // CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1085 // CHECK-NEXT-NEXT: ret <1 x i128>
1086   return vec_xl_len(sint128,0);
1087 }
1088 
1089 void test100(void) {
1090 // CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1091 // CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1092   return vec_xst_len(vuca,uc,0);
1093 }
1094 
1095 void test101(void) {
1096 // CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1097 // CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1098   return vec_xst_len(vsca,sc,0);
1099 }
1100 
1101 void test102(void) {
1102 // CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1103 // CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1104  return vec_xst_len(vusa,us,0);
1105 }
1106 
1107 void test103(void) {
1108 // CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1109 // CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1110  return vec_xst_len(vssa,ss,0);
1111 }
1112 
1113 void test104(void) {
1114 // CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1115 // CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1116  return vec_xst_len(vuia,ui,0);
1117 }
1118 
1119 void test105(void) {
1120 // CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1121 // CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1122  return vec_xst_len(vsia,si,0);
1123 }
1124 
1125 void test106(void) {
1126 // CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1127 // CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1128  return vec_xst_len(vfa,f,0);
1129 }
1130 
1131 void test107(void) {
1132 // CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1133 // CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1134  return vec_xst_len(vula,ull,0);
1135 }
1136 
1137 void test108(void) {
1138 // CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1139 // CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1140  return vec_xst_len(vsla,sll,0);
1141 }
1142 
1143 void test109(void) {
1144 // CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1145 // CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1146  return vec_xst_len(vda,d,0);
1147 }
1148 
1149 void test110(void) {
1150 // CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1151 // CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1152  return vec_xst_len(vui128a,uint128,0);
1153 }
1154 
1155 void test111(void) {
1156 // CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1157 // CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1158  return vec_xst_len(vsi128a,sint128,0);
1159 }
1160 
1161 vector unsigned char test112(void) {
1162 // CHECK-BE: @llvm.ppc.vsx.lxvll(i8* %{{.+}}, i64
1163 // CHECK-BE: @llvm.ppc.altivec.lvsr(i8* %{{.+}}
1164 // CHECK-BE: @llvm.ppc.altivec.vperm
1165 // CHECK: @llvm.ppc.vsx.lxvll(i8* %{{.+}}, i64
1166 // CHECK: @llvm.ppc.altivec.lvsr(i8* %{{.+}}
1167 // CHECK: @llvm.ppc.altivec.vperm
1168   return vec_xl_len_r(uc,0);
1169 }
1170 void test113(void) {
1171 // CHECK-BE: @llvm.ppc.altivec.lvsl(i8* %{{.+}}
1172 // CHECK-BE: @llvm.ppc.altivec.vperm
1173 // CHECK-BE: @llvm.ppc.vsx.stxvll(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1174 // CHECK: @llvm.ppc.altivec.lvsl(i8* %{{.+}}
1175 // CHECK: @llvm.ppc.altivec.vperm
1176 // CHECK: @llvm.ppc.vsx.stxvll(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1177   return vec_xst_len_r(vuca,uc,0);
1178 }
1179 vector float test114(void) {
1180 // CHECK-BE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 undef, i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3>
1181 // CHECK-BE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})
1182 // CHECK-BE-NEXT: ret <4 x float>
1183 // CHECK: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef>
1184 // CHECK: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})
1185 // CHECK-NEXT: ret <4 x float>
1186   return vec_extract_fp32_from_shorth(vusa);
1187 }
1188 vector float test115(void) {
1189 // CHECK-BE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 undef, i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7>
1190 // CHECK-BE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})
1191 // CHECK-BE-NEXT: ret <4 x float>
1192 // CHECK: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7, i32 undef>
1193 // CHECK: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})
1194 // CHECK-NEXT: ret <4 x float>
1195   return vec_extract_fp32_from_shortl(vusa);
1196 }
1197 vector unsigned char test116(void) {
1198 // CHECK-BE: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> {{.+}}, <2 x i64> {{.+}}, i32 7)
1199 // CHECK-BE-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>
1200 // CHECK: [[T1:%.+]] = shufflevector <2 x i64> {{.+}}, <2 x i64> {{.+}}, <2 x i32> <i32 1, i32 0>
1201 // CHECK-NEXT: [[T2:%.+]] =  bitcast <2 x i64> [[T1]] to <4 x i32>
1202 // CHECK-NEXT: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> [[T2]], <2 x i64> {{.+}}, i32 5)
1203 // CHECK-NEXT: bitcast <4 x i32> [[T3]] to <16 x i8>
1204   return vec_insert4b(vuia, vuca, 7);
1205 }
1206 vector unsigned char test117(void) {
1207 // CHECK-BE: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> {{.+}}, <2 x i64> {{.+}}, i32 12)
1208 // CHECK-BE-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>
1209 // CHECK: [[T1:%.+]] = shufflevector <2 x i64> {{.+}}, <2 x i64> {{.+}}, <2 x i32> <i32 1, i32 0>
1210 // CHECK-NEXT: [[T2:%.+]] =  bitcast <2 x i64> [[T1]] to <4 x i32>
1211 // CHECK-NEXT: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> [[T2]], <2 x i64> {{.+}}, i32 0)
1212 // CHECK-NEXT: bitcast <4 x i32> [[T3]] to <16 x i8>
1213   return vec_insert4b(vuia, vuca, 13);
1214 }
1215 vector unsigned long long test118(void) {
1216 // CHECK-BE: call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 11)
1217 // CHECK-BE-NEXT: ret <2 x i64>
1218 // CHECK: [[T1:%.+]] = call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 1)
1219 // CHECK-NEXT: shufflevector <2 x i64> [[T1]], <2 x i64> [[T1]], <2 x i32> <i32 1, i32 0>
1220 // CHECK-NEXT: ret <2 x i64>
1221   return vec_extract4b(vuca, 11);
1222 }
1223 vector unsigned long long test119(void) {
1224 // CHECK-BE: call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 0)
1225 // CHECK-BE-NEXT: ret <2 x i64>
1226 // CHECK: [[T1:%.+]] = call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 12)
1227 // CHECK-NEXT: shufflevector <2 x i64> [[T1]], <2 x i64> [[T1]], <2 x i32> <i32 1, i32 0>
1228 // CHECK-NEXT: ret <2 x i64>
1229   return vec_extract4b(vuca, -5);
1230 }
1231 
1232 vector signed int test_vec_signexti_si_sc(void) {
1233     // CHECK: @llvm.ppc.altivec.vextsb2w(<16 x i8>
1234     // CHECK-NEXT: ret <4 x i32>
1235     return vec_signexti(vsca);
1236 }
1237 
1238 vector signed int test_vec_signexti_si_ss(void) {
1239     // CHECK: @llvm.ppc.altivec.vextsh2w(<8 x i16>
1240     // CHECK-NEXT: ret <4 x i32>
1241     return vec_signexti(vssa);
1242 }
1243 
1244 vector signed long long test_vec_signextll_sll_sc(void) {
1245     // CHECK: @llvm.ppc.altivec.vextsb2d(<16 x i8>
1246     // CHECK-NEXT: ret <2 x i64>
1247     return vec_signextll(vsca);
1248 }
1249 
1250 vector signed long long test_vec_signextll_sll_ss(void) {
1251     // CHECK: @llvm.ppc.altivec.vextsh2d(<8 x i16>
1252     // CHECK-NEXT: ret <2 x i64>
1253     return vec_signextll(vssa);
1254 }
1255 
1256 vector signed long long test_vec_signextll_sll_si(void) {
1257     // CHECK: @llvm.ppc.altivec.vextsw2d(<4 x i32>
1258     // CHECK-NEXT: ret <2 x i64>
1259     return vec_signextll(vsia);
1260 }
1261 
1262 vector unsigned long long test_vbpermd(void) {
1263   // CHECK: @llvm.ppc.altivec.vbpermd(<2 x i64>
1264   // CHECK-BE: @llvm.ppc.altivec.vbpermd(<2 x i64>
1265   return vec_bperm(vula, vuca);
1266 }
1267