1 // REQUIRES: powerpc-registered-target 2 // RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +vsx \ 3 // RUN: -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \ 4 // RUN: -o - | FileCheck %s -check-prefixes=CHECK-BE,CHECK 5 // RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +vsx \ 6 // RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \ 7 // RUN: -o - | FileCheck %s -check-prefixes=CHECK-LE,CHECK 8 9 #include <altivec.h> 10 11 vector signed __int128 vi128a; 12 vector signed char vsca, vscb; 13 vector unsigned char vuca, vucb, vucc; 14 vector signed short vssa, vssb; 15 vector unsigned short vusa, vusb, vusc; 16 vector signed int vsia, vsib; 17 vector unsigned int vuia, vuib, vuic; 18 vector signed long long vslla, vsllb; 19 vector unsigned long long vulla, vullb, vullc; 20 vector signed __int128 vsi128a, vsi128b, vsi128c; 21 vector unsigned __int128 vui128a, vui128b, vui128c; 22 vector bool __int128 vbi128a, vbi128b; 23 vector float vfa, vfb; 24 vector double vda, vdb; 25 float fa; 26 double da; 27 signed int sia; 28 signed int *iap; 29 unsigned int uia, uib, *uiap; 30 signed char *cap; 31 unsigned char uca; 32 const unsigned char *ucap; 33 const signed short *sap; 34 unsigned short usa; 35 const unsigned short *usap; 36 const signed long long *llap; 37 signed long long llb; 38 unsigned long long ulla; 39 const unsigned long long *ullap; 40 41 vector signed long long test_vec_mul_sll(void) { 42 // CHECK: mul <2 x i64> 43 // CHECK-NEXT: ret <2 x i64> 44 return vec_mul(vslla, vsllb); 45 } 46 47 vector unsigned long long test_vec_mul_ull(void) { 48 // CHECK: mul <2 x i64> 49 // CHECK-NEXT: ret <2 x i64> 50 return vec_mul(vulla, vullb); 51 } 52 53 vector signed int test_vec_div_si(void) { 54 // CHECK: sdiv <4 x i32> 55 // CHECK-NEXT: ret <4 x i32> 56 return vec_div(vsia, vsib); 57 } 58 59 vector unsigned int test_vec_div_ui(void) { 60 // CHECK: udiv <4 x i32> 61 // CHECK-NEXT: ret <4 x i32> 62 return vec_div(vuia, vuib); 63 } 64 65 vector signed long long test_vec_div_sll(void) { 66 // CHECK: sdiv <2 x i64> 67 // CHECK-NEXT: ret <2 x i64> 68 return vec_div(vslla, vsllb); 69 } 70 71 vector unsigned long long test_vec_div_ull(void) { 72 // CHECK: udiv <2 x i64> 73 // CHECK-NEXT: ret <2 x i64> 74 return vec_div(vulla, vullb); 75 } 76 77 vector unsigned __int128 test_vec_div_u128(void) { 78 // CHECK: udiv <1 x i128> 79 // CHECK-NEXT: ret <1 x i128> 80 return vec_div(vui128a, vui128b); 81 } 82 83 vector signed __int128 test_vec_div_s128(void) { 84 // CHECK: sdiv <1 x i128> 85 // CHECK-NEXT: ret <1 x i128> 86 return vec_div(vsi128a, vsi128b); 87 } 88 89 vector signed int test_vec_dive_si(void) { 90 // CHECK: @llvm.ppc.altivec.vdivesw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}) 91 // CHECK-NEXT: ret <4 x i32> 92 return vec_dive(vsia, vsib); 93 } 94 95 vector unsigned int test_vec_dive_ui(void) { 96 // CHECK: @llvm.ppc.altivec.vdiveuw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}) 97 // CHECK-NEXT: ret <4 x i32> 98 return vec_dive(vuia, vuib); 99 } 100 101 vector signed long long test_vec_dive_sll(void) { 102 // CHECK: @llvm.ppc.altivec.vdivesd(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}) 103 // CHECK-NEXT: ret <2 x i64> 104 return vec_dive(vslla, vsllb); 105 } 106 107 vector unsigned long long test_vec_dive_ull(void) { 108 // CHECK: @llvm.ppc.altivec.vdiveud(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}) 109 // CHECK-NEXT: ret <2 x i64> 110 return vec_dive(vulla, vullb); 111 } 112 113 vector unsigned __int128 test_vec_dive_u128(void) { 114 // CHECK: @llvm.ppc.altivec.vdiveuq(<1 x i128> %{{.+}}, <1 x i128> %{{.+}}) 115 // CHECK-NEXT: ret <1 x i128> 116 return vec_dive(vui128a, vui128b); 117 } 118 119 vector signed __int128 test_vec_dive_s128(void) { 120 // CHECK: @llvm.ppc.altivec.vdivesq(<1 x i128> %{{.+}}, <1 x i128> %{{.+}}) 121 // CHECK-NEXT: ret <1 x i128> 122 return vec_dive(vsi128a, vsi128b); 123 } 124 125 vector signed int test_vec_mulh_si(void) { 126 // CHECK: @llvm.ppc.altivec.vmulhsw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}) 127 // CHECK-NEXT: ret <4 x i32> 128 return vec_mulh(vsia, vsib); 129 } 130 131 vector unsigned int test_vec_mulh_ui(void) { 132 // CHECK: @llvm.ppc.altivec.vmulhuw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}) 133 // CHECK-NEXT: ret <4 x i32> 134 return vec_mulh(vuia, vuib); 135 } 136 137 vector signed long long test_vec_mulh_sll(void) { 138 // CHECK: @llvm.ppc.altivec.vmulhsd(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}) 139 // CHECK-NEXT: ret <2 x i64> 140 return vec_mulh(vslla, vsllb); 141 } 142 143 vector unsigned long long test_vec_mulh_ull(void) { 144 // CHECK: @llvm.ppc.altivec.vmulhud(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}) 145 // CHECK-NEXT: ret <2 x i64> 146 return vec_mulh(vulla, vullb); 147 } 148 149 vector signed int test_vec_mod_si(void) { 150 // CHECK: srem <4 x i32> 151 // CHECK-NEXT: ret <4 x i32> 152 return vec_mod(vsia, vsib); 153 } 154 155 vector unsigned int test_vec_mod_ui(void) { 156 // CHECK: urem <4 x i32> 157 // CHECK-NEXT: ret <4 x i32> 158 return vec_mod(vuia, vuib); 159 } 160 161 vector signed long long test_vec_mod_sll(void) { 162 // CHECK: srem <2 x i64> 163 // CHECK-NEXT: ret <2 x i64> 164 return vec_mod(vslla, vsllb); 165 } 166 167 vector unsigned long long test_vec_mod_ull(void) { 168 // CHECK: urem <2 x i64> 169 // CHECK-NEXT: ret <2 x i64> 170 return vec_mod(vulla, vullb); 171 } 172 173 vector unsigned char test_xvcvspbf16(vector unsigned char vc) { 174 // CHECK-LABEL: @test_xvcvspbf16( 175 // CHECK: [[TMP0:%.*]] = call <16 x i8> @llvm.ppc.vsx.xvcvspbf16(<16 x i8> [[VC:%.*]]) 176 return __builtin_vsx_xvcvspbf16(vc); 177 } 178 179 vector unsigned char test_xvcvbf16spn(vector unsigned char vc) { 180 // CHECK-LABEL: @test_xvcvbf16spn( 181 // CHECK: [[TMP0:%.*]] = call <16 x i8> @llvm.ppc.vsx.xvcvbf16spn(<16 x i8> [[VC:%.*]]) 182 return __builtin_vsx_xvcvbf16spn(vc); 183 } 184 185 vector unsigned long long test_vpdepd(void) { 186 // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64> 187 // CHECK-NEXT: ret <2 x i64> 188 return vec_pdep(vulla, vullb); 189 } 190 191 vector unsigned long long test_vpextd(void) { 192 // CHECK: @llvm.ppc.altivec.vpextd(<2 x i64> 193 // CHECK-NEXT: ret <2 x i64> 194 return vec_pext(vulla, vullb); 195 } 196 197 vector unsigned char test_vec_stril_uc(void) { 198 // CHECK-BE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 199 // CHECK-BE-NEXT: ret <16 x i8> 200 // CHECK-LE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 201 // CHECK-LE-NEXT: ret <16 x i8> 202 return vec_stril(vuca); 203 } 204 205 vector signed char test_vec_stril_sc(void) { 206 // CHECK-BE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 207 // CHECK-BE-NEXT: ret <16 x i8> 208 // CHECK-LE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 209 // CHECK-LE-NEXT: ret <16 x i8> 210 return vec_stril(vsca); 211 } 212 213 vector unsigned short test_vec_stril_us(void) { 214 // CHECK-BE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 215 // CHECK-BE-NEXT: ret <8 x i16> 216 // CHECK-LE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 217 // CHECK-LE-NEXT: ret <8 x i16> 218 return vec_stril(vusa); 219 } 220 221 vector signed short test_vec_stril_ss(void) { 222 // CHECK-BE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 223 // CHECK-BE-NEXT: ret <8 x i16> 224 // CHECK-LE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 225 // CHECK-LE-NEXT: ret <8 x i16> 226 return vec_stril(vssa); 227 } 228 229 int test_vec_stril_p_uc(void) { 230 // CHECK-BE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 231 // CHECK-BE-NEXT: ret i32 232 // CHECK-LE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 233 // CHECK-LE-NEXT: ret i32 234 return vec_stril_p(vuca); 235 } 236 237 int test_vec_stril_p_sc(void) { 238 // CHECK-BE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 239 // CHECK-BE-NEXT: ret i32 240 // CHECK-LE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 241 // CHECK-LE-NEXT: ret i32 242 return vec_stril_p(vsca); 243 } 244 245 int test_vec_stril_p_us(void) { 246 // CHECK-BE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 247 // CHECK-BE-NEXT: ret i32 248 // CHECK-LE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 249 // CHECK-LE-NEXT: ret i32 250 return vec_stril_p(vusa); 251 } 252 253 int test_vec_stril_p_ss(void) { 254 // CHECK-BE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 255 // CHECK-BE-NEXT: ret i32 256 // CHECK-LE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 257 // CHECK-LE-NEXT: ret i32 258 return vec_stril_p(vssa); 259 } 260 261 vector unsigned char test_vec_stril_p_uc_2(vector unsigned char *ptr, int len) { 262 // CHECK-BE: icmp slt i32 263 // CHECK-BE: br i1 264 // CHECK-BE: for.body: 265 // CHECK-BE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 266 // CHECK-BE: if.then: 267 // CHECK-BE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 268 // CHECK-BE: ret <16 x i8> 269 // CHECK-LE: icmp slt i32 270 // CHECK-LE: br i1 271 // CHECK-LE: for.body: 272 // CHECK-LE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 273 // CHECK-LE: if.then: 274 // CHECK-LE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 275 // CHECK-LE: ret <16 x i8> 276 for (int i = 0; i < len; i++) { 277 if (vec_stril_p(*(ptr + i))) { 278 return vec_stril(*(ptr + i)); 279 } 280 } 281 return vec_stril(*(ptr)); 282 } 283 284 vector signed char test_vec_stril_p_sc_2(vector signed char *ptr, int len) { 285 // CHECK-BE: icmp slt i32 286 // CHECK-BE: br i1 287 // CHECK-BE: for.body: 288 // CHECK-BE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 289 // CHECK-BE: if.then: 290 // CHECK-BE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 291 // CHECK-BE: ret <16 x i8> 292 // CHECK-LE: icmp slt i32 293 // CHECK-LE: br i1 294 // CHECK-LE: for.body: 295 // CHECK-LE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 296 // CHECK-LE: if.then: 297 // CHECK-LE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 298 // CHECK-LE: ret <16 x i8> 299 for (int i = 0; i < len; i++) { 300 if (vec_stril_p(*(ptr + i))) { 301 return vec_stril(*(ptr + i)); 302 } 303 } 304 return vec_stril(*(ptr)); 305 } 306 307 vector unsigned short test_vec_stril_p_us_2(vector unsigned short *ptr, int len) { 308 // CHECK-BE: icmp slt i32 309 // CHECK-BE: br i1 310 // CHECK-BE: for.body: 311 // CHECK-BE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 312 // CHECK-BE: if.then: 313 // CHECK-BE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 314 // CHECK-BE: ret <8 x i16> 315 // CHECK-LE: icmp slt i32 316 // CHECK-LE: br i1 317 // CHECK-LE: for.body: 318 // CHECK-LE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 319 // CHECK-LE: if.then: 320 // CHECK-LE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 321 // CHECK-LE: ret <8 x i16> 322 for (int i = 0; i < len; i++) { 323 if (vec_stril_p(*(ptr + i))) { 324 return vec_stril(*(ptr + i)); 325 } 326 } 327 return vec_stril(*(ptr)); 328 } 329 330 vector signed short test_vec_stril_p_ss_2(vector signed short *ptr, int len) { 331 // CHECK-BE: icmp slt i32 332 // CHECK-BE: br i1 333 // CHECK-BE: for.body: 334 // CHECK-BE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 335 // CHECK-BE: if.then: 336 // CHECK-BE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 337 // CHECK-BE: ret <8 x i16> 338 // CHECK-LE: icmp slt i32 339 // CHECK-LE: br i1 340 // CHECK-LE: for.body: 341 // CHECK-LE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 342 // CHECK-LE: if.then: 343 // CHECK-LE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 344 // CHECK-LE: ret <8 x i16> 345 for (int i = 0; i < len; i++) { 346 if (vec_stril_p(*(ptr + i))) { 347 return vec_stril(*(ptr + i)); 348 } 349 } 350 return vec_stril(*(ptr)); 351 } 352 353 vector unsigned char test_vec_strir_uc(void) { 354 // CHECK-BE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 355 // CHECK-BE-NEXT: ret <16 x i8> 356 // CHECK-LE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 357 // CHECK-LE-NEXT: ret <16 x i8> 358 return vec_strir(vuca); 359 } 360 361 vector signed char test_vec_strir_sc(void) { 362 // CHECK-BE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 363 // CHECK-BE-NEXT: ret <16 x i8> 364 // CHECK-LE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 365 // CHECK-LE-NEXT: ret <16 x i8> 366 return vec_strir(vsca); 367 } 368 369 vector unsigned short test_vec_strir_us(void) { 370 // CHECK-BE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 371 // CHECK-BE-NEXT: ret <8 x i16> 372 // CHECK-LE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 373 // CHECK-LE-NEXT: ret <8 x i16> 374 return vec_strir(vusa); 375 } 376 377 vector signed short test_vec_strir_ss(void) { 378 // CHECK-BE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 379 // CHECK-BE-NEXT: ret <8 x i16> 380 // CHECK-LE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 381 // CHECK-LE-NEXT: ret <8 x i16> 382 return vec_strir(vssa); 383 } 384 385 int test_vec_strir_p_uc(void) { 386 // CHECK-BE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 387 // CHECK-BE-NEXT: ret i32 388 // CHECK-LE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 389 // CHECK-LE-NEXT: ret i32 390 return vec_strir_p(vuca); 391 } 392 393 int test_vec_strir_p_sc(void) { 394 // CHECK-BE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 395 // CHECK-BE-NEXT: ret i32 396 // CHECK-LE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 397 // CHECK-LE-NEXT: ret i32 398 return vec_strir_p(vsca); 399 } 400 401 int test_vec_strir_p_us(void) { 402 // CHECK-BE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 403 // CHECK-BE-NEXT: ret i32 404 // CHECK-LE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 405 // CHECK-LE-NEXT: ret i32 406 return vec_strir_p(vusa); 407 } 408 409 int test_vec_strir_p_ss(void) { 410 // CHECK-BE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 411 // CHECK-BE-NEXT: ret i32 412 // CHECK-LE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 413 // CHECK-LE-NEXT: ret i32 414 return vec_strir_p(vssa); 415 } 416 417 vector unsigned char test_vec_strir_p_uc_2(vector unsigned char *ptr, int len) { 418 // CHECK-BE: icmp slt i32 419 // CHECK-BE: br i1 420 // CHECK-BE: for.body: 421 // CHECK-BE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 422 // CHECK-BE: if.then: 423 // CHECK-BE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 424 // CHECK-BE: ret <16 x i8> 425 // CHECK-LE: icmp slt i32 426 // CHECK-LE: br i1 427 // CHECK-LE: for.body: 428 // CHECK-LE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 429 // CHECK-LE: if.then: 430 // CHECK-LE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 431 // CHECK-LE: ret <16 x i8> 432 for (int i = 0; i < len; i++) { 433 if (vec_strir_p(*(ptr + i))) { 434 return vec_strir(*(ptr + i)); 435 } 436 } 437 return vec_strir(*(ptr)); 438 } 439 440 vector signed char test_vec_strir_p_sc_2(vector signed char *ptr, int len) { 441 // CHECK-BE: icmp slt i32 442 // CHECK-BE: br i1 443 // CHECK-BE: for.body: 444 // CHECK-BE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 445 // CHECK-BE: if.then: 446 // CHECK-BE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 447 // CHECK-BE: ret <16 x i8> 448 // CHECK-LE: icmp slt i32 449 // CHECK-LE: br i1 450 // CHECK-LE: for.body: 451 // CHECK-LE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 452 // CHECK-LE: if.then: 453 // CHECK-LE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 454 // CHECK-LE: ret <16 x i8> 455 for (int i = 0; i < len; i++) { 456 if (vec_strir_p(*(ptr + i))) { 457 return vec_strir(*(ptr + i)); 458 } 459 } 460 return vec_strir(*(ptr)); 461 } 462 463 vector unsigned short test_vec_strir_p_us_2(vector unsigned short *ptr, int len) { 464 // CHECK-BE: icmp slt i32 465 // CHECK-BE: br i1 466 // CHECK-BE: for.body: 467 // CHECK-BE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 468 // CHECK-BE: if.then: 469 // CHECK-BE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 470 // CHECK-BE: ret <8 x i16> 471 // CHECK-LE: icmp slt i32 472 // CHECK-LE: br i1 473 // CHECK-LE: for.body: 474 // CHECK-LE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 475 // CHECK-LE: if.then: 476 // CHECK-LE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 477 // CHECK-LE: ret <8 x i16> 478 for (int i = 0; i < len; i++) { 479 if (vec_strir_p(*(ptr + i))) { 480 return vec_strir(*(ptr + i)); 481 } 482 } 483 return vec_strir(*(ptr)); 484 } 485 486 vector signed short test_vec_strir_p_ss_2(vector signed short *ptr, int len) { 487 // CHECK-BE: icmp slt i32 488 // CHECK-BE: br i1 489 // CHECK-BE: for.body: 490 // CHECK-BE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 491 // CHECK-BE: if.then: 492 // CHECK-BE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 493 // CHECK-BE: ret <8 x i16> 494 // CHECK-LE: icmp slt i32 495 // CHECK-LE: br i1 496 // CHECK-LE: for.body: 497 // CHECK-LE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 498 // CHECK-LE: if.then: 499 // CHECK-LE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 500 // CHECK-LE: ret <8 x i16> 501 for (int i = 0; i < len; i++) { 502 if (vec_strir_p(*(ptr + i))) { 503 return vec_strir(*(ptr + i)); 504 } 505 } 506 return vec_strir(*(ptr)); 507 } 508 509 unsigned int test_vec_extractm_uc(void) { 510 // CHECK: @llvm.ppc.altivec.vextractbm(<16 x i8> %{{.+}}) 511 // CHECK-NEXT: ret i32 512 return vec_extractm(vuca); 513 } 514 515 unsigned int test_vec_extractm_us(void) { 516 // CHECK: @llvm.ppc.altivec.vextracthm(<8 x i16> %{{.+}}) 517 // CHECK-NEXT: ret i32 518 return vec_extractm(vusa); 519 } 520 521 unsigned int test_vec_extractm_ui(void) { 522 // CHECK: @llvm.ppc.altivec.vextractwm(<4 x i32> %{{.+}}) 523 // CHECK-NEXT: ret i32 524 return vec_extractm(vuia); 525 } 526 527 unsigned int test_vec_extractm_ull(void) { 528 // CHECK: @llvm.ppc.altivec.vextractdm(<2 x i64> %{{.+}}) 529 // CHECK-NEXT: ret i32 530 return vec_extractm(vulla); 531 } 532 533 unsigned int test_vec_extractm_u128(void) { 534 // CHECK: @llvm.ppc.altivec.vextractqm(<1 x i128> %{{.+}}) 535 // CHECK-NEXT: ret i32 536 return vec_extractm(vui128a); 537 } 538 539 vector unsigned long long test_vcfuged(void) { 540 // CHECK: @llvm.ppc.altivec.vcfuged(<2 x i64> 541 // CHECK-NEXT: ret <2 x i64> 542 return vec_cfuge(vulla, vullb); 543 } 544 545 vector unsigned char test_vec_expandm_uc(void) { 546 // CHECK: @llvm.ppc.altivec.vexpandbm(<16 x i8> %{{.+}}) 547 // CHECK-NEXT: ret <16 x i8> 548 return vec_expandm(vuca); 549 } 550 551 vector unsigned short test_vec_expandm_us(void) { 552 // CHECK: @llvm.ppc.altivec.vexpandhm(<8 x i16> %{{.+}}) 553 // CHECK-NEXT: ret <8 x i16> 554 return vec_expandm(vusa); 555 } 556 557 vector unsigned int test_vec_expandm_ui(void) { 558 // CHECK: @llvm.ppc.altivec.vexpandwm(<4 x i32> %{{.+}}) 559 // CHECK-NEXT: ret <4 x i32> 560 return vec_expandm(vuia); 561 } 562 563 vector unsigned long long test_vec_expandm_ull(void) { 564 // CHECK: @llvm.ppc.altivec.vexpanddm(<2 x i64> %{{.+}}) 565 // CHECK-NEXT: ret <2 x i64> 566 return vec_expandm(vulla); 567 } 568 569 vector unsigned __int128 test_vec_expandm_u128(void) { 570 // CHECK: @llvm.ppc.altivec.vexpandqm(<1 x i128> %{{.+}}) 571 // CHECK-NEXT: ret <1 x i128> 572 return vec_expandm(vui128a); 573 } 574 575 unsigned long long test_vec_cntm_uc(void) { 576 // CHECK: @llvm.ppc.altivec.vcntmbb(<16 x i8> %{{.+}}, i32 577 // CHECK-NEXT: ret i64 578 return vec_cntm(vuca, 1); 579 } 580 581 unsigned long long test_vec_cntm_us(void) { 582 // CHECK: @llvm.ppc.altivec.vcntmbh(<8 x i16> %{{.+}}, i32 583 // CHECK-NEXT: ret i64 584 return vec_cntm(vusa, 0); 585 } 586 587 unsigned long long test_vec_cntm_ui(void) { 588 // CHECK: @llvm.ppc.altivec.vcntmbw(<4 x i32> %{{.+}}, i32 589 // CHECK-NEXT: ret i64 590 return vec_cntm(vuia, 1); 591 } 592 593 unsigned long long test_vec_cntm_ull(void) { 594 // CHECK: @llvm.ppc.altivec.vcntmbd(<2 x i64> %{{.+}}, i32 595 // CHECK-NEXT: ret i64 596 return vec_cntm(vulla, 0); 597 } 598 599 vector unsigned char test_vec_genbm(void) { 600 // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}}) 601 // CHECK-NEXT: ret <16 x i8> 602 return vec_genbm(ulla); 603 } 604 605 vector unsigned char test_vec_genbm_imm(void) { 606 // CHECK: store i64 1 607 // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}}) 608 // CHECK-NEXT: ret <16 x i8> 609 return vec_genbm(1); 610 } 611 612 vector unsigned char test_vec_genbm_imm2(void) { 613 // CHECK: store i64 255 614 // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}}) 615 // CHECK-NEXT: ret <16 x i8> 616 return vec_genbm(255); 617 } 618 619 vector unsigned char test_vec_genbm_imm3(void) { 620 // CHECK: store i64 65535 621 // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}}) 622 // CHECK-NEXT: ret <16 x i8> 623 return vec_genbm(65535); 624 } 625 626 vector unsigned char test_vec_genbm_imm4(void) { 627 // CHECK: store i64 65536 628 // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}}) 629 // CHECK-NEXT: ret <16 x i8> 630 return vec_genbm(65536); 631 } 632 633 vector unsigned char test_vec_genbm_imm5(void) { 634 // CHECK: store i64 65546 635 // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}}) 636 // CHECK-NEXT: ret <16 x i8> 637 return vec_genbm(65546); 638 } 639 640 vector unsigned short test_vec_genhm(void) { 641 // CHECK: @llvm.ppc.altivec.mtvsrhm(i64 %{{.+}}) 642 // CHECK-NEXT: ret <8 x i16> 643 return vec_genhm(ulla); 644 } 645 646 vector unsigned int test_vec_genwm(void) { 647 // CHECK: @llvm.ppc.altivec.mtvsrwm(i64 %{{.+}}) 648 // CHECK-NEXT: ret <4 x i32> 649 return vec_genwm(ulla); 650 } 651 652 vector unsigned long long test_vec_gendm(void) { 653 // CHECK: @llvm.ppc.altivec.mtvsrdm(i64 %{{.+}}) 654 // CHECK-NEXT: ret <2 x i64> 655 return vec_gendm(ulla); 656 } 657 658 vector unsigned __int128 test_vec_genqm(void) { 659 // CHECK: @llvm.ppc.altivec.mtvsrqm(i64 %{{.+}}) 660 // CHECK-NEXT: ret <1 x i128> 661 return vec_genqm(ulla); 662 } 663 664 unsigned long long test_vgnb_1(void) { 665 // CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 2) 666 // CHECK-NEXT: ret i64 667 return vec_gnb(vui128a, 2); 668 } 669 670 unsigned long long test_vgnb_2(void) { 671 // CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 7) 672 // CHECK-NEXT: ret i64 673 return vec_gnb(vui128a, 7); 674 } 675 676 unsigned long long test_vgnb_3(void) { 677 // CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 5) 678 // CHECK-NEXT: ret i64 679 return vec_gnb(vui128a, 5); 680 } 681 682 vector unsigned char test_xxeval_uc(void) { 683 // CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 0) 684 // CHECK: ret <16 x i8> 685 return vec_ternarylogic(vuca, vucb, vucc, 0); 686 } 687 688 vector unsigned short test_xxeval_us(void) { 689 // CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 255) 690 // CHECK: ret <8 x i16> 691 return vec_ternarylogic(vusa, vusb, vusc, 255); 692 } 693 694 vector unsigned int test_xxeval_ui(void) { 695 // CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 150) 696 // CHECK: ret <4 x i32> 697 return vec_ternarylogic(vuia, vuib, vuic, 150); 698 } 699 700 vector unsigned long long test_xxeval_ull(void) { 701 // CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 1) 702 // CHECK: ret <2 x i64> 703 return vec_ternarylogic(vulla, vullb, vullc, 1); 704 } 705 706 vector unsigned __int128 test_xxeval_ui128(void) { 707 // CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 246) 708 // CHECK: ret <1 x i128> 709 return vec_ternarylogic(vui128a, vui128b, vui128c, 246); 710 } 711 712 vector unsigned char test_xxgenpcvbm(void) { 713 // CHECK: @llvm.ppc.vsx.xxgenpcvbm(<16 x i8> %{{.+}}, i32 714 // CHECK-NEXT: ret <16 x i8> 715 return vec_genpcvm(vuca, 0); 716 } 717 718 vector unsigned short test_xxgenpcvhm(void) { 719 // CHECK: @llvm.ppc.vsx.xxgenpcvhm(<8 x i16> %{{.+}}, i32 720 // CHECK-NEXT: ret <8 x i16> 721 return vec_genpcvm(vusa, 0); 722 } 723 724 vector unsigned int test_xxgenpcvwm(void) { 725 // CHECK: @llvm.ppc.vsx.xxgenpcvwm(<4 x i32> %{{.+}}, i32 726 // CHECK-NEXT: ret <4 x i32> 727 return vec_genpcvm(vuia, 0); 728 } 729 730 vector unsigned long long test_xxgenpcvdm(void) { 731 // CHECK: @llvm.ppc.vsx.xxgenpcvdm(<2 x i64> %{{.+}}, i32 732 // CHECK-NEXT: ret <2 x i64> 733 return vec_genpcvm(vulla, 0); 734 } 735 736 vector signed char test_vec_clr_first_sc(void) { 737 // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8> 738 // CHECK-BE-NEXT: ret <16 x i8> 739 // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8> 740 // CHECK-LE-NEXT: ret <16 x i8> 741 return vec_clr_first(vsca, uia); 742 } 743 744 vector unsigned char test_vec_clr_first_uc(void) { 745 // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8> 746 // CHECK-BE-NEXT: ret <16 x i8> 747 // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8> 748 // CHECK-LE-NEXT: ret <16 x i8> 749 return vec_clr_first(vuca, uia); 750 } 751 752 vector signed char test_vec_clr_last_sc(void) { 753 // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8> 754 // CHECK-BE-NEXT: ret <16 x i8> 755 // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8> 756 // CHECK-LE-NEXT: ret <16 x i8> 757 return vec_clr_last(vsca, uia); 758 } 759 760 vector unsigned char test_vec_clr_last_uc(void) { 761 // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8> 762 // CHECK-BE-NEXT: ret <16 x i8> 763 // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8> 764 // CHECK-LE-NEXT: ret <16 x i8> 765 return vec_clr_last(vuca, uia); 766 } 767 768 vector unsigned long long test_vclzdm(void) { 769 // CHECK: @llvm.ppc.altivec.vclzdm(<2 x i64> 770 // CHECK-NEXT: ret <2 x i64> 771 return vec_cntlzm(vulla, vullb); 772 } 773 774 vector unsigned long long test_vctzdm(void) { 775 // CHECK: @llvm.ppc.altivec.vctzdm(<2 x i64> 776 // CHECK-NEXT: ret <2 x i64> 777 return vec_cnttzm(vulla, vullb); 778 } 779 780 vector signed char test_vec_sldb_sc(void) { 781 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 0 782 // CHECK-NEXT: ret <16 x i8> 783 return vec_sldb(vsca, vscb, 0); 784 } 785 786 vector unsigned char test_vec_sldb_uc(void) { 787 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 1 788 // CHECK-NEXT: ret <16 x i8> 789 return vec_sldb(vuca, vucb, 1); 790 } 791 792 vector signed short test_vec_sldb_ss(void) { 793 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 2 794 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16> 795 // CHECK-NEXT: ret <8 x i16> 796 return vec_sldb(vssa, vssb, 2); 797 } 798 799 vector unsigned short test_vec_sldb_us(void) { 800 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 3 801 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16> 802 // CHECK-NEXT: ret <8 x i16> 803 return vec_sldb(vusa, vusb, 3); 804 } 805 806 vector signed int test_vec_sldb_si(void) { 807 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 4 808 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32> 809 // CHECK-NEXT: ret <4 x i32> 810 return vec_sldb(vsia, vsib, 4); 811 } 812 813 vector unsigned int test_vec_sldb_ui(void) { 814 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 5 815 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32> 816 // CHECK-NEXT: ret <4 x i32> 817 return vec_sldb(vuia, vuib, 5); 818 } 819 820 vector signed long long test_vec_sldb_sll(void) { 821 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 6 822 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64> 823 // CHECK-NEXT: ret <2 x i64> 824 return vec_sldb(vslla, vsllb, 6); 825 } 826 827 vector unsigned long long test_vec_sldb_ull(void) { 828 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 7 829 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64> 830 // CHECK-NEXT: ret <2 x i64> 831 return vec_sldb(vulla, vullb, 7); 832 } 833 834 vector signed char test_vec_srdb_sc(void) { 835 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 0 836 // CHECK-NEXT: ret <16 x i8> 837 return vec_srdb(vsca, vscb, 8); 838 } 839 840 vector unsigned char test_vec_srdb_uc(void) { 841 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 1 842 // CHECK-NEXT: ret <16 x i8> 843 return vec_srdb(vuca, vucb, 9); 844 } 845 846 vector signed short test_vec_srdb_ss(void) { 847 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 2 848 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16> 849 // CHECK-NEXT: ret <8 x i16> 850 return vec_srdb(vssa, vssb, 10); 851 } 852 853 vector unsigned short test_vec_srdb_us(void) { 854 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 3 855 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16> 856 // CHECK-NEXT: ret <8 x i16> 857 return vec_srdb(vusa, vusb, 3); 858 } 859 860 vector signed int test_vec_srdb_si(void) { 861 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 4 862 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32> 863 // CHECK-NEXT: ret <4 x i32> 864 return vec_srdb(vsia, vsib, 4); 865 } 866 867 vector unsigned int test_vec_srdb_ui(void) { 868 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 5 869 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32> 870 // CHECK-NEXT: ret <4 x i32> 871 return vec_srdb(vuia, vuib, 5); 872 } 873 874 vector signed long long test_vec_srdb_sll(void) { 875 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 6 876 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64> 877 // CHECK-NEXT: ret <2 x i64> 878 return vec_srdb(vslla, vsllb, 6); 879 } 880 881 vector unsigned long long test_vec_srdb_ull(void) { 882 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 7 883 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64> 884 // CHECK-NEXT: ret <2 x i64> 885 return vec_srdb(vulla, vullb, 7); 886 } 887 888 vector signed char test_vec_permx_sc(void) { 889 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 890 // CHECK-NEXT: ret <16 x i8> 891 return vec_permx(vsca, vscb, vucc, 0); 892 } 893 894 vector unsigned char test_vec_permx_uc(void) { 895 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 896 // CHECK-NEXT: ret <16 x i8> 897 return vec_permx(vuca, vucb, vucc, 1); 898 } 899 900 vector signed short test_vec_permx_ss(void) { 901 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 902 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16> 903 // CHECK-NEXT: ret <8 x i16> 904 return vec_permx(vssa, vssb, vucc, 2); 905 } 906 907 vector unsigned short test_vec_permx_us(void) { 908 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 909 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16> 910 // CHECK-NEXT: ret <8 x i16> 911 return vec_permx(vusa, vusb, vucc, 3); 912 } 913 914 vector signed int test_vec_permx_si(void) { 915 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 916 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32> 917 // CHECK-NEXT: ret <4 x i32> 918 return vec_permx(vsia, vsib, vucc, 4); 919 } 920 921 vector unsigned int test_vec_permx_ui(void) { 922 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 923 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32> 924 // CHECK-NEXT: ret <4 x i32> 925 return vec_permx(vuia, vuib, vucc, 5); 926 } 927 928 vector signed long long test_vec_permx_sll(void) { 929 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 930 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64> 931 // CHECK-NEXT: ret <2 x i64> 932 return vec_permx(vslla, vsllb, vucc, 6); 933 } 934 935 vector unsigned long long test_vec_permx_ull(void) { 936 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 937 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64> 938 // CHECK-NEXT: ret <2 x i64> 939 return vec_permx(vulla, vullb, vucc, 7); 940 } 941 942 vector float test_vec_permx_f(void) { 943 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 944 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x float> 945 // CHECK-NEXT: ret <4 x float> 946 return vec_permx(vfa, vfb, vucc, 0); 947 } 948 949 vector double test_vec_permx_d(void) { 950 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 951 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x double> 952 // CHECK-NEXT: ret <2 x double> 953 return vec_permx(vda, vdb, vucc, 1); 954 } 955 956 vector signed char test_vec_blend_sc(void) { 957 // CHECK: @llvm.ppc.vsx.xxblendvb(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> 958 // CHECK-NEXT: ret <16 x i8> 959 return vec_blendv(vsca, vscb, vucc); 960 } 961 962 vector unsigned char test_vec_blend_uc(void) { 963 // CHECK: @llvm.ppc.vsx.xxblendvb(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> 964 // CHECK-NEXT: ret <16 x i8> 965 return vec_blendv(vuca, vucb, vucc); 966 } 967 968 vector signed short test_vec_blend_ss(void) { 969 // CHECK: @llvm.ppc.vsx.xxblendvh(<8 x i16> %{{.+}}, <8 x i16> %{{.+}}, <8 x i16> 970 // CHECK-NEXT: ret <8 x i16> 971 return vec_blendv(vssa, vssb, vusc); 972 } 973 974 vector unsigned short test_vec_blend_us(void) { 975 // CHECK: @llvm.ppc.vsx.xxblendvh(<8 x i16> %{{.+}}, <8 x i16> %{{.+}}, <8 x i16> 976 // CHECK-NEXT: ret <8 x i16> 977 return vec_blendv(vusa, vusb, vusc); 978 } 979 980 vector signed int test_vec_blend_si(void) { 981 // CHECK: @llvm.ppc.vsx.xxblendvw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, <4 x i32> 982 // CHECK-NEXT: ret <4 x i32> 983 return vec_blendv(vsia, vsib, vuic); 984 } 985 986 vector unsigned int test_vec_blend_ui(void) { 987 // CHECK: @llvm.ppc.vsx.xxblendvw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, <4 x i32> 988 // CHECK-NEXT: ret <4 x i32> 989 return vec_blendv(vuia, vuib, vuic); 990 } 991 992 vector signed long long test_vec_blend_sll(void) { 993 // CHECK: @llvm.ppc.vsx.xxblendvd(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> 994 // CHECK-NEXT: ret <2 x i64> 995 return vec_blendv(vslla, vsllb, vullc); 996 } 997 998 vector unsigned long long test_vec_blend_ull(void) { 999 // CHECK: @llvm.ppc.vsx.xxblendvd(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> 1000 // CHECK-NEXT: ret <2 x i64> 1001 return vec_blendv(vulla, vullb, vullc); 1002 } 1003 1004 vector float test_vec_blend_f(void) { 1005 // CHECK: @llvm.ppc.vsx.xxblendvw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, <4 x i32> 1006 // CHECK-NEXT: bitcast <4 x i32> %{{.*}} to <4 x float> 1007 // CHECK-NEXT: ret <4 x float> 1008 return vec_blendv(vfa, vfb, vuic); 1009 } 1010 1011 vector double test_vec_blend_d(void) { 1012 // CHECK: @llvm.ppc.vsx.xxblendvd(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> 1013 // CHECK-NEXT: bitcast <2 x i64> %{{.*}} to <2 x double> 1014 // CHECK-NEXT: ret <2 x double> 1015 return vec_blendv(vda, vdb, vullc); 1016 } 1017 1018 // CHECK-BE-LABEL: @test_vec_replace_elt_si( 1019 // CHECK-BE-NEXT: entry: 1020 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 1021 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1022 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 1023 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1024 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 0) 1025 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1026 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> 1027 // CHECK-BE-NEXT: ret <4 x i32> [[TMP6]] 1028 // 1029 // CHECK-LE-LABEL: @test_vec_replace_elt_si( 1030 // CHECK-LE-NEXT: entry: 1031 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 1032 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1033 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 1034 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1035 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 12) 1036 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1037 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> 1038 // CHECK-LE-NEXT: ret <4 x i32> [[TMP6]] 1039 // 1040 vector signed int test_vec_replace_elt_si(void) { 1041 return vec_replace_elt(vsia, sia, 0); 1042 } 1043 1044 // CHECK-BE-LABEL: @test_vec_replace_elt_ui( 1045 // CHECK-BE-NEXT: entry: 1046 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 1047 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1048 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 1049 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1050 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 4) 1051 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1052 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> 1053 // CHECK-BE-NEXT: ret <4 x i32> [[TMP6]] 1054 // 1055 // CHECK-LE-LABEL: @test_vec_replace_elt_ui( 1056 // CHECK-LE-NEXT: entry: 1057 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 1058 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1059 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 1060 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1061 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) 1062 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1063 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> 1064 // CHECK-LE-NEXT: ret <4 x i32> [[TMP6]] 1065 // 1066 vector unsigned int test_vec_replace_elt_ui(void) { 1067 return vec_replace_elt(vuia, uia, 1); 1068 } 1069 1070 // CHECK-BE-LABEL: @test_vec_replace_elt_f( 1071 // CHECK-BE-NEXT: entry: 1072 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 1073 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> 1074 // CHECK-BE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 1075 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 1076 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1077 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 8) 1078 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1079 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float> 1080 // CHECK-BE-NEXT: ret <4 x float> [[TMP6]] 1081 // 1082 // CHECK-LE-LABEL: @test_vec_replace_elt_f( 1083 // CHECK-LE-NEXT: entry: 1084 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 1085 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> 1086 // CHECK-LE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 1087 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 1088 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1089 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 4) 1090 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1091 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float> 1092 // CHECK-LE-NEXT: ret <4 x float> [[TMP6]] 1093 // 1094 vector float test_vec_replace_elt_f(void) { 1095 return vec_replace_elt(vfa, fa, 2); 1096 } 1097 1098 // CHECK-BE-LABEL: @test_vec_replace_elt_sll( 1099 // CHECK-BE-NEXT: entry: 1100 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 1101 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1102 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 1103 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1104 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 0) 1105 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1106 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> 1107 // CHECK-BE-NEXT: ret <2 x i64> [[TMP6]] 1108 // 1109 // CHECK-LE-LABEL: @test_vec_replace_elt_sll( 1110 // CHECK-LE-NEXT: entry: 1111 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 1112 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1113 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 1114 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1115 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 8) 1116 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1117 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> 1118 // CHECK-LE-NEXT: ret <2 x i64> [[TMP6]] 1119 // 1120 vector signed long long test_vec_replace_elt_sll(void) { 1121 return vec_replace_elt(vslla, llb, 0); 1122 } 1123 1124 // CHECK-BE-LABEL: @test_vec_replace_elt_ull( 1125 // CHECK-BE-NEXT: entry: 1126 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 1127 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1128 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 1129 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1130 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 0) 1131 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1132 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> 1133 // CHECK-BE-NEXT: ret <2 x i64> [[TMP6]] 1134 // 1135 // CHECK-LE-LABEL: @test_vec_replace_elt_ull( 1136 // CHECK-LE-NEXT: entry: 1137 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 1138 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1139 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 1140 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1141 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 8) 1142 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1143 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> 1144 // CHECK-LE-NEXT: ret <2 x i64> [[TMP6]] 1145 // 1146 vector unsigned long long test_vec_replace_elt_ull(void) { 1147 return vec_replace_elt(vulla, ulla, 0); 1148 } 1149 1150 // CHECK-BE-LABEL: @test_vec_replace_elt_d( 1151 // CHECK-BE-NEXT: entry: 1152 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 1153 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> 1154 // CHECK-BE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 1155 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 1156 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1157 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) 1158 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1159 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double> 1160 // CHECK-BE-NEXT: ret <2 x double> [[TMP6]] 1161 // 1162 // CHECK-LE-LABEL: @test_vec_replace_elt_d( 1163 // CHECK-LE-NEXT: entry: 1164 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 1165 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> 1166 // CHECK-LE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 1167 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 1168 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1169 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 0) 1170 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1171 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double> 1172 // CHECK-LE-NEXT: ret <2 x double> [[TMP6]] 1173 // 1174 vector double test_vec_replace_elt_d(void) { 1175 return vec_replace_elt(vda, da, 1); 1176 } 1177 1178 // CHECK-BE-LABEL: @test_vec_replace_unaligned_si( 1179 // CHECK-BE-NEXT: entry: 1180 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 1181 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1182 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 1183 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1184 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6) 1185 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1186 // CHECK-BE-NEXT: ret <16 x i8> [[TMP5]] 1187 // 1188 // CHECK-LE-LABEL: @test_vec_replace_unaligned_si( 1189 // CHECK-LE-NEXT: entry: 1190 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 1191 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1192 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 1193 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1194 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6) 1195 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1196 // CHECK-LE-NEXT: ret <16 x i8> [[TMP5]] 1197 // 1198 vector unsigned char test_vec_replace_unaligned_si(void) { 1199 return vec_replace_unaligned(vsia, sia, 6); 1200 } 1201 1202 // CHECK-BE-LABEL: @test_vec_replace_unaligned_ui( 1203 // CHECK-BE-NEXT: entry: 1204 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 1205 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1206 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 1207 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1208 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) 1209 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1210 // CHECK-BE-NEXT: ret <16 x i8> [[TMP5]] 1211 // 1212 // CHECK-LE-LABEL: @test_vec_replace_unaligned_ui( 1213 // CHECK-LE-NEXT: entry: 1214 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 1215 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1216 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 1217 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1218 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) 1219 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1220 // CHECK-LE-NEXT: ret <16 x i8> [[TMP5]] 1221 // 1222 vector unsigned char test_vec_replace_unaligned_ui(void) { 1223 return vec_replace_unaligned(vuia, uia, 8); 1224 } 1225 1226 // CHECK-BE-LABEL: @test_vec_replace_unaligned_f( 1227 // CHECK-BE-NEXT: entry: 1228 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 1229 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> 1230 // CHECK-BE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 1231 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 1232 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1233 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12) 1234 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1235 // CHECK-BE-NEXT: ret <16 x i8> [[TMP5]] 1236 // 1237 // CHECK-LE-LABEL: @test_vec_replace_unaligned_f( 1238 // CHECK-LE-NEXT: entry: 1239 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 1240 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> 1241 // CHECK-LE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 1242 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 1243 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1244 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12) 1245 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1246 // CHECK-LE-NEXT: ret <16 x i8> [[TMP5]] 1247 // 1248 vector unsigned char test_vec_replace_unaligned_f(void) { 1249 return vec_replace_unaligned(vfa, fa, 12); 1250 } 1251 1252 // CHECK-BE-LABEL: @test_vec_replace_unaligned_sll( 1253 // CHECK-BE-NEXT: entry: 1254 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 1255 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1256 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 1257 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1258 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 6) 1259 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1260 // CHECK-BE-NEXT: ret <16 x i8> [[TMP5]] 1261 // 1262 // CHECK-LE-LABEL: @test_vec_replace_unaligned_sll( 1263 // CHECK-LE-NEXT: entry: 1264 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 1265 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1266 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 1267 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1268 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 6) 1269 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1270 // CHECK-LE-NEXT: ret <16 x i8> [[TMP5]] 1271 // 1272 vector unsigned char test_vec_replace_unaligned_sll(void) { 1273 return vec_replace_unaligned(vslla, llb, 6); 1274 } 1275 1276 // CHECK-BE-LABEL: @test_vec_replace_unaligned_ull( 1277 // CHECK-BE-NEXT: entry: 1278 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 1279 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1280 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 1281 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1282 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 7) 1283 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1284 // CHECK-BE-NEXT: ret <16 x i8> [[TMP5]] 1285 // 1286 // CHECK-LE-LABEL: @test_vec_replace_unaligned_ull( 1287 // CHECK-LE-NEXT: entry: 1288 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 1289 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1290 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 1291 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1292 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 7) 1293 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1294 // CHECK-LE-NEXT: ret <16 x i8> [[TMP5]] 1295 // 1296 vector unsigned char test_vec_replace_unaligned_ull(void) { 1297 return vec_replace_unaligned(vulla, ulla, 7); 1298 } 1299 1300 // CHECK-BE-LABEL: @test_vec_replace_unaligned_d( 1301 // CHECK-BE-NEXT: entry: 1302 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 1303 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> 1304 // CHECK-BE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 1305 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 1306 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1307 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) 1308 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1309 // CHECK-BE-NEXT: ret <16 x i8> [[TMP5]] 1310 // 1311 // CHECK-LE-LABEL: @test_vec_replace_unaligned_d( 1312 // CHECK-LE-NEXT: entry: 1313 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 1314 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> 1315 // CHECK-LE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 1316 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 1317 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1318 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) 1319 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1320 // CHECK-LE-NEXT: ret <16 x i8> [[TMP5]] 1321 // 1322 vector unsigned char test_vec_replace_unaligned_d(void) { 1323 return vec_replace_unaligned(vda, da, 8); 1324 } 1325 1326 vector unsigned char test_vec_insertl_uc(void) { 1327 // CHECK-BE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32 1328 // CHECK-BE-NEXT: ret <16 x i8> 1329 // CHECK-LE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32 1330 // CHECK-LE-NEXT: ret <16 x i8> 1331 return vec_insertl(uca, vuca, uia); 1332 } 1333 1334 vector unsigned short test_vec_insertl_us(void) { 1335 // CHECK-BE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32 1336 // CHECK-BE-NEXT: ret <8 x i16> 1337 // CHECK-LE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32 1338 // CHECK-LE-NEXT: ret <8 x i16> 1339 return vec_insertl(usa, vusa, uia); 1340 } 1341 1342 vector unsigned int test_vec_insertl_ui(void) { 1343 // CHECK-BE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 1344 // CHECK-BE-NEXT: ret <4 x i32> 1345 // CHECK-LE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 1346 // CHECK-LE-NEXT: ret <4 x i32> 1347 return vec_insertl(uib, vuia, uia); 1348 } 1349 1350 vector unsigned long long test_vec_insertl_ul(void) { 1351 // CHECK-BE: @llvm.ppc.altivec.vinsdlx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64 1352 // CHECK-BE-NEXT: ret <2 x i64> 1353 // CHECK-LE: @llvm.ppc.altivec.vinsdrx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64 1354 // CHECK-LE-NEXT: ret <2 x i64> 1355 return vec_insertl(ulla, vulla, uia); 1356 } 1357 1358 vector unsigned char test_vec_insertl_ucv(void) { 1359 // CHECK-BE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 x i8> 1360 // CHECK-BE-NEXT: ret <16 x i8> 1361 // CHECK-LE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 x i8> 1362 // CHECK-LE-NEXT: ret <16 x i8> 1363 return vec_insertl(vuca, vucb, uia); 1364 } 1365 1366 vector unsigned short test_vec_insertl_usv(void) { 1367 // CHECK-BE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x i16> 1368 // CHECK-BE-NEXT: ret <8 x i16> 1369 // CHECK-LE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x i16> 1370 // CHECK-LE-NEXT: ret <8 x i16> 1371 return vec_insertl(vusa, vusb, uia); 1372 } 1373 1374 vector unsigned int test_vec_insertl_uiv(void) { 1375 // CHECK-BE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> 1376 // CHECK-BE-NEXT: ret <4 x i32> 1377 // CHECK-LE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> 1378 // CHECK-LE-NEXT: ret <4 x i32> 1379 return vec_insertl(vuia, vuib, uia); 1380 } 1381 1382 vector unsigned char test_vec_inserth_uc(void) { 1383 // CHECK-BE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32 1384 // CHECK-BE-NEXT: ret <16 x i8> 1385 // CHECK-LE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32 1386 // CHECK-LE-NEXT: ret <16 x i8> 1387 return vec_inserth(uca, vuca, uia); 1388 } 1389 1390 vector unsigned short test_vec_inserth_us(void) { 1391 // CHECK-BE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32 1392 // CHECK-BE-NEXT: ret <8 x i16> 1393 // CHECK-LE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32 1394 // CHECK-LE-NEXT: ret <8 x i16> 1395 return vec_inserth(usa, vusa, uia); 1396 } 1397 1398 vector unsigned int test_vec_inserth_ui(void) { 1399 // CHECK-BE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 1400 // CHECK-BE-NEXT: ret <4 x i32> 1401 // CHECK-LE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 1402 // CHECK-LE-NEXT: ret <4 x i32> 1403 return vec_inserth(uib, vuia, uia); 1404 } 1405 1406 vector unsigned long long test_vec_inserth_ul(void) { 1407 // CHECK-BE: @llvm.ppc.altivec.vinsdrx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64 1408 // CHECK-BE-NEXT: ret <2 x i64> 1409 // CHECK-LE: @llvm.ppc.altivec.vinsdlx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64 1410 // CHECK-LE-NEXT: ret <2 x i64> 1411 return vec_inserth(ulla, vulla, uia); 1412 } 1413 1414 vector unsigned char test_vec_inserth_ucv(void) { 1415 // CHECK-BE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 x i8> 1416 // CHECK-BE-NEXT: ret <16 x i8> 1417 // CHECK-LE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 x i8> 1418 // CHECK-LE-NEXT: ret <16 x i8> 1419 return vec_inserth(vuca, vucb, uia); 1420 } 1421 1422 vector unsigned short test_vec_inserth_usv(void) { 1423 // CHECK-BE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x i16> 1424 // CHECK-BE-NEXT: ret <8 x i16> 1425 // CHECK-LE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x i16> 1426 // CHECK-LE-NEXT: ret <8 x i16> 1427 return vec_inserth(vusa, vusb, uia); 1428 } 1429 1430 vector unsigned int test_vec_inserth_uiv(void) { 1431 // CHECK-BE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> 1432 // CHECK-BE-NEXT: ret <4 x i32> 1433 // CHECK-LE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> 1434 // CHECK-LE-NEXT: ret <4 x i32> 1435 return vec_inserth(vuia, vuib, uia); 1436 } 1437 1438 vector unsigned long long test_vec_extractl_uc(void) { 1439 // CHECK-BE: @llvm.ppc.altivec.vextdubvlx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 1440 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1441 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1442 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1443 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1444 // CHECK-BE: ret <2 x i64> 1445 // CHECK-LE: @llvm.ppc.altivec.vextdubvrx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 1446 // CHECK-LE-NEXT: ret <2 x i64> 1447 return vec_extractl(vuca, vucb, uia); 1448 } 1449 1450 vector unsigned long long test_vec_extractl_us(void) { 1451 // CHECK-BE: @llvm.ppc.altivec.vextduhvlx(<8 x i16> %{{.+}}, <8 x i16> %{{.+}}, i32 1452 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1453 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1454 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1455 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1456 // CHECK-BE: ret <2 x i64> 1457 // CHECK-LE: @llvm.ppc.altivec.vextduhvrx(<8 x i16> %{{.+}}, <8 x i16> %{{.+}}, i32 1458 // CHECK-LE-NEXT: ret <2 x i64> 1459 return vec_extractl(vusa, vusb, uia); 1460 } 1461 1462 vector unsigned long long test_vec_extractl_ui(void) { 1463 // CHECK-BE: @llvm.ppc.altivec.vextduwvlx(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, i32 1464 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1465 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1466 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1467 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1468 // CHECK-BE: ret <2 x i64> 1469 // CHECK-LE: @llvm.ppc.altivec.vextduwvrx(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, i32 1470 // CHECK-LE-NEXT: ret <2 x i64> 1471 return vec_extractl(vuia, vuib, uia); 1472 } 1473 1474 vector unsigned long long test_vec_extractl_ul(void) { 1475 // CHECK-BE: @llvm.ppc.altivec.vextddvlx(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 1476 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1477 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1478 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1479 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1480 // CHECK-BE: ret <2 x i64> 1481 // CHECK-LE: @llvm.ppc.altivec.vextddvrx(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 1482 // CHECK-LE-NEXT: ret <2 x i64> 1483 return vec_extractl(vulla, vullb, uia); 1484 } 1485 1486 vector unsigned long long test_vec_extracth_uc(void) { 1487 // CHECK-BE: @llvm.ppc.altivec.vextdubvrx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 1488 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1489 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1490 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1491 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1492 // CHECK-BE: ret <2 x i64> 1493 // CHECK-LE: @llvm.ppc.altivec.vextdubvlx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 1494 // CHECK-LE-NEXT: ret <2 x i64> 1495 return vec_extracth(vuca, vucb, uia); 1496 } 1497 1498 vector unsigned long long test_vec_extracth_us(void) { 1499 // CHECK-BE: @llvm.ppc.altivec.vextduhvrx(<8 x i16> %{{.+}}, <8 x i16> %{{.+}}, i32 1500 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1501 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1502 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1503 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1504 // CHECK-BE: ret <2 x i64> 1505 // CHECK-LE: @llvm.ppc.altivec.vextduhvlx(<8 x i16> %{{.+}}, <8 x i16> %{{.+}}, i32 1506 // CHECK-LE-NEXT: ret <2 x i64> 1507 return vec_extracth(vusa, vusb, uia); 1508 } 1509 1510 vector unsigned long long test_vec_extracth_ui(void) { 1511 // CHECK-BE: @llvm.ppc.altivec.vextduwvrx(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, i32 1512 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1513 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1514 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1515 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1516 // CHECK-BE: ret <2 x i64> 1517 // CHECK-LE: @llvm.ppc.altivec.vextduwvlx(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, i32 1518 // CHECK-LE-NEXT: ret <2 x i64> 1519 return vec_extracth(vuia, vuib, uia); 1520 } 1521 1522 vector unsigned long long test_vec_extracth_ul(void) { 1523 // CHECK-BE: @llvm.ppc.altivec.vextddvrx(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 1524 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1525 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1526 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1527 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1528 // CHECK-BE: ret <2 x i64> 1529 // CHECK-LE: @llvm.ppc.altivec.vextddvlx(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 1530 // CHECK-LE-NEXT: ret <2 x i64> 1531 return vec_extracth(vulla, vullb, uia); 1532 } 1533 1534 vector signed int test_vec_vec_splati_si(void) { 1535 // CHECK: ret <4 x i32> <i32 -17, i32 -17, i32 -17, i32 -17> 1536 return vec_splati(-17); 1537 } 1538 1539 vector unsigned int test_vec_vec_splati_ui(void) { 1540 // CHECK: ret <4 x i32> <i32 16, i32 16, i32 16, i32 16> 1541 return vec_splati(16U); 1542 } 1543 1544 vector float test_vec_vec_splati_f(void) { 1545 // CHECK: ret <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> 1546 return vec_splati(1.0f); 1547 } 1548 1549 vector double test_vec_vec_splatid(void) { 1550 // CHECK-BE: [[T1:%.+]] = fpext float %{{.+}} to double 1551 // CHECK-BE-NEXT: [[T2:%.+]] = insertelement <2 x double> poison, double [[T1:%.+]], i32 0 1552 // CHECK-BE-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x double> poison, <2 x i32> zeroinitialize 1553 // CHECK-BE-NEXT: ret <2 x double> [[T3:%.+]] 1554 // CHECK-LE: [[T1:%.+]] = fpext float %{{.+}} to double 1555 // CHECK-LE-NEXT: [[T2:%.+]] = insertelement <2 x double> poison, double [[T1:%.+]], i32 0 1556 // CHECK-LE-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x double> poison, <2 x i32> zeroinitialize 1557 // CHECK-LE-NEXT: ret <2 x double> [[T3:%.+]] 1558 return vec_splatid(1.0); 1559 } 1560 1561 vector signed int test_vec_vec_splati_ins_si(void) { 1562 // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1 1563 // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}} 1564 // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}} 1565 // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] 1566 // CHECK-BE: ret <4 x i32> 1567 // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1 1568 // CHECK-LE: [[T1:%.+]] = sub i32 1, %{{.+}} 1569 // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] 1570 // CHECK-LE: [[T2:%.+]] = sub i32 3, %{{.+}} 1571 // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]] 1572 // CHECK-LE: ret <4 x i32> 1573 return vec_splati_ins(vsia, 0, -17); 1574 } 1575 1576 vector unsigned int test_vec_vec_splati_ins_ui(void) { 1577 // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1 1578 // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}} 1579 // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}} 1580 // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] 1581 // CHECK-BE: ret <4 x i32> 1582 // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1 1583 // CHECK-LE: [[T1:%.+]] = sub i32 1, %{{.+}} 1584 // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] 1585 // CHECK-LE: [[T2:%.+]] = sub i32 3, %{{.+}} 1586 // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]] 1587 // CHECK-LE: ret <4 x i32> 1588 return vec_splati_ins(vuia, 1, 16U); 1589 } 1590 1591 vector float test_vec_vec_splati_ins_f(void) { 1592 // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1 1593 // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}} 1594 // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}} 1595 // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]] 1596 // CHECK-BE: ret <4 x float> 1597 // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1 1598 // CHECK-LE: [[T1:%.+]] = sub i32 1, %{{.+}} 1599 // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]] 1600 // CHECK-LE: [[T2:%.+]] = sub i32 3, %{{.+}} 1601 // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T2]] 1602 // CHECK-LE: ret <4 x float> 1603 return vec_splati_ins(vfa, 0, 1.0f); 1604 } 1605 1606 // In this test case, the second argument of vec_splati_ins is outside of the 1607 // expected range [0,1]. A mask of 0x01 is applied to obtain an in-range value 1608 // for the second argument. 1609 vector signed int test_vec_vec_splati_ins_range(void) { 1610 // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1 1611 // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}} 1612 // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}} 1613 // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] 1614 // CHECK-BE: ret <4 x i32> 1615 // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1 1616 // CHECK-LE: [[T1:%.+]] = sub i32 1, %{{.+}} 1617 // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] 1618 // CHECK-LE: [[T2:%.+]] = sub i32 3, %{{.+}} 1619 // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]] 1620 // CHECK-LE: ret <4 x i32> 1621 return vec_splati_ins(vsia, 2, -17); 1622 } 1623 1624 void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b, 1625 signed char *__c) { 1626 // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1 1627 vec_xst_trunc(__a, __b, __c); 1628 } 1629 1630 void test_vec_xst_trunc_uc(vector unsigned __int128 __a, signed long long __b, 1631 unsigned char *__c) { 1632 // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1 1633 vec_xst_trunc(__a, __b, __c); 1634 } 1635 1636 void test_vec_xst_trunc_ss(vector signed __int128 __a, signed long long __b, 1637 signed short *__c) { 1638 // CHECK: store i16 %{{.+}}, i16* %{{.+}}, align 2 1639 vec_xst_trunc(__a, __b, __c); 1640 } 1641 1642 void test_vec_xst_trunc_us(vector unsigned __int128 __a, signed long long __b, 1643 unsigned short *__c) { 1644 // CHECK: store i16 %{{.+}}, i16* %{{.+}}, align 2 1645 vec_xst_trunc(__a, __b, __c); 1646 } 1647 1648 void test_vec_xst_trunc_si(vector signed __int128 __a, signed long long __b, 1649 signed int *__c) { 1650 // CHECK: store i32 %{{.+}}, i32* %{{.+}}, align 4 1651 vec_xst_trunc(__a, __b, __c); 1652 } 1653 1654 void test_vec_xst_trunc_ui(vector unsigned __int128 __a, signed long long __b, 1655 unsigned int *__c) { 1656 // CHECK: store i32 %{{.+}}, i32* %{{.+}}, align 4 1657 vec_xst_trunc(__a, __b, __c); 1658 } 1659 1660 void test_vec_xst_trunc_sll(vector signed __int128 __a, signed long long __b, 1661 signed long long *__c) { 1662 // CHECK: store i64 %{{.+}}, i64* %{{.+}}, align 8 1663 vec_xst_trunc(__a, __b, __c); 1664 } 1665 1666 void test_vec_xst_trunc_ull(vector unsigned __int128 __a, signed long long __b, 1667 unsigned long long *__c) { 1668 // CHECK: store i64 %{{.+}}, i64* %{{.+}}, align 8 1669 vec_xst_trunc(__a, __b, __c); 1670 } 1671 1672 vector unsigned __int128 test_vec_slq_unsigned (void) { 1673 // CHECK-LABEL: test_vec_slq_unsigned 1674 // CHECK: shl <1 x i128> %{{.+}}, %{{.+}} 1675 // CHECK: ret <1 x i128> %{{.+}} 1676 return vec_sl(vui128a, vui128b); 1677 } 1678 1679 vector signed __int128 test_vec_slq_signed (void) { 1680 // CHECK-LABEL: test_vec_slq_signed 1681 // CHECK: shl <1 x i128> %{{.+}}, %{{.+}} 1682 // CHECK: ret <1 x i128> 1683 return vec_sl(vi128a, vui128a); 1684 } 1685 1686 vector unsigned __int128 test_vec_srq_unsigned (void) { 1687 // CHECK-LABEL: test_vec_srq_unsigned 1688 // CHECK: lshr <1 x i128> %{{.+}}, %{{.+}} 1689 // CHECK: ret <1 x i128> 1690 return vec_sr(vui128a, vui128b); 1691 } 1692 1693 vector signed __int128 test_vec_srq_signed (void) { 1694 // CHECK-LABEL: test_vec_srq_signed 1695 // CHECK: lshr <1 x i128> %{{.+}}, %{{.+}} 1696 // CHECK: ret <1 x i128> 1697 return vec_sr(vi128a, vui128a); 1698 } 1699 1700 vector unsigned __int128 test_vec_sraq_unsigned (void) { 1701 // CHECK-LABEL: test_vec_sraq_unsigned 1702 // CHECK: ashr <1 x i128> %{{.+}}, %{{.+}} 1703 // CHECK: ret <1 x i128> 1704 return vec_sra(vui128a, vui128b); 1705 } 1706 1707 vector signed __int128 test_vec_sraq_signed (void) { 1708 // CHECK-LABEL: test_vec_sraq_signed 1709 // CHECK: ashr <1 x i128> %{{.+}}, %{{.+}} 1710 // CHECK: ret <1 x i128> 1711 return vec_sra(vi128a, vui128a); 1712 } 1713 1714 1715 int test_vec_test_lsbb_all_ones(void) { 1716 // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i32 1 1717 // CHECK-NEXT: ret i32 1718 return vec_test_lsbb_all_ones(vuca); 1719 } 1720 1721 int test_vec_test_lsbb_all_zeros(void) { 1722 // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i32 0 1723 // CHECK-NEXT: ret i32 1724 return vec_test_lsbb_all_zeros(vuca); 1725 } 1726 1727 vector unsigned __int128 test_vec_mule_u128(void) { 1728 // CHECK-BE: @llvm.ppc.altivec.vmuleud(<2 x i64> 1729 // CHECK-BE-NEXT: ret <1 x i128> 1730 // CHECK-LE: @llvm.ppc.altivec.vmuloud(<2 x i64> 1731 // CHECK-LE-NEXT: ret <1 x i128> 1732 return vec_mule(vulla, vullb); 1733 } 1734 1735 vector signed __int128 test_vec_mule_s128(void) { 1736 // CHECK-BE: @llvm.ppc.altivec.vmulesd(<2 x i64> 1737 // CHECK-BE-NEXT: ret <1 x i128> 1738 // CHECK-LE: @llvm.ppc.altivec.vmulosd(<2 x i64> 1739 // CHECK-LE-NEXT: ret <1 x i128> 1740 return vec_mule(vslla, vsllb); 1741 } 1742 1743 vector unsigned __int128 test_vec_mulo_u128(void) { 1744 // CHECK-BE: @llvm.ppc.altivec.vmuloud(<2 x i64> 1745 // CHECK-BE-NEXT: ret <1 x i128> 1746 // CHECK-LE: @llvm.ppc.altivec.vmuleud(<2 x i64> 1747 // CHECK-LE-NEXT: ret <1 x i128> 1748 return vec_mulo(vulla, vullb); 1749 } 1750 1751 vector signed __int128 test_vec_mulo_s128(void) { 1752 // CHECK-BE: @llvm.ppc.altivec.vmulosd(<2 x i64> 1753 // CHECK-BE-NEXT: ret <1 x i128> 1754 // CHECK-LE: @llvm.ppc.altivec.vmulesd(<2 x i64> 1755 // CHECK-LE-NEXT: ret <1 x i128> 1756 return vec_mulo(vslla, vsllb); 1757 } 1758 1759 vector unsigned __int128 test_vec_msumc_u128(void) { 1760 // CHECK: @llvm.ppc.altivec.vmsumcud(<2 x i64> 1761 // CHECK-NEXT: ret <1 x i128> 1762 return vec_msumc(vulla, vullb, vui128a); 1763 } 1764 1765 vector signed __int128 test_vec_xl_sext_i8(void) { 1766 // CHECK: load i8 1767 // CHECK: sext i8 1768 // CHECK: ret <1 x i128> 1769 return vec_xl_sext(llb, cap); 1770 } 1771 1772 vector signed __int128 test_vec_xl_sext_i16(void) { 1773 // CHECK: load i16 1774 // CHECK: sext i16 1775 // CHECK: ret <1 x i128> 1776 return vec_xl_sext(llb, sap); 1777 } 1778 1779 vector signed __int128 test_vec_xl_sext_i32(void) { 1780 // CHECK: load i32 1781 // CHECK: sext i32 1782 // CHECK: ret <1 x i128> 1783 return vec_xl_sext(llb, iap); 1784 } 1785 1786 vector signed __int128 test_vec_xl_sext_i64(void) { 1787 // CHECK: load i64 1788 // CHECK: sext i64 1789 // CHECK: ret <1 x i128> 1790 return vec_xl_sext(llb, llap); 1791 } 1792 1793 vector unsigned __int128 test_vec_xl_zext_i8(void) { 1794 // CHECK: load i8 1795 // CHECK: zext i8 1796 // CHECK: ret <1 x i128> 1797 return vec_xl_zext(llb, ucap); 1798 } 1799 1800 vector unsigned __int128 test_vec_xl_zext_i16(void) { 1801 // CHECK: load i16 1802 // CHECK: zext i16 1803 // CHECK: ret <1 x i128> 1804 return vec_xl_zext(llb, usap); 1805 } 1806 1807 vector unsigned __int128 test_vec_xl_zext_i32(void) { 1808 // CHECK: load i32 1809 // CHECK: zext i32 1810 // CHECK: ret <1 x i128> 1811 return vec_xl_zext(llb, uiap); 1812 } 1813 1814 vector unsigned __int128 test_vec_xl_zext_i64(void) { 1815 // CHECK: load i64 1816 // CHECK: zext i64 1817 // CHECK: ret <1 x i128> 1818 return vec_xl_zext(llb, ullap); 1819 } 1820 1821 vector signed __int128 test_vec_signextq_s128(void) { 1822 // CHECK: @llvm.ppc.altivec.vextsd2q(<2 x i64> 1823 // CHECK-NEXT: ret <1 x i128> 1824 return vec_signextq(vslla); 1825 } 1826 1827 vector unsigned __int128 test_vec_mod_u128(void) { 1828 // CHECK: urem <1 x i128> 1829 // CHECK-NEXT: ret <1 x i128> 1830 return vec_mod(vui128a, vui128b); 1831 } 1832 1833 vector signed __int128 test_vec_mod_s128(void) { 1834 // CHECK: srem <1 x i128> 1835 // CHECK-NEXT: ret <1 x i128> 1836 return vec_mod(vsi128a, vsi128b); 1837 } 1838 1839 vector bool __int128 test_vec_cmpeq_s128(void) { 1840 // CHECK-LABEL: @test_vec_cmpeq_s128( 1841 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> 1842 // CHECK-NEXT: ret <1 x i128> 1843 return vec_cmpeq(vsi128a, vsi128b); 1844 } 1845 1846 vector bool __int128 test_vec_cmpeq_u128(void) { 1847 // CHECK-LABEL: @test_vec_cmpeq_u128( 1848 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> 1849 // CHECK-NEXT: ret <1 x i128> 1850 return vec_cmpeq(vui128a, vui128b); 1851 } 1852 1853 vector bool __int128 test_vec_cmpeq_bool_int128(void) { 1854 // CHECK-LABEL: @test_vec_cmpeq_bool_int128( 1855 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> 1856 // CHECK-NEXT: ret <1 x i128> 1857 return vec_cmpeq(vbi128a, vbi128b); 1858 } 1859 1860 vector bool __int128 test_vec_cmpne_s128(void) { 1861 // CHECK-LABEL: @test_vec_cmpne_s128( 1862 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> 1863 // CHECK-NEXT: %neg.i = xor <1 x i128> %4, <i128 -1> 1864 // CHECK-NEXT: ret <1 x i128> %neg.i 1865 return vec_cmpne(vsi128a, vsi128b); 1866 } 1867 1868 vector bool __int128 test_vec_cmpne_u128(void) { 1869 // CHECK-LABEL: @test_vec_cmpne_u128( 1870 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> 1871 // CHECK-NEXT: %neg.i = xor <1 x i128> %4, <i128 -1> 1872 // CHECK-NEXT: ret <1 x i128> 1873 return vec_cmpne(vui128a, vui128b); 1874 } 1875 1876 vector bool __int128 test_vec_cmpne_bool_int128(void) { 1877 // CHECK-LABEL: @test_vec_cmpne_bool_int128( 1878 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> 1879 // CHECK-NEXT: %neg.i = xor <1 x i128> %4, <i128 -1> 1880 // CHECK-NEXT: ret <1 x i128> 1881 return vec_cmpne(vbi128a, vbi128b); 1882 } 1883 1884 vector bool __int128 test_vec_cmpgt_s128(void) { 1885 // CHECK-LABEL: @test_vec_cmpgt_s128( 1886 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128> 1887 // CHECK-NEXT: ret <1 x i128> 1888 return vec_cmpgt(vsi128a, vsi128b); 1889 } 1890 1891 vector bool __int128 test_vec_cmpgt_u128(void) { 1892 // CHECK-LABEL: @test_vec_cmpgt_u128( 1893 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128> 1894 // CHECK-NEXT: ret <1 x i128> 1895 return vec_cmpgt(vui128a, vui128b); 1896 } 1897 1898 vector bool __int128 test_vec_cmplt_s128(void) { 1899 // CHECK-LABEL: @test_vec_cmplt_s128( 1900 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128> 1901 // CHECK-NEXT: ret <1 x i128> 1902 return vec_cmplt(vsi128a, vsi128b); 1903 } 1904 1905 vector bool __int128 test_vec_cmplt_u128(void) { 1906 // CHECK-LABEL: @test_vec_cmplt_u128( 1907 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128> 1908 // CHECK-NEXT: ret <1 x i128> 1909 return vec_cmplt(vui128a, vui128b); 1910 } 1911 1912 vector bool __int128 test_vec_cmpge_s128(void) { 1913 // CHECK-LABEL: @test_vec_cmpge_s128( 1914 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128> 1915 // CHECK-NEXT: %neg.i = xor <1 x i128> %6, <i128 -1> 1916 // CHECK-NEXT: ret <1 x i128> 1917 return vec_cmpge(vsi128a, vsi128b); 1918 } 1919 1920 vector bool __int128 test_vec_cmpge_u128(void) { 1921 // CHECK-LABEL: @test_vec_cmpge_u128( 1922 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128> 1923 // CHECK-NEXT: %neg.i = xor <1 x i128> %6, <i128 -1> 1924 // CHECK-NEXT: ret <1 x i128> 1925 return vec_cmpge(vui128a, vui128b); 1926 } 1927 1928 vector bool __int128 test_vec_cmple_s128(void) { 1929 // CHECK-LABEL: @test_vec_cmple_s128( 1930 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128> 1931 // CHECK-NEXT: %neg.i.i = xor <1 x i128> %8, <i128 -1> 1932 // CHECK-NEXT: ret <1 x i128> 1933 return vec_cmple(vsi128a, vsi128b); 1934 } 1935 1936 vector bool __int128 test_vec_cmple_u128(void) { 1937 // CHECK-LABEL: @test_vec_cmple_u128( 1938 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128> 1939 // CHECK-NEXT: %neg.i.i = xor <1 x i128> %8, <i128 -1> 1940 // CHECK-NEXT: ret <1 x i128> 1941 return vec_cmple(vui128a, vui128b); 1942 } 1943 1944 int test_vec_any_eq_u128(void) { 1945 // CHECK-LABEL: @test_vec_any_eq_u128( 1946 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 1947 // CHECK-NEXT: ret i32 1948 return vec_any_eq(vui128a, vui128b); 1949 } 1950 1951 int test_vec_any_eq_s128(void) { 1952 // CHECK-LABEL: @test_vec_any_eq_s128( 1953 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 1954 // CHECK-NEXT: ret i32 1955 return vec_any_eq(vsi128a, vsi128b); 1956 } 1957 1958 int test_vec_any_eq_bool_int128(void) { 1959 // CHECK-LABEL: @test_vec_any_eq_bool_int128( 1960 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 1961 // CHECK-NEXT: ret i32 1962 return vec_any_eq(vbi128a, vbi128b); 1963 } 1964 1965 int test_vec_any_ne_s128(void) { 1966 // CHECK-LABEL: @test_vec_any_ne_s128( 1967 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 1968 // CHECK-NEXT: ret i32 1969 return vec_any_ne(vsi128a, vsi128b); 1970 } 1971 1972 int test_vec_any_ne_u128(void) { 1973 // CHECK-LABEL: @test_vec_any_ne_u128( 1974 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 1975 // CHECK-NEXT: ret i32 1976 return vec_any_ne(vui128a, vui128b); 1977 } 1978 1979 int test_vec_any_ne_bool_int128(void) { 1980 // CHECK-LABEL: @test_vec_any_ne_bool_int128( 1981 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 1982 // CHECK-NEXT: ret i32 1983 return vec_any_ne(vbi128a, vbi128b); 1984 } 1985 1986 int test_vec_any_lt_s128(void) { 1987 // CHECK-LABEL: @test_vec_any_lt_s128( 1988 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 1989 // CHECK-NEXT: ret i32 1990 return vec_any_lt(vsi128a, vsi128b); 1991 } 1992 1993 int test_vec_any_lt_u128(void) { 1994 // CHECK-LABEL: @test_vec_any_lt_u128( 1995 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 1996 // CHECK-NEXT: ret i32 1997 return vec_any_lt(vui128a, vui128b); 1998 } 1999 2000 int test_vec_any_gt_s128(void) { 2001 // CHECK-LABEL: @test_vec_any_gt_s128( 2002 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 2003 // CHECK-NEXT: ret i32 2004 return vec_any_gt(vsi128a, vsi128b); 2005 } 2006 2007 int test_vec_any_gt_u128(void) { 2008 // CHECK-LABEL: @test_vec_any_gt_u128( 2009 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 2010 // CHECK-NEXT: ret i32 2011 return vec_any_gt(vui128a, vui128b); 2012 } 2013 2014 int test_vec_any_le_s128(void) { 2015 // CHECK-LABEL: @test_vec_any_le_s128( 2016 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 2017 // CHECK-NEXT: ret i32 2018 return vec_any_le(vsi128a, vsi128b); 2019 } 2020 2021 int test_vec_any_le_u128(void) { 2022 // CHECK-LABEL: @test_vec_any_le_u128( 2023 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 2024 // CHECK-NEXT: ret i32 2025 return vec_any_le(vui128a, vui128b); 2026 } 2027 2028 int test_vec_any_ge_s128(void) { 2029 // CHECK-LABEL: @test_vec_any_ge_s128( 2030 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 2031 // CHECK-NEXT: ret i32 2032 return vec_any_ge(vsi128a, vsi128b); 2033 } 2034 2035 int test_vec_any_ge_u128(void) { 2036 // CHECK-LABEL: @test_vec_any_ge_u128( 2037 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 2038 // CHECK-NEXT: ret i32 2039 return vec_any_ge(vui128a, vui128b); 2040 } 2041 2042 int test_vec_all_eq_s128(void) { 2043 // CHECK-LABEL: @test_vec_all_eq_s128( 2044 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2045 // CHECK-NEXT: ret i32 2046 return vec_all_eq(vsi128a, vsi128b); 2047 } 2048 2049 int test_vec_all_eq_u128(void) { 2050 // CHECK-LABEL: @test_vec_all_eq_u128( 2051 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2052 // CHECK-NEXT: ret i32 2053 return vec_all_eq(vui128a, vui128b); 2054 } 2055 2056 int test_vec_all_eq_bool_int128(void) { 2057 // CHECK-LABEL: @test_vec_all_eq_bool_int128 2058 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2059 // CHECK-NEXT: ret i32 2060 return vec_all_eq(vbi128a, vbi128b); 2061 } 2062 2063 int test_vec_all_ne_s128(void) { 2064 // CHECK-LABEL: @test_vec_all_ne_s128( 2065 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2066 // CHECK-NEXT: ret i32 2067 return vec_all_ne(vsi128a, vsi128b); 2068 } 2069 2070 int test_vec_all_ne_u128(void) { 2071 // CHECK-LABEL: @test_vec_all_ne_u128( 2072 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2073 // CHECK-NEXT: ret i32 2074 return vec_all_ne(vui128a, vui128b); 2075 } 2076 2077 int test_vec_all_ne_bool_int128(void) { 2078 // CHECK-LABEL: test_vec_all_ne_bool_int128 2079 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2080 // CHECK-NEXT: ret i32 2081 return vec_all_ne(vbi128a, vbi128b); 2082 } 2083 2084 int test_vec_all_lt_s128(void) { 2085 // CHECK-LABEL: @test_vec_all_lt_s128( 2086 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2087 // CHECK-NEXT: ret i32 2088 return vec_all_lt(vsi128a, vsi128b); 2089 } 2090 2091 int test_vec_all_lt_u128(void) { 2092 // CHECK-LABEL: @test_vec_all_lt_u128( 2093 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2094 // CHECK: ret i32 2095 return vec_all_lt(vui128a, vui128b); 2096 } 2097 2098 int test_vec_all_gt_s128(void) { 2099 // CHECK-LABEL: @test_vec_all_gt_s128( 2100 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2101 // CHECK-NEXT: ret i32 2102 return vec_all_gt(vsi128a, vsi128b); 2103 } 2104 2105 int test_vec_all_gt_u128(void) { 2106 // CHECK-LABEL: @test_vec_all_gt_u128( 2107 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2108 // CHECK-NEXT: ret i32 2109 return vec_all_gt(vui128a, vui128b); 2110 } 2111 2112 int test_vec_all_le_s128(void) { 2113 // CHECK-LABEL: @test_vec_all_le_s128( 2114 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2115 // CHECK-NEXT: ret i32 2116 return vec_all_le(vsi128a, vsi128b); 2117 } 2118 2119 int test_vec_all_le_u128(void) { 2120 // CHECK-LABEL: @test_vec_all_le_u128( 2121 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2122 // CHECK-NEXT: ret i32 2123 return vec_all_le(vui128a, vui128b); 2124 } 2125 2126 int test_vec_all_ge_s128(void) { 2127 // CHECK-LABEL: @test_vec_all_ge_s128( 2128 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2129 // CHECK-NEXT: ret i32 2130 return vec_all_ge(vsi128a, vsi128b); 2131 } 2132 2133 int test_vec_all_ge_u128(void) { 2134 // CHECK-LABEL: @test_vec_all_ge_u128( 2135 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2136 // CHECK-NEXT: ret i32 2137 return vec_all_ge(vui128a, vui128b); 2138 } 2139 2140 vector signed __int128 test_vec_rl_s128(void) { 2141 // CHECK-LABEL: @test_vec_rl_s128( 2142 // CHECK: sub <1 x i128> 2143 // CHECK-NEXT: lshr <1 x i128> 2144 // CHECK-NEXT: or <1 x i128> 2145 // CHECK-NEXT: ret <1 x i128> 2146 return vec_rl(vsi128a, vui128b); 2147 } 2148 2149 vector unsigned __int128 test_vec_rl_u128(void) { 2150 // CHECK-LABEL: @test_vec_rl_u128( 2151 // CHECK: sub <1 x i128> 2152 // CHECK: lshr <1 x i128> 2153 // CHECK: or <1 x i128> 2154 // CHECK-NEXT: ret <1 x i128> 2155 return vec_rl(vui128a, vui128b); 2156 } 2157 2158 vector signed __int128 test_vec_rlnm_s128(void) { 2159 // CHECK-LABEL: @test_vec_rlnm_s128( 2160 // CHECK-LE: %shuffle.i = shufflevector <16 x i8> %7, <16 x i8> %8, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 2161 // CHECK-BE: %shuffle.i = shufflevector <16 x i8> %7, <16 x i8> %8, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 31, i32 30, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 2162 // CHECK: call <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128> 2163 // CHECK-NEXT: ret <1 x i128> 2164 return vec_rlnm(vsi128a, vsi128b, vsi128c); 2165 } 2166 2167 vector unsigned __int128 test_vec_rlnm_u128(void) { 2168 // CHECK-LABEL: @test_vec_rlnm_u128( 2169 // CHECK-LE: %shuffle.i = shufflevector <16 x i8> %7, <16 x i8> %8, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 2170 // CHECK-BE: %shuffle.i = shufflevector <16 x i8> %7, <16 x i8> %8, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 31, i32 30, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 2171 // CHECK: call <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128> 2172 // CHECK-NEXT: ret <1 x i128> 2173 return vec_rlnm(vui128a, vui128b, vui128c); 2174 } 2175 2176 vector signed __int128 test_vec_rlmi_s128(void) { 2177 // CHECK-LABEL: @test_vec_rlmi_s128( 2178 // CHECK: call <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128> 2179 // CHECK-NEXT: ret <1 x i128> 2180 return vec_rlmi(vsi128a, vsi128b, vsi128c); 2181 } 2182 2183 vector unsigned __int128 test_vec_rlmi_u128(void) { 2184 // CHECK-LABEL: @test_vec_rlmi_u128( 2185 // CHECK: call <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128> 2186 // CHECK-NEXT: ret <1 x i128> 2187 return vec_rlmi(vui128a, vui128b, vui128c); 2188 } 2189