1 // REQUIRES: powerpc-registered-target 2 // RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +vsx \ 3 // RUN: -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \ 4 // RUN: -o - | FileCheck %s -check-prefixes=CHECK-BE,CHECK 5 // RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +vsx \ 6 // RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \ 7 // RUN: -o - | FileCheck %s -check-prefixes=CHECK-LE,CHECK 8 9 #include <altivec.h> 10 11 vector signed __int128 vi128a; 12 vector signed char vsca, vscb; 13 vector unsigned char vuca, vucb, vucc; 14 vector signed short vssa, vssb; 15 vector unsigned short vusa, vusb, vusc; 16 vector signed int vsia, vsib; 17 vector unsigned int vuia, vuib, vuic; 18 vector signed long long vslla, vsllb; 19 vector unsigned long long vulla, vullb, vullc; 20 vector signed __int128 vsi128a, vsi128b, vsi128c; 21 vector unsigned __int128 vui128a, vui128b, vui128c; 22 vector bool __int128 vbi128a, vbi128b; 23 vector float vfa, vfb; 24 vector double vda, vdb; 25 float fa; 26 double da; 27 signed int sia; 28 signed int *iap; 29 unsigned int uia, uib, *uiap; 30 signed char *cap; 31 unsigned char uca; 32 const unsigned char *ucap; 33 const signed short *sap; 34 unsigned short usa; 35 const unsigned short *usap; 36 const signed long long *llap; 37 signed long long llb; 38 unsigned long long ulla; 39 const unsigned long long *ullap; 40 41 vector signed long long test_vec_mul_sll(void) { 42 // CHECK: mul <2 x i64> 43 // CHECK-NEXT: ret <2 x i64> 44 return vec_mul(vslla, vsllb); 45 } 46 47 vector unsigned long long test_vec_mul_ull(void) { 48 // CHECK: mul <2 x i64> 49 // CHECK-NEXT: ret <2 x i64> 50 return vec_mul(vulla, vullb); 51 } 52 53 vector signed int test_vec_div_si(void) { 54 // CHECK: sdiv <4 x i32> 55 // CHECK-NEXT: ret <4 x i32> 56 return vec_div(vsia, vsib); 57 } 58 59 vector unsigned int test_vec_div_ui(void) { 60 // CHECK: udiv <4 x i32> 61 // CHECK-NEXT: ret <4 x i32> 62 return vec_div(vuia, vuib); 63 } 64 65 vector signed long long test_vec_div_sll(void) { 66 // CHECK: sdiv <2 x i64> 67 // CHECK-NEXT: ret <2 x i64> 68 return vec_div(vslla, vsllb); 69 } 70 71 vector unsigned long long test_vec_div_ull(void) { 72 // CHECK: udiv <2 x i64> 73 // CHECK-NEXT: ret <2 x i64> 74 return vec_div(vulla, vullb); 75 } 76 77 vector unsigned __int128 test_vec_div_u128(void) { 78 // CHECK: udiv <1 x i128> 79 // CHECK-NEXT: ret <1 x i128> 80 return vec_div(vui128a, vui128b); 81 } 82 83 vector signed __int128 test_vec_div_s128(void) { 84 // CHECK: sdiv <1 x i128> 85 // CHECK-NEXT: ret <1 x i128> 86 return vec_div(vsi128a, vsi128b); 87 } 88 89 vector signed int test_vec_dive_si(void) { 90 // CHECK: @llvm.ppc.altivec.vdivesw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}) 91 // CHECK-NEXT: ret <4 x i32> 92 return vec_dive(vsia, vsib); 93 } 94 95 vector unsigned int test_vec_dive_ui(void) { 96 // CHECK: @llvm.ppc.altivec.vdiveuw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}) 97 // CHECK-NEXT: ret <4 x i32> 98 return vec_dive(vuia, vuib); 99 } 100 101 vector signed long long test_vec_dive_sll(void) { 102 // CHECK: @llvm.ppc.altivec.vdivesd(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}) 103 // CHECK-NEXT: ret <2 x i64> 104 return vec_dive(vslla, vsllb); 105 } 106 107 vector unsigned long long test_vec_dive_ull(void) { 108 // CHECK: @llvm.ppc.altivec.vdiveud(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}) 109 // CHECK-NEXT: ret <2 x i64> 110 return vec_dive(vulla, vullb); 111 } 112 113 vector unsigned __int128 test_vec_dive_u128(void) { 114 // CHECK: @llvm.ppc.altivec.vdiveuq(<1 x i128> %{{.+}}, <1 x i128> %{{.+}}) 115 // CHECK-NEXT: ret <1 x i128> 116 return vec_dive(vui128a, vui128b); 117 } 118 119 vector signed __int128 test_vec_dive_s128(void) { 120 // CHECK: @llvm.ppc.altivec.vdivesq(<1 x i128> %{{.+}}, <1 x i128> %{{.+}}) 121 // CHECK-NEXT: ret <1 x i128> 122 return vec_dive(vsi128a, vsi128b); 123 } 124 125 vector signed int test_vec_mulh_si(void) { 126 // CHECK: @llvm.ppc.altivec.vmulhsw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}) 127 // CHECK-NEXT: ret <4 x i32> 128 return vec_mulh(vsia, vsib); 129 } 130 131 vector unsigned int test_vec_mulh_ui(void) { 132 // CHECK: @llvm.ppc.altivec.vmulhuw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}) 133 // CHECK-NEXT: ret <4 x i32> 134 return vec_mulh(vuia, vuib); 135 } 136 137 vector signed long long test_vec_mulh_sll(void) { 138 // CHECK: @llvm.ppc.altivec.vmulhsd(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}) 139 // CHECK-NEXT: ret <2 x i64> 140 return vec_mulh(vslla, vsllb); 141 } 142 143 vector unsigned long long test_vec_mulh_ull(void) { 144 // CHECK: @llvm.ppc.altivec.vmulhud(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}) 145 // CHECK-NEXT: ret <2 x i64> 146 return vec_mulh(vulla, vullb); 147 } 148 149 vector signed int test_vec_mod_si(void) { 150 // CHECK: srem <4 x i32> 151 // CHECK-NEXT: ret <4 x i32> 152 return vec_mod(vsia, vsib); 153 } 154 155 vector unsigned int test_vec_mod_ui(void) { 156 // CHECK: urem <4 x i32> 157 // CHECK-NEXT: ret <4 x i32> 158 return vec_mod(vuia, vuib); 159 } 160 161 vector signed long long test_vec_mod_sll(void) { 162 // CHECK: srem <2 x i64> 163 // CHECK-NEXT: ret <2 x i64> 164 return vec_mod(vslla, vsllb); 165 } 166 167 vector unsigned long long test_vec_mod_ull(void) { 168 // CHECK: urem <2 x i64> 169 // CHECK-NEXT: ret <2 x i64> 170 return vec_mod(vulla, vullb); 171 } 172 173 vector unsigned char test_xvcvspbf16(vector unsigned char vc) { 174 // CHECK-LABEL: @test_xvcvspbf16( 175 // CHECK: [[TMP0:%.*]] = call <16 x i8> @llvm.ppc.vsx.xvcvspbf16(<16 x i8> [[VC:%.*]]) 176 return __builtin_vsx_xvcvspbf16(vc); 177 } 178 179 vector unsigned char test_xvcvbf16spn(vector unsigned char vc) { 180 // CHECK-LABEL: @test_xvcvbf16spn( 181 // CHECK: [[TMP0:%.*]] = call <16 x i8> @llvm.ppc.vsx.xvcvbf16spn(<16 x i8> [[VC:%.*]]) 182 return __builtin_vsx_xvcvbf16spn(vc); 183 } 184 185 vector unsigned long long test_vpdepd(void) { 186 // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64> 187 // CHECK-NEXT: ret <2 x i64> 188 return vec_pdep(vulla, vullb); 189 } 190 191 vector unsigned long long test_vpextd(void) { 192 // CHECK: @llvm.ppc.altivec.vpextd(<2 x i64> 193 // CHECK-NEXT: ret <2 x i64> 194 return vec_pext(vulla, vullb); 195 } 196 197 vector unsigned char test_vec_stril_uc(void) { 198 // CHECK-BE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 199 // CHECK-BE-NEXT: ret <16 x i8> 200 // CHECK-LE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 201 // CHECK-LE-NEXT: ret <16 x i8> 202 return vec_stril(vuca); 203 } 204 205 vector signed char test_vec_stril_sc(void) { 206 // CHECK-BE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 207 // CHECK-BE-NEXT: ret <16 x i8> 208 // CHECK-LE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 209 // CHECK-LE-NEXT: ret <16 x i8> 210 return vec_stril(vsca); 211 } 212 213 vector unsigned short test_vec_stril_us(void) { 214 // CHECK-BE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 215 // CHECK-BE-NEXT: ret <8 x i16> 216 // CHECK-LE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 217 // CHECK-LE-NEXT: ret <8 x i16> 218 return vec_stril(vusa); 219 } 220 221 vector signed short test_vec_stril_ss(void) { 222 // CHECK-BE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 223 // CHECK-BE-NEXT: ret <8 x i16> 224 // CHECK-LE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 225 // CHECK-LE-NEXT: ret <8 x i16> 226 return vec_stril(vssa); 227 } 228 229 int test_vec_stril_p_uc(void) { 230 // CHECK-BE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 231 // CHECK-BE-NEXT: ret i32 232 // CHECK-LE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 233 // CHECK-LE-NEXT: ret i32 234 return vec_stril_p(vuca); 235 } 236 237 int test_vec_stril_p_sc(void) { 238 // CHECK-BE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 239 // CHECK-BE-NEXT: ret i32 240 // CHECK-LE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 241 // CHECK-LE-NEXT: ret i32 242 return vec_stril_p(vsca); 243 } 244 245 int test_vec_stril_p_us(void) { 246 // CHECK-BE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 247 // CHECK-BE-NEXT: ret i32 248 // CHECK-LE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 249 // CHECK-LE-NEXT: ret i32 250 return vec_stril_p(vusa); 251 } 252 253 int test_vec_stril_p_ss(void) { 254 // CHECK-BE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 255 // CHECK-BE-NEXT: ret i32 256 // CHECK-LE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 257 // CHECK-LE-NEXT: ret i32 258 return vec_stril_p(vssa); 259 } 260 261 vector unsigned char test_vec_stril_p_uc_2(vector unsigned char *ptr, int len) { 262 // CHECK-BE: icmp slt i32 263 // CHECK-BE: br i1 264 // CHECK-BE: for.body: 265 // CHECK-BE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 266 // CHECK-BE: if.then: 267 // CHECK-BE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 268 // CHECK-BE: ret <16 x i8> 269 // CHECK-LE: icmp slt i32 270 // CHECK-LE: br i1 271 // CHECK-LE: for.body: 272 // CHECK-LE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 273 // CHECK-LE: if.then: 274 // CHECK-LE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 275 // CHECK-LE: ret <16 x i8> 276 for (int i = 0; i < len; i++) { 277 if (vec_stril_p(*(ptr + i))) { 278 return vec_stril(*(ptr + i)); 279 } 280 } 281 return vec_stril(*(ptr)); 282 } 283 284 vector signed char test_vec_stril_p_sc_2(vector signed char *ptr, int len) { 285 // CHECK-BE: icmp slt i32 286 // CHECK-BE: br i1 287 // CHECK-BE: for.body: 288 // CHECK-BE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 289 // CHECK-BE: if.then: 290 // CHECK-BE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 291 // CHECK-BE: ret <16 x i8> 292 // CHECK-LE: icmp slt i32 293 // CHECK-LE: br i1 294 // CHECK-LE: for.body: 295 // CHECK-LE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 296 // CHECK-LE: if.then: 297 // CHECK-LE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 298 // CHECK-LE: ret <16 x i8> 299 for (int i = 0; i < len; i++) { 300 if (vec_stril_p(*(ptr + i))) { 301 return vec_stril(*(ptr + i)); 302 } 303 } 304 return vec_stril(*(ptr)); 305 } 306 307 vector unsigned short test_vec_stril_p_us_2(vector unsigned short *ptr, int len) { 308 // CHECK-BE: icmp slt i32 309 // CHECK-BE: br i1 310 // CHECK-BE: for.body: 311 // CHECK-BE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 312 // CHECK-BE: if.then: 313 // CHECK-BE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 314 // CHECK-BE: ret <8 x i16> 315 // CHECK-LE: icmp slt i32 316 // CHECK-LE: br i1 317 // CHECK-LE: for.body: 318 // CHECK-LE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 319 // CHECK-LE: if.then: 320 // CHECK-LE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 321 // CHECK-LE: ret <8 x i16> 322 for (int i = 0; i < len; i++) { 323 if (vec_stril_p(*(ptr + i))) { 324 return vec_stril(*(ptr + i)); 325 } 326 } 327 return vec_stril(*(ptr)); 328 } 329 330 vector signed short test_vec_stril_p_ss_2(vector signed short *ptr, int len) { 331 // CHECK-BE: icmp slt i32 332 // CHECK-BE: br i1 333 // CHECK-BE: for.body: 334 // CHECK-BE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 335 // CHECK-BE: if.then: 336 // CHECK-BE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 337 // CHECK-BE: ret <8 x i16> 338 // CHECK-LE: icmp slt i32 339 // CHECK-LE: br i1 340 // CHECK-LE: for.body: 341 // CHECK-LE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 342 // CHECK-LE: if.then: 343 // CHECK-LE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 344 // CHECK-LE: ret <8 x i16> 345 for (int i = 0; i < len; i++) { 346 if (vec_stril_p(*(ptr + i))) { 347 return vec_stril(*(ptr + i)); 348 } 349 } 350 return vec_stril(*(ptr)); 351 } 352 353 vector unsigned char test_vec_strir_uc(void) { 354 // CHECK-BE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 355 // CHECK-BE-NEXT: ret <16 x i8> 356 // CHECK-LE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 357 // CHECK-LE-NEXT: ret <16 x i8> 358 return vec_strir(vuca); 359 } 360 361 vector signed char test_vec_strir_sc(void) { 362 // CHECK-BE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 363 // CHECK-BE-NEXT: ret <16 x i8> 364 // CHECK-LE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 365 // CHECK-LE-NEXT: ret <16 x i8> 366 return vec_strir(vsca); 367 } 368 369 vector unsigned short test_vec_strir_us(void) { 370 // CHECK-BE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 371 // CHECK-BE-NEXT: ret <8 x i16> 372 // CHECK-LE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 373 // CHECK-LE-NEXT: ret <8 x i16> 374 return vec_strir(vusa); 375 } 376 377 vector signed short test_vec_strir_ss(void) { 378 // CHECK-BE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 379 // CHECK-BE-NEXT: ret <8 x i16> 380 // CHECK-LE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 381 // CHECK-LE-NEXT: ret <8 x i16> 382 return vec_strir(vssa); 383 } 384 385 int test_vec_strir_p_uc(void) { 386 // CHECK-BE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 387 // CHECK-BE-NEXT: ret i32 388 // CHECK-LE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 389 // CHECK-LE-NEXT: ret i32 390 return vec_strir_p(vuca); 391 } 392 393 int test_vec_strir_p_sc(void) { 394 // CHECK-BE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 395 // CHECK-BE-NEXT: ret i32 396 // CHECK-LE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 397 // CHECK-LE-NEXT: ret i32 398 return vec_strir_p(vsca); 399 } 400 401 int test_vec_strir_p_us(void) { 402 // CHECK-BE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 403 // CHECK-BE-NEXT: ret i32 404 // CHECK-LE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 405 // CHECK-LE-NEXT: ret i32 406 return vec_strir_p(vusa); 407 } 408 409 int test_vec_strir_p_ss(void) { 410 // CHECK-BE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 411 // CHECK-BE-NEXT: ret i32 412 // CHECK-LE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 413 // CHECK-LE-NEXT: ret i32 414 return vec_strir_p(vssa); 415 } 416 417 vector unsigned char test_vec_strir_p_uc_2(vector unsigned char *ptr, int len) { 418 // CHECK-BE: icmp slt i32 419 // CHECK-BE: br i1 420 // CHECK-BE: for.body: 421 // CHECK-BE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 422 // CHECK-BE: if.then: 423 // CHECK-BE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 424 // CHECK-BE: ret <16 x i8> 425 // CHECK-LE: icmp slt i32 426 // CHECK-LE: br i1 427 // CHECK-LE: for.body: 428 // CHECK-LE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 429 // CHECK-LE: if.then: 430 // CHECK-LE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 431 // CHECK-LE: ret <16 x i8> 432 for (int i = 0; i < len; i++) { 433 if (vec_strir_p(*(ptr + i))) { 434 return vec_strir(*(ptr + i)); 435 } 436 } 437 return vec_strir(*(ptr)); 438 } 439 440 vector signed char test_vec_strir_p_sc_2(vector signed char *ptr, int len) { 441 // CHECK-BE: icmp slt i32 442 // CHECK-BE: br i1 443 // CHECK-BE: for.body: 444 // CHECK-BE: @llvm.ppc.altivec.vstribr.p(i32 0, <16 x i8> %{{.+}}) 445 // CHECK-BE: if.then: 446 // CHECK-BE: @llvm.ppc.altivec.vstribr(<16 x i8> %{{.+}}) 447 // CHECK-BE: ret <16 x i8> 448 // CHECK-LE: icmp slt i32 449 // CHECK-LE: br i1 450 // CHECK-LE: for.body: 451 // CHECK-LE: @llvm.ppc.altivec.vstribl.p(i32 0, <16 x i8> %{{.+}}) 452 // CHECK-LE: if.then: 453 // CHECK-LE: @llvm.ppc.altivec.vstribl(<16 x i8> %{{.+}}) 454 // CHECK-LE: ret <16 x i8> 455 for (int i = 0; i < len; i++) { 456 if (vec_strir_p(*(ptr + i))) { 457 return vec_strir(*(ptr + i)); 458 } 459 } 460 return vec_strir(*(ptr)); 461 } 462 463 vector unsigned short test_vec_strir_p_us_2(vector unsigned short *ptr, int len) { 464 // CHECK-BE: icmp slt i32 465 // CHECK-BE: br i1 466 // CHECK-BE: for.body: 467 // CHECK-BE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 468 // CHECK-BE: if.then: 469 // CHECK-BE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 470 // CHECK-BE: ret <8 x i16> 471 // CHECK-LE: icmp slt i32 472 // CHECK-LE: br i1 473 // CHECK-LE: for.body: 474 // CHECK-LE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 475 // CHECK-LE: if.then: 476 // CHECK-LE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 477 // CHECK-LE: ret <8 x i16> 478 for (int i = 0; i < len; i++) { 479 if (vec_strir_p(*(ptr + i))) { 480 return vec_strir(*(ptr + i)); 481 } 482 } 483 return vec_strir(*(ptr)); 484 } 485 486 vector signed short test_vec_strir_p_ss_2(vector signed short *ptr, int len) { 487 // CHECK-BE: icmp slt i32 488 // CHECK-BE: br i1 489 // CHECK-BE: for.body: 490 // CHECK-BE: @llvm.ppc.altivec.vstrihr.p(i32 0, <8 x i16> %{{.+}}) 491 // CHECK-BE: if.then: 492 // CHECK-BE: @llvm.ppc.altivec.vstrihr(<8 x i16> %{{.+}}) 493 // CHECK-BE: ret <8 x i16> 494 // CHECK-LE: icmp slt i32 495 // CHECK-LE: br i1 496 // CHECK-LE: for.body: 497 // CHECK-LE: @llvm.ppc.altivec.vstrihl.p(i32 0, <8 x i16> %{{.+}}) 498 // CHECK-LE: if.then: 499 // CHECK-LE: @llvm.ppc.altivec.vstrihl(<8 x i16> %{{.+}}) 500 // CHECK-LE: ret <8 x i16> 501 for (int i = 0; i < len; i++) { 502 if (vec_strir_p(*(ptr + i))) { 503 return vec_strir(*(ptr + i)); 504 } 505 } 506 return vec_strir(*(ptr)); 507 } 508 509 unsigned int test_vec_extractm_uc(void) { 510 // CHECK: @llvm.ppc.altivec.vextractbm(<16 x i8> %{{.+}}) 511 // CHECK-NEXT: ret i32 512 return vec_extractm(vuca); 513 } 514 515 unsigned int test_vec_extractm_us(void) { 516 // CHECK: @llvm.ppc.altivec.vextracthm(<8 x i16> %{{.+}}) 517 // CHECK-NEXT: ret i32 518 return vec_extractm(vusa); 519 } 520 521 unsigned int test_vec_extractm_ui(void) { 522 // CHECK: @llvm.ppc.altivec.vextractwm(<4 x i32> %{{.+}}) 523 // CHECK-NEXT: ret i32 524 return vec_extractm(vuia); 525 } 526 527 unsigned int test_vec_extractm_ull(void) { 528 // CHECK: @llvm.ppc.altivec.vextractdm(<2 x i64> %{{.+}}) 529 // CHECK-NEXT: ret i32 530 return vec_extractm(vulla); 531 } 532 533 unsigned int test_vec_extractm_u128(void) { 534 // CHECK: @llvm.ppc.altivec.vextractqm(<1 x i128> %{{.+}}) 535 // CHECK-NEXT: ret i32 536 return vec_extractm(vui128a); 537 } 538 539 vector unsigned long long test_vcfuged(void) { 540 // CHECK: @llvm.ppc.altivec.vcfuged(<2 x i64> 541 // CHECK-NEXT: ret <2 x i64> 542 return vec_cfuge(vulla, vullb); 543 } 544 545 vector unsigned char test_vec_expandm_uc(void) { 546 // CHECK: @llvm.ppc.altivec.vexpandbm(<16 x i8> %{{.+}}) 547 // CHECK-NEXT: ret <16 x i8> 548 return vec_expandm(vuca); 549 } 550 551 vector unsigned short test_vec_expandm_us(void) { 552 // CHECK: @llvm.ppc.altivec.vexpandhm(<8 x i16> %{{.+}}) 553 // CHECK-NEXT: ret <8 x i16> 554 return vec_expandm(vusa); 555 } 556 557 vector unsigned int test_vec_expandm_ui(void) { 558 // CHECK: @llvm.ppc.altivec.vexpandwm(<4 x i32> %{{.+}}) 559 // CHECK-NEXT: ret <4 x i32> 560 return vec_expandm(vuia); 561 } 562 563 vector unsigned long long test_vec_expandm_ull(void) { 564 // CHECK: @llvm.ppc.altivec.vexpanddm(<2 x i64> %{{.+}}) 565 // CHECK-NEXT: ret <2 x i64> 566 return vec_expandm(vulla); 567 } 568 569 vector unsigned __int128 test_vec_expandm_u128(void) { 570 // CHECK: @llvm.ppc.altivec.vexpandqm(<1 x i128> %{{.+}}) 571 // CHECK-NEXT: ret <1 x i128> 572 return vec_expandm(vui128a); 573 } 574 575 unsigned long long test_vec_cntm_uc(void) { 576 // CHECK: @llvm.ppc.altivec.vcntmbb(<16 x i8> %{{.+}}, i32 577 // CHECK-NEXT: ret i64 578 return vec_cntm(vuca, 1); 579 } 580 581 unsigned long long test_vec_cntm_us(void) { 582 // CHECK: @llvm.ppc.altivec.vcntmbh(<8 x i16> %{{.+}}, i32 583 // CHECK-NEXT: ret i64 584 return vec_cntm(vusa, 0); 585 } 586 587 unsigned long long test_vec_cntm_ui(void) { 588 // CHECK: @llvm.ppc.altivec.vcntmbw(<4 x i32> %{{.+}}, i32 589 // CHECK-NEXT: ret i64 590 return vec_cntm(vuia, 1); 591 } 592 593 unsigned long long test_vec_cntm_ull(void) { 594 // CHECK: @llvm.ppc.altivec.vcntmbd(<2 x i64> %{{.+}}, i32 595 // CHECK-NEXT: ret i64 596 return vec_cntm(vulla, 0); 597 } 598 599 vector unsigned char test_vec_genbm(void) { 600 // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}}) 601 // CHECK-NEXT: ret <16 x i8> 602 return vec_genbm(ulla); 603 } 604 605 vector unsigned char test_vec_genbm_imm(void) { 606 // CHECK: store i64 1 607 // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}}) 608 // CHECK-NEXT: ret <16 x i8> 609 return vec_genbm(1); 610 } 611 612 vector unsigned char test_vec_genbm_imm2(void) { 613 // CHECK: store i64 255 614 // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}}) 615 // CHECK-NEXT: ret <16 x i8> 616 return vec_genbm(255); 617 } 618 619 vector unsigned char test_vec_genbm_imm3(void) { 620 // CHECK: store i64 65535 621 // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}}) 622 // CHECK-NEXT: ret <16 x i8> 623 return vec_genbm(65535); 624 } 625 626 vector unsigned char test_vec_genbm_imm4(void) { 627 // CHECK: store i64 65536 628 // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}}) 629 // CHECK-NEXT: ret <16 x i8> 630 return vec_genbm(65536); 631 } 632 633 vector unsigned char test_vec_genbm_imm5(void) { 634 // CHECK: store i64 65546 635 // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}}) 636 // CHECK-NEXT: ret <16 x i8> 637 return vec_genbm(65546); 638 } 639 640 vector unsigned short test_vec_genhm(void) { 641 // CHECK: @llvm.ppc.altivec.mtvsrhm(i64 %{{.+}}) 642 // CHECK-NEXT: ret <8 x i16> 643 return vec_genhm(ulla); 644 } 645 646 vector unsigned int test_vec_genwm(void) { 647 // CHECK: @llvm.ppc.altivec.mtvsrwm(i64 %{{.+}}) 648 // CHECK-NEXT: ret <4 x i32> 649 return vec_genwm(ulla); 650 } 651 652 vector unsigned long long test_vec_gendm(void) { 653 // CHECK: @llvm.ppc.altivec.mtvsrdm(i64 %{{.+}}) 654 // CHECK-NEXT: ret <2 x i64> 655 return vec_gendm(ulla); 656 } 657 658 vector unsigned __int128 test_vec_genqm(void) { 659 // CHECK: @llvm.ppc.altivec.mtvsrqm(i64 %{{.+}}) 660 // CHECK-NEXT: ret <1 x i128> 661 return vec_genqm(ulla); 662 } 663 664 unsigned long long test_vgnb_1(void) { 665 // CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 2) 666 // CHECK-NEXT: ret i64 667 return vec_gnb(vui128a, 2); 668 } 669 670 unsigned long long test_vgnb_2(void) { 671 // CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 7) 672 // CHECK-NEXT: ret i64 673 return vec_gnb(vui128a, 7); 674 } 675 676 unsigned long long test_vgnb_3(void) { 677 // CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 5) 678 // CHECK-NEXT: ret i64 679 return vec_gnb(vui128a, 5); 680 } 681 682 vector unsigned char test_xxeval_uc(void) { 683 // CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 0) 684 // CHECK: ret <16 x i8> 685 return vec_ternarylogic(vuca, vucb, vucc, 0); 686 } 687 688 vector unsigned short test_xxeval_us(void) { 689 // CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 255) 690 // CHECK: ret <8 x i16> 691 return vec_ternarylogic(vusa, vusb, vusc, 255); 692 } 693 694 vector unsigned int test_xxeval_ui(void) { 695 // CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 150) 696 // CHECK: ret <4 x i32> 697 return vec_ternarylogic(vuia, vuib, vuic, 150); 698 } 699 700 vector unsigned long long test_xxeval_ull(void) { 701 // CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 1) 702 // CHECK: ret <2 x i64> 703 return vec_ternarylogic(vulla, vullb, vullc, 1); 704 } 705 706 vector unsigned __int128 test_xxeval_ui128(void) { 707 // CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 246) 708 // CHECK: ret <1 x i128> 709 return vec_ternarylogic(vui128a, vui128b, vui128c, 246); 710 } 711 712 vector unsigned char test_xxgenpcvbm(void) { 713 // CHECK: @llvm.ppc.vsx.xxgenpcvbm(<16 x i8> %{{.+}}, i32 714 // CHECK-NEXT: ret <16 x i8> 715 return vec_genpcvm(vuca, 0); 716 } 717 718 vector unsigned short test_xxgenpcvhm(void) { 719 // CHECK: @llvm.ppc.vsx.xxgenpcvhm(<8 x i16> %{{.+}}, i32 720 // CHECK-NEXT: ret <8 x i16> 721 return vec_genpcvm(vusa, 0); 722 } 723 724 vector unsigned int test_xxgenpcvwm(void) { 725 // CHECK: @llvm.ppc.vsx.xxgenpcvwm(<4 x i32> %{{.+}}, i32 726 // CHECK-NEXT: ret <4 x i32> 727 return vec_genpcvm(vuia, 0); 728 } 729 730 vector unsigned long long test_xxgenpcvdm(void) { 731 // CHECK: @llvm.ppc.vsx.xxgenpcvdm(<2 x i64> %{{.+}}, i32 732 // CHECK-NEXT: ret <2 x i64> 733 return vec_genpcvm(vulla, 0); 734 } 735 736 vector signed char test_vec_clr_first_sc(void) { 737 // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8> 738 // CHECK-BE-NEXT: ret <16 x i8> 739 // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8> 740 // CHECK-LE-NEXT: ret <16 x i8> 741 return vec_clr_first(vsca, uia); 742 } 743 744 vector unsigned char test_vec_clr_first_uc(void) { 745 // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8> 746 // CHECK-BE-NEXT: ret <16 x i8> 747 // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8> 748 // CHECK-LE-NEXT: ret <16 x i8> 749 return vec_clr_first(vuca, uia); 750 } 751 752 vector signed char test_vec_clr_last_sc(void) { 753 // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8> 754 // CHECK-BE-NEXT: ret <16 x i8> 755 // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8> 756 // CHECK-LE-NEXT: ret <16 x i8> 757 return vec_clr_last(vsca, uia); 758 } 759 760 vector unsigned char test_vec_clr_last_uc(void) { 761 // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8> 762 // CHECK-BE-NEXT: ret <16 x i8> 763 // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8> 764 // CHECK-LE-NEXT: ret <16 x i8> 765 return vec_clr_last(vuca, uia); 766 } 767 768 vector unsigned long long test_vclzdm(void) { 769 // CHECK: @llvm.ppc.altivec.vclzdm(<2 x i64> 770 // CHECK-NEXT: ret <2 x i64> 771 return vec_cntlzm(vulla, vullb); 772 } 773 774 vector unsigned long long test_vctzdm(void) { 775 // CHECK: @llvm.ppc.altivec.vctzdm(<2 x i64> 776 // CHECK-NEXT: ret <2 x i64> 777 return vec_cnttzm(vulla, vullb); 778 } 779 780 vector signed char test_vec_sldb_sc(void) { 781 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 0 782 // CHECK-NEXT: ret <16 x i8> 783 return vec_sldb(vsca, vscb, 0); 784 } 785 786 vector unsigned char test_vec_sldb_uc(void) { 787 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 1 788 // CHECK-NEXT: ret <16 x i8> 789 return vec_sldb(vuca, vucb, 1); 790 } 791 792 vector signed short test_vec_sldb_ss(void) { 793 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 2 794 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16> 795 // CHECK-NEXT: ret <8 x i16> 796 return vec_sldb(vssa, vssb, 2); 797 } 798 799 vector unsigned short test_vec_sldb_us(void) { 800 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 3 801 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16> 802 // CHECK-NEXT: ret <8 x i16> 803 return vec_sldb(vusa, vusb, 3); 804 } 805 806 vector signed int test_vec_sldb_si(void) { 807 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 4 808 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32> 809 // CHECK-NEXT: ret <4 x i32> 810 return vec_sldb(vsia, vsib, 4); 811 } 812 813 vector unsigned int test_vec_sldb_ui(void) { 814 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 5 815 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32> 816 // CHECK-NEXT: ret <4 x i32> 817 return vec_sldb(vuia, vuib, 5); 818 } 819 820 vector signed long long test_vec_sldb_sll(void) { 821 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 6 822 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64> 823 // CHECK-NEXT: ret <2 x i64> 824 return vec_sldb(vslla, vsllb, 6); 825 } 826 827 vector unsigned long long test_vec_sldb_ull(void) { 828 // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 7 829 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64> 830 // CHECK-NEXT: ret <2 x i64> 831 return vec_sldb(vulla, vullb, 7); 832 } 833 834 vector signed char test_vec_srdb_sc(void) { 835 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 0 836 // CHECK-NEXT: ret <16 x i8> 837 return vec_srdb(vsca, vscb, 8); 838 } 839 840 vector unsigned char test_vec_srdb_uc(void) { 841 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 1 842 // CHECK-NEXT: ret <16 x i8> 843 return vec_srdb(vuca, vucb, 9); 844 } 845 846 vector signed short test_vec_srdb_ss(void) { 847 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 2 848 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16> 849 // CHECK-NEXT: ret <8 x i16> 850 return vec_srdb(vssa, vssb, 10); 851 } 852 853 vector unsigned short test_vec_srdb_us(void) { 854 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 3 855 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16> 856 // CHECK-NEXT: ret <8 x i16> 857 return vec_srdb(vusa, vusb, 3); 858 } 859 860 vector signed int test_vec_srdb_si(void) { 861 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 4 862 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32> 863 // CHECK-NEXT: ret <4 x i32> 864 return vec_srdb(vsia, vsib, 4); 865 } 866 867 vector unsigned int test_vec_srdb_ui(void) { 868 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 5 869 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32> 870 // CHECK-NEXT: ret <4 x i32> 871 return vec_srdb(vuia, vuib, 5); 872 } 873 874 vector signed long long test_vec_srdb_sll(void) { 875 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 6 876 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64> 877 // CHECK-NEXT: ret <2 x i64> 878 return vec_srdb(vslla, vsllb, 6); 879 } 880 881 vector unsigned long long test_vec_srdb_ull(void) { 882 // CHECK: @llvm.ppc.altivec.vsrdbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 7 883 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64> 884 // CHECK-NEXT: ret <2 x i64> 885 return vec_srdb(vulla, vullb, 7); 886 } 887 888 vector signed char test_vec_permx_sc(void) { 889 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 890 // CHECK-NEXT: ret <16 x i8> 891 return vec_permx(vsca, vscb, vucc, 0); 892 } 893 894 vector unsigned char test_vec_permx_uc(void) { 895 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 896 // CHECK-NEXT: ret <16 x i8> 897 return vec_permx(vuca, vucb, vucc, 1); 898 } 899 900 vector signed short test_vec_permx_ss(void) { 901 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 902 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16> 903 // CHECK-NEXT: ret <8 x i16> 904 return vec_permx(vssa, vssb, vucc, 2); 905 } 906 907 vector unsigned short test_vec_permx_us(void) { 908 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 909 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16> 910 // CHECK-NEXT: ret <8 x i16> 911 return vec_permx(vusa, vusb, vucc, 3); 912 } 913 914 vector signed int test_vec_permx_si(void) { 915 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 916 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32> 917 // CHECK-NEXT: ret <4 x i32> 918 return vec_permx(vsia, vsib, vucc, 4); 919 } 920 921 vector unsigned int test_vec_permx_ui(void) { 922 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 923 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32> 924 // CHECK-NEXT: ret <4 x i32> 925 return vec_permx(vuia, vuib, vucc, 5); 926 } 927 928 vector signed long long test_vec_permx_sll(void) { 929 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 930 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64> 931 // CHECK-NEXT: ret <2 x i64> 932 return vec_permx(vslla, vsllb, vucc, 6); 933 } 934 935 vector unsigned long long test_vec_permx_ull(void) { 936 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 937 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64> 938 // CHECK-NEXT: ret <2 x i64> 939 return vec_permx(vulla, vullb, vucc, 7); 940 } 941 942 vector float test_vec_permx_f(void) { 943 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 944 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x float> 945 // CHECK-NEXT: ret <4 x float> 946 return vec_permx(vfa, vfb, vucc, 0); 947 } 948 949 vector double test_vec_permx_d(void) { 950 // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 951 // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x double> 952 // CHECK-NEXT: ret <2 x double> 953 return vec_permx(vda, vdb, vucc, 1); 954 } 955 956 vector signed char test_vec_blend_sc(void) { 957 // CHECK: @llvm.ppc.vsx.xxblendvb(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> 958 // CHECK-NEXT: ret <16 x i8> 959 return vec_blendv(vsca, vscb, vucc); 960 } 961 962 vector unsigned char test_vec_blend_uc(void) { 963 // CHECK: @llvm.ppc.vsx.xxblendvb(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> 964 // CHECK-NEXT: ret <16 x i8> 965 return vec_blendv(vuca, vucb, vucc); 966 } 967 968 vector signed short test_vec_blend_ss(void) { 969 // CHECK: @llvm.ppc.vsx.xxblendvh(<8 x i16> %{{.+}}, <8 x i16> %{{.+}}, <8 x i16> 970 // CHECK-NEXT: ret <8 x i16> 971 return vec_blendv(vssa, vssb, vusc); 972 } 973 974 vector unsigned short test_vec_blend_us(void) { 975 // CHECK: @llvm.ppc.vsx.xxblendvh(<8 x i16> %{{.+}}, <8 x i16> %{{.+}}, <8 x i16> 976 // CHECK-NEXT: ret <8 x i16> 977 return vec_blendv(vusa, vusb, vusc); 978 } 979 980 vector signed int test_vec_blend_si(void) { 981 // CHECK: @llvm.ppc.vsx.xxblendvw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, <4 x i32> 982 // CHECK-NEXT: ret <4 x i32> 983 return vec_blendv(vsia, vsib, vuic); 984 } 985 986 vector unsigned int test_vec_blend_ui(void) { 987 // CHECK: @llvm.ppc.vsx.xxblendvw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, <4 x i32> 988 // CHECK-NEXT: ret <4 x i32> 989 return vec_blendv(vuia, vuib, vuic); 990 } 991 992 vector signed long long test_vec_blend_sll(void) { 993 // CHECK: @llvm.ppc.vsx.xxblendvd(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> 994 // CHECK-NEXT: ret <2 x i64> 995 return vec_blendv(vslla, vsllb, vullc); 996 } 997 998 vector unsigned long long test_vec_blend_ull(void) { 999 // CHECK: @llvm.ppc.vsx.xxblendvd(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> 1000 // CHECK-NEXT: ret <2 x i64> 1001 return vec_blendv(vulla, vullb, vullc); 1002 } 1003 1004 vector float test_vec_blend_f(void) { 1005 // CHECK: @llvm.ppc.vsx.xxblendvw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, <4 x i32> 1006 // CHECK-NEXT: bitcast <4 x i32> %{{.*}} to <4 x float> 1007 // CHECK-NEXT: ret <4 x float> 1008 return vec_blendv(vfa, vfb, vuic); 1009 } 1010 1011 vector double test_vec_blend_d(void) { 1012 // CHECK: @llvm.ppc.vsx.xxblendvd(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> 1013 // CHECK-NEXT: bitcast <2 x i64> %{{.*}} to <2 x double> 1014 // CHECK-NEXT: ret <2 x double> 1015 return vec_blendv(vda, vdb, vullc); 1016 } 1017 1018 // CHECK-BE-LABEL: @test_vec_replace_elt_si( 1019 // CHECK-BE-NEXT: entry: 1020 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 1021 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1022 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 1023 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1024 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 0) 1025 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1026 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> 1027 // CHECK-BE-NEXT: ret <4 x i32> [[TMP6]] 1028 // 1029 // CHECK-LE-LABEL: @test_vec_replace_elt_si( 1030 // CHECK-LE-NEXT: entry: 1031 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 1032 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1033 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 1034 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1035 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 12) 1036 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1037 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> 1038 // CHECK-LE-NEXT: ret <4 x i32> [[TMP6]] 1039 // 1040 vector signed int test_vec_replace_elt_si(void) { 1041 return vec_replace_elt(vsia, sia, 0); 1042 } 1043 1044 // CHECK-BE-LABEL: @test_vec_replace_elt_ui( 1045 // CHECK-BE-NEXT: entry: 1046 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 1047 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1048 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 1049 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1050 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 4) 1051 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1052 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> 1053 // CHECK-BE-NEXT: ret <4 x i32> [[TMP6]] 1054 // 1055 // CHECK-LE-LABEL: @test_vec_replace_elt_ui( 1056 // CHECK-LE-NEXT: entry: 1057 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 1058 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1059 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 1060 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1061 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) 1062 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1063 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> 1064 // CHECK-LE-NEXT: ret <4 x i32> [[TMP6]] 1065 // 1066 vector unsigned int test_vec_replace_elt_ui(void) { 1067 return vec_replace_elt(vuia, uia, 1); 1068 } 1069 1070 // CHECK-BE-LABEL: @test_vec_replace_elt_f( 1071 // CHECK-BE-NEXT: entry: 1072 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 1073 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> 1074 // CHECK-BE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 1075 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 1076 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1077 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 8) 1078 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1079 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float> 1080 // CHECK-BE-NEXT: ret <4 x float> [[TMP6]] 1081 // 1082 // CHECK-LE-LABEL: @test_vec_replace_elt_f( 1083 // CHECK-LE-NEXT: entry: 1084 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 1085 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> 1086 // CHECK-LE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 1087 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 1088 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1089 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 4) 1090 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1091 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float> 1092 // CHECK-LE-NEXT: ret <4 x float> [[TMP6]] 1093 // 1094 vector float test_vec_replace_elt_f(void) { 1095 return vec_replace_elt(vfa, fa, 2); 1096 } 1097 1098 // CHECK-BE-LABEL: @test_vec_replace_elt_sll( 1099 // CHECK-BE-NEXT: entry: 1100 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 1101 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1102 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 1103 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1104 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 0) 1105 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1106 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> 1107 // CHECK-BE-NEXT: ret <2 x i64> [[TMP6]] 1108 // 1109 // CHECK-LE-LABEL: @test_vec_replace_elt_sll( 1110 // CHECK-LE-NEXT: entry: 1111 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 1112 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1113 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 1114 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1115 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 8) 1116 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1117 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> 1118 // CHECK-LE-NEXT: ret <2 x i64> [[TMP6]] 1119 // 1120 vector signed long long test_vec_replace_elt_sll(void) { 1121 return vec_replace_elt(vslla, llb, 0); 1122 } 1123 1124 // CHECK-BE-LABEL: @test_vec_replace_elt_ull( 1125 // CHECK-BE-NEXT: entry: 1126 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 1127 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1128 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 1129 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1130 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 0) 1131 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1132 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> 1133 // CHECK-BE-NEXT: ret <2 x i64> [[TMP6]] 1134 // 1135 // CHECK-LE-LABEL: @test_vec_replace_elt_ull( 1136 // CHECK-LE-NEXT: entry: 1137 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 1138 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1139 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 1140 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1141 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 8) 1142 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1143 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> 1144 // CHECK-LE-NEXT: ret <2 x i64> [[TMP6]] 1145 // 1146 vector unsigned long long test_vec_replace_elt_ull(void) { 1147 return vec_replace_elt(vulla, ulla, 0); 1148 } 1149 1150 // CHECK-BE-LABEL: @test_vec_replace_elt_d( 1151 // CHECK-BE-NEXT: entry: 1152 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 1153 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> 1154 // CHECK-BE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 1155 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 1156 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1157 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) 1158 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1159 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double> 1160 // CHECK-BE-NEXT: ret <2 x double> [[TMP6]] 1161 // 1162 // CHECK-LE-LABEL: @test_vec_replace_elt_d( 1163 // CHECK-LE-NEXT: entry: 1164 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 1165 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> 1166 // CHECK-LE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 1167 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 1168 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1169 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 0) 1170 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1171 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double> 1172 // CHECK-LE-NEXT: ret <2 x double> [[TMP6]] 1173 // 1174 vector double test_vec_replace_elt_d(void) { 1175 return vec_replace_elt(vda, da, 1); 1176 } 1177 1178 // CHECK-BE-LABEL: @test_vec_replace_unaligned_si( 1179 // CHECK-BE-NEXT: entry: 1180 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 1181 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1182 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 1183 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1184 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6) 1185 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1186 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> 1187 // CHECK-BE-NEXT: ret <4 x i32> [[TMP6]] 1188 // 1189 // CHECK-LE-LABEL: @test_vec_replace_unaligned_si( 1190 // CHECK-LE-NEXT: entry: 1191 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 1192 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1193 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 1194 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1195 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6) 1196 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1197 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> 1198 // CHECK-LE-NEXT: ret <4 x i32> [[TMP6]] 1199 // 1200 vector signed int test_vec_replace_unaligned_si(void) { 1201 return vec_replace_unaligned(vsia, sia, 6); 1202 } 1203 1204 // CHECK-BE-LABEL: @test_vec_replace_unaligned_ui( 1205 // CHECK-BE-NEXT: entry: 1206 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 1207 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1208 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 1209 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1210 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) 1211 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1212 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> 1213 // CHECK-BE-NEXT: ret <4 x i32> [[TMP6]] 1214 // 1215 // CHECK-LE-LABEL: @test_vec_replace_unaligned_ui( 1216 // CHECK-LE-NEXT: entry: 1217 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 1218 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> 1219 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 1220 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1221 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) 1222 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1223 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> 1224 // CHECK-LE-NEXT: ret <4 x i32> [[TMP6]] 1225 // 1226 vector unsigned int test_vec_replace_unaligned_ui(void) { 1227 return vec_replace_unaligned(vuia, uia, 8); 1228 } 1229 1230 // CHECK-BE-LABEL: @test_vec_replace_unaligned_f( 1231 // CHECK-BE-NEXT: entry: 1232 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 1233 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> 1234 // CHECK-BE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 1235 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 1236 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1237 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12) 1238 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1239 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float> 1240 // CHECK-BE-NEXT: ret <4 x float> [[TMP6]] 1241 // 1242 // CHECK-LE-LABEL: @test_vec_replace_unaligned_f( 1243 // CHECK-LE-NEXT: entry: 1244 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 1245 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> 1246 // CHECK-LE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 1247 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 1248 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> 1249 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12) 1250 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> 1251 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float> 1252 // CHECK-LE-NEXT: ret <4 x float> [[TMP6]] 1253 // 1254 vector float test_vec_replace_unaligned_f(void) { 1255 return vec_replace_unaligned(vfa, fa, 12); 1256 } 1257 1258 // CHECK-BE-LABEL: @test_vec_replace_unaligned_sll( 1259 // CHECK-BE-NEXT: entry: 1260 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 1261 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1262 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 1263 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1264 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 6) 1265 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1266 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> 1267 // CHECK-BE-NEXT: ret <2 x i64> [[TMP6]] 1268 // 1269 // CHECK-LE-LABEL: @test_vec_replace_unaligned_sll( 1270 // CHECK-LE-NEXT: entry: 1271 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 1272 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1273 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 1274 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1275 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 6) 1276 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1277 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> 1278 // CHECK-LE-NEXT: ret <2 x i64> [[TMP6]] 1279 // 1280 vector signed long long test_vec_replace_unaligned_sll(void) { 1281 return vec_replace_unaligned(vslla, llb, 6); 1282 } 1283 1284 // CHECK-BE-LABEL: @test_vec_replace_unaligned_ull( 1285 // CHECK-BE-NEXT: entry: 1286 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 1287 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1288 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 1289 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1290 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 7) 1291 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1292 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> 1293 // CHECK-BE-NEXT: ret <2 x i64> [[TMP6]] 1294 // 1295 // CHECK-LE-LABEL: @test_vec_replace_unaligned_ull( 1296 // CHECK-LE-NEXT: entry: 1297 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 1298 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> 1299 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 1300 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1301 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 7) 1302 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1303 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> 1304 // CHECK-LE-NEXT: ret <2 x i64> [[TMP6]] 1305 // 1306 vector unsigned long long test_vec_replace_unaligned_ull(void) { 1307 return vec_replace_unaligned(vulla, ulla, 7); 1308 } 1309 1310 // CHECK-BE-LABEL: @test_vec_replace_unaligned_d( 1311 // CHECK-BE-NEXT: entry: 1312 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 1313 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> 1314 // CHECK-BE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 1315 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 1316 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1317 // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) 1318 // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1319 // CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double> 1320 // CHECK-BE-NEXT: ret <2 x double> [[TMP6]] 1321 // 1322 // CHECK-LE-LABEL: @test_vec_replace_unaligned_d( 1323 // CHECK-LE-NEXT: entry: 1324 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 1325 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> 1326 // CHECK-LE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 1327 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 1328 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> 1329 // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) 1330 // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> 1331 // CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double> 1332 // CHECK-LE-NEXT: ret <2 x double> [[TMP6]] 1333 // 1334 vector double test_vec_replace_unaligned_d(void) { 1335 return vec_replace_unaligned(vda, da, 8); 1336 } 1337 1338 vector unsigned char test_vec_insertl_uc(void) { 1339 // CHECK-BE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32 1340 // CHECK-BE-NEXT: ret <16 x i8> 1341 // CHECK-LE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32 1342 // CHECK-LE-NEXT: ret <16 x i8> 1343 return vec_insertl(uca, vuca, uia); 1344 } 1345 1346 vector unsigned short test_vec_insertl_us(void) { 1347 // CHECK-BE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32 1348 // CHECK-BE-NEXT: ret <8 x i16> 1349 // CHECK-LE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32 1350 // CHECK-LE-NEXT: ret <8 x i16> 1351 return vec_insertl(usa, vusa, uia); 1352 } 1353 1354 vector unsigned int test_vec_insertl_ui(void) { 1355 // CHECK-BE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 1356 // CHECK-BE-NEXT: ret <4 x i32> 1357 // CHECK-LE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 1358 // CHECK-LE-NEXT: ret <4 x i32> 1359 return vec_insertl(uib, vuia, uia); 1360 } 1361 1362 vector unsigned long long test_vec_insertl_ul(void) { 1363 // CHECK-BE: @llvm.ppc.altivec.vinsdlx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64 1364 // CHECK-BE-NEXT: ret <2 x i64> 1365 // CHECK-LE: @llvm.ppc.altivec.vinsdrx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64 1366 // CHECK-LE-NEXT: ret <2 x i64> 1367 return vec_insertl(ulla, vulla, uia); 1368 } 1369 1370 vector unsigned char test_vec_insertl_ucv(void) { 1371 // CHECK-BE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 x i8> 1372 // CHECK-BE-NEXT: ret <16 x i8> 1373 // CHECK-LE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 x i8> 1374 // CHECK-LE-NEXT: ret <16 x i8> 1375 return vec_insertl(vuca, vucb, uia); 1376 } 1377 1378 vector unsigned short test_vec_insertl_usv(void) { 1379 // CHECK-BE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x i16> 1380 // CHECK-BE-NEXT: ret <8 x i16> 1381 // CHECK-LE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x i16> 1382 // CHECK-LE-NEXT: ret <8 x i16> 1383 return vec_insertl(vusa, vusb, uia); 1384 } 1385 1386 vector unsigned int test_vec_insertl_uiv(void) { 1387 // CHECK-BE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> 1388 // CHECK-BE-NEXT: ret <4 x i32> 1389 // CHECK-LE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> 1390 // CHECK-LE-NEXT: ret <4 x i32> 1391 return vec_insertl(vuia, vuib, uia); 1392 } 1393 1394 vector unsigned char test_vec_inserth_uc(void) { 1395 // CHECK-BE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32 1396 // CHECK-BE-NEXT: ret <16 x i8> 1397 // CHECK-LE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32 1398 // CHECK-LE-NEXT: ret <16 x i8> 1399 return vec_inserth(uca, vuca, uia); 1400 } 1401 1402 vector unsigned short test_vec_inserth_us(void) { 1403 // CHECK-BE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32 1404 // CHECK-BE-NEXT: ret <8 x i16> 1405 // CHECK-LE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32 1406 // CHECK-LE-NEXT: ret <8 x i16> 1407 return vec_inserth(usa, vusa, uia); 1408 } 1409 1410 vector unsigned int test_vec_inserth_ui(void) { 1411 // CHECK-BE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 1412 // CHECK-BE-NEXT: ret <4 x i32> 1413 // CHECK-LE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 1414 // CHECK-LE-NEXT: ret <4 x i32> 1415 return vec_inserth(uib, vuia, uia); 1416 } 1417 1418 vector unsigned long long test_vec_inserth_ul(void) { 1419 // CHECK-BE: @llvm.ppc.altivec.vinsdrx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64 1420 // CHECK-BE-NEXT: ret <2 x i64> 1421 // CHECK-LE: @llvm.ppc.altivec.vinsdlx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64 1422 // CHECK-LE-NEXT: ret <2 x i64> 1423 return vec_inserth(ulla, vulla, uia); 1424 } 1425 1426 vector unsigned char test_vec_inserth_ucv(void) { 1427 // CHECK-BE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 x i8> 1428 // CHECK-BE-NEXT: ret <16 x i8> 1429 // CHECK-LE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 x i8> 1430 // CHECK-LE-NEXT: ret <16 x i8> 1431 return vec_inserth(vuca, vucb, uia); 1432 } 1433 1434 vector unsigned short test_vec_inserth_usv(void) { 1435 // CHECK-BE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x i16> 1436 // CHECK-BE-NEXT: ret <8 x i16> 1437 // CHECK-LE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x i16> 1438 // CHECK-LE-NEXT: ret <8 x i16> 1439 return vec_inserth(vusa, vusb, uia); 1440 } 1441 1442 vector unsigned int test_vec_inserth_uiv(void) { 1443 // CHECK-BE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> 1444 // CHECK-BE-NEXT: ret <4 x i32> 1445 // CHECK-LE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> 1446 // CHECK-LE-NEXT: ret <4 x i32> 1447 return vec_inserth(vuia, vuib, uia); 1448 } 1449 1450 vector unsigned long long test_vec_extractl_uc(void) { 1451 // CHECK-BE: @llvm.ppc.altivec.vextdubvlx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 1452 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1453 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1454 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1455 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1456 // CHECK-BE: ret <2 x i64> 1457 // CHECK-LE: @llvm.ppc.altivec.vextdubvrx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 1458 // CHECK-LE-NEXT: ret <2 x i64> 1459 return vec_extractl(vuca, vucb, uia); 1460 } 1461 1462 vector unsigned long long test_vec_extractl_us(void) { 1463 // CHECK-BE: @llvm.ppc.altivec.vextduhvlx(<8 x i16> %{{.+}}, <8 x i16> %{{.+}}, i32 1464 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1465 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1466 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1467 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1468 // CHECK-BE: ret <2 x i64> 1469 // CHECK-LE: @llvm.ppc.altivec.vextduhvrx(<8 x i16> %{{.+}}, <8 x i16> %{{.+}}, i32 1470 // CHECK-LE-NEXT: ret <2 x i64> 1471 return vec_extractl(vusa, vusb, uia); 1472 } 1473 1474 vector unsigned long long test_vec_extractl_ui(void) { 1475 // CHECK-BE: @llvm.ppc.altivec.vextduwvlx(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, i32 1476 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1477 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1478 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1479 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1480 // CHECK-BE: ret <2 x i64> 1481 // CHECK-LE: @llvm.ppc.altivec.vextduwvrx(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, i32 1482 // CHECK-LE-NEXT: ret <2 x i64> 1483 return vec_extractl(vuia, vuib, uia); 1484 } 1485 1486 vector unsigned long long test_vec_extractl_ul(void) { 1487 // CHECK-BE: @llvm.ppc.altivec.vextddvlx(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 1488 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1489 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1490 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1491 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1492 // CHECK-BE: ret <2 x i64> 1493 // CHECK-LE: @llvm.ppc.altivec.vextddvrx(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 1494 // CHECK-LE-NEXT: ret <2 x i64> 1495 return vec_extractl(vulla, vullb, uia); 1496 } 1497 1498 vector unsigned long long test_vec_extracth_uc(void) { 1499 // CHECK-BE: @llvm.ppc.altivec.vextdubvrx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 1500 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1501 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1502 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1503 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1504 // CHECK-BE: ret <2 x i64> 1505 // CHECK-LE: @llvm.ppc.altivec.vextdubvlx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 1506 // CHECK-LE-NEXT: ret <2 x i64> 1507 return vec_extracth(vuca, vucb, uia); 1508 } 1509 1510 vector unsigned long long test_vec_extracth_us(void) { 1511 // CHECK-BE: @llvm.ppc.altivec.vextduhvrx(<8 x i16> %{{.+}}, <8 x i16> %{{.+}}, i32 1512 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1513 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1514 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1515 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1516 // CHECK-BE: ret <2 x i64> 1517 // CHECK-LE: @llvm.ppc.altivec.vextduhvlx(<8 x i16> %{{.+}}, <8 x i16> %{{.+}}, i32 1518 // CHECK-LE-NEXT: ret <2 x i64> 1519 return vec_extracth(vusa, vusb, uia); 1520 } 1521 1522 vector unsigned long long test_vec_extracth_ui(void) { 1523 // CHECK-BE: @llvm.ppc.altivec.vextduwvrx(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, i32 1524 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1525 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1526 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1527 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1528 // CHECK-BE: ret <2 x i64> 1529 // CHECK-LE: @llvm.ppc.altivec.vextduwvlx(<4 x i32> %{{.+}}, <4 x i32> %{{.+}}, i32 1530 // CHECK-LE-NEXT: ret <2 x i64> 1531 return vec_extracth(vuia, vuib, uia); 1532 } 1533 1534 vector unsigned long long test_vec_extracth_ul(void) { 1535 // CHECK-BE: @llvm.ppc.altivec.vextddvrx(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 1536 // CHECK-BE: [[T1:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1537 // CHECK-BE: [[T2:%.+]] = bitcast <2 x i64> %{{.*}} to <4 x i32> 1538 // CHECK-BE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8> {{.+}}) 1539 // CHECK-BE: [[T4:%.+]] = bitcast <4 x i32> [[T3]] to <2 x i64> 1540 // CHECK-BE: ret <2 x i64> 1541 // CHECK-LE: @llvm.ppc.altivec.vextddvlx(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 1542 // CHECK-LE-NEXT: ret <2 x i64> 1543 return vec_extracth(vulla, vullb, uia); 1544 } 1545 1546 vector signed int test_vec_vec_splati_si(void) { 1547 // CHECK: ret <4 x i32> <i32 -17, i32 -17, i32 -17, i32 -17> 1548 return vec_splati(-17); 1549 } 1550 1551 vector unsigned int test_vec_vec_splati_ui(void) { 1552 // CHECK: ret <4 x i32> <i32 16, i32 16, i32 16, i32 16> 1553 return vec_splati(16U); 1554 } 1555 1556 vector float test_vec_vec_splati_f(void) { 1557 // CHECK: ret <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> 1558 return vec_splati(1.0f); 1559 } 1560 1561 vector double test_vec_vec_splatid(void) { 1562 // CHECK-BE: [[T1:%.+]] = fpext float %{{.+}} to double 1563 // CHECK-BE-NEXT: [[T2:%.+]] = insertelement <2 x double> poison, double [[T1:%.+]], i32 0 1564 // CHECK-BE-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x double> poison, <2 x i32> zeroinitialize 1565 // CHECK-BE-NEXT: ret <2 x double> [[T3:%.+]] 1566 // CHECK-LE: [[T1:%.+]] = fpext float %{{.+}} to double 1567 // CHECK-LE-NEXT: [[T2:%.+]] = insertelement <2 x double> poison, double [[T1:%.+]], i32 0 1568 // CHECK-LE-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x double> poison, <2 x i32> zeroinitialize 1569 // CHECK-LE-NEXT: ret <2 x double> [[T3:%.+]] 1570 return vec_splatid(1.0); 1571 } 1572 1573 vector signed int test_vec_vec_splati_ins_si(void) { 1574 // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1 1575 // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}} 1576 // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}} 1577 // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] 1578 // CHECK-BE: ret <4 x i32> 1579 // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1 1580 // CHECK-LE: [[T1:%.+]] = sub i32 1, %{{.+}} 1581 // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] 1582 // CHECK-LE: [[T2:%.+]] = sub i32 3, %{{.+}} 1583 // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]] 1584 // CHECK-LE: ret <4 x i32> 1585 return vec_splati_ins(vsia, 0, -17); 1586 } 1587 1588 vector unsigned int test_vec_vec_splati_ins_ui(void) { 1589 // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1 1590 // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}} 1591 // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}} 1592 // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] 1593 // CHECK-BE: ret <4 x i32> 1594 // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1 1595 // CHECK-LE: [[T1:%.+]] = sub i32 1, %{{.+}} 1596 // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] 1597 // CHECK-LE: [[T2:%.+]] = sub i32 3, %{{.+}} 1598 // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]] 1599 // CHECK-LE: ret <4 x i32> 1600 return vec_splati_ins(vuia, 1, 16U); 1601 } 1602 1603 vector float test_vec_vec_splati_ins_f(void) { 1604 // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1 1605 // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}} 1606 // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}} 1607 // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]] 1608 // CHECK-BE: ret <4 x float> 1609 // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1 1610 // CHECK-LE: [[T1:%.+]] = sub i32 1, %{{.+}} 1611 // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]] 1612 // CHECK-LE: [[T2:%.+]] = sub i32 3, %{{.+}} 1613 // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T2]] 1614 // CHECK-LE: ret <4 x float> 1615 return vec_splati_ins(vfa, 0, 1.0f); 1616 } 1617 1618 // In this test case, the second argument of vec_splati_ins is outside of the 1619 // expected range [0,1]. A mask of 0x01 is applied to obtain an in-range value 1620 // for the second argument. 1621 vector signed int test_vec_vec_splati_ins_range(void) { 1622 // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1 1623 // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}} 1624 // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}} 1625 // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] 1626 // CHECK-BE: ret <4 x i32> 1627 // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1 1628 // CHECK-LE: [[T1:%.+]] = sub i32 1, %{{.+}} 1629 // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] 1630 // CHECK-LE: [[T2:%.+]] = sub i32 3, %{{.+}} 1631 // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]] 1632 // CHECK-LE: ret <4 x i32> 1633 return vec_splati_ins(vsia, 2, -17); 1634 } 1635 1636 void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b, 1637 signed char *__c) { 1638 // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1 1639 vec_xst_trunc(__a, __b, __c); 1640 } 1641 1642 void test_vec_xst_trunc_uc(vector unsigned __int128 __a, signed long long __b, 1643 unsigned char *__c) { 1644 // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1 1645 vec_xst_trunc(__a, __b, __c); 1646 } 1647 1648 void test_vec_xst_trunc_ss(vector signed __int128 __a, signed long long __b, 1649 signed short *__c) { 1650 // CHECK: store i16 %{{.+}}, i16* %{{.+}}, align 2 1651 vec_xst_trunc(__a, __b, __c); 1652 } 1653 1654 void test_vec_xst_trunc_us(vector unsigned __int128 __a, signed long long __b, 1655 unsigned short *__c) { 1656 // CHECK: store i16 %{{.+}}, i16* %{{.+}}, align 2 1657 vec_xst_trunc(__a, __b, __c); 1658 } 1659 1660 void test_vec_xst_trunc_si(vector signed __int128 __a, signed long long __b, 1661 signed int *__c) { 1662 // CHECK: store i32 %{{.+}}, i32* %{{.+}}, align 4 1663 vec_xst_trunc(__a, __b, __c); 1664 } 1665 1666 void test_vec_xst_trunc_ui(vector unsigned __int128 __a, signed long long __b, 1667 unsigned int *__c) { 1668 // CHECK: store i32 %{{.+}}, i32* %{{.+}}, align 4 1669 vec_xst_trunc(__a, __b, __c); 1670 } 1671 1672 void test_vec_xst_trunc_sll(vector signed __int128 __a, signed long long __b, 1673 signed long long *__c) { 1674 // CHECK: store i64 %{{.+}}, i64* %{{.+}}, align 8 1675 vec_xst_trunc(__a, __b, __c); 1676 } 1677 1678 void test_vec_xst_trunc_ull(vector unsigned __int128 __a, signed long long __b, 1679 unsigned long long *__c) { 1680 // CHECK: store i64 %{{.+}}, i64* %{{.+}}, align 8 1681 vec_xst_trunc(__a, __b, __c); 1682 } 1683 1684 vector unsigned __int128 test_vec_slq_unsigned (void) { 1685 // CHECK-LABEL: test_vec_slq_unsigned 1686 // CHECK: shl <1 x i128> %{{.+}}, %{{.+}} 1687 // CHECK: ret <1 x i128> %{{.+}} 1688 return vec_sl(vui128a, vui128b); 1689 } 1690 1691 vector signed __int128 test_vec_slq_signed (void) { 1692 // CHECK-LABEL: test_vec_slq_signed 1693 // CHECK: shl <1 x i128> %{{.+}}, %{{.+}} 1694 // CHECK: ret <1 x i128> 1695 return vec_sl(vi128a, vui128a); 1696 } 1697 1698 vector unsigned __int128 test_vec_srq_unsigned (void) { 1699 // CHECK-LABEL: test_vec_srq_unsigned 1700 // CHECK: lshr <1 x i128> %{{.+}}, %{{.+}} 1701 // CHECK: ret <1 x i128> 1702 return vec_sr(vui128a, vui128b); 1703 } 1704 1705 vector signed __int128 test_vec_srq_signed (void) { 1706 // CHECK-LABEL: test_vec_srq_signed 1707 // CHECK: lshr <1 x i128> %{{.+}}, %{{.+}} 1708 // CHECK: ret <1 x i128> 1709 return vec_sr(vi128a, vui128a); 1710 } 1711 1712 vector unsigned __int128 test_vec_sraq_unsigned (void) { 1713 // CHECK-LABEL: test_vec_sraq_unsigned 1714 // CHECK: ashr <1 x i128> %{{.+}}, %{{.+}} 1715 // CHECK: ret <1 x i128> 1716 return vec_sra(vui128a, vui128b); 1717 } 1718 1719 vector signed __int128 test_vec_sraq_signed (void) { 1720 // CHECK-LABEL: test_vec_sraq_signed 1721 // CHECK: ashr <1 x i128> %{{.+}}, %{{.+}} 1722 // CHECK: ret <1 x i128> 1723 return vec_sra(vi128a, vui128a); 1724 } 1725 1726 1727 int test_vec_test_lsbb_all_ones(void) { 1728 // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i32 1 1729 // CHECK-NEXT: ret i32 1730 return vec_test_lsbb_all_ones(vuca); 1731 } 1732 1733 int test_vec_test_lsbb_all_zeros(void) { 1734 // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i32 0 1735 // CHECK-NEXT: ret i32 1736 return vec_test_lsbb_all_zeros(vuca); 1737 } 1738 1739 vector unsigned __int128 test_vec_mule_u128(void) { 1740 // CHECK-BE: @llvm.ppc.altivec.vmuleud(<2 x i64> 1741 // CHECK-BE-NEXT: ret <1 x i128> 1742 // CHECK-LE: @llvm.ppc.altivec.vmuloud(<2 x i64> 1743 // CHECK-LE-NEXT: ret <1 x i128> 1744 return vec_mule(vulla, vullb); 1745 } 1746 1747 vector signed __int128 test_vec_mule_s128(void) { 1748 // CHECK-BE: @llvm.ppc.altivec.vmulesd(<2 x i64> 1749 // CHECK-BE-NEXT: ret <1 x i128> 1750 // CHECK-LE: @llvm.ppc.altivec.vmulosd(<2 x i64> 1751 // CHECK-LE-NEXT: ret <1 x i128> 1752 return vec_mule(vslla, vsllb); 1753 } 1754 1755 vector unsigned __int128 test_vec_mulo_u128(void) { 1756 // CHECK-BE: @llvm.ppc.altivec.vmuloud(<2 x i64> 1757 // CHECK-BE-NEXT: ret <1 x i128> 1758 // CHECK-LE: @llvm.ppc.altivec.vmuleud(<2 x i64> 1759 // CHECK-LE-NEXT: ret <1 x i128> 1760 return vec_mulo(vulla, vullb); 1761 } 1762 1763 vector signed __int128 test_vec_mulo_s128(void) { 1764 // CHECK-BE: @llvm.ppc.altivec.vmulosd(<2 x i64> 1765 // CHECK-BE-NEXT: ret <1 x i128> 1766 // CHECK-LE: @llvm.ppc.altivec.vmulesd(<2 x i64> 1767 // CHECK-LE-NEXT: ret <1 x i128> 1768 return vec_mulo(vslla, vsllb); 1769 } 1770 1771 vector unsigned __int128 test_vec_msumc_u128(void) { 1772 // CHECK: @llvm.ppc.altivec.vmsumcud(<2 x i64> 1773 // CHECK-NEXT: ret <1 x i128> 1774 return vec_msumc(vulla, vullb, vui128a); 1775 } 1776 1777 vector signed __int128 test_vec_xl_sext_i8(void) { 1778 // CHECK: load i8 1779 // CHECK: sext i8 1780 // CHECK: ret <1 x i128> 1781 return vec_xl_sext(llb, cap); 1782 } 1783 1784 vector signed __int128 test_vec_xl_sext_i16(void) { 1785 // CHECK: load i16 1786 // CHECK: sext i16 1787 // CHECK: ret <1 x i128> 1788 return vec_xl_sext(llb, sap); 1789 } 1790 1791 vector signed __int128 test_vec_xl_sext_i32(void) { 1792 // CHECK: load i32 1793 // CHECK: sext i32 1794 // CHECK: ret <1 x i128> 1795 return vec_xl_sext(llb, iap); 1796 } 1797 1798 vector signed __int128 test_vec_xl_sext_i64(void) { 1799 // CHECK: load i64 1800 // CHECK: sext i64 1801 // CHECK: ret <1 x i128> 1802 return vec_xl_sext(llb, llap); 1803 } 1804 1805 vector unsigned __int128 test_vec_xl_zext_i8(void) { 1806 // CHECK: load i8 1807 // CHECK: zext i8 1808 // CHECK: ret <1 x i128> 1809 return vec_xl_zext(llb, ucap); 1810 } 1811 1812 vector unsigned __int128 test_vec_xl_zext_i16(void) { 1813 // CHECK: load i16 1814 // CHECK: zext i16 1815 // CHECK: ret <1 x i128> 1816 return vec_xl_zext(llb, usap); 1817 } 1818 1819 vector unsigned __int128 test_vec_xl_zext_i32(void) { 1820 // CHECK: load i32 1821 // CHECK: zext i32 1822 // CHECK: ret <1 x i128> 1823 return vec_xl_zext(llb, uiap); 1824 } 1825 1826 vector unsigned __int128 test_vec_xl_zext_i64(void) { 1827 // CHECK: load i64 1828 // CHECK: zext i64 1829 // CHECK: ret <1 x i128> 1830 return vec_xl_zext(llb, ullap); 1831 } 1832 1833 vector signed __int128 test_vec_signextq_s128(void) { 1834 // CHECK: @llvm.ppc.altivec.vextsd2q(<2 x i64> 1835 // CHECK-NEXT: ret <1 x i128> 1836 return vec_signextq(vslla); 1837 } 1838 1839 vector unsigned __int128 test_vec_mod_u128(void) { 1840 // CHECK: urem <1 x i128> 1841 // CHECK-NEXT: ret <1 x i128> 1842 return vec_mod(vui128a, vui128b); 1843 } 1844 1845 vector signed __int128 test_vec_mod_s128(void) { 1846 // CHECK: srem <1 x i128> 1847 // CHECK-NEXT: ret <1 x i128> 1848 return vec_mod(vsi128a, vsi128b); 1849 } 1850 1851 vector bool __int128 test_vec_cmpeq_s128(void) { 1852 // CHECK-LABEL: @test_vec_cmpeq_s128( 1853 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> 1854 // CHECK-NEXT: ret <1 x i128> 1855 return vec_cmpeq(vsi128a, vsi128b); 1856 } 1857 1858 vector bool __int128 test_vec_cmpeq_u128(void) { 1859 // CHECK-LABEL: @test_vec_cmpeq_u128( 1860 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> 1861 // CHECK-NEXT: ret <1 x i128> 1862 return vec_cmpeq(vui128a, vui128b); 1863 } 1864 1865 vector bool __int128 test_vec_cmpeq_bool_int128(void) { 1866 // CHECK-LABEL: @test_vec_cmpeq_bool_int128( 1867 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> 1868 // CHECK-NEXT: ret <1 x i128> 1869 return vec_cmpeq(vbi128a, vbi128b); 1870 } 1871 1872 vector bool __int128 test_vec_cmpne_s128(void) { 1873 // CHECK-LABEL: @test_vec_cmpne_s128( 1874 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> 1875 // CHECK-NEXT: %neg.i = xor <1 x i128> %4, <i128 -1> 1876 // CHECK-NEXT: ret <1 x i128> %neg.i 1877 return vec_cmpne(vsi128a, vsi128b); 1878 } 1879 1880 vector bool __int128 test_vec_cmpne_u128(void) { 1881 // CHECK-LABEL: @test_vec_cmpne_u128( 1882 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> 1883 // CHECK-NEXT: %neg.i = xor <1 x i128> %4, <i128 -1> 1884 // CHECK-NEXT: ret <1 x i128> 1885 return vec_cmpne(vui128a, vui128b); 1886 } 1887 1888 vector bool __int128 test_vec_cmpne_bool_int128(void) { 1889 // CHECK-LABEL: @test_vec_cmpne_bool_int128( 1890 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> 1891 // CHECK-NEXT: %neg.i = xor <1 x i128> %4, <i128 -1> 1892 // CHECK-NEXT: ret <1 x i128> 1893 return vec_cmpne(vbi128a, vbi128b); 1894 } 1895 1896 vector bool __int128 test_vec_cmpgt_s128(void) { 1897 // CHECK-LABEL: @test_vec_cmpgt_s128( 1898 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128> 1899 // CHECK-NEXT: ret <1 x i128> 1900 return vec_cmpgt(vsi128a, vsi128b); 1901 } 1902 1903 vector bool __int128 test_vec_cmpgt_u128(void) { 1904 // CHECK-LABEL: @test_vec_cmpgt_u128( 1905 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128> 1906 // CHECK-NEXT: ret <1 x i128> 1907 return vec_cmpgt(vui128a, vui128b); 1908 } 1909 1910 vector bool __int128 test_vec_cmplt_s128(void) { 1911 // CHECK-LABEL: @test_vec_cmplt_s128( 1912 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128> 1913 // CHECK-NEXT: ret <1 x i128> 1914 return vec_cmplt(vsi128a, vsi128b); 1915 } 1916 1917 vector bool __int128 test_vec_cmplt_u128(void) { 1918 // CHECK-LABEL: @test_vec_cmplt_u128( 1919 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128> 1920 // CHECK-NEXT: ret <1 x i128> 1921 return vec_cmplt(vui128a, vui128b); 1922 } 1923 1924 vector bool __int128 test_vec_cmpge_s128(void) { 1925 // CHECK-LABEL: @test_vec_cmpge_s128( 1926 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128> 1927 // CHECK-NEXT: %neg.i = xor <1 x i128> %6, <i128 -1> 1928 // CHECK-NEXT: ret <1 x i128> 1929 return vec_cmpge(vsi128a, vsi128b); 1930 } 1931 1932 vector bool __int128 test_vec_cmpge_u128(void) { 1933 // CHECK-LABEL: @test_vec_cmpge_u128( 1934 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128> 1935 // CHECK-NEXT: %neg.i = xor <1 x i128> %6, <i128 -1> 1936 // CHECK-NEXT: ret <1 x i128> 1937 return vec_cmpge(vui128a, vui128b); 1938 } 1939 1940 vector bool __int128 test_vec_cmple_s128(void) { 1941 // CHECK-LABEL: @test_vec_cmple_s128( 1942 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128> 1943 // CHECK-NEXT: %neg.i.i = xor <1 x i128> %8, <i128 -1> 1944 // CHECK-NEXT: ret <1 x i128> 1945 return vec_cmple(vsi128a, vsi128b); 1946 } 1947 1948 vector bool __int128 test_vec_cmple_u128(void) { 1949 // CHECK-LABEL: @test_vec_cmple_u128( 1950 // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128> 1951 // CHECK-NEXT: %neg.i.i = xor <1 x i128> %8, <i128 -1> 1952 // CHECK-NEXT: ret <1 x i128> 1953 return vec_cmple(vui128a, vui128b); 1954 } 1955 1956 int test_vec_any_eq_u128(void) { 1957 // CHECK-LABEL: @test_vec_any_eq_u128( 1958 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 1959 // CHECK-NEXT: ret i32 1960 return vec_any_eq(vui128a, vui128b); 1961 } 1962 1963 int test_vec_any_eq_s128(void) { 1964 // CHECK-LABEL: @test_vec_any_eq_s128( 1965 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 1966 // CHECK-NEXT: ret i32 1967 return vec_any_eq(vsi128a, vsi128b); 1968 } 1969 1970 int test_vec_any_eq_bool_int128(void) { 1971 // CHECK-LABEL: @test_vec_any_eq_bool_int128( 1972 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 1973 // CHECK-NEXT: ret i32 1974 return vec_any_eq(vbi128a, vbi128b); 1975 } 1976 1977 int test_vec_any_ne_s128(void) { 1978 // CHECK-LABEL: @test_vec_any_ne_s128( 1979 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 1980 // CHECK-NEXT: ret i32 1981 return vec_any_ne(vsi128a, vsi128b); 1982 } 1983 1984 int test_vec_any_ne_u128(void) { 1985 // CHECK-LABEL: @test_vec_any_ne_u128( 1986 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 1987 // CHECK-NEXT: ret i32 1988 return vec_any_ne(vui128a, vui128b); 1989 } 1990 1991 int test_vec_any_ne_bool_int128(void) { 1992 // CHECK-LABEL: @test_vec_any_ne_bool_int128( 1993 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 1994 // CHECK-NEXT: ret i32 1995 return vec_any_ne(vbi128a, vbi128b); 1996 } 1997 1998 int test_vec_any_lt_s128(void) { 1999 // CHECK-LABEL: @test_vec_any_lt_s128( 2000 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 2001 // CHECK-NEXT: ret i32 2002 return vec_any_lt(vsi128a, vsi128b); 2003 } 2004 2005 int test_vec_any_lt_u128(void) { 2006 // CHECK-LABEL: @test_vec_any_lt_u128( 2007 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 2008 // CHECK-NEXT: ret i32 2009 return vec_any_lt(vui128a, vui128b); 2010 } 2011 2012 int test_vec_any_gt_s128(void) { 2013 // CHECK-LABEL: @test_vec_any_gt_s128( 2014 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 2015 // CHECK-NEXT: ret i32 2016 return vec_any_gt(vsi128a, vsi128b); 2017 } 2018 2019 int test_vec_any_gt_u128(void) { 2020 // CHECK-LABEL: @test_vec_any_gt_u128( 2021 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 1, <1 x i128> %2, <1 x i128> %3) 2022 // CHECK-NEXT: ret i32 2023 return vec_any_gt(vui128a, vui128b); 2024 } 2025 2026 int test_vec_any_le_s128(void) { 2027 // CHECK-LABEL: @test_vec_any_le_s128( 2028 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 2029 // CHECK-NEXT: ret i32 2030 return vec_any_le(vsi128a, vsi128b); 2031 } 2032 2033 int test_vec_any_le_u128(void) { 2034 // CHECK-LABEL: @test_vec_any_le_u128( 2035 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 2036 // CHECK-NEXT: ret i32 2037 return vec_any_le(vui128a, vui128b); 2038 } 2039 2040 int test_vec_any_ge_s128(void) { 2041 // CHECK-LABEL: @test_vec_any_ge_s128( 2042 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 2043 // CHECK-NEXT: ret i32 2044 return vec_any_ge(vsi128a, vsi128b); 2045 } 2046 2047 int test_vec_any_ge_u128(void) { 2048 // CHECK-LABEL: @test_vec_any_ge_u128( 2049 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 3, <1 x i128> %2, <1 x i128> %3) 2050 // CHECK-NEXT: ret i32 2051 return vec_any_ge(vui128a, vui128b); 2052 } 2053 2054 int test_vec_all_eq_s128(void) { 2055 // CHECK-LABEL: @test_vec_all_eq_s128( 2056 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2057 // CHECK-NEXT: ret i32 2058 return vec_all_eq(vsi128a, vsi128b); 2059 } 2060 2061 int test_vec_all_eq_u128(void) { 2062 // CHECK-LABEL: @test_vec_all_eq_u128( 2063 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2064 // CHECK-NEXT: ret i32 2065 return vec_all_eq(vui128a, vui128b); 2066 } 2067 2068 int test_vec_all_eq_bool_int128(void) { 2069 // CHECK-LABEL: @test_vec_all_eq_bool_int128 2070 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2071 // CHECK-NEXT: ret i32 2072 return vec_all_eq(vbi128a, vbi128b); 2073 } 2074 2075 int test_vec_all_ne_s128(void) { 2076 // CHECK-LABEL: @test_vec_all_ne_s128( 2077 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2078 // CHECK-NEXT: ret i32 2079 return vec_all_ne(vsi128a, vsi128b); 2080 } 2081 2082 int test_vec_all_ne_u128(void) { 2083 // CHECK-LABEL: @test_vec_all_ne_u128( 2084 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2085 // CHECK-NEXT: ret i32 2086 return vec_all_ne(vui128a, vui128b); 2087 } 2088 2089 int test_vec_all_ne_bool_int128(void) { 2090 // CHECK-LABEL: test_vec_all_ne_bool_int128 2091 // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2092 // CHECK-NEXT: ret i32 2093 return vec_all_ne(vbi128a, vbi128b); 2094 } 2095 2096 int test_vec_all_lt_s128(void) { 2097 // CHECK-LABEL: @test_vec_all_lt_s128( 2098 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2099 // CHECK-NEXT: ret i32 2100 return vec_all_lt(vsi128a, vsi128b); 2101 } 2102 2103 int test_vec_all_lt_u128(void) { 2104 // CHECK-LABEL: @test_vec_all_lt_u128( 2105 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2106 // CHECK: ret i32 2107 return vec_all_lt(vui128a, vui128b); 2108 } 2109 2110 int test_vec_all_gt_s128(void) { 2111 // CHECK-LABEL: @test_vec_all_gt_s128( 2112 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2113 // CHECK-NEXT: ret i32 2114 return vec_all_gt(vsi128a, vsi128b); 2115 } 2116 2117 int test_vec_all_gt_u128(void) { 2118 // CHECK-LABEL: @test_vec_all_gt_u128( 2119 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 2, <1 x i128> %2, <1 x i128> %3) 2120 // CHECK-NEXT: ret i32 2121 return vec_all_gt(vui128a, vui128b); 2122 } 2123 2124 int test_vec_all_le_s128(void) { 2125 // CHECK-LABEL: @test_vec_all_le_s128( 2126 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2127 // CHECK-NEXT: ret i32 2128 return vec_all_le(vsi128a, vsi128b); 2129 } 2130 2131 int test_vec_all_le_u128(void) { 2132 // CHECK-LABEL: @test_vec_all_le_u128( 2133 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2134 // CHECK-NEXT: ret i32 2135 return vec_all_le(vui128a, vui128b); 2136 } 2137 2138 int test_vec_all_ge_s128(void) { 2139 // CHECK-LABEL: @test_vec_all_ge_s128( 2140 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2141 // CHECK-NEXT: ret i32 2142 return vec_all_ge(vsi128a, vsi128b); 2143 } 2144 2145 int test_vec_all_ge_u128(void) { 2146 // CHECK-LABEL: @test_vec_all_ge_u128( 2147 // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 0, <1 x i128> %2, <1 x i128> %3) 2148 // CHECK-NEXT: ret i32 2149 return vec_all_ge(vui128a, vui128b); 2150 } 2151 2152 vector signed __int128 test_vec_rl_s128(void) { 2153 // CHECK-LABEL: @test_vec_rl_s128( 2154 // CHECK: sub <1 x i128> 2155 // CHECK-NEXT: lshr <1 x i128> 2156 // CHECK-NEXT: or <1 x i128> 2157 // CHECK-NEXT: ret <1 x i128> 2158 return vec_rl(vsi128a, vui128b); 2159 } 2160 2161 vector unsigned __int128 test_vec_rl_u128(void) { 2162 // CHECK-LABEL: @test_vec_rl_u128( 2163 // CHECK: sub <1 x i128> 2164 // CHECK: lshr <1 x i128> 2165 // CHECK: or <1 x i128> 2166 // CHECK-NEXT: ret <1 x i128> 2167 return vec_rl(vui128a, vui128b); 2168 } 2169 2170 vector signed __int128 test_vec_rlnm_s128(void) { 2171 // CHECK-LABEL: @test_vec_rlnm_s128( 2172 // CHECK-LE: %shuffle.i = shufflevector <16 x i8> %7, <16 x i8> %8, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 2173 // CHECK-BE: %shuffle.i = shufflevector <16 x i8> %7, <16 x i8> %8, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 31, i32 30, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 2174 // CHECK: call <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128> 2175 // CHECK-NEXT: ret <1 x i128> 2176 return vec_rlnm(vsi128a, vsi128b, vsi128c); 2177 } 2178 2179 vector unsigned __int128 test_vec_rlnm_u128(void) { 2180 // CHECK-LABEL: @test_vec_rlnm_u128( 2181 // CHECK-LE: %shuffle.i = shufflevector <16 x i8> %7, <16 x i8> %8, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 2182 // CHECK-BE: %shuffle.i = shufflevector <16 x i8> %7, <16 x i8> %8, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 31, i32 30, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 2183 // CHECK: call <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128> 2184 // CHECK-NEXT: ret <1 x i128> 2185 return vec_rlnm(vui128a, vui128b, vui128c); 2186 } 2187 2188 vector signed __int128 test_vec_rlmi_s128(void) { 2189 // CHECK-LABEL: @test_vec_rlmi_s128( 2190 // CHECK: call <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128> 2191 // CHECK-NEXT: ret <1 x i128> 2192 return vec_rlmi(vsi128a, vsi128b, vsi128c); 2193 } 2194 2195 vector unsigned __int128 test_vec_rlmi_u128(void) { 2196 // CHECK-LABEL: @test_vec_rlmi_u128( 2197 // CHECK: call <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128> 2198 // CHECK-NEXT: ret <1 x i128> 2199 return vec_rlmi(vui128a, vui128b, vui128c); 2200 } 2201