1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 15 16 #include "OSTargets.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/Compiler.h" 22 23 namespace clang { 24 namespace targets { 25 26 // PPC abstract base class 27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { 28 29 /// Flags for architecture specific defines. 30 typedef enum { 31 ArchDefineNone = 0, 32 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 33 ArchDefinePpcgr = 1 << 1, 34 ArchDefinePpcsq = 1 << 2, 35 ArchDefine440 = 1 << 3, 36 ArchDefine603 = 1 << 4, 37 ArchDefine604 = 1 << 5, 38 ArchDefinePwr4 = 1 << 6, 39 ArchDefinePwr5 = 1 << 7, 40 ArchDefinePwr5x = 1 << 8, 41 ArchDefinePwr6 = 1 << 9, 42 ArchDefinePwr6x = 1 << 10, 43 ArchDefinePwr7 = 1 << 11, 44 ArchDefinePwr8 = 1 << 12, 45 ArchDefinePwr9 = 1 << 13, 46 ArchDefinePwr10 = 1 << 14, 47 ArchDefineFuture = 1 << 15, 48 ArchDefineA2 = 1 << 16, 49 ArchDefineA2q = 1 << 17, 50 ArchDefineE500 = 1 << 18 51 } ArchDefineTypes; 52 53 ArchDefineTypes ArchDefs = ArchDefineNone; 54 static const Builtin::Info BuiltinInfo[]; 55 static const char *const GCCRegNames[]; 56 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 57 std::string CPU; 58 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; 59 60 // Target cpu features. 61 bool HasAltivec = false; 62 bool HasVSX = false; 63 bool HasP8Vector = false; 64 bool HasP8Crypto = false; 65 bool HasDirectMove = false; 66 bool HasQPX = false; 67 bool HasHTM = false; 68 bool HasBPERMD = false; 69 bool HasExtDiv = false; 70 bool HasP9Vector = false; 71 bool HasSPE = false; 72 73 protected: 74 std::string ABI; 75 76 public: 77 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 78 : TargetInfo(Triple) { 79 SuitableAlign = 128; 80 SimdDefaultAlign = 128; 81 LongDoubleWidth = LongDoubleAlign = 128; 82 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 83 } 84 85 // Set the language option for altivec based on our value. 86 void adjust(LangOptions &Opts) override; 87 88 // Note: GCC recognizes the following additional cpus: 89 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 90 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64. 91 bool isValidCPUName(StringRef Name) const override; 92 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 93 94 bool setCPU(const std::string &Name) override { 95 bool CPUKnown = isValidCPUName(Name); 96 if (CPUKnown) { 97 CPU = Name; 98 99 // CPU identification. 100 ArchDefs = 101 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 102 .Case("440", ArchDefineName) 103 .Case("450", ArchDefineName | ArchDefine440) 104 .Case("601", ArchDefineName) 105 .Case("602", ArchDefineName | ArchDefinePpcgr) 106 .Case("603", ArchDefineName | ArchDefinePpcgr) 107 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 108 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 109 .Case("604", ArchDefineName | ArchDefinePpcgr) 110 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 111 .Case("620", ArchDefineName | ArchDefinePpcgr) 112 .Case("630", ArchDefineName | ArchDefinePpcgr) 113 .Case("7400", ArchDefineName | ArchDefinePpcgr) 114 .Case("7450", ArchDefineName | ArchDefinePpcgr) 115 .Case("750", ArchDefineName | ArchDefinePpcgr) 116 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 117 ArchDefinePpcsq) 118 .Case("a2", ArchDefineA2) 119 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 120 .Cases("power3", "pwr3", ArchDefinePpcgr) 121 .Cases("power4", "pwr4", 122 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 123 .Cases("power5", "pwr5", 124 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 125 ArchDefinePpcsq) 126 .Cases("power5x", "pwr5x", 127 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 128 ArchDefinePpcgr | ArchDefinePpcsq) 129 .Cases("power6", "pwr6", 130 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 131 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 132 .Cases("power6x", "pwr6x", 133 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 134 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 135 ArchDefinePpcsq) 136 .Cases("power7", "pwr7", 137 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 138 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 139 ArchDefinePpcsq) 140 // powerpc64le automatically defaults to at least power8. 141 .Cases("power8", "pwr8", "ppc64le", 142 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 143 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 144 ArchDefinePpcgr | ArchDefinePpcsq) 145 .Cases("power9", "pwr9", 146 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 147 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 148 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 149 .Cases("power10", "pwr10", 150 ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 | 151 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 152 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 153 ArchDefinePpcsq) 154 .Case("future", 155 ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 | 156 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 157 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 158 ArchDefinePpcgr | ArchDefinePpcsq) 159 .Cases("8548", "e500", ArchDefineE500) 160 .Default(ArchDefineNone); 161 } 162 return CPUKnown; 163 } 164 165 StringRef getABI() const override { return ABI; } 166 167 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 168 169 bool isCLZForZeroUndef() const override { return false; } 170 171 void getTargetDefines(const LangOptions &Opts, 172 MacroBuilder &Builder) const override; 173 174 bool 175 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 176 StringRef CPU, 177 const std::vector<std::string> &FeaturesVec) const override; 178 179 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const; 180 181 bool handleTargetFeatures(std::vector<std::string> &Features, 182 DiagnosticsEngine &Diags) override; 183 184 bool hasFeature(StringRef Feature) const override; 185 186 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 187 bool Enabled) const override; 188 189 ArrayRef<const char *> getGCCRegNames() const override; 190 191 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 192 193 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; 194 195 bool validateAsmConstraint(const char *&Name, 196 TargetInfo::ConstraintInfo &Info) const override { 197 switch (*Name) { 198 default: 199 return false; 200 case 'O': // Zero 201 break; 202 case 'f': // Floating point register 203 // Don't use floating point registers on soft float ABI. 204 if (FloatABI == SoftFloat) 205 return false; 206 LLVM_FALLTHROUGH; 207 case 'b': // Base register 208 Info.setAllowsRegister(); 209 break; 210 // FIXME: The following are added to allow parsing. 211 // I just took a guess at what the actions should be. 212 // Also, is more specific checking needed? I.e. specific registers? 213 case 'd': // Floating point register (containing 64-bit value) 214 case 'v': // Altivec vector register 215 // Don't use floating point and altivec vector registers 216 // on soft float ABI 217 if (FloatABI == SoftFloat) 218 return false; 219 Info.setAllowsRegister(); 220 break; 221 case 'w': 222 switch (Name[1]) { 223 case 'd': // VSX vector register to hold vector double data 224 case 'f': // VSX vector register to hold vector float data 225 case 's': // VSX vector register to hold scalar double data 226 case 'w': // VSX vector register to hold scalar double data 227 case 'a': // Any VSX register 228 case 'c': // An individual CR bit 229 case 'i': // FP or VSX register to hold 64-bit integers data 230 break; 231 default: 232 return false; 233 } 234 Info.setAllowsRegister(); 235 Name++; // Skip over 'w'. 236 break; 237 case 'h': // `MQ', `CTR', or `LINK' register 238 case 'q': // `MQ' register 239 case 'c': // `CTR' register 240 case 'l': // `LINK' register 241 case 'x': // `CR' register (condition register) number 0 242 case 'y': // `CR' register (condition register) 243 case 'z': // `XER[CA]' carry bit (part of the XER register) 244 Info.setAllowsRegister(); 245 break; 246 case 'I': // Signed 16-bit constant 247 case 'J': // Unsigned 16-bit constant shifted left 16 bits 248 // (use `L' instead for SImode constants) 249 case 'K': // Unsigned 16-bit constant 250 case 'L': // Signed 16-bit constant shifted left 16 bits 251 case 'M': // Constant larger than 31 252 case 'N': // Exact power of 2 253 case 'P': // Constant whose negation is a signed 16-bit constant 254 case 'G': // Floating point constant that can be loaded into a 255 // register with one instruction per word 256 case 'H': // Integer/Floating point constant that can be loaded 257 // into a register using three instructions 258 break; 259 case 'm': // Memory operand. Note that on PowerPC targets, m can 260 // include addresses that update the base register. It 261 // is therefore only safe to use `m' in an asm statement 262 // if that asm statement accesses the operand exactly once. 263 // The asm statement must also use `%U<opno>' as a 264 // placeholder for the "update" flag in the corresponding 265 // load or store instruction. For example: 266 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 267 // is correct but: 268 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 269 // is not. Use es rather than m if you don't want the base 270 // register to be updated. 271 case 'e': 272 if (Name[1] != 's') 273 return false; 274 // es: A "stable" memory operand; that is, one which does not 275 // include any automodification of the base register. Unlike 276 // `m', this constraint can be used in asm statements that 277 // might access the operand several times, or that might not 278 // access it at all. 279 Info.setAllowsMemory(); 280 Name++; // Skip over 'e'. 281 break; 282 case 'Q': // Memory operand that is an offset from a register (it is 283 // usually better to use `m' or `es' in asm statements) 284 Info.setAllowsRegister(); 285 LLVM_FALLTHROUGH; 286 case 'Z': // Memory operand that is an indexed or indirect from a 287 // register (it is usually better to use `m' or `es' in 288 // asm statements) 289 Info.setAllowsMemory(); 290 break; 291 case 'R': // AIX TOC entry 292 case 'a': // Address operand that is an indexed or indirect from a 293 // register (`p' is preferable for asm statements) 294 case 'S': // Constant suitable as a 64-bit mask operand 295 case 'T': // Constant suitable as a 32-bit mask operand 296 case 'U': // System V Release 4 small data area reference 297 case 't': // AND masks that can be performed by two rldic{l, r} 298 // instructions 299 case 'W': // Vector constant that does not require memory 300 case 'j': // Vector constant that is all zeros. 301 break; 302 // End FIXME. 303 } 304 return true; 305 } 306 307 std::string convertConstraint(const char *&Constraint) const override { 308 std::string R; 309 switch (*Constraint) { 310 case 'e': 311 case 'w': 312 // Two-character constraint; add "^" hint for later parsing. 313 R = std::string("^") + std::string(Constraint, 2); 314 Constraint++; 315 break; 316 default: 317 return TargetInfo::convertConstraint(Constraint); 318 } 319 return R; 320 } 321 322 const char *getClobbers() const override { return ""; } 323 int getEHDataRegisterNumber(unsigned RegNo) const override { 324 if (RegNo == 0) 325 return 3; 326 if (RegNo == 1) 327 return 4; 328 return -1; 329 } 330 331 bool hasSjLjLowering() const override { return true; } 332 333 const char *getLongDoubleMangling() const override { 334 if (LongDoubleWidth == 64) 335 return "e"; 336 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() 337 ? "g" 338 : "u9__ieee128"; 339 } 340 const char *getFloat128Mangling() const override { return "u9__ieee128"; } 341 342 bool hasExtIntType() const override { return true; } 343 }; 344 345 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { 346 public: 347 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 348 : PPCTargetInfo(Triple, Opts) { 349 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 350 351 switch (getTriple().getOS()) { 352 case llvm::Triple::Linux: 353 case llvm::Triple::FreeBSD: 354 case llvm::Triple::NetBSD: 355 SizeType = UnsignedInt; 356 PtrDiffType = SignedInt; 357 IntPtrType = SignedInt; 358 break; 359 case llvm::Triple::AIX: 360 SizeType = UnsignedLong; 361 PtrDiffType = SignedLong; 362 IntPtrType = SignedLong; 363 SuitableAlign = 64; 364 break; 365 default: 366 break; 367 } 368 369 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() || 370 Triple.getOS() == llvm::Triple::AIX || Triple.isMusl()) { 371 LongDoubleWidth = LongDoubleAlign = 64; 372 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 373 } 374 375 // PPC32 supports atomics up to 4 bytes. 376 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 377 } 378 379 BuiltinVaListKind getBuiltinVaListKind() const override { 380 // This is the ELF definition, and is overridden by the Darwin sub-target 381 return TargetInfo::PowerABIBuiltinVaList; 382 } 383 }; 384 385 // Note: ABI differences may eventually require us to have a separate 386 // TargetInfo for little endian. 387 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo { 388 public: 389 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 390 : PPCTargetInfo(Triple, Opts) { 391 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 392 IntMaxType = SignedLong; 393 Int64Type = SignedLong; 394 395 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 396 resetDataLayout("e-m:e-i64:64-n32:64"); 397 ABI = "elfv2"; 398 } else { 399 resetDataLayout("E-m:e-i64:64-n32:64"); 400 ABI = "elfv1"; 401 } 402 403 if (Triple.getOS() == llvm::Triple::AIX) 404 SuitableAlign = 64; 405 406 if (Triple.isOSFreeBSD() || Triple.getOS() == llvm::Triple::AIX || 407 Triple.isMusl()) { 408 LongDoubleWidth = LongDoubleAlign = 64; 409 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 410 } 411 412 // PPC64 supports atomics up to 8 bytes. 413 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 414 } 415 416 BuiltinVaListKind getBuiltinVaListKind() const override { 417 return TargetInfo::CharPtrBuiltinVaList; 418 } 419 420 // PPC64 Linux-specific ABI options. 421 bool setABI(const std::string &Name) override { 422 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 423 ABI = Name; 424 return true; 425 } 426 return false; 427 } 428 429 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 430 switch (CC) { 431 case CC_Swift: 432 return CCCR_OK; 433 default: 434 return CCCR_Warning; 435 } 436 } 437 }; 438 439 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo 440 : public DarwinTargetInfo<PPC32TargetInfo> { 441 public: 442 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 443 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 444 HasAlignMac68kSupport = true; 445 BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool? 446 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 447 LongLongAlign = 32; 448 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 449 } 450 451 BuiltinVaListKind getBuiltinVaListKind() const override { 452 return TargetInfo::CharPtrBuiltinVaList; 453 } 454 }; 455 456 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo 457 : public DarwinTargetInfo<PPC64TargetInfo> { 458 public: 459 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 460 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 461 HasAlignMac68kSupport = true; 462 resetDataLayout("E-m:o-i64:64-n32:64"); 463 } 464 }; 465 466 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : 467 public AIXTargetInfo<PPC32TargetInfo> { 468 public: 469 using AIXTargetInfo::AIXTargetInfo; 470 BuiltinVaListKind getBuiltinVaListKind() const override { 471 return TargetInfo::CharPtrBuiltinVaList; 472 } 473 }; 474 475 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : 476 public AIXTargetInfo<PPC64TargetInfo> { 477 public: 478 using AIXTargetInfo::AIXTargetInfo; 479 }; 480 481 } // namespace targets 482 } // namespace clang 483 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 484