1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 15 16 #include "OSTargets.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/Compiler.h" 22 23 namespace clang { 24 namespace targets { 25 26 // PPC abstract base class 27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { 28 29 /// Flags for architecture specific defines. 30 typedef enum { 31 ArchDefineNone = 0, 32 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 33 ArchDefinePpcgr = 1 << 1, 34 ArchDefinePpcsq = 1 << 2, 35 ArchDefine440 = 1 << 3, 36 ArchDefine603 = 1 << 4, 37 ArchDefine604 = 1 << 5, 38 ArchDefinePwr4 = 1 << 6, 39 ArchDefinePwr5 = 1 << 7, 40 ArchDefinePwr5x = 1 << 8, 41 ArchDefinePwr6 = 1 << 9, 42 ArchDefinePwr6x = 1 << 10, 43 ArchDefinePwr7 = 1 << 11, 44 ArchDefinePwr8 = 1 << 12, 45 ArchDefinePwr9 = 1 << 13, 46 ArchDefinePwr10 = 1 << 14, 47 ArchDefineFuture = 1 << 15, 48 ArchDefineA2 = 1 << 16, 49 ArchDefineE500 = 1 << 18 50 } ArchDefineTypes; 51 52 ArchDefineTypes ArchDefs = ArchDefineNone; 53 static const Builtin::Info BuiltinInfo[]; 54 static const char *const GCCRegNames[]; 55 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 56 std::string CPU; 57 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; 58 59 // Target cpu features. 60 bool HasAltivec = false; 61 bool HasVSX = false; 62 bool HasP8Vector = false; 63 bool HasP8Crypto = false; 64 bool HasDirectMove = false; 65 bool HasHTM = false; 66 bool HasBPERMD = false; 67 bool HasExtDiv = false; 68 bool HasP9Vector = false; 69 bool HasSPE = false; 70 bool PairedVectorMemops = false; 71 bool HasP10Vector = false; 72 bool HasPCRelativeMemops = false; 73 74 protected: 75 std::string ABI; 76 77 public: 78 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 79 : TargetInfo(Triple) { 80 SuitableAlign = 128; 81 SimdDefaultAlign = 128; 82 LongDoubleWidth = LongDoubleAlign = 128; 83 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 84 } 85 86 // Set the language option for altivec based on our value. 87 void adjust(LangOptions &Opts) override; 88 89 // Note: GCC recognizes the following additional cpus: 90 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 91 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64. 92 bool isValidCPUName(StringRef Name) const override; 93 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 94 95 bool setCPU(const std::string &Name) override { 96 bool CPUKnown = isValidCPUName(Name); 97 if (CPUKnown) { 98 CPU = Name; 99 100 // CPU identification. 101 ArchDefs = 102 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 103 .Case("440", ArchDefineName) 104 .Case("450", ArchDefineName | ArchDefine440) 105 .Case("601", ArchDefineName) 106 .Case("602", ArchDefineName | ArchDefinePpcgr) 107 .Case("603", ArchDefineName | ArchDefinePpcgr) 108 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 109 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 110 .Case("604", ArchDefineName | ArchDefinePpcgr) 111 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 112 .Case("620", ArchDefineName | ArchDefinePpcgr) 113 .Case("630", ArchDefineName | ArchDefinePpcgr) 114 .Case("7400", ArchDefineName | ArchDefinePpcgr) 115 .Case("7450", ArchDefineName | ArchDefinePpcgr) 116 .Case("750", ArchDefineName | ArchDefinePpcgr) 117 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 118 ArchDefinePpcsq) 119 .Case("a2", ArchDefineA2) 120 .Cases("power3", "pwr3", ArchDefinePpcgr) 121 .Cases("power4", "pwr4", 122 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 123 .Cases("power5", "pwr5", 124 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 125 ArchDefinePpcsq) 126 .Cases("power5x", "pwr5x", 127 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 128 ArchDefinePpcgr | ArchDefinePpcsq) 129 .Cases("power6", "pwr6", 130 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 131 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 132 .Cases("power6x", "pwr6x", 133 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 134 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 135 ArchDefinePpcsq) 136 .Cases("power7", "pwr7", 137 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 138 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 139 ArchDefinePpcsq) 140 // powerpc64le automatically defaults to at least power8. 141 .Cases("power8", "pwr8", "ppc64le", 142 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 143 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 144 ArchDefinePpcgr | ArchDefinePpcsq) 145 .Cases("power9", "pwr9", 146 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 147 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 148 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 149 .Cases("power10", "pwr10", 150 ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 | 151 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 152 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 153 ArchDefinePpcsq) 154 .Case("future", 155 ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 | 156 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 157 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 158 ArchDefinePpcgr | ArchDefinePpcsq) 159 .Cases("8548", "e500", ArchDefineE500) 160 .Default(ArchDefineNone); 161 } 162 return CPUKnown; 163 } 164 165 StringRef getABI() const override { return ABI; } 166 167 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 168 169 bool isCLZForZeroUndef() const override { return false; } 170 171 void getTargetDefines(const LangOptions &Opts, 172 MacroBuilder &Builder) const override; 173 174 bool 175 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 176 StringRef CPU, 177 const std::vector<std::string> &FeaturesVec) const override; 178 179 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const; 180 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const; 181 182 bool handleTargetFeatures(std::vector<std::string> &Features, 183 DiagnosticsEngine &Diags) override; 184 185 bool hasFeature(StringRef Feature) const override; 186 187 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 188 bool Enabled) const override; 189 190 ArrayRef<const char *> getGCCRegNames() const override; 191 192 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 193 194 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; 195 196 bool validateAsmConstraint(const char *&Name, 197 TargetInfo::ConstraintInfo &Info) const override { 198 switch (*Name) { 199 default: 200 return false; 201 case 'O': // Zero 202 break; 203 case 'f': // Floating point register 204 // Don't use floating point registers on soft float ABI. 205 if (FloatABI == SoftFloat) 206 return false; 207 LLVM_FALLTHROUGH; 208 case 'b': // Base register 209 Info.setAllowsRegister(); 210 break; 211 // FIXME: The following are added to allow parsing. 212 // I just took a guess at what the actions should be. 213 // Also, is more specific checking needed? I.e. specific registers? 214 case 'd': // Floating point register (containing 64-bit value) 215 case 'v': // Altivec vector register 216 // Don't use floating point and altivec vector registers 217 // on soft float ABI 218 if (FloatABI == SoftFloat) 219 return false; 220 Info.setAllowsRegister(); 221 break; 222 case 'w': 223 switch (Name[1]) { 224 case 'd': // VSX vector register to hold vector double data 225 case 'f': // VSX vector register to hold vector float data 226 case 's': // VSX vector register to hold scalar double data 227 case 'w': // VSX vector register to hold scalar double data 228 case 'a': // Any VSX register 229 case 'c': // An individual CR bit 230 case 'i': // FP or VSX register to hold 64-bit integers data 231 break; 232 default: 233 return false; 234 } 235 Info.setAllowsRegister(); 236 Name++; // Skip over 'w'. 237 break; 238 case 'h': // `MQ', `CTR', or `LINK' register 239 case 'q': // `MQ' register 240 case 'c': // `CTR' register 241 case 'l': // `LINK' register 242 case 'x': // `CR' register (condition register) number 0 243 case 'y': // `CR' register (condition register) 244 case 'z': // `XER[CA]' carry bit (part of the XER register) 245 Info.setAllowsRegister(); 246 break; 247 case 'I': // Signed 16-bit constant 248 case 'J': // Unsigned 16-bit constant shifted left 16 bits 249 // (use `L' instead for SImode constants) 250 case 'K': // Unsigned 16-bit constant 251 case 'L': // Signed 16-bit constant shifted left 16 bits 252 case 'M': // Constant larger than 31 253 case 'N': // Exact power of 2 254 case 'P': // Constant whose negation is a signed 16-bit constant 255 case 'G': // Floating point constant that can be loaded into a 256 // register with one instruction per word 257 case 'H': // Integer/Floating point constant that can be loaded 258 // into a register using three instructions 259 break; 260 case 'm': // Memory operand. Note that on PowerPC targets, m can 261 // include addresses that update the base register. It 262 // is therefore only safe to use `m' in an asm statement 263 // if that asm statement accesses the operand exactly once. 264 // The asm statement must also use `%U<opno>' as a 265 // placeholder for the "update" flag in the corresponding 266 // load or store instruction. For example: 267 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 268 // is correct but: 269 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 270 // is not. Use es rather than m if you don't want the base 271 // register to be updated. 272 case 'e': 273 if (Name[1] != 's') 274 return false; 275 // es: A "stable" memory operand; that is, one which does not 276 // include any automodification of the base register. Unlike 277 // `m', this constraint can be used in asm statements that 278 // might access the operand several times, or that might not 279 // access it at all. 280 Info.setAllowsMemory(); 281 Name++; // Skip over 'e'. 282 break; 283 case 'Q': // Memory operand that is an offset from a register (it is 284 // usually better to use `m' or `es' in asm statements) 285 Info.setAllowsRegister(); 286 LLVM_FALLTHROUGH; 287 case 'Z': // Memory operand that is an indexed or indirect from a 288 // register (it is usually better to use `m' or `es' in 289 // asm statements) 290 Info.setAllowsMemory(); 291 break; 292 case 'R': // AIX TOC entry 293 case 'a': // Address operand that is an indexed or indirect from a 294 // register (`p' is preferable for asm statements) 295 case 'S': // Constant suitable as a 64-bit mask operand 296 case 'T': // Constant suitable as a 32-bit mask operand 297 case 'U': // System V Release 4 small data area reference 298 case 't': // AND masks that can be performed by two rldic{l, r} 299 // instructions 300 case 'W': // Vector constant that does not require memory 301 case 'j': // Vector constant that is all zeros. 302 break; 303 // End FIXME. 304 } 305 return true; 306 } 307 308 std::string convertConstraint(const char *&Constraint) const override { 309 std::string R; 310 switch (*Constraint) { 311 case 'e': 312 case 'w': 313 // Two-character constraint; add "^" hint for later parsing. 314 R = std::string("^") + std::string(Constraint, 2); 315 Constraint++; 316 break; 317 default: 318 return TargetInfo::convertConstraint(Constraint); 319 } 320 return R; 321 } 322 323 const char *getClobbers() const override { return ""; } 324 int getEHDataRegisterNumber(unsigned RegNo) const override { 325 if (RegNo == 0) 326 return 3; 327 if (RegNo == 1) 328 return 4; 329 return -1; 330 } 331 332 bool hasSjLjLowering() const override { return true; } 333 334 const char *getLongDoubleMangling() const override { 335 if (LongDoubleWidth == 64) 336 return "e"; 337 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() 338 ? "g" 339 : "u9__ieee128"; 340 } 341 const char *getFloat128Mangling() const override { return "u9__ieee128"; } 342 343 bool hasExtIntType() const override { return true; } 344 345 bool isSPRegName(StringRef RegName) const override { 346 return RegName.equals("r1") || RegName.equals("x1"); 347 } 348 }; 349 350 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { 351 public: 352 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 353 : PPCTargetInfo(Triple, Opts) { 354 if (Triple.isOSAIX()) 355 resetDataLayout("E-m:a-p:32:32-i64:64-n32"); 356 else 357 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 358 359 switch (getTriple().getOS()) { 360 case llvm::Triple::Linux: 361 case llvm::Triple::FreeBSD: 362 case llvm::Triple::NetBSD: 363 SizeType = UnsignedInt; 364 PtrDiffType = SignedInt; 365 IntPtrType = SignedInt; 366 break; 367 case llvm::Triple::AIX: 368 SizeType = UnsignedLong; 369 PtrDiffType = SignedLong; 370 IntPtrType = SignedLong; 371 SuitableAlign = 64; 372 LongDoubleWidth = 64; 373 LongDoubleAlign = DoubleAlign = 32; 374 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 375 break; 376 default: 377 break; 378 } 379 380 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() || 381 Triple.isMusl()) { 382 LongDoubleWidth = LongDoubleAlign = 64; 383 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 384 } 385 386 // PPC32 supports atomics up to 4 bytes. 387 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 388 } 389 390 BuiltinVaListKind getBuiltinVaListKind() const override { 391 // This is the ELF definition, and is overridden by the Darwin sub-target 392 return TargetInfo::PowerABIBuiltinVaList; 393 } 394 }; 395 396 // Note: ABI differences may eventually require us to have a separate 397 // TargetInfo for little endian. 398 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo { 399 public: 400 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 401 : PPCTargetInfo(Triple, Opts) { 402 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 403 IntMaxType = SignedLong; 404 Int64Type = SignedLong; 405 406 if (Triple.isOSAIX()) { 407 // TODO: Set appropriate ABI for AIX platform. 408 resetDataLayout("E-m:a-i64:64-n32:64"); 409 SuitableAlign = 64; 410 LongDoubleWidth = 64; 411 LongDoubleAlign = DoubleAlign = 32; 412 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 413 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) { 414 resetDataLayout("e-m:e-i64:64-n32:64"); 415 ABI = "elfv2"; 416 } else { 417 resetDataLayout("E-m:e-i64:64-n32:64"); 418 ABI = "elfv1"; 419 } 420 421 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) { 422 LongDoubleWidth = LongDoubleAlign = 64; 423 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 424 } 425 426 // PPC64 supports atomics up to 8 bytes. 427 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 428 } 429 430 BuiltinVaListKind getBuiltinVaListKind() const override { 431 return TargetInfo::CharPtrBuiltinVaList; 432 } 433 434 // PPC64 Linux-specific ABI options. 435 bool setABI(const std::string &Name) override { 436 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 437 ABI = Name; 438 return true; 439 } 440 return false; 441 } 442 443 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 444 switch (CC) { 445 case CC_Swift: 446 return CCCR_OK; 447 default: 448 return CCCR_Warning; 449 } 450 } 451 }; 452 453 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo 454 : public DarwinTargetInfo<PPC32TargetInfo> { 455 public: 456 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 457 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 458 HasAlignMac68kSupport = true; 459 BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool? 460 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 461 LongLongAlign = 32; 462 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 463 } 464 465 BuiltinVaListKind getBuiltinVaListKind() const override { 466 return TargetInfo::CharPtrBuiltinVaList; 467 } 468 }; 469 470 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo 471 : public DarwinTargetInfo<PPC64TargetInfo> { 472 public: 473 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 474 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 475 HasAlignMac68kSupport = true; 476 resetDataLayout("E-m:o-i64:64-n32:64"); 477 } 478 }; 479 480 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : 481 public AIXTargetInfo<PPC32TargetInfo> { 482 public: 483 using AIXTargetInfo::AIXTargetInfo; 484 BuiltinVaListKind getBuiltinVaListKind() const override { 485 return TargetInfo::CharPtrBuiltinVaList; 486 } 487 }; 488 489 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : 490 public AIXTargetInfo<PPC64TargetInfo> { 491 public: 492 using AIXTargetInfo::AIXTargetInfo; 493 }; 494 495 } // namespace targets 496 } // namespace clang 497 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 498