1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 15 16 #include "OSTargets.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/Compiler.h" 22 23 namespace clang { 24 namespace targets { 25 26 // PPC abstract base class 27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { 28 29 /// Flags for architecture specific defines. 30 typedef enum { 31 ArchDefineNone = 0, 32 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 33 ArchDefinePpcgr = 1 << 1, 34 ArchDefinePpcsq = 1 << 2, 35 ArchDefine440 = 1 << 3, 36 ArchDefine603 = 1 << 4, 37 ArchDefine604 = 1 << 5, 38 ArchDefinePwr4 = 1 << 6, 39 ArchDefinePwr5 = 1 << 7, 40 ArchDefinePwr5x = 1 << 8, 41 ArchDefinePwr6 = 1 << 9, 42 ArchDefinePwr6x = 1 << 10, 43 ArchDefinePwr7 = 1 << 11, 44 ArchDefinePwr8 = 1 << 12, 45 ArchDefinePwr9 = 1 << 13, 46 ArchDefinePwr10 = 1 << 14, 47 ArchDefineFuture = 1 << 15, 48 ArchDefineA2 = 1 << 16, 49 ArchDefineE500 = 1 << 18 50 } ArchDefineTypes; 51 52 ArchDefineTypes ArchDefs = ArchDefineNone; 53 static const Builtin::Info BuiltinInfo[]; 54 static const char *const GCCRegNames[]; 55 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 56 std::string CPU; 57 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; 58 59 // Target cpu features. 60 bool HasAltivec = false; 61 bool HasMMA = false; 62 bool HasROPProtect = false; 63 bool HasPrivileged = false; 64 bool HasVSX = false; 65 bool HasP8Vector = false; 66 bool HasP8Crypto = false; 67 bool HasDirectMove = false; 68 bool HasHTM = false; 69 bool HasBPERMD = false; 70 bool HasExtDiv = false; 71 bool HasP9Vector = false; 72 bool HasSPE = false; 73 bool PairedVectorMemops = false; 74 bool HasP10Vector = false; 75 bool HasPCRelativeMemops = false; 76 bool HasPrefixInstrs = false; 77 bool IsISA2_07 = false; 78 bool IsISA3_0 = false; 79 bool IsISA3_1 = false; 80 81 protected: 82 std::string ABI; 83 84 public: 85 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 86 : TargetInfo(Triple) { 87 SuitableAlign = 128; 88 SimdDefaultAlign = 128; 89 LongDoubleWidth = LongDoubleAlign = 128; 90 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 91 HasStrictFP = true; 92 HasIbm128 = true; 93 } 94 95 // Set the language option for altivec based on our value. 96 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override; 97 98 // Note: GCC recognizes the following additional cpus: 99 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 100 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64. 101 bool isValidCPUName(StringRef Name) const override; 102 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 103 104 bool setCPU(const std::string &Name) override { 105 bool CPUKnown = isValidCPUName(Name); 106 if (CPUKnown) { 107 CPU = Name; 108 109 // CPU identification. 110 ArchDefs = 111 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 112 .Case("440", ArchDefineName) 113 .Case("450", ArchDefineName | ArchDefine440) 114 .Case("601", ArchDefineName) 115 .Case("602", ArchDefineName | ArchDefinePpcgr) 116 .Case("603", ArchDefineName | ArchDefinePpcgr) 117 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 118 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 119 .Case("604", ArchDefineName | ArchDefinePpcgr) 120 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 121 .Case("620", ArchDefineName | ArchDefinePpcgr) 122 .Case("630", ArchDefineName | ArchDefinePpcgr) 123 .Case("7400", ArchDefineName | ArchDefinePpcgr) 124 .Case("7450", ArchDefineName | ArchDefinePpcgr) 125 .Case("750", ArchDefineName | ArchDefinePpcgr) 126 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 127 ArchDefinePpcsq) 128 .Case("a2", ArchDefineA2) 129 .Cases("power3", "pwr3", ArchDefinePpcgr) 130 .Cases("power4", "pwr4", 131 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 132 .Cases("power5", "pwr5", 133 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 134 ArchDefinePpcsq) 135 .Cases("power5x", "pwr5x", 136 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 137 ArchDefinePpcgr | ArchDefinePpcsq) 138 .Cases("power6", "pwr6", 139 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 140 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 141 .Cases("power6x", "pwr6x", 142 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 143 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 144 ArchDefinePpcsq) 145 .Cases("power7", "pwr7", 146 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 147 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 148 ArchDefinePpcsq) 149 // powerpc64le automatically defaults to at least power8. 150 .Cases("power8", "pwr8", "ppc64le", 151 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 152 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 153 ArchDefinePpcgr | ArchDefinePpcsq) 154 .Cases("power9", "pwr9", 155 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 156 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 157 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 158 .Cases("power10", "pwr10", 159 ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 | 160 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 161 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 162 ArchDefinePpcsq) 163 .Case("future", 164 ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 | 165 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 166 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 167 ArchDefinePpcgr | ArchDefinePpcsq) 168 .Cases("8548", "e500", ArchDefineE500) 169 .Default(ArchDefineNone); 170 } 171 return CPUKnown; 172 } 173 174 StringRef getABI() const override { return ABI; } 175 176 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 177 178 bool isCLZForZeroUndef() const override { return false; } 179 180 void getTargetDefines(const LangOptions &Opts, 181 MacroBuilder &Builder) const override; 182 183 bool 184 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 185 StringRef CPU, 186 const std::vector<std::string> &FeaturesVec) const override; 187 188 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const; 189 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const; 190 191 bool handleTargetFeatures(std::vector<std::string> &Features, 192 DiagnosticsEngine &Diags) override; 193 194 bool hasFeature(StringRef Feature) const override; 195 196 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 197 bool Enabled) const override; 198 199 ArrayRef<const char *> getGCCRegNames() const override; 200 201 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 202 203 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; 204 205 bool validateAsmConstraint(const char *&Name, 206 TargetInfo::ConstraintInfo &Info) const override { 207 switch (*Name) { 208 default: 209 return false; 210 case 'O': // Zero 211 break; 212 case 'f': // Floating point register 213 // Don't use floating point registers on soft float ABI. 214 if (FloatABI == SoftFloat) 215 return false; 216 LLVM_FALLTHROUGH; 217 case 'b': // Base register 218 Info.setAllowsRegister(); 219 break; 220 // FIXME: The following are added to allow parsing. 221 // I just took a guess at what the actions should be. 222 // Also, is more specific checking needed? I.e. specific registers? 223 case 'd': // Floating point register (containing 64-bit value) 224 case 'v': // Altivec vector register 225 // Don't use floating point and altivec vector registers 226 // on soft float ABI 227 if (FloatABI == SoftFloat) 228 return false; 229 Info.setAllowsRegister(); 230 break; 231 case 'w': 232 switch (Name[1]) { 233 case 'd': // VSX vector register to hold vector double data 234 case 'f': // VSX vector register to hold vector float data 235 case 's': // VSX vector register to hold scalar double data 236 case 'w': // VSX vector register to hold scalar double data 237 case 'a': // Any VSX register 238 case 'c': // An individual CR bit 239 case 'i': // FP or VSX register to hold 64-bit integers data 240 break; 241 default: 242 return false; 243 } 244 Info.setAllowsRegister(); 245 Name++; // Skip over 'w'. 246 break; 247 case 'h': // `MQ', `CTR', or `LINK' register 248 case 'q': // `MQ' register 249 case 'c': // `CTR' register 250 case 'l': // `LINK' register 251 case 'x': // `CR' register (condition register) number 0 252 case 'y': // `CR' register (condition register) 253 case 'z': // `XER[CA]' carry bit (part of the XER register) 254 Info.setAllowsRegister(); 255 break; 256 case 'I': // Signed 16-bit constant 257 case 'J': // Unsigned 16-bit constant shifted left 16 bits 258 // (use `L' instead for SImode constants) 259 case 'K': // Unsigned 16-bit constant 260 case 'L': // Signed 16-bit constant shifted left 16 bits 261 case 'M': // Constant larger than 31 262 case 'N': // Exact power of 2 263 case 'P': // Constant whose negation is a signed 16-bit constant 264 case 'G': // Floating point constant that can be loaded into a 265 // register with one instruction per word 266 case 'H': // Integer/Floating point constant that can be loaded 267 // into a register using three instructions 268 break; 269 case 'm': // Memory operand. Note that on PowerPC targets, m can 270 // include addresses that update the base register. It 271 // is therefore only safe to use `m' in an asm statement 272 // if that asm statement accesses the operand exactly once. 273 // The asm statement must also use `%U<opno>' as a 274 // placeholder for the "update" flag in the corresponding 275 // load or store instruction. For example: 276 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 277 // is correct but: 278 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 279 // is not. Use es rather than m if you don't want the base 280 // register to be updated. 281 case 'e': 282 if (Name[1] != 's') 283 return false; 284 // es: A "stable" memory operand; that is, one which does not 285 // include any automodification of the base register. Unlike 286 // `m', this constraint can be used in asm statements that 287 // might access the operand several times, or that might not 288 // access it at all. 289 Info.setAllowsMemory(); 290 Name++; // Skip over 'e'. 291 break; 292 case 'Q': // Memory operand that is an offset from a register (it is 293 // usually better to use `m' or `es' in asm statements) 294 Info.setAllowsRegister(); 295 LLVM_FALLTHROUGH; 296 case 'Z': // Memory operand that is an indexed or indirect from a 297 // register (it is usually better to use `m' or `es' in 298 // asm statements) 299 Info.setAllowsMemory(); 300 break; 301 case 'R': // AIX TOC entry 302 case 'a': // Address operand that is an indexed or indirect from a 303 // register (`p' is preferable for asm statements) 304 case 'S': // Constant suitable as a 64-bit mask operand 305 case 'T': // Constant suitable as a 32-bit mask operand 306 case 'U': // System V Release 4 small data area reference 307 case 't': // AND masks that can be performed by two rldic{l, r} 308 // instructions 309 case 'W': // Vector constant that does not require memory 310 case 'j': // Vector constant that is all zeros. 311 break; 312 // End FIXME. 313 } 314 return true; 315 } 316 317 std::string convertConstraint(const char *&Constraint) const override { 318 std::string R; 319 switch (*Constraint) { 320 case 'e': 321 case 'w': 322 // Two-character constraint; add "^" hint for later parsing. 323 R = std::string("^") + std::string(Constraint, 2); 324 Constraint++; 325 break; 326 default: 327 return TargetInfo::convertConstraint(Constraint); 328 } 329 return R; 330 } 331 332 const char *getClobbers() const override { return ""; } 333 int getEHDataRegisterNumber(unsigned RegNo) const override { 334 if (RegNo == 0) 335 return 3; 336 if (RegNo == 1) 337 return 4; 338 return -1; 339 } 340 341 bool hasSjLjLowering() const override { return true; } 342 343 const char *getLongDoubleMangling() const override { 344 if (LongDoubleWidth == 64) 345 return "e"; 346 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() 347 ? "g" 348 : "u9__ieee128"; 349 } 350 const char *getFloat128Mangling() const override { return "u9__ieee128"; } 351 const char *getIbm128Mangling() const override { return "g"; } 352 353 bool hasExtIntType() const override { return true; } 354 355 bool isSPRegName(StringRef RegName) const override { 356 return RegName.equals("r1") || RegName.equals("x1"); 357 } 358 }; 359 360 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { 361 public: 362 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 363 : PPCTargetInfo(Triple, Opts) { 364 if (Triple.isOSAIX()) 365 resetDataLayout("E-m:a-p:32:32-i64:64-n32"); 366 else if (Triple.getArch() == llvm::Triple::ppcle) 367 resetDataLayout("e-m:e-p:32:32-i64:64-n32"); 368 else 369 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 370 371 switch (getTriple().getOS()) { 372 case llvm::Triple::Linux: 373 case llvm::Triple::FreeBSD: 374 case llvm::Triple::NetBSD: 375 SizeType = UnsignedInt; 376 PtrDiffType = SignedInt; 377 IntPtrType = SignedInt; 378 break; 379 case llvm::Triple::AIX: 380 SizeType = UnsignedLong; 381 PtrDiffType = SignedLong; 382 IntPtrType = SignedLong; 383 LongDoubleWidth = 64; 384 LongDoubleAlign = DoubleAlign = 32; 385 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 386 break; 387 default: 388 break; 389 } 390 391 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() || 392 Triple.isMusl()) { 393 LongDoubleWidth = LongDoubleAlign = 64; 394 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 395 } 396 397 // PPC32 supports atomics up to 4 bytes. 398 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 399 } 400 401 BuiltinVaListKind getBuiltinVaListKind() const override { 402 // This is the ELF definition, and is overridden by the Darwin sub-target 403 return TargetInfo::PowerABIBuiltinVaList; 404 } 405 }; 406 407 // Note: ABI differences may eventually require us to have a separate 408 // TargetInfo for little endian. 409 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo { 410 public: 411 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 412 : PPCTargetInfo(Triple, Opts) { 413 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 414 IntMaxType = SignedLong; 415 Int64Type = SignedLong; 416 std::string DataLayout = ""; 417 418 if (Triple.isOSAIX()) { 419 // TODO: Set appropriate ABI for AIX platform. 420 DataLayout = "E-m:a-i64:64-n32:64"; 421 LongDoubleWidth = 64; 422 LongDoubleAlign = DoubleAlign = 32; 423 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 424 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) { 425 DataLayout = "e-m:e-i64:64-n32:64"; 426 ABI = "elfv2"; 427 } else { 428 DataLayout = "E-m:e-i64:64-n32:64"; 429 ABI = "elfv1"; 430 } 431 432 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) { 433 LongDoubleWidth = LongDoubleAlign = 64; 434 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 435 } 436 437 if (Triple.isOSAIX() || Triple.isOSLinux()) 438 DataLayout += "-S128-v256:256:256-v512:512:512"; 439 resetDataLayout(DataLayout); 440 441 // PPC64 supports atomics up to 8 bytes. 442 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 443 } 444 445 BuiltinVaListKind getBuiltinVaListKind() const override { 446 return TargetInfo::CharPtrBuiltinVaList; 447 } 448 449 // PPC64 Linux-specific ABI options. 450 bool setABI(const std::string &Name) override { 451 if (Name == "elfv1" || Name == "elfv2") { 452 ABI = Name; 453 return true; 454 } 455 return false; 456 } 457 458 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 459 switch (CC) { 460 case CC_Swift: 461 return CCCR_OK; 462 case CC_SwiftAsync: 463 return CCCR_Error; 464 default: 465 return CCCR_Warning; 466 } 467 } 468 }; 469 470 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo 471 : public DarwinTargetInfo<PPC32TargetInfo> { 472 public: 473 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 474 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 475 HasAlignMac68kSupport = true; 476 BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool? 477 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 478 LongLongAlign = 32; 479 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32", "_"); 480 } 481 482 BuiltinVaListKind getBuiltinVaListKind() const override { 483 return TargetInfo::CharPtrBuiltinVaList; 484 } 485 }; 486 487 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo 488 : public DarwinTargetInfo<PPC64TargetInfo> { 489 public: 490 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 491 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 492 HasAlignMac68kSupport = true; 493 resetDataLayout("E-m:o-i64:64-n32:64", "_"); 494 } 495 }; 496 497 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : 498 public AIXTargetInfo<PPC32TargetInfo> { 499 public: 500 using AIXTargetInfo::AIXTargetInfo; 501 BuiltinVaListKind getBuiltinVaListKind() const override { 502 return TargetInfo::CharPtrBuiltinVaList; 503 } 504 }; 505 506 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : 507 public AIXTargetInfo<PPC64TargetInfo> { 508 public: 509 using AIXTargetInfo::AIXTargetInfo; 510 }; 511 512 } // namespace targets 513 } // namespace clang 514 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 515