1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 15 16 #include "OSTargets.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/Compiler.h" 22 23 namespace clang { 24 namespace targets { 25 26 // PPC abstract base class 27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { 28 29 /// Flags for architecture specific defines. 30 typedef enum { 31 ArchDefineNone = 0, 32 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 33 ArchDefinePpcgr = 1 << 1, 34 ArchDefinePpcsq = 1 << 2, 35 ArchDefine440 = 1 << 3, 36 ArchDefine603 = 1 << 4, 37 ArchDefine604 = 1 << 5, 38 ArchDefinePwr4 = 1 << 6, 39 ArchDefinePwr5 = 1 << 7, 40 ArchDefinePwr5x = 1 << 8, 41 ArchDefinePwr6 = 1 << 9, 42 ArchDefinePwr6x = 1 << 10, 43 ArchDefinePwr7 = 1 << 11, 44 ArchDefinePwr8 = 1 << 12, 45 ArchDefinePwr9 = 1 << 13, 46 ArchDefineA2 = 1 << 14, 47 ArchDefineA2q = 1 << 15 48 } ArchDefineTypes; 49 50 51 ArchDefineTypes ArchDefs = ArchDefineNone; 52 static const Builtin::Info BuiltinInfo[]; 53 static const char *const GCCRegNames[]; 54 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 55 std::string CPU; 56 57 // Target cpu features. 58 bool HasAltivec = false; 59 bool HasVSX = false; 60 bool HasP8Vector = false; 61 bool HasP8Crypto = false; 62 bool HasDirectMove = false; 63 bool HasQPX = false; 64 bool HasHTM = false; 65 bool HasBPERMD = false; 66 bool HasExtDiv = false; 67 bool HasP9Vector = false; 68 69 protected: 70 std::string ABI; 71 72 public: 73 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 74 : TargetInfo(Triple) { 75 SuitableAlign = 128; 76 SimdDefaultAlign = 128; 77 LongDoubleWidth = LongDoubleAlign = 128; 78 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 79 } 80 81 // Set the language option for altivec based on our value. 82 void adjust(LangOptions &Opts) override; 83 84 // Note: GCC recognizes the following additional cpus: 85 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 86 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 87 // titan, rs64. 88 bool isValidCPUName(StringRef Name) const override; 89 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 90 91 bool setCPU(const std::string &Name) override { 92 bool CPUKnown = isValidCPUName(Name); 93 if (CPUKnown) { 94 CPU = Name; 95 96 // CPU identification. 97 ArchDefs = 98 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 99 .Case("440", ArchDefineName) 100 .Case("450", ArchDefineName | ArchDefine440) 101 .Case("601", ArchDefineName) 102 .Case("602", ArchDefineName | ArchDefinePpcgr) 103 .Case("603", ArchDefineName | ArchDefinePpcgr) 104 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 105 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 106 .Case("604", ArchDefineName | ArchDefinePpcgr) 107 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 108 .Case("620", ArchDefineName | ArchDefinePpcgr) 109 .Case("630", ArchDefineName | ArchDefinePpcgr) 110 .Case("7400", ArchDefineName | ArchDefinePpcgr) 111 .Case("7450", ArchDefineName | ArchDefinePpcgr) 112 .Case("750", ArchDefineName | ArchDefinePpcgr) 113 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 114 ArchDefinePpcsq) 115 .Case("a2", ArchDefineA2) 116 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 117 .Cases("power3", "pwr3", ArchDefinePpcgr) 118 .Cases("power4", "pwr4", 119 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 120 .Cases("power5", "pwr5", 121 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 122 ArchDefinePpcsq) 123 .Cases("power5x", "pwr5x", 124 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 125 ArchDefinePpcgr | ArchDefinePpcsq) 126 .Cases("power6", "pwr6", 127 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 128 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 129 .Cases("power6x", "pwr6x", 130 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 131 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 132 ArchDefinePpcsq) 133 .Cases("power7", "pwr7", 134 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 135 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 136 ArchDefinePpcsq) 137 // powerpc64le automatically defaults to at least power8. 138 .Cases("power8", "pwr8", "ppc64le", 139 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 140 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 141 ArchDefinePpcgr | ArchDefinePpcsq) 142 .Cases("power9", "pwr9", 143 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 144 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 145 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 146 .Default(ArchDefineNone); 147 } 148 return CPUKnown; 149 } 150 151 StringRef getABI() const override { return ABI; } 152 153 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 154 155 bool isCLZForZeroUndef() const override { return false; } 156 157 void getTargetDefines(const LangOptions &Opts, 158 MacroBuilder &Builder) const override; 159 160 bool 161 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 162 StringRef CPU, 163 const std::vector<std::string> &FeaturesVec) const override; 164 165 bool handleTargetFeatures(std::vector<std::string> &Features, 166 DiagnosticsEngine &Diags) override; 167 168 bool hasFeature(StringRef Feature) const override; 169 170 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 171 bool Enabled) const override; 172 173 ArrayRef<const char *> getGCCRegNames() const override; 174 175 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 176 177 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; 178 179 bool validateAsmConstraint(const char *&Name, 180 TargetInfo::ConstraintInfo &Info) const override { 181 switch (*Name) { 182 default: 183 return false; 184 case 'O': // Zero 185 break; 186 case 'b': // Base register 187 case 'f': // Floating point register 188 Info.setAllowsRegister(); 189 break; 190 // FIXME: The following are added to allow parsing. 191 // I just took a guess at what the actions should be. 192 // Also, is more specific checking needed? I.e. specific registers? 193 case 'd': // Floating point register (containing 64-bit value) 194 case 'v': // Altivec vector register 195 Info.setAllowsRegister(); 196 break; 197 case 'w': 198 switch (Name[1]) { 199 case 'd': // VSX vector register to hold vector double data 200 case 'f': // VSX vector register to hold vector float data 201 case 's': // VSX vector register to hold scalar float data 202 case 'a': // Any VSX register 203 case 'c': // An individual CR bit 204 case 'i': // FP or VSX register to hold 64-bit integers data 205 break; 206 default: 207 return false; 208 } 209 Info.setAllowsRegister(); 210 Name++; // Skip over 'w'. 211 break; 212 case 'h': // `MQ', `CTR', or `LINK' register 213 case 'q': // `MQ' register 214 case 'c': // `CTR' register 215 case 'l': // `LINK' register 216 case 'x': // `CR' register (condition register) number 0 217 case 'y': // `CR' register (condition register) 218 case 'z': // `XER[CA]' carry bit (part of the XER register) 219 Info.setAllowsRegister(); 220 break; 221 case 'I': // Signed 16-bit constant 222 case 'J': // Unsigned 16-bit constant shifted left 16 bits 223 // (use `L' instead for SImode constants) 224 case 'K': // Unsigned 16-bit constant 225 case 'L': // Signed 16-bit constant shifted left 16 bits 226 case 'M': // Constant larger than 31 227 case 'N': // Exact power of 2 228 case 'P': // Constant whose negation is a signed 16-bit constant 229 case 'G': // Floating point constant that can be loaded into a 230 // register with one instruction per word 231 case 'H': // Integer/Floating point constant that can be loaded 232 // into a register using three instructions 233 break; 234 case 'm': // Memory operand. Note that on PowerPC targets, m can 235 // include addresses that update the base register. It 236 // is therefore only safe to use `m' in an asm statement 237 // if that asm statement accesses the operand exactly once. 238 // The asm statement must also use `%U<opno>' as a 239 // placeholder for the "update" flag in the corresponding 240 // load or store instruction. For example: 241 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 242 // is correct but: 243 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 244 // is not. Use es rather than m if you don't want the base 245 // register to be updated. 246 case 'e': 247 if (Name[1] != 's') 248 return false; 249 // es: A "stable" memory operand; that is, one which does not 250 // include any automodification of the base register. Unlike 251 // `m', this constraint can be used in asm statements that 252 // might access the operand several times, or that might not 253 // access it at all. 254 Info.setAllowsMemory(); 255 Name++; // Skip over 'e'. 256 break; 257 case 'Q': // Memory operand that is an offset from a register (it is 258 // usually better to use `m' or `es' in asm statements) 259 case 'Z': // Memory operand that is an indexed or indirect from a 260 // register (it is usually better to use `m' or `es' in 261 // asm statements) 262 Info.setAllowsMemory(); 263 Info.setAllowsRegister(); 264 break; 265 case 'R': // AIX TOC entry 266 case 'a': // Address operand that is an indexed or indirect from a 267 // register (`p' is preferable for asm statements) 268 case 'S': // Constant suitable as a 64-bit mask operand 269 case 'T': // Constant suitable as a 32-bit mask operand 270 case 'U': // System V Release 4 small data area reference 271 case 't': // AND masks that can be performed by two rldic{l, r} 272 // instructions 273 case 'W': // Vector constant that does not require memory 274 case 'j': // Vector constant that is all zeros. 275 break; 276 // End FIXME. 277 } 278 return true; 279 } 280 281 std::string convertConstraint(const char *&Constraint) const override { 282 std::string R; 283 switch (*Constraint) { 284 case 'e': 285 case 'w': 286 // Two-character constraint; add "^" hint for later parsing. 287 R = std::string("^") + std::string(Constraint, 2); 288 Constraint++; 289 break; 290 default: 291 return TargetInfo::convertConstraint(Constraint); 292 } 293 return R; 294 } 295 296 const char *getClobbers() const override { return ""; } 297 int getEHDataRegisterNumber(unsigned RegNo) const override { 298 if (RegNo == 0) 299 return 3; 300 if (RegNo == 1) 301 return 4; 302 return -1; 303 } 304 305 bool hasSjLjLowering() const override { return true; } 306 307 bool useFloat128ManglingForLongDouble() const override { 308 return LongDoubleWidth == 128 && 309 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 310 getTriple().isOSBinFormatELF(); 311 } 312 }; 313 314 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { 315 public: 316 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 317 : PPCTargetInfo(Triple, Opts) { 318 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 319 320 switch (getTriple().getOS()) { 321 case llvm::Triple::Linux: 322 case llvm::Triple::FreeBSD: 323 case llvm::Triple::NetBSD: 324 SizeType = UnsignedInt; 325 PtrDiffType = SignedInt; 326 IntPtrType = SignedInt; 327 break; 328 default: 329 break; 330 } 331 332 switch (getTriple().getOS()) { 333 case llvm::Triple::FreeBSD: 334 case llvm::Triple::NetBSD: 335 case llvm::Triple::OpenBSD: 336 LongDoubleWidth = LongDoubleAlign = 64; 337 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 338 break; 339 default: 340 break; 341 } 342 343 // PPC32 supports atomics up to 4 bytes. 344 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 345 } 346 347 BuiltinVaListKind getBuiltinVaListKind() const override { 348 // This is the ELF definition, and is overridden by the Darwin sub-target 349 return TargetInfo::PowerABIBuiltinVaList; 350 } 351 }; 352 353 // Note: ABI differences may eventually require us to have a separate 354 // TargetInfo for little endian. 355 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo { 356 public: 357 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 358 : PPCTargetInfo(Triple, Opts) { 359 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 360 IntMaxType = SignedLong; 361 Int64Type = SignedLong; 362 363 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 364 resetDataLayout("e-m:e-i64:64-n32:64"); 365 ABI = "elfv2"; 366 } else { 367 resetDataLayout("E-m:e-i64:64-n32:64"); 368 ABI = "elfv1"; 369 } 370 371 switch (getTriple().getOS()) { 372 case llvm::Triple::FreeBSD: 373 LongDoubleWidth = LongDoubleAlign = 64; 374 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 375 break; 376 default: 377 break; 378 } 379 380 // PPC64 supports atomics up to 8 bytes. 381 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 382 } 383 384 BuiltinVaListKind getBuiltinVaListKind() const override { 385 return TargetInfo::CharPtrBuiltinVaList; 386 } 387 388 // PPC64 Linux-specific ABI options. 389 bool setABI(const std::string &Name) override { 390 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 391 ABI = Name; 392 return true; 393 } 394 return false; 395 } 396 397 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 398 switch (CC) { 399 case CC_Swift: 400 return CCCR_OK; 401 default: 402 return CCCR_Warning; 403 } 404 } 405 }; 406 407 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo 408 : public DarwinTargetInfo<PPC32TargetInfo> { 409 public: 410 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 411 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 412 HasAlignMac68kSupport = true; 413 BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool? 414 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 415 LongLongAlign = 32; 416 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 417 } 418 419 BuiltinVaListKind getBuiltinVaListKind() const override { 420 return TargetInfo::CharPtrBuiltinVaList; 421 } 422 }; 423 424 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo 425 : public DarwinTargetInfo<PPC64TargetInfo> { 426 public: 427 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 428 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 429 HasAlignMac68kSupport = true; 430 resetDataLayout("E-m:o-i64:64-n32:64"); 431 } 432 }; 433 434 } // namespace targets 435 } // namespace clang 436 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 437