1 //===--- ARM.h - Declare ARM target feature support -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares ARM TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H
14 #define LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H
15 
16 #include "OSTargets.h"
17 #include "clang/Basic/TargetInfo.h"
18 #include "clang/Basic/TargetOptions.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/Support/Compiler.h"
21 #include "llvm/Support/TargetParser.h"
22 
23 namespace clang {
24 namespace targets {
25 
26 class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {
27   // Possible FPU choices.
28   enum FPUMode {
29     VFP2FPU = (1 << 0),
30     VFP3FPU = (1 << 1),
31     VFP4FPU = (1 << 2),
32     NeonFPU = (1 << 3),
33     FPARMV8 = (1 << 4)
34   };
35 
36   // Possible HWDiv features.
37   enum HWDivMode { HWDivThumb = (1 << 0), HWDivARM = (1 << 1) };
38 
39   static bool FPUModeIsVFP(FPUMode Mode) {
40     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
41   }
42 
43   static const TargetInfo::GCCRegAlias GCCRegAliases[];
44   static const char *const GCCRegNames[];
45 
46   std::string ABI, CPU;
47 
48   StringRef CPUProfile;
49   StringRef CPUAttr;
50 
51   enum { FP_Default, FP_VFP, FP_Neon } FPMath;
52 
53   llvm::ARM::ISAKind ArchISA;
54   llvm::ARM::ArchKind ArchKind = llvm::ARM::ArchKind::ARMV4T;
55   llvm::ARM::ProfileKind ArchProfile;
56   unsigned ArchVersion;
57 
58   unsigned FPU : 5;
59 
60   unsigned IsAAPCS : 1;
61   unsigned HWDiv : 2;
62 
63   // Initialized via features.
64   unsigned SoftFloat : 1;
65   unsigned SoftFloatABI : 1;
66 
67   unsigned CRC : 1;
68   unsigned Crypto : 1;
69   unsigned DSP : 1;
70   unsigned Unaligned : 1;
71   unsigned DotProd : 1;
72 
73   enum {
74     LDREX_B = (1 << 0), /// byte (8-bit)
75     LDREX_H = (1 << 1), /// half (16-bit)
76     LDREX_W = (1 << 2), /// word (32-bit)
77     LDREX_D = (1 << 3), /// double (64-bit)
78   };
79 
80   uint32_t LDREX;
81 
82   // ACLE 6.5.1 Hardware floating point
83   enum {
84     HW_FP_HP = (1 << 1), /// half (16-bit)
85     HW_FP_SP = (1 << 2), /// single (32-bit)
86     HW_FP_DP = (1 << 3), /// double (64-bit)
87   };
88   uint32_t HW_FP;
89 
90   static const Builtin::Info BuiltinInfo[];
91 
92   void setABIAAPCS();
93   void setABIAPCS(bool IsAAPCS16);
94 
95   void setArchInfo();
96   void setArchInfo(llvm::ARM::ArchKind Kind);
97 
98   void setAtomic();
99 
100   bool isThumb() const;
101   bool supportsThumb() const;
102   bool supportsThumb2() const;
103 
104   StringRef getCPUAttr() const;
105   StringRef getCPUProfile() const;
106 
107 public:
108   ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
109 
110   StringRef getABI() const override;
111   bool setABI(const std::string &Name) override;
112 
113   // FIXME: This should be based on Arch attributes, not CPU names.
114   bool
115   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
116                  StringRef CPU,
117                  const std::vector<std::string> &FeaturesVec) const override;
118 
119   bool handleTargetFeatures(std::vector<std::string> &Features,
120                             DiagnosticsEngine &Diags) override;
121 
122   bool hasFeature(StringRef Feature) const override;
123 
124   bool isValidCPUName(StringRef Name) const override;
125   void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
126 
127   bool setCPU(const std::string &Name) override;
128 
129   bool setFPMath(StringRef Name) override;
130 
131   bool useFP16ConversionIntrinsics() const override {
132     return false;
133   }
134 
135   void getTargetDefinesARMV81A(const LangOptions &Opts,
136                                MacroBuilder &Builder) const;
137 
138   void getTargetDefinesARMV82A(const LangOptions &Opts,
139                                MacroBuilder &Builder) const;
140   void getTargetDefines(const LangOptions &Opts,
141                         MacroBuilder &Builder) const override;
142 
143   ArrayRef<Builtin::Info> getTargetBuiltins() const override;
144 
145   bool isCLZForZeroUndef() const override;
146   BuiltinVaListKind getBuiltinVaListKind() const override;
147 
148   ArrayRef<const char *> getGCCRegNames() const override;
149   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
150   bool validateAsmConstraint(const char *&Name,
151                              TargetInfo::ConstraintInfo &Info) const override;
152   std::string convertConstraint(const char *&Constraint) const override;
153   bool
154   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
155                              std::string &SuggestedModifier) const override;
156   const char *getClobbers() const override;
157 
158   StringRef getConstraintRegister(StringRef Constraint,
159                                   StringRef Expression) const override {
160     return Expression;
161   }
162 
163   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override;
164 
165   int getEHDataRegisterNumber(unsigned RegNo) const override;
166 
167   bool hasSjLjLowering() const override;
168 };
169 
170 class LLVM_LIBRARY_VISIBILITY ARMleTargetInfo : public ARMTargetInfo {
171 public:
172   ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
173   void getTargetDefines(const LangOptions &Opts,
174                         MacroBuilder &Builder) const override;
175 };
176 
177 class LLVM_LIBRARY_VISIBILITY ARMbeTargetInfo : public ARMTargetInfo {
178 public:
179   ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
180   void getTargetDefines(const LangOptions &Opts,
181                         MacroBuilder &Builder) const override;
182 };
183 
184 class LLVM_LIBRARY_VISIBILITY WindowsARMTargetInfo
185     : public WindowsTargetInfo<ARMleTargetInfo> {
186   const llvm::Triple Triple;
187 
188 public:
189   WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
190 
191   void getVisualStudioDefines(const LangOptions &Opts,
192                               MacroBuilder &Builder) const;
193 
194   BuiltinVaListKind getBuiltinVaListKind() const override;
195 
196   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override;
197 };
198 
199 // Windows ARM + Itanium C++ ABI Target
200 class LLVM_LIBRARY_VISIBILITY ItaniumWindowsARMleTargetInfo
201     : public WindowsARMTargetInfo {
202 public:
203   ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,
204                                 const TargetOptions &Opts);
205 
206   void getTargetDefines(const LangOptions &Opts,
207                         MacroBuilder &Builder) const override;
208 };
209 
210 // Windows ARM, MS (C++) ABI
211 class LLVM_LIBRARY_VISIBILITY MicrosoftARMleTargetInfo
212     : public WindowsARMTargetInfo {
213 public:
214   MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
215                            const TargetOptions &Opts);
216 
217   void getTargetDefines(const LangOptions &Opts,
218                         MacroBuilder &Builder) const override;
219 };
220 
221 // ARM MinGW target
222 class LLVM_LIBRARY_VISIBILITY MinGWARMTargetInfo : public WindowsARMTargetInfo {
223 public:
224   MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
225 
226   void getTargetDefines(const LangOptions &Opts,
227                         MacroBuilder &Builder) const override;
228 };
229 
230 // ARM Cygwin target
231 class LLVM_LIBRARY_VISIBILITY CygwinARMTargetInfo : public ARMleTargetInfo {
232 public:
233   CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
234 
235   void getTargetDefines(const LangOptions &Opts,
236                         MacroBuilder &Builder) const override;
237 };
238 
239 class LLVM_LIBRARY_VISIBILITY DarwinARMTargetInfo
240     : public DarwinTargetInfo<ARMleTargetInfo> {
241 protected:
242   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
243                     MacroBuilder &Builder) const override;
244 
245 public:
246   DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
247 };
248 
249 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes
250 class LLVM_LIBRARY_VISIBILITY RenderScript32TargetInfo
251     : public ARMleTargetInfo {
252 public:
253   RenderScript32TargetInfo(const llvm::Triple &Triple,
254                            const TargetOptions &Opts);
255 
256   void getTargetDefines(const LangOptions &Opts,
257                         MacroBuilder &Builder) const override;
258 };
259 
260 } // namespace targets
261 } // namespace clang
262 
263 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H
264