1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 if (Maj) 469 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 470 } 471 if (Opts.POSIXThreads) 472 Builder.defineMacro("_REENTRANT"); 473 if (Opts.CPlusPlus) 474 Builder.defineMacro("_GNU_SOURCE"); 475 if (this->HasFloat128) 476 Builder.defineMacro("__FLOAT128__"); 477 } 478 public: 479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 480 : OSTargetInfo<Target>(Triple, Opts) { 481 this->WIntType = TargetInfo::UnsignedInt; 482 483 switch (Triple.getArch()) { 484 default: 485 break; 486 case llvm::Triple::ppc: 487 case llvm::Triple::ppc64: 488 case llvm::Triple::ppc64le: 489 this->MCountName = "_mcount"; 490 break; 491 case llvm::Triple::x86: 492 case llvm::Triple::x86_64: 493 case llvm::Triple::systemz: 494 this->HasFloat128 = true; 495 break; 496 } 497 } 498 499 const char *getStaticInitSectionSpecifier() const override { 500 return ".text.startup"; 501 } 502 }; 503 504 // NetBSD Target 505 template<typename Target> 506 class NetBSDTargetInfo : public OSTargetInfo<Target> { 507 protected: 508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 509 MacroBuilder &Builder) const override { 510 // NetBSD defines; list based off of gcc output 511 Builder.defineMacro("__NetBSD__"); 512 Builder.defineMacro("__unix__"); 513 Builder.defineMacro("__ELF__"); 514 if (Opts.POSIXThreads) 515 Builder.defineMacro("_POSIX_THREADS"); 516 517 switch (Triple.getArch()) { 518 default: 519 break; 520 case llvm::Triple::arm: 521 case llvm::Triple::armeb: 522 case llvm::Triple::thumb: 523 case llvm::Triple::thumbeb: 524 Builder.defineMacro("__ARM_DWARF_EH__"); 525 break; 526 } 527 } 528 public: 529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 530 : OSTargetInfo<Target>(Triple, Opts) { 531 this->MCountName = "_mcount"; 532 } 533 }; 534 535 // OpenBSD Target 536 template<typename Target> 537 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 538 protected: 539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 540 MacroBuilder &Builder) const override { 541 // OpenBSD defines; list based off of gcc output 542 543 Builder.defineMacro("__OpenBSD__"); 544 DefineStd(Builder, "unix", Opts); 545 Builder.defineMacro("__ELF__"); 546 if (Opts.POSIXThreads) 547 Builder.defineMacro("_REENTRANT"); 548 } 549 public: 550 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 551 : OSTargetInfo<Target>(Triple, Opts) { 552 this->TLSSupported = false; 553 554 switch (Triple.getArch()) { 555 default: 556 case llvm::Triple::x86: 557 case llvm::Triple::x86_64: 558 case llvm::Triple::arm: 559 case llvm::Triple::sparc: 560 this->MCountName = "__mcount"; 561 break; 562 case llvm::Triple::mips64: 563 case llvm::Triple::mips64el: 564 case llvm::Triple::ppc: 565 case llvm::Triple::sparcv9: 566 this->MCountName = "_mcount"; 567 break; 568 } 569 } 570 }; 571 572 // Bitrig Target 573 template<typename Target> 574 class BitrigTargetInfo : public OSTargetInfo<Target> { 575 protected: 576 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 577 MacroBuilder &Builder) const override { 578 // Bitrig defines; list based off of gcc output 579 580 Builder.defineMacro("__Bitrig__"); 581 DefineStd(Builder, "unix", Opts); 582 Builder.defineMacro("__ELF__"); 583 if (Opts.POSIXThreads) 584 Builder.defineMacro("_REENTRANT"); 585 586 switch (Triple.getArch()) { 587 default: 588 break; 589 case llvm::Triple::arm: 590 case llvm::Triple::armeb: 591 case llvm::Triple::thumb: 592 case llvm::Triple::thumbeb: 593 Builder.defineMacro("__ARM_DWARF_EH__"); 594 break; 595 } 596 } 597 public: 598 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 599 : OSTargetInfo<Target>(Triple, Opts) { 600 this->MCountName = "__mcount"; 601 } 602 }; 603 604 // PSP Target 605 template<typename Target> 606 class PSPTargetInfo : public OSTargetInfo<Target> { 607 protected: 608 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 609 MacroBuilder &Builder) const override { 610 // PSP defines; list based on the output of the pspdev gcc toolchain. 611 Builder.defineMacro("PSP"); 612 Builder.defineMacro("_PSP"); 613 Builder.defineMacro("__psp__"); 614 Builder.defineMacro("__ELF__"); 615 } 616 public: 617 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 618 }; 619 620 // PS3 PPU Target 621 template<typename Target> 622 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 623 protected: 624 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 625 MacroBuilder &Builder) const override { 626 // PS3 PPU defines. 627 Builder.defineMacro("__PPC__"); 628 Builder.defineMacro("__PPU__"); 629 Builder.defineMacro("__CELLOS_LV2__"); 630 Builder.defineMacro("__ELF__"); 631 Builder.defineMacro("__LP32__"); 632 Builder.defineMacro("_ARCH_PPC64"); 633 Builder.defineMacro("__powerpc64__"); 634 } 635 public: 636 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 637 : OSTargetInfo<Target>(Triple, Opts) { 638 this->LongWidth = this->LongAlign = 32; 639 this->PointerWidth = this->PointerAlign = 32; 640 this->IntMaxType = TargetInfo::SignedLongLong; 641 this->Int64Type = TargetInfo::SignedLongLong; 642 this->SizeType = TargetInfo::UnsignedInt; 643 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 644 } 645 }; 646 647 template <typename Target> 648 class PS4OSTargetInfo : public OSTargetInfo<Target> { 649 protected: 650 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 651 MacroBuilder &Builder) const override { 652 Builder.defineMacro("__FreeBSD__", "9"); 653 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 654 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 655 DefineStd(Builder, "unix", Opts); 656 Builder.defineMacro("__ELF__"); 657 Builder.defineMacro("__ORBIS__"); 658 } 659 public: 660 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 661 : OSTargetInfo<Target>(Triple, Opts) { 662 this->WCharType = this->UnsignedShort; 663 664 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 665 this->MaxTLSAlign = 256; 666 667 // On PS4, do not honor explicit bit field alignment, 668 // as in "__attribute__((aligned(2))) int b : 1;". 669 this->UseExplicitBitFieldAlignment = false; 670 671 switch (Triple.getArch()) { 672 default: 673 case llvm::Triple::x86_64: 674 this->MCountName = ".mcount"; 675 break; 676 } 677 } 678 }; 679 680 // Solaris target 681 template<typename Target> 682 class SolarisTargetInfo : public OSTargetInfo<Target> { 683 protected: 684 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 685 MacroBuilder &Builder) const override { 686 DefineStd(Builder, "sun", Opts); 687 DefineStd(Builder, "unix", Opts); 688 Builder.defineMacro("__ELF__"); 689 Builder.defineMacro("__svr4__"); 690 Builder.defineMacro("__SVR4"); 691 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 692 // newer, but to 500 for everything else. feature_test.h has a check to 693 // ensure that you are not using C99 with an old version of X/Open or C89 694 // with a new version. 695 if (Opts.C99) 696 Builder.defineMacro("_XOPEN_SOURCE", "600"); 697 else 698 Builder.defineMacro("_XOPEN_SOURCE", "500"); 699 if (Opts.CPlusPlus) 700 Builder.defineMacro("__C99FEATURES__"); 701 Builder.defineMacro("_LARGEFILE_SOURCE"); 702 Builder.defineMacro("_LARGEFILE64_SOURCE"); 703 Builder.defineMacro("__EXTENSIONS__"); 704 Builder.defineMacro("_REENTRANT"); 705 } 706 public: 707 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 708 : OSTargetInfo<Target>(Triple, Opts) { 709 this->WCharType = this->SignedInt; 710 // FIXME: WIntType should be SignedLong 711 } 712 }; 713 714 // Windows target 715 template<typename Target> 716 class WindowsTargetInfo : public OSTargetInfo<Target> { 717 protected: 718 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 719 MacroBuilder &Builder) const override { 720 Builder.defineMacro("_WIN32"); 721 } 722 void getVisualStudioDefines(const LangOptions &Opts, 723 MacroBuilder &Builder) const { 724 if (Opts.CPlusPlus) { 725 if (Opts.RTTIData) 726 Builder.defineMacro("_CPPRTTI"); 727 728 if (Opts.CXXExceptions) 729 Builder.defineMacro("_CPPUNWIND"); 730 } 731 732 if (Opts.Bool) 733 Builder.defineMacro("__BOOL_DEFINED"); 734 735 if (!Opts.CharIsSigned) 736 Builder.defineMacro("_CHAR_UNSIGNED"); 737 738 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 739 // but it works for now. 740 if (Opts.POSIXThreads) 741 Builder.defineMacro("_MT"); 742 743 if (Opts.MSCompatibilityVersion) { 744 Builder.defineMacro("_MSC_VER", 745 Twine(Opts.MSCompatibilityVersion / 100000)); 746 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 747 // FIXME We cannot encode the revision information into 32-bits 748 Builder.defineMacro("_MSC_BUILD", Twine(1)); 749 750 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 751 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 752 753 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 754 if (Opts.CPlusPlus1z) 755 Builder.defineMacro("_MSVC_LANG", "201403L"); 756 else if (Opts.CPlusPlus14) 757 Builder.defineMacro("_MSVC_LANG", "201402L"); 758 } 759 } 760 761 if (Opts.MicrosoftExt) { 762 Builder.defineMacro("_MSC_EXTENSIONS"); 763 764 if (Opts.CPlusPlus11) { 765 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 766 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 767 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 768 } 769 } 770 771 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 772 } 773 774 public: 775 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 776 : OSTargetInfo<Target>(Triple, Opts) {} 777 }; 778 779 template <typename Target> 780 class NaClTargetInfo : public OSTargetInfo<Target> { 781 protected: 782 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 783 MacroBuilder &Builder) const override { 784 if (Opts.POSIXThreads) 785 Builder.defineMacro("_REENTRANT"); 786 if (Opts.CPlusPlus) 787 Builder.defineMacro("_GNU_SOURCE"); 788 789 DefineStd(Builder, "unix", Opts); 790 Builder.defineMacro("__ELF__"); 791 Builder.defineMacro("__native_client__"); 792 } 793 794 public: 795 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 796 : OSTargetInfo<Target>(Triple, Opts) { 797 this->LongAlign = 32; 798 this->LongWidth = 32; 799 this->PointerAlign = 32; 800 this->PointerWidth = 32; 801 this->IntMaxType = TargetInfo::SignedLongLong; 802 this->Int64Type = TargetInfo::SignedLongLong; 803 this->DoubleAlign = 64; 804 this->LongDoubleWidth = 64; 805 this->LongDoubleAlign = 64; 806 this->LongLongWidth = 64; 807 this->LongLongAlign = 64; 808 this->SizeType = TargetInfo::UnsignedInt; 809 this->PtrDiffType = TargetInfo::SignedInt; 810 this->IntPtrType = TargetInfo::SignedInt; 811 // RegParmMax is inherited from the underlying architecture. 812 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 813 if (Triple.getArch() == llvm::Triple::arm) { 814 // Handled in ARM's setABI(). 815 } else if (Triple.getArch() == llvm::Triple::x86) { 816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 817 } else if (Triple.getArch() == llvm::Triple::x86_64) { 818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 819 } else if (Triple.getArch() == llvm::Triple::mipsel) { 820 // Handled on mips' setDataLayout. 821 } else { 822 assert(Triple.getArch() == llvm::Triple::le32); 823 this->resetDataLayout("e-p:32:32-i64:64"); 824 } 825 } 826 }; 827 828 // Fuchsia Target 829 template<typename Target> 830 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 831 protected: 832 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 833 MacroBuilder &Builder) const override { 834 Builder.defineMacro("__Fuchsia__"); 835 Builder.defineMacro("__ELF__"); 836 if (Opts.POSIXThreads) 837 Builder.defineMacro("_REENTRANT"); 838 // Required by the libc++ locale support. 839 if (Opts.CPlusPlus) 840 Builder.defineMacro("_GNU_SOURCE"); 841 } 842 public: 843 FuchsiaTargetInfo(const llvm::Triple &Triple, 844 const TargetOptions &Opts) 845 : OSTargetInfo<Target>(Triple, Opts) { 846 this->MCountName = "__mcount"; 847 } 848 }; 849 850 // WebAssembly target 851 template <typename Target> 852 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 853 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 854 MacroBuilder &Builder) const final { 855 // A common platform macro. 856 if (Opts.POSIXThreads) 857 Builder.defineMacro("_REENTRANT"); 858 // Follow g++ convention and predefine _GNU_SOURCE for C++. 859 if (Opts.CPlusPlus) 860 Builder.defineMacro("_GNU_SOURCE"); 861 } 862 863 // As an optimization, group static init code together in a section. 864 const char *getStaticInitSectionSpecifier() const final { 865 return ".text.__startup"; 866 } 867 868 public: 869 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 870 const TargetOptions &Opts) 871 : OSTargetInfo<Target>(Triple, Opts) { 872 this->MCountName = "__mcount"; 873 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 874 } 875 }; 876 877 //===----------------------------------------------------------------------===// 878 // Specific target implementations. 879 //===----------------------------------------------------------------------===// 880 881 // PPC abstract base class 882 class PPCTargetInfo : public TargetInfo { 883 static const Builtin::Info BuiltinInfo[]; 884 static const char * const GCCRegNames[]; 885 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 886 std::string CPU; 887 888 // Target cpu features. 889 bool HasVSX; 890 bool HasP8Vector; 891 bool HasP8Crypto; 892 bool HasDirectMove; 893 bool HasQPX; 894 bool HasHTM; 895 bool HasBPERMD; 896 bool HasExtDiv; 897 bool HasP9Vector; 898 899 protected: 900 std::string ABI; 901 902 public: 903 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 904 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 905 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 906 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 907 SimdDefaultAlign = 128; 908 LongDoubleWidth = LongDoubleAlign = 128; 909 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 910 } 911 912 /// \brief Flags for architecture specific defines. 913 typedef enum { 914 ArchDefineNone = 0, 915 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 916 ArchDefinePpcgr = 1 << 1, 917 ArchDefinePpcsq = 1 << 2, 918 ArchDefine440 = 1 << 3, 919 ArchDefine603 = 1 << 4, 920 ArchDefine604 = 1 << 5, 921 ArchDefinePwr4 = 1 << 6, 922 ArchDefinePwr5 = 1 << 7, 923 ArchDefinePwr5x = 1 << 8, 924 ArchDefinePwr6 = 1 << 9, 925 ArchDefinePwr6x = 1 << 10, 926 ArchDefinePwr7 = 1 << 11, 927 ArchDefinePwr8 = 1 << 12, 928 ArchDefinePwr9 = 1 << 13, 929 ArchDefineA2 = 1 << 14, 930 ArchDefineA2q = 1 << 15 931 } ArchDefineTypes; 932 933 // Note: GCC recognizes the following additional cpus: 934 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 935 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 936 // titan, rs64. 937 bool setCPU(const std::string &Name) override { 938 bool CPUKnown = llvm::StringSwitch<bool>(Name) 939 .Case("generic", true) 940 .Case("440", true) 941 .Case("450", true) 942 .Case("601", true) 943 .Case("602", true) 944 .Case("603", true) 945 .Case("603e", true) 946 .Case("603ev", true) 947 .Case("604", true) 948 .Case("604e", true) 949 .Case("620", true) 950 .Case("630", true) 951 .Case("g3", true) 952 .Case("7400", true) 953 .Case("g4", true) 954 .Case("7450", true) 955 .Case("g4+", true) 956 .Case("750", true) 957 .Case("970", true) 958 .Case("g5", true) 959 .Case("a2", true) 960 .Case("a2q", true) 961 .Case("e500mc", true) 962 .Case("e5500", true) 963 .Case("power3", true) 964 .Case("pwr3", true) 965 .Case("power4", true) 966 .Case("pwr4", true) 967 .Case("power5", true) 968 .Case("pwr5", true) 969 .Case("power5x", true) 970 .Case("pwr5x", true) 971 .Case("power6", true) 972 .Case("pwr6", true) 973 .Case("power6x", true) 974 .Case("pwr6x", true) 975 .Case("power7", true) 976 .Case("pwr7", true) 977 .Case("power8", true) 978 .Case("pwr8", true) 979 .Case("power9", true) 980 .Case("pwr9", true) 981 .Case("powerpc", true) 982 .Case("ppc", true) 983 .Case("powerpc64", true) 984 .Case("ppc64", true) 985 .Case("powerpc64le", true) 986 .Case("ppc64le", true) 987 .Default(false); 988 989 if (CPUKnown) 990 CPU = Name; 991 992 return CPUKnown; 993 } 994 995 996 StringRef getABI() const override { return ABI; } 997 998 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 999 return llvm::makeArrayRef(BuiltinInfo, 1000 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1001 } 1002 1003 bool isCLZForZeroUndef() const override { return false; } 1004 1005 void getTargetDefines(const LangOptions &Opts, 1006 MacroBuilder &Builder) const override; 1007 1008 bool 1009 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1010 StringRef CPU, 1011 const std::vector<std::string> &FeaturesVec) const override; 1012 1013 bool handleTargetFeatures(std::vector<std::string> &Features, 1014 DiagnosticsEngine &Diags) override; 1015 bool hasFeature(StringRef Feature) const override; 1016 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1017 bool Enabled) const override; 1018 1019 ArrayRef<const char *> getGCCRegNames() const override; 1020 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1021 bool validateAsmConstraint(const char *&Name, 1022 TargetInfo::ConstraintInfo &Info) const override { 1023 switch (*Name) { 1024 default: return false; 1025 case 'O': // Zero 1026 break; 1027 case 'b': // Base register 1028 case 'f': // Floating point register 1029 Info.setAllowsRegister(); 1030 break; 1031 // FIXME: The following are added to allow parsing. 1032 // I just took a guess at what the actions should be. 1033 // Also, is more specific checking needed? I.e. specific registers? 1034 case 'd': // Floating point register (containing 64-bit value) 1035 case 'v': // Altivec vector register 1036 Info.setAllowsRegister(); 1037 break; 1038 case 'w': 1039 switch (Name[1]) { 1040 case 'd':// VSX vector register to hold vector double data 1041 case 'f':// VSX vector register to hold vector float data 1042 case 's':// VSX vector register to hold scalar float data 1043 case 'a':// Any VSX register 1044 case 'c':// An individual CR bit 1045 break; 1046 default: 1047 return false; 1048 } 1049 Info.setAllowsRegister(); 1050 Name++; // Skip over 'w'. 1051 break; 1052 case 'h': // `MQ', `CTR', or `LINK' register 1053 case 'q': // `MQ' register 1054 case 'c': // `CTR' register 1055 case 'l': // `LINK' register 1056 case 'x': // `CR' register (condition register) number 0 1057 case 'y': // `CR' register (condition register) 1058 case 'z': // `XER[CA]' carry bit (part of the XER register) 1059 Info.setAllowsRegister(); 1060 break; 1061 case 'I': // Signed 16-bit constant 1062 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1063 // (use `L' instead for SImode constants) 1064 case 'K': // Unsigned 16-bit constant 1065 case 'L': // Signed 16-bit constant shifted left 16 bits 1066 case 'M': // Constant larger than 31 1067 case 'N': // Exact power of 2 1068 case 'P': // Constant whose negation is a signed 16-bit constant 1069 case 'G': // Floating point constant that can be loaded into a 1070 // register with one instruction per word 1071 case 'H': // Integer/Floating point constant that can be loaded 1072 // into a register using three instructions 1073 break; 1074 case 'm': // Memory operand. Note that on PowerPC targets, m can 1075 // include addresses that update the base register. It 1076 // is therefore only safe to use `m' in an asm statement 1077 // if that asm statement accesses the operand exactly once. 1078 // The asm statement must also use `%U<opno>' as a 1079 // placeholder for the "update" flag in the corresponding 1080 // load or store instruction. For example: 1081 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1082 // is correct but: 1083 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1084 // is not. Use es rather than m if you don't want the base 1085 // register to be updated. 1086 case 'e': 1087 if (Name[1] != 's') 1088 return false; 1089 // es: A "stable" memory operand; that is, one which does not 1090 // include any automodification of the base register. Unlike 1091 // `m', this constraint can be used in asm statements that 1092 // might access the operand several times, or that might not 1093 // access it at all. 1094 Info.setAllowsMemory(); 1095 Name++; // Skip over 'e'. 1096 break; 1097 case 'Q': // Memory operand that is an offset from a register (it is 1098 // usually better to use `m' or `es' in asm statements) 1099 case 'Z': // Memory operand that is an indexed or indirect from a 1100 // register (it is usually better to use `m' or `es' in 1101 // asm statements) 1102 Info.setAllowsMemory(); 1103 Info.setAllowsRegister(); 1104 break; 1105 case 'R': // AIX TOC entry 1106 case 'a': // Address operand that is an indexed or indirect from a 1107 // register (`p' is preferable for asm statements) 1108 case 'S': // Constant suitable as a 64-bit mask operand 1109 case 'T': // Constant suitable as a 32-bit mask operand 1110 case 'U': // System V Release 4 small data area reference 1111 case 't': // AND masks that can be performed by two rldic{l, r} 1112 // instructions 1113 case 'W': // Vector constant that does not require memory 1114 case 'j': // Vector constant that is all zeros. 1115 break; 1116 // End FIXME. 1117 } 1118 return true; 1119 } 1120 std::string convertConstraint(const char *&Constraint) const override { 1121 std::string R; 1122 switch (*Constraint) { 1123 case 'e': 1124 case 'w': 1125 // Two-character constraint; add "^" hint for later parsing. 1126 R = std::string("^") + std::string(Constraint, 2); 1127 Constraint++; 1128 break; 1129 default: 1130 return TargetInfo::convertConstraint(Constraint); 1131 } 1132 return R; 1133 } 1134 const char *getClobbers() const override { 1135 return ""; 1136 } 1137 int getEHDataRegisterNumber(unsigned RegNo) const override { 1138 if (RegNo == 0) return 3; 1139 if (RegNo == 1) return 4; 1140 return -1; 1141 } 1142 1143 bool hasSjLjLowering() const override { 1144 return true; 1145 } 1146 1147 bool useFloat128ManglingForLongDouble() const override { 1148 return LongDoubleWidth == 128 && 1149 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1150 getTriple().isOSBinFormatELF(); 1151 } 1152 }; 1153 1154 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1155 #define BUILTIN(ID, TYPE, ATTRS) \ 1156 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1157 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1158 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1159 #include "clang/Basic/BuiltinsPPC.def" 1160 }; 1161 1162 /// handleTargetFeatures - Perform initialization based on the user 1163 /// configured set of features. 1164 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1165 DiagnosticsEngine &Diags) { 1166 for (const auto &Feature : Features) { 1167 if (Feature == "+vsx") { 1168 HasVSX = true; 1169 } else if (Feature == "+bpermd") { 1170 HasBPERMD = true; 1171 } else if (Feature == "+extdiv") { 1172 HasExtDiv = true; 1173 } else if (Feature == "+power8-vector") { 1174 HasP8Vector = true; 1175 } else if (Feature == "+crypto") { 1176 HasP8Crypto = true; 1177 } else if (Feature == "+direct-move") { 1178 HasDirectMove = true; 1179 } else if (Feature == "+qpx") { 1180 HasQPX = true; 1181 } else if (Feature == "+htm") { 1182 HasHTM = true; 1183 } else if (Feature == "+float128") { 1184 HasFloat128 = true; 1185 } else if (Feature == "+power9-vector") { 1186 HasP9Vector = true; 1187 } 1188 // TODO: Finish this list and add an assert that we've handled them 1189 // all. 1190 } 1191 1192 return true; 1193 } 1194 1195 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1196 /// #defines that are not tied to a specific subtarget. 1197 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1198 MacroBuilder &Builder) const { 1199 // Target identification. 1200 Builder.defineMacro("__ppc__"); 1201 Builder.defineMacro("__PPC__"); 1202 Builder.defineMacro("_ARCH_PPC"); 1203 Builder.defineMacro("__powerpc__"); 1204 Builder.defineMacro("__POWERPC__"); 1205 if (PointerWidth == 64) { 1206 Builder.defineMacro("_ARCH_PPC64"); 1207 Builder.defineMacro("__powerpc64__"); 1208 Builder.defineMacro("__ppc64__"); 1209 Builder.defineMacro("__PPC64__"); 1210 } 1211 1212 // Target properties. 1213 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1214 Builder.defineMacro("_LITTLE_ENDIAN"); 1215 } else { 1216 if (getTriple().getOS() != llvm::Triple::NetBSD && 1217 getTriple().getOS() != llvm::Triple::OpenBSD) 1218 Builder.defineMacro("_BIG_ENDIAN"); 1219 } 1220 1221 // ABI options. 1222 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1223 Builder.defineMacro("_CALL_ELF", "1"); 1224 if (ABI == "elfv2") 1225 Builder.defineMacro("_CALL_ELF", "2"); 1226 1227 // Subtarget options. 1228 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1229 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1230 1231 // FIXME: Should be controlled by command line option. 1232 if (LongDoubleWidth == 128) 1233 Builder.defineMacro("__LONG_DOUBLE_128__"); 1234 1235 if (Opts.AltiVec) { 1236 Builder.defineMacro("__VEC__", "10206"); 1237 Builder.defineMacro("__ALTIVEC__"); 1238 } 1239 1240 // CPU identification. 1241 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1242 .Case("440", ArchDefineName) 1243 .Case("450", ArchDefineName | ArchDefine440) 1244 .Case("601", ArchDefineName) 1245 .Case("602", ArchDefineName | ArchDefinePpcgr) 1246 .Case("603", ArchDefineName | ArchDefinePpcgr) 1247 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1248 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1249 .Case("604", ArchDefineName | ArchDefinePpcgr) 1250 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1251 .Case("620", ArchDefineName | ArchDefinePpcgr) 1252 .Case("630", ArchDefineName | ArchDefinePpcgr) 1253 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1254 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1255 .Case("750", ArchDefineName | ArchDefinePpcgr) 1256 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1257 | ArchDefinePpcsq) 1258 .Case("a2", ArchDefineA2) 1259 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1260 .Case("pwr3", ArchDefinePpcgr) 1261 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1262 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1263 | ArchDefinePpcsq) 1264 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1265 | ArchDefinePpcgr | ArchDefinePpcsq) 1266 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1267 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1268 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1269 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1270 | ArchDefinePpcsq) 1271 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1272 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1273 | ArchDefinePpcgr | ArchDefinePpcsq) 1274 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1275 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1276 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1277 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1278 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1279 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1280 | ArchDefinePpcsq) 1281 .Case("power3", ArchDefinePpcgr) 1282 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1283 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1284 | ArchDefinePpcsq) 1285 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1286 | ArchDefinePpcgr | ArchDefinePpcsq) 1287 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1288 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1289 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1290 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1291 | ArchDefinePpcsq) 1292 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1293 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1294 | ArchDefinePpcgr | ArchDefinePpcsq) 1295 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1296 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1297 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1298 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1299 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1300 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1301 | ArchDefinePpcsq) 1302 .Default(ArchDefineNone); 1303 1304 if (defs & ArchDefineName) 1305 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1306 if (defs & ArchDefinePpcgr) 1307 Builder.defineMacro("_ARCH_PPCGR"); 1308 if (defs & ArchDefinePpcsq) 1309 Builder.defineMacro("_ARCH_PPCSQ"); 1310 if (defs & ArchDefine440) 1311 Builder.defineMacro("_ARCH_440"); 1312 if (defs & ArchDefine603) 1313 Builder.defineMacro("_ARCH_603"); 1314 if (defs & ArchDefine604) 1315 Builder.defineMacro("_ARCH_604"); 1316 if (defs & ArchDefinePwr4) 1317 Builder.defineMacro("_ARCH_PWR4"); 1318 if (defs & ArchDefinePwr5) 1319 Builder.defineMacro("_ARCH_PWR5"); 1320 if (defs & ArchDefinePwr5x) 1321 Builder.defineMacro("_ARCH_PWR5X"); 1322 if (defs & ArchDefinePwr6) 1323 Builder.defineMacro("_ARCH_PWR6"); 1324 if (defs & ArchDefinePwr6x) 1325 Builder.defineMacro("_ARCH_PWR6X"); 1326 if (defs & ArchDefinePwr7) 1327 Builder.defineMacro("_ARCH_PWR7"); 1328 if (defs & ArchDefinePwr8) 1329 Builder.defineMacro("_ARCH_PWR8"); 1330 if (defs & ArchDefinePwr9) 1331 Builder.defineMacro("_ARCH_PWR9"); 1332 if (defs & ArchDefineA2) 1333 Builder.defineMacro("_ARCH_A2"); 1334 if (defs & ArchDefineA2q) { 1335 Builder.defineMacro("_ARCH_A2Q"); 1336 Builder.defineMacro("_ARCH_QP"); 1337 } 1338 1339 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1340 Builder.defineMacro("__bg__"); 1341 Builder.defineMacro("__THW_BLUEGENE__"); 1342 Builder.defineMacro("__bgq__"); 1343 Builder.defineMacro("__TOS_BGQ__"); 1344 } 1345 1346 if (HasVSX) 1347 Builder.defineMacro("__VSX__"); 1348 if (HasP8Vector) 1349 Builder.defineMacro("__POWER8_VECTOR__"); 1350 if (HasP8Crypto) 1351 Builder.defineMacro("__CRYPTO__"); 1352 if (HasHTM) 1353 Builder.defineMacro("__HTM__"); 1354 if (HasFloat128) 1355 Builder.defineMacro("__FLOAT128__"); 1356 if (HasP9Vector) 1357 Builder.defineMacro("__POWER9_VECTOR__"); 1358 1359 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1360 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1361 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1362 if (PointerWidth == 64) 1363 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1364 1365 // FIXME: The following are not yet generated here by Clang, but are 1366 // generated by GCC: 1367 // 1368 // _SOFT_FLOAT_ 1369 // __RECIP_PRECISION__ 1370 // __APPLE_ALTIVEC__ 1371 // __RECIP__ 1372 // __RECIPF__ 1373 // __RSQRTE__ 1374 // __RSQRTEF__ 1375 // _SOFT_DOUBLE_ 1376 // __NO_LWSYNC__ 1377 // __HAVE_BSWAP__ 1378 // __LONGDOUBLE128 1379 // __CMODEL_MEDIUM__ 1380 // __CMODEL_LARGE__ 1381 // _CALL_SYSV 1382 // _CALL_DARWIN 1383 // __NO_FPRS__ 1384 } 1385 1386 // Handle explicit options being passed to the compiler here: if we've 1387 // explicitly turned off vsx and turned on any of: 1388 // - power8-vector 1389 // - direct-move 1390 // - float128 1391 // - power9-vector 1392 // then go ahead and error since the customer has expressed an incompatible 1393 // set of options. 1394 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1395 const std::vector<std::string> &FeaturesVec) { 1396 1397 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1398 FeaturesVec.end()) { 1399 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1400 FeaturesVec.end()) { 1401 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1402 << "-mno-vsx"; 1403 return false; 1404 } 1405 1406 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1407 FeaturesVec.end()) { 1408 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1409 << "-mno-vsx"; 1410 return false; 1411 } 1412 1413 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1414 FeaturesVec.end()) { 1415 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1416 << "-mno-vsx"; 1417 return false; 1418 } 1419 1420 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1421 FeaturesVec.end()) { 1422 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1423 << "-mno-vsx"; 1424 return false; 1425 } 1426 } 1427 1428 return true; 1429 } 1430 1431 bool PPCTargetInfo::initFeatureMap( 1432 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1433 const std::vector<std::string> &FeaturesVec) const { 1434 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1435 .Case("7400", true) 1436 .Case("g4", true) 1437 .Case("7450", true) 1438 .Case("g4+", true) 1439 .Case("970", true) 1440 .Case("g5", true) 1441 .Case("pwr6", true) 1442 .Case("pwr7", true) 1443 .Case("pwr8", true) 1444 .Case("pwr9", true) 1445 .Case("ppc64", true) 1446 .Case("ppc64le", true) 1447 .Default(false); 1448 1449 Features["qpx"] = (CPU == "a2q"); 1450 Features["power9-vector"] = (CPU == "pwr9"); 1451 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1452 .Case("ppc64le", true) 1453 .Case("pwr9", true) 1454 .Case("pwr8", true) 1455 .Default(false); 1456 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1457 .Case("ppc64le", true) 1458 .Case("pwr9", true) 1459 .Case("pwr8", true) 1460 .Default(false); 1461 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1462 .Case("ppc64le", true) 1463 .Case("pwr9", true) 1464 .Case("pwr8", true) 1465 .Case("pwr7", true) 1466 .Default(false); 1467 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1468 .Case("ppc64le", true) 1469 .Case("pwr9", true) 1470 .Case("pwr8", true) 1471 .Case("pwr7", true) 1472 .Default(false); 1473 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1474 .Case("ppc64le", true) 1475 .Case("pwr9", true) 1476 .Case("pwr8", true) 1477 .Default(false); 1478 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1479 .Case("ppc64le", true) 1480 .Case("pwr9", true) 1481 .Case("pwr8", true) 1482 .Case("pwr7", true) 1483 .Default(false); 1484 1485 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1486 return false; 1487 1488 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1489 } 1490 1491 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1492 return llvm::StringSwitch<bool>(Feature) 1493 .Case("powerpc", true) 1494 .Case("vsx", HasVSX) 1495 .Case("power8-vector", HasP8Vector) 1496 .Case("crypto", HasP8Crypto) 1497 .Case("direct-move", HasDirectMove) 1498 .Case("qpx", HasQPX) 1499 .Case("htm", HasHTM) 1500 .Case("bpermd", HasBPERMD) 1501 .Case("extdiv", HasExtDiv) 1502 .Case("float128", HasFloat128) 1503 .Case("power9-vector", HasP9Vector) 1504 .Default(false); 1505 } 1506 1507 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1508 StringRef Name, bool Enabled) const { 1509 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1510 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1511 // incompatible options. 1512 if (Enabled) { 1513 if (Name == "direct-move" || 1514 Name == "power8-vector" || 1515 Name == "float128" || 1516 Name == "power9-vector") { 1517 // power9-vector is really a superset of power8-vector so encode that. 1518 Features[Name] = Features["vsx"] = true; 1519 if (Name == "power9-vector") 1520 Features["power8-vector"] = true; 1521 } else { 1522 Features[Name] = true; 1523 } 1524 } else { 1525 if (Name == "vsx") { 1526 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1527 Features["float128"] = Features["power9-vector"] = false; 1528 } else { 1529 Features[Name] = false; 1530 } 1531 } 1532 } 1533 1534 const char * const PPCTargetInfo::GCCRegNames[] = { 1535 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1536 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1537 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1538 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1539 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1540 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1541 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1542 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1543 "mq", "lr", "ctr", "ap", 1544 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1545 "xer", 1546 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1547 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1548 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1549 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1550 "vrsave", "vscr", 1551 "spe_acc", "spefscr", 1552 "sfp" 1553 }; 1554 1555 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1556 return llvm::makeArrayRef(GCCRegNames); 1557 } 1558 1559 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1560 // While some of these aliases do map to different registers 1561 // they still share the same register name. 1562 { { "0" }, "r0" }, 1563 { { "1"}, "r1" }, 1564 { { "2" }, "r2" }, 1565 { { "3" }, "r3" }, 1566 { { "4" }, "r4" }, 1567 { { "5" }, "r5" }, 1568 { { "6" }, "r6" }, 1569 { { "7" }, "r7" }, 1570 { { "8" }, "r8" }, 1571 { { "9" }, "r9" }, 1572 { { "10" }, "r10" }, 1573 { { "11" }, "r11" }, 1574 { { "12" }, "r12" }, 1575 { { "13" }, "r13" }, 1576 { { "14" }, "r14" }, 1577 { { "15" }, "r15" }, 1578 { { "16" }, "r16" }, 1579 { { "17" }, "r17" }, 1580 { { "18" }, "r18" }, 1581 { { "19" }, "r19" }, 1582 { { "20" }, "r20" }, 1583 { { "21" }, "r21" }, 1584 { { "22" }, "r22" }, 1585 { { "23" }, "r23" }, 1586 { { "24" }, "r24" }, 1587 { { "25" }, "r25" }, 1588 { { "26" }, "r26" }, 1589 { { "27" }, "r27" }, 1590 { { "28" }, "r28" }, 1591 { { "29" }, "r29" }, 1592 { { "30" }, "r30" }, 1593 { { "31" }, "r31" }, 1594 { { "fr0" }, "f0" }, 1595 { { "fr1" }, "f1" }, 1596 { { "fr2" }, "f2" }, 1597 { { "fr3" }, "f3" }, 1598 { { "fr4" }, "f4" }, 1599 { { "fr5" }, "f5" }, 1600 { { "fr6" }, "f6" }, 1601 { { "fr7" }, "f7" }, 1602 { { "fr8" }, "f8" }, 1603 { { "fr9" }, "f9" }, 1604 { { "fr10" }, "f10" }, 1605 { { "fr11" }, "f11" }, 1606 { { "fr12" }, "f12" }, 1607 { { "fr13" }, "f13" }, 1608 { { "fr14" }, "f14" }, 1609 { { "fr15" }, "f15" }, 1610 { { "fr16" }, "f16" }, 1611 { { "fr17" }, "f17" }, 1612 { { "fr18" }, "f18" }, 1613 { { "fr19" }, "f19" }, 1614 { { "fr20" }, "f20" }, 1615 { { "fr21" }, "f21" }, 1616 { { "fr22" }, "f22" }, 1617 { { "fr23" }, "f23" }, 1618 { { "fr24" }, "f24" }, 1619 { { "fr25" }, "f25" }, 1620 { { "fr26" }, "f26" }, 1621 { { "fr27" }, "f27" }, 1622 { { "fr28" }, "f28" }, 1623 { { "fr29" }, "f29" }, 1624 { { "fr30" }, "f30" }, 1625 { { "fr31" }, "f31" }, 1626 { { "cc" }, "cr0" }, 1627 }; 1628 1629 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1630 return llvm::makeArrayRef(GCCRegAliases); 1631 } 1632 1633 class PPC32TargetInfo : public PPCTargetInfo { 1634 public: 1635 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1636 : PPCTargetInfo(Triple, Opts) { 1637 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1638 1639 switch (getTriple().getOS()) { 1640 case llvm::Triple::Linux: 1641 case llvm::Triple::FreeBSD: 1642 case llvm::Triple::NetBSD: 1643 SizeType = UnsignedInt; 1644 PtrDiffType = SignedInt; 1645 IntPtrType = SignedInt; 1646 break; 1647 default: 1648 break; 1649 } 1650 1651 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1652 LongDoubleWidth = LongDoubleAlign = 64; 1653 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1654 } 1655 1656 // PPC32 supports atomics up to 4 bytes. 1657 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1658 } 1659 1660 BuiltinVaListKind getBuiltinVaListKind() const override { 1661 // This is the ELF definition, and is overridden by the Darwin sub-target 1662 return TargetInfo::PowerABIBuiltinVaList; 1663 } 1664 }; 1665 1666 // Note: ABI differences may eventually require us to have a separate 1667 // TargetInfo for little endian. 1668 class PPC64TargetInfo : public PPCTargetInfo { 1669 public: 1670 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1671 : PPCTargetInfo(Triple, Opts) { 1672 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1673 IntMaxType = SignedLong; 1674 Int64Type = SignedLong; 1675 1676 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1677 resetDataLayout("e-m:e-i64:64-n32:64"); 1678 ABI = "elfv2"; 1679 } else { 1680 resetDataLayout("E-m:e-i64:64-n32:64"); 1681 ABI = "elfv1"; 1682 } 1683 1684 switch (getTriple().getOS()) { 1685 case llvm::Triple::FreeBSD: 1686 LongDoubleWidth = LongDoubleAlign = 64; 1687 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1688 break; 1689 case llvm::Triple::NetBSD: 1690 IntMaxType = SignedLongLong; 1691 Int64Type = SignedLongLong; 1692 break; 1693 default: 1694 break; 1695 } 1696 1697 // PPC64 supports atomics up to 8 bytes. 1698 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1699 } 1700 BuiltinVaListKind getBuiltinVaListKind() const override { 1701 return TargetInfo::CharPtrBuiltinVaList; 1702 } 1703 // PPC64 Linux-specific ABI options. 1704 bool setABI(const std::string &Name) override { 1705 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1706 ABI = Name; 1707 return true; 1708 } 1709 return false; 1710 } 1711 }; 1712 1713 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1714 public: 1715 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1716 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1717 HasAlignMac68kSupport = true; 1718 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1719 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1720 LongLongAlign = 32; 1721 SuitableAlign = 128; 1722 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1723 } 1724 BuiltinVaListKind getBuiltinVaListKind() const override { 1725 return TargetInfo::CharPtrBuiltinVaList; 1726 } 1727 }; 1728 1729 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1730 public: 1731 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1732 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1733 HasAlignMac68kSupport = true; 1734 SuitableAlign = 128; 1735 resetDataLayout("E-m:o-i64:64-n32:64"); 1736 } 1737 }; 1738 1739 static const unsigned NVPTXAddrSpaceMap[] = { 1740 1, // opencl_global 1741 3, // opencl_local 1742 4, // opencl_constant 1743 // FIXME: generic has to be added to the target 1744 0, // opencl_generic 1745 1, // cuda_device 1746 4, // cuda_constant 1747 3, // cuda_shared 1748 }; 1749 1750 class NVPTXTargetInfo : public TargetInfo { 1751 static const char *const GCCRegNames[]; 1752 static const Builtin::Info BuiltinInfo[]; 1753 CudaArch GPU; 1754 1755 public: 1756 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1757 : TargetInfo(Triple) { 1758 TLSSupported = false; 1759 LongWidth = LongAlign = 64; 1760 AddrSpaceMap = &NVPTXAddrSpaceMap; 1761 UseAddrSpaceMapMangling = true; 1762 // Define available target features 1763 // These must be defined in sorted order! 1764 NoAsmVariants = true; 1765 GPU = CudaArch::SM_20; 1766 1767 // If possible, get a TargetInfo for our host triple, so we can match its 1768 // types. 1769 llvm::Triple HostTriple(Opts.HostTriple); 1770 if (HostTriple.isNVPTX()) 1771 return; 1772 std::unique_ptr<TargetInfo> HostTarget( 1773 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1774 if (!HostTarget) { 1775 return; 1776 } 1777 1778 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1779 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1780 BoolWidth = HostTarget->getBoolWidth(); 1781 BoolAlign = HostTarget->getBoolAlign(); 1782 IntWidth = HostTarget->getIntWidth(); 1783 IntAlign = HostTarget->getIntAlign(); 1784 HalfWidth = HostTarget->getHalfWidth(); 1785 HalfAlign = HostTarget->getHalfAlign(); 1786 FloatWidth = HostTarget->getFloatWidth(); 1787 FloatAlign = HostTarget->getFloatAlign(); 1788 DoubleWidth = HostTarget->getDoubleWidth(); 1789 DoubleAlign = HostTarget->getDoubleAlign(); 1790 LongWidth = HostTarget->getLongWidth(); 1791 LongAlign = HostTarget->getLongAlign(); 1792 LongLongWidth = HostTarget->getLongLongWidth(); 1793 LongLongAlign = HostTarget->getLongLongAlign(); 1794 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1795 NewAlign = HostTarget->getNewAlign(); 1796 DefaultAlignForAttributeAligned = 1797 HostTarget->getDefaultAlignForAttributeAligned(); 1798 SizeType = HostTarget->getSizeType(); 1799 IntMaxType = HostTarget->getIntMaxType(); 1800 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1801 IntPtrType = HostTarget->getIntPtrType(); 1802 WCharType = HostTarget->getWCharType(); 1803 WIntType = HostTarget->getWIntType(); 1804 Char16Type = HostTarget->getChar16Type(); 1805 Char32Type = HostTarget->getChar32Type(); 1806 Int64Type = HostTarget->getInt64Type(); 1807 SigAtomicType = HostTarget->getSigAtomicType(); 1808 ProcessIDType = HostTarget->getProcessIDType(); 1809 1810 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1811 UseZeroLengthBitfieldAlignment = 1812 HostTarget->useZeroLengthBitfieldAlignment(); 1813 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1814 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1815 1816 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1817 // we need those macros to be identical on host and device, because (among 1818 // other things) they affect which standard library classes are defined, and 1819 // we need all classes to be defined on both the host and device. 1820 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1821 1822 // Properties intentionally not copied from host: 1823 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1824 // host/device boundary. 1825 // - SuitableAlign: Not visible across the host/device boundary, and may 1826 // correctly be different on host/device, e.g. if host has wider vector 1827 // types than device. 1828 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1829 // as its double type, but that's not necessarily true on the host. 1830 // TODO: nvcc emits a warning when using long double on device; we should 1831 // do the same. 1832 } 1833 void getTargetDefines(const LangOptions &Opts, 1834 MacroBuilder &Builder) const override { 1835 Builder.defineMacro("__PTX__"); 1836 Builder.defineMacro("__NVPTX__"); 1837 if (Opts.CUDAIsDevice) { 1838 // Set __CUDA_ARCH__ for the GPU specified. 1839 std::string CUDAArchCode = [this] { 1840 switch (GPU) { 1841 case CudaArch::UNKNOWN: 1842 assert(false && "No GPU arch when compiling CUDA device code."); 1843 return ""; 1844 case CudaArch::SM_20: 1845 return "200"; 1846 case CudaArch::SM_21: 1847 return "210"; 1848 case CudaArch::SM_30: 1849 return "300"; 1850 case CudaArch::SM_32: 1851 return "320"; 1852 case CudaArch::SM_35: 1853 return "350"; 1854 case CudaArch::SM_37: 1855 return "370"; 1856 case CudaArch::SM_50: 1857 return "500"; 1858 case CudaArch::SM_52: 1859 return "520"; 1860 case CudaArch::SM_53: 1861 return "530"; 1862 case CudaArch::SM_60: 1863 return "600"; 1864 case CudaArch::SM_61: 1865 return "610"; 1866 case CudaArch::SM_62: 1867 return "620"; 1868 } 1869 llvm_unreachable("unhandled CudaArch"); 1870 }(); 1871 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1872 } 1873 } 1874 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1875 return llvm::makeArrayRef(BuiltinInfo, 1876 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1877 } 1878 bool 1879 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1880 StringRef CPU, 1881 const std::vector<std::string> &FeaturesVec) const override { 1882 Features["satom"] = GPU >= CudaArch::SM_60; 1883 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1884 } 1885 1886 bool hasFeature(StringRef Feature) const override { 1887 return llvm::StringSwitch<bool>(Feature) 1888 .Cases("ptx", "nvptx", true) 1889 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1890 .Default(false); 1891 } 1892 1893 ArrayRef<const char *> getGCCRegNames() const override; 1894 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1895 // No aliases. 1896 return None; 1897 } 1898 bool validateAsmConstraint(const char *&Name, 1899 TargetInfo::ConstraintInfo &Info) const override { 1900 switch (*Name) { 1901 default: 1902 return false; 1903 case 'c': 1904 case 'h': 1905 case 'r': 1906 case 'l': 1907 case 'f': 1908 case 'd': 1909 Info.setAllowsRegister(); 1910 return true; 1911 } 1912 } 1913 const char *getClobbers() const override { 1914 // FIXME: Is this really right? 1915 return ""; 1916 } 1917 BuiltinVaListKind getBuiltinVaListKind() const override { 1918 // FIXME: implement 1919 return TargetInfo::CharPtrBuiltinVaList; 1920 } 1921 bool setCPU(const std::string &Name) override { 1922 GPU = StringToCudaArch(Name); 1923 return GPU != CudaArch::UNKNOWN; 1924 } 1925 void setSupportedOpenCLOpts() override { 1926 auto &Opts = getSupportedOpenCLOpts(); 1927 Opts.cl_clang_storage_class_specifiers = 1; 1928 Opts.cl_khr_gl_sharing = 1; 1929 Opts.cl_khr_icd = 1; 1930 1931 Opts.cl_khr_fp64 = 1; 1932 Opts.cl_khr_byte_addressable_store = 1; 1933 Opts.cl_khr_global_int32_base_atomics = 1; 1934 Opts.cl_khr_global_int32_extended_atomics = 1; 1935 Opts.cl_khr_local_int32_base_atomics = 1; 1936 Opts.cl_khr_local_int32_extended_atomics = 1; 1937 } 1938 }; 1939 1940 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1941 #define BUILTIN(ID, TYPE, ATTRS) \ 1942 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1943 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1944 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1945 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 1946 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 1947 #include "clang/Basic/BuiltinsNVPTX.def" 1948 }; 1949 1950 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1951 1952 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1953 return llvm::makeArrayRef(GCCRegNames); 1954 } 1955 1956 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1957 public: 1958 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1959 : NVPTXTargetInfo(Triple, Opts) { 1960 LongWidth = LongAlign = 32; 1961 PointerWidth = PointerAlign = 32; 1962 SizeType = TargetInfo::UnsignedInt; 1963 PtrDiffType = TargetInfo::SignedInt; 1964 IntPtrType = TargetInfo::SignedInt; 1965 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1966 } 1967 }; 1968 1969 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1970 public: 1971 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1972 : NVPTXTargetInfo(Triple, Opts) { 1973 PointerWidth = PointerAlign = 64; 1974 SizeType = TargetInfo::UnsignedLong; 1975 PtrDiffType = TargetInfo::SignedLong; 1976 IntPtrType = TargetInfo::SignedLong; 1977 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1978 } 1979 }; 1980 1981 static const unsigned AMDGPUAddrSpaceMap[] = { 1982 1, // opencl_global 1983 3, // opencl_local 1984 2, // opencl_constant 1985 4, // opencl_generic 1986 1, // cuda_device 1987 2, // cuda_constant 1988 3 // cuda_shared 1989 }; 1990 1991 // If you edit the description strings, make sure you update 1992 // getPointerWidthV(). 1993 1994 static const char *const DataLayoutStringR600 = 1995 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1996 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1997 1998 static const char *const DataLayoutStringSI = 1999 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2000 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2001 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2002 2003 class AMDGPUTargetInfo final : public TargetInfo { 2004 static const Builtin::Info BuiltinInfo[]; 2005 static const char * const GCCRegNames[]; 2006 2007 /// \brief The GPU profiles supported by the AMDGPU target. 2008 enum GPUKind { 2009 GK_NONE, 2010 GK_R600, 2011 GK_R600_DOUBLE_OPS, 2012 GK_R700, 2013 GK_R700_DOUBLE_OPS, 2014 GK_EVERGREEN, 2015 GK_EVERGREEN_DOUBLE_OPS, 2016 GK_NORTHERN_ISLANDS, 2017 GK_CAYMAN, 2018 GK_GFX6, 2019 GK_GFX7, 2020 GK_GFX8 2021 } GPU; 2022 2023 bool hasFP64:1; 2024 bool hasFMAF:1; 2025 bool hasLDEXPF:1; 2026 bool hasFullSpeedFP32Denorms:1; 2027 2028 static bool isAMDGCN(const llvm::Triple &TT) { 2029 return TT.getArch() == llvm::Triple::amdgcn; 2030 } 2031 2032 public: 2033 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2034 : TargetInfo(Triple) , 2035 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2036 hasFP64(false), 2037 hasFMAF(false), 2038 hasLDEXPF(false), 2039 hasFullSpeedFP32Denorms(false){ 2040 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2041 hasFP64 = true; 2042 hasFMAF = true; 2043 hasLDEXPF = true; 2044 } 2045 2046 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2047 DataLayoutStringSI : DataLayoutStringR600); 2048 2049 AddrSpaceMap = &AMDGPUAddrSpaceMap; 2050 UseAddrSpaceMapMangling = true; 2051 } 2052 2053 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2054 if (GPU <= GK_CAYMAN) 2055 return 32; 2056 2057 switch(AddrSpace) { 2058 default: 2059 return 64; 2060 case 0: 2061 case 3: 2062 case 5: 2063 return 32; 2064 } 2065 } 2066 2067 uint64_t getMaxPointerWidth() const override { 2068 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2069 } 2070 2071 const char * getClobbers() const override { 2072 return ""; 2073 } 2074 2075 ArrayRef<const char *> getGCCRegNames() const override; 2076 2077 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2078 return None; 2079 } 2080 2081 bool validateAsmConstraint(const char *&Name, 2082 TargetInfo::ConstraintInfo &Info) const override { 2083 switch (*Name) { 2084 default: break; 2085 case 'v': // vgpr 2086 case 's': // sgpr 2087 Info.setAllowsRegister(); 2088 return true; 2089 } 2090 return false; 2091 } 2092 2093 bool initFeatureMap(llvm::StringMap<bool> &Features, 2094 DiagnosticsEngine &Diags, StringRef CPU, 2095 const std::vector<std::string> &FeatureVec) const override; 2096 2097 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2098 TargetOptions &TargetOpts) const override { 2099 bool hasFP32Denormals = false; 2100 bool hasFP64Denormals = false; 2101 for (auto &I : TargetOpts.FeaturesAsWritten) { 2102 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2103 hasFP32Denormals = true; 2104 if (I == "+fp64-denormals" || I == "-fp64-denormals") 2105 hasFP64Denormals = true; 2106 } 2107 if (!hasFP32Denormals) 2108 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms && 2109 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2110 // Always do not flush fp64 denorms. 2111 if (!hasFP64Denormals && hasFP64) 2112 TargetOpts.Features.push_back("+fp64-denormals"); 2113 } 2114 2115 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2116 return llvm::makeArrayRef(BuiltinInfo, 2117 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2118 } 2119 2120 void getTargetDefines(const LangOptions &Opts, 2121 MacroBuilder &Builder) const override { 2122 if (getTriple().getArch() == llvm::Triple::amdgcn) 2123 Builder.defineMacro("__AMDGCN__"); 2124 else 2125 Builder.defineMacro("__R600__"); 2126 2127 if (hasFMAF) 2128 Builder.defineMacro("__HAS_FMAF__"); 2129 if (hasLDEXPF) 2130 Builder.defineMacro("__HAS_LDEXPF__"); 2131 if (hasFP64) 2132 Builder.defineMacro("__HAS_FP64__"); 2133 } 2134 2135 BuiltinVaListKind getBuiltinVaListKind() const override { 2136 return TargetInfo::CharPtrBuiltinVaList; 2137 } 2138 2139 static GPUKind parseR600Name(StringRef Name) { 2140 return llvm::StringSwitch<GPUKind>(Name) 2141 .Case("r600" , GK_R600) 2142 .Case("rv610", GK_R600) 2143 .Case("rv620", GK_R600) 2144 .Case("rv630", GK_R600) 2145 .Case("rv635", GK_R600) 2146 .Case("rs780", GK_R600) 2147 .Case("rs880", GK_R600) 2148 .Case("rv670", GK_R600_DOUBLE_OPS) 2149 .Case("rv710", GK_R700) 2150 .Case("rv730", GK_R700) 2151 .Case("rv740", GK_R700_DOUBLE_OPS) 2152 .Case("rv770", GK_R700_DOUBLE_OPS) 2153 .Case("palm", GK_EVERGREEN) 2154 .Case("cedar", GK_EVERGREEN) 2155 .Case("sumo", GK_EVERGREEN) 2156 .Case("sumo2", GK_EVERGREEN) 2157 .Case("redwood", GK_EVERGREEN) 2158 .Case("juniper", GK_EVERGREEN) 2159 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2160 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2161 .Case("barts", GK_NORTHERN_ISLANDS) 2162 .Case("turks", GK_NORTHERN_ISLANDS) 2163 .Case("caicos", GK_NORTHERN_ISLANDS) 2164 .Case("cayman", GK_CAYMAN) 2165 .Case("aruba", GK_CAYMAN) 2166 .Default(GK_NONE); 2167 } 2168 2169 static GPUKind parseAMDGCNName(StringRef Name) { 2170 return llvm::StringSwitch<GPUKind>(Name) 2171 .Case("tahiti", GK_GFX6) 2172 .Case("pitcairn", GK_GFX6) 2173 .Case("verde", GK_GFX6) 2174 .Case("oland", GK_GFX6) 2175 .Case("hainan", GK_GFX6) 2176 .Case("bonaire", GK_GFX7) 2177 .Case("kabini", GK_GFX7) 2178 .Case("kaveri", GK_GFX7) 2179 .Case("hawaii", GK_GFX7) 2180 .Case("mullins", GK_GFX7) 2181 .Case("gfx700", GK_GFX7) 2182 .Case("gfx701", GK_GFX7) 2183 .Case("gfx702", GK_GFX7) 2184 .Case("tonga", GK_GFX8) 2185 .Case("iceland", GK_GFX8) 2186 .Case("carrizo", GK_GFX8) 2187 .Case("fiji", GK_GFX8) 2188 .Case("stoney", GK_GFX8) 2189 .Case("polaris10", GK_GFX8) 2190 .Case("polaris11", GK_GFX8) 2191 .Case("gfx800", GK_GFX8) 2192 .Case("gfx801", GK_GFX8) 2193 .Case("gfx802", GK_GFX8) 2194 .Case("gfx803", GK_GFX8) 2195 .Case("gfx804", GK_GFX8) 2196 .Case("gfx810", GK_GFX8) 2197 .Default(GK_NONE); 2198 } 2199 2200 bool setCPU(const std::string &Name) override { 2201 if (getTriple().getArch() == llvm::Triple::amdgcn) 2202 GPU = parseAMDGCNName(Name); 2203 else 2204 GPU = parseR600Name(Name); 2205 2206 return GPU != GK_NONE; 2207 } 2208 2209 void setSupportedOpenCLOpts() override { 2210 auto &Opts = getSupportedOpenCLOpts(); 2211 Opts.cl_clang_storage_class_specifiers = 1; 2212 Opts.cl_khr_icd = 1; 2213 2214 if (hasFP64) 2215 Opts.cl_khr_fp64 = 1; 2216 if (GPU >= GK_EVERGREEN) { 2217 Opts.cl_khr_byte_addressable_store = 1; 2218 Opts.cl_khr_global_int32_base_atomics = 1; 2219 Opts.cl_khr_global_int32_extended_atomics = 1; 2220 Opts.cl_khr_local_int32_base_atomics = 1; 2221 Opts.cl_khr_local_int32_extended_atomics = 1; 2222 } 2223 if (GPU >= GK_GFX6) { 2224 Opts.cl_khr_fp16 = 1; 2225 Opts.cl_khr_int64_base_atomics = 1; 2226 Opts.cl_khr_int64_extended_atomics = 1; 2227 Opts.cl_khr_mipmap_image = 1; 2228 Opts.cl_khr_subgroups = 1; 2229 Opts.cl_khr_3d_image_writes = 1; 2230 Opts.cl_amd_media_ops = 1; 2231 Opts.cl_amd_media_ops2 = 1; 2232 } 2233 } 2234 2235 LangAS::ID getOpenCLImageAddrSpace() const override { 2236 return LangAS::opencl_constant; 2237 } 2238 2239 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2240 switch (CC) { 2241 default: 2242 return CCCR_Warning; 2243 case CC_C: 2244 case CC_OpenCLKernel: 2245 return CCCR_OK; 2246 } 2247 } 2248 2249 // In amdgcn target the null pointer in global, constant, and generic 2250 // address space has value 0 but in private and local address space has 2251 // value ~0. 2252 uint64_t getNullPointerValue(unsigned AS) const override { 2253 return AS != LangAS::opencl_local && AS != 0 ? 0 : ~0; 2254 } 2255 }; 2256 2257 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2258 #define BUILTIN(ID, TYPE, ATTRS) \ 2259 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2260 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2261 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2262 #include "clang/Basic/BuiltinsAMDGPU.def" 2263 }; 2264 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2265 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2266 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2267 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2268 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2269 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2270 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2271 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2272 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2273 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2274 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2275 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2276 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2277 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2278 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2279 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2280 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2281 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2282 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2283 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2284 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2285 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2286 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2287 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2288 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2289 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2290 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2291 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2292 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2293 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2294 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2295 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2296 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2297 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2298 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2299 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2300 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2301 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2302 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2303 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2304 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2305 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2306 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2307 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2308 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2309 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2310 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2311 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2312 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2313 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2314 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2315 }; 2316 2317 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2318 return llvm::makeArrayRef(GCCRegNames); 2319 } 2320 2321 bool AMDGPUTargetInfo::initFeatureMap( 2322 llvm::StringMap<bool> &Features, 2323 DiagnosticsEngine &Diags, StringRef CPU, 2324 const std::vector<std::string> &FeatureVec) const { 2325 2326 // XXX - What does the member GPU mean if device name string passed here? 2327 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2328 if (CPU.empty()) 2329 CPU = "tahiti"; 2330 2331 switch (parseAMDGCNName(CPU)) { 2332 case GK_GFX6: 2333 case GK_GFX7: 2334 break; 2335 2336 case GK_GFX8: 2337 Features["s-memrealtime"] = true; 2338 Features["16-bit-insts"] = true; 2339 break; 2340 2341 case GK_NONE: 2342 return false; 2343 default: 2344 llvm_unreachable("unhandled subtarget"); 2345 } 2346 } else { 2347 if (CPU.empty()) 2348 CPU = "r600"; 2349 2350 switch (parseR600Name(CPU)) { 2351 case GK_R600: 2352 case GK_R700: 2353 case GK_EVERGREEN: 2354 case GK_NORTHERN_ISLANDS: 2355 break; 2356 case GK_R600_DOUBLE_OPS: 2357 case GK_R700_DOUBLE_OPS: 2358 case GK_EVERGREEN_DOUBLE_OPS: 2359 case GK_CAYMAN: 2360 Features["fp64"] = true; 2361 break; 2362 case GK_NONE: 2363 return false; 2364 default: 2365 llvm_unreachable("unhandled subtarget"); 2366 } 2367 } 2368 2369 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2370 } 2371 2372 const Builtin::Info BuiltinInfoX86[] = { 2373 #define BUILTIN(ID, TYPE, ATTRS) \ 2374 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2375 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2376 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2377 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2378 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2379 #include "clang/Basic/BuiltinsX86.def" 2380 2381 #define BUILTIN(ID, TYPE, ATTRS) \ 2382 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2383 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2384 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2385 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2386 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2387 #include "clang/Basic/BuiltinsX86_64.def" 2388 }; 2389 2390 2391 static const char* const GCCRegNames[] = { 2392 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2393 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2394 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2395 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2396 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2397 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2398 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2399 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2400 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2401 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2402 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2403 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2404 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2405 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2406 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2407 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2408 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2409 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2410 }; 2411 2412 const TargetInfo::AddlRegName AddlRegNames[] = { 2413 { { "al", "ah", "eax", "rax" }, 0 }, 2414 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2415 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2416 { { "dl", "dh", "edx", "rdx" }, 1 }, 2417 { { "esi", "rsi" }, 4 }, 2418 { { "edi", "rdi" }, 5 }, 2419 { { "esp", "rsp" }, 7 }, 2420 { { "ebp", "rbp" }, 6 }, 2421 { { "r8d", "r8w", "r8b" }, 38 }, 2422 { { "r9d", "r9w", "r9b" }, 39 }, 2423 { { "r10d", "r10w", "r10b" }, 40 }, 2424 { { "r11d", "r11w", "r11b" }, 41 }, 2425 { { "r12d", "r12w", "r12b" }, 42 }, 2426 { { "r13d", "r13w", "r13b" }, 43 }, 2427 { { "r14d", "r14w", "r14b" }, 44 }, 2428 { { "r15d", "r15w", "r15b" }, 45 }, 2429 }; 2430 2431 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2432 // most of the implementation can be shared. 2433 class X86TargetInfo : public TargetInfo { 2434 enum X86SSEEnum { 2435 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2436 } SSELevel = NoSSE; 2437 enum MMX3DNowEnum { 2438 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2439 } MMX3DNowLevel = NoMMX3DNow; 2440 enum XOPEnum { 2441 NoXOP, 2442 SSE4A, 2443 FMA4, 2444 XOP 2445 } XOPLevel = NoXOP; 2446 2447 bool HasAES = false; 2448 bool HasPCLMUL = false; 2449 bool HasLZCNT = false; 2450 bool HasRDRND = false; 2451 bool HasFSGSBASE = false; 2452 bool HasBMI = false; 2453 bool HasBMI2 = false; 2454 bool HasPOPCNT = false; 2455 bool HasRTM = false; 2456 bool HasPRFCHW = false; 2457 bool HasRDSEED = false; 2458 bool HasADX = false; 2459 bool HasTBM = false; 2460 bool HasFMA = false; 2461 bool HasF16C = false; 2462 bool HasAVX512CD = false; 2463 bool HasAVX512ER = false; 2464 bool HasAVX512PF = false; 2465 bool HasAVX512DQ = false; 2466 bool HasAVX512BW = false; 2467 bool HasAVX512VL = false; 2468 bool HasAVX512VBMI = false; 2469 bool HasAVX512IFMA = false; 2470 bool HasSHA = false; 2471 bool HasMPX = false; 2472 bool HasSGX = false; 2473 bool HasCX16 = false; 2474 bool HasFXSR = false; 2475 bool HasXSAVE = false; 2476 bool HasXSAVEOPT = false; 2477 bool HasXSAVEC = false; 2478 bool HasXSAVES = false; 2479 bool HasMWAITX = false; 2480 bool HasPKU = false; 2481 bool HasCLFLUSHOPT = false; 2482 bool HasPCOMMIT = false; 2483 bool HasCLWB = false; 2484 bool HasUMIP = false; 2485 bool HasMOVBE = false; 2486 bool HasPREFETCHWT1 = false; 2487 2488 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2489 /// 2490 /// Each enumeration represents a particular CPU supported by Clang. These 2491 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2492 enum CPUKind { 2493 CK_Generic, 2494 2495 /// \name i386 2496 /// i386-generation processors. 2497 //@{ 2498 CK_i386, 2499 //@} 2500 2501 /// \name i486 2502 /// i486-generation processors. 2503 //@{ 2504 CK_i486, 2505 CK_WinChipC6, 2506 CK_WinChip2, 2507 CK_C3, 2508 //@} 2509 2510 /// \name i586 2511 /// i586-generation processors, P5 microarchitecture based. 2512 //@{ 2513 CK_i586, 2514 CK_Pentium, 2515 CK_PentiumMMX, 2516 //@} 2517 2518 /// \name i686 2519 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2520 //@{ 2521 CK_i686, 2522 CK_PentiumPro, 2523 CK_Pentium2, 2524 CK_Pentium3, 2525 CK_Pentium3M, 2526 CK_PentiumM, 2527 CK_C3_2, 2528 2529 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2530 /// Clang however has some logic to suport this. 2531 // FIXME: Warn, deprecate, and potentially remove this. 2532 CK_Yonah, 2533 //@} 2534 2535 /// \name Netburst 2536 /// Netburst microarchitecture based processors. 2537 //@{ 2538 CK_Pentium4, 2539 CK_Pentium4M, 2540 CK_Prescott, 2541 CK_Nocona, 2542 //@} 2543 2544 /// \name Core 2545 /// Core microarchitecture based processors. 2546 //@{ 2547 CK_Core2, 2548 2549 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2550 /// codename which GCC no longer accepts as an option to -march, but Clang 2551 /// has some logic for recognizing it. 2552 // FIXME: Warn, deprecate, and potentially remove this. 2553 CK_Penryn, 2554 //@} 2555 2556 /// \name Atom 2557 /// Atom processors 2558 //@{ 2559 CK_Bonnell, 2560 CK_Silvermont, 2561 //@} 2562 2563 /// \name Nehalem 2564 /// Nehalem microarchitecture based processors. 2565 CK_Nehalem, 2566 2567 /// \name Westmere 2568 /// Westmere microarchitecture based processors. 2569 CK_Westmere, 2570 2571 /// \name Sandy Bridge 2572 /// Sandy Bridge microarchitecture based processors. 2573 CK_SandyBridge, 2574 2575 /// \name Ivy Bridge 2576 /// Ivy Bridge microarchitecture based processors. 2577 CK_IvyBridge, 2578 2579 /// \name Haswell 2580 /// Haswell microarchitecture based processors. 2581 CK_Haswell, 2582 2583 /// \name Broadwell 2584 /// Broadwell microarchitecture based processors. 2585 CK_Broadwell, 2586 2587 /// \name Skylake Client 2588 /// Skylake client microarchitecture based processors. 2589 CK_SkylakeClient, 2590 2591 /// \name Skylake Server 2592 /// Skylake server microarchitecture based processors. 2593 CK_SkylakeServer, 2594 2595 /// \name Cannonlake Client 2596 /// Cannonlake client microarchitecture based processors. 2597 CK_Cannonlake, 2598 2599 /// \name Knights Landing 2600 /// Knights Landing processor. 2601 CK_KNL, 2602 2603 /// \name Lakemont 2604 /// Lakemont microarchitecture based processors. 2605 CK_Lakemont, 2606 2607 /// \name K6 2608 /// K6 architecture processors. 2609 //@{ 2610 CK_K6, 2611 CK_K6_2, 2612 CK_K6_3, 2613 //@} 2614 2615 /// \name K7 2616 /// K7 architecture processors. 2617 //@{ 2618 CK_Athlon, 2619 CK_AthlonThunderbird, 2620 CK_Athlon4, 2621 CK_AthlonXP, 2622 CK_AthlonMP, 2623 //@} 2624 2625 /// \name K8 2626 /// K8 architecture processors. 2627 //@{ 2628 CK_Athlon64, 2629 CK_Athlon64SSE3, 2630 CK_AthlonFX, 2631 CK_K8, 2632 CK_K8SSE3, 2633 CK_Opteron, 2634 CK_OpteronSSE3, 2635 CK_AMDFAM10, 2636 //@} 2637 2638 /// \name Bobcat 2639 /// Bobcat architecture processors. 2640 //@{ 2641 CK_BTVER1, 2642 CK_BTVER2, 2643 //@} 2644 2645 /// \name Bulldozer 2646 /// Bulldozer architecture processors. 2647 //@{ 2648 CK_BDVER1, 2649 CK_BDVER2, 2650 CK_BDVER3, 2651 CK_BDVER4, 2652 //@} 2653 2654 /// This specification is deprecated and will be removed in the future. 2655 /// Users should prefer \see CK_K8. 2656 // FIXME: Warn on this when the CPU is set to it. 2657 //@{ 2658 CK_x86_64, 2659 //@} 2660 2661 /// \name Geode 2662 /// Geode processors. 2663 //@{ 2664 CK_Geode 2665 //@} 2666 } CPU = CK_Generic; 2667 2668 CPUKind getCPUKind(StringRef CPU) const { 2669 return llvm::StringSwitch<CPUKind>(CPU) 2670 .Case("i386", CK_i386) 2671 .Case("i486", CK_i486) 2672 .Case("winchip-c6", CK_WinChipC6) 2673 .Case("winchip2", CK_WinChip2) 2674 .Case("c3", CK_C3) 2675 .Case("i586", CK_i586) 2676 .Case("pentium", CK_Pentium) 2677 .Case("pentium-mmx", CK_PentiumMMX) 2678 .Case("i686", CK_i686) 2679 .Case("pentiumpro", CK_PentiumPro) 2680 .Case("pentium2", CK_Pentium2) 2681 .Case("pentium3", CK_Pentium3) 2682 .Case("pentium3m", CK_Pentium3M) 2683 .Case("pentium-m", CK_PentiumM) 2684 .Case("c3-2", CK_C3_2) 2685 .Case("yonah", CK_Yonah) 2686 .Case("pentium4", CK_Pentium4) 2687 .Case("pentium4m", CK_Pentium4M) 2688 .Case("prescott", CK_Prescott) 2689 .Case("nocona", CK_Nocona) 2690 .Case("core2", CK_Core2) 2691 .Case("penryn", CK_Penryn) 2692 .Case("bonnell", CK_Bonnell) 2693 .Case("atom", CK_Bonnell) // Legacy name. 2694 .Case("silvermont", CK_Silvermont) 2695 .Case("slm", CK_Silvermont) // Legacy name. 2696 .Case("nehalem", CK_Nehalem) 2697 .Case("corei7", CK_Nehalem) // Legacy name. 2698 .Case("westmere", CK_Westmere) 2699 .Case("sandybridge", CK_SandyBridge) 2700 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2701 .Case("ivybridge", CK_IvyBridge) 2702 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2703 .Case("haswell", CK_Haswell) 2704 .Case("core-avx2", CK_Haswell) // Legacy name. 2705 .Case("broadwell", CK_Broadwell) 2706 .Case("skylake", CK_SkylakeClient) 2707 .Case("skylake-avx512", CK_SkylakeServer) 2708 .Case("skx", CK_SkylakeServer) // Legacy name. 2709 .Case("cannonlake", CK_Cannonlake) 2710 .Case("knl", CK_KNL) 2711 .Case("lakemont", CK_Lakemont) 2712 .Case("k6", CK_K6) 2713 .Case("k6-2", CK_K6_2) 2714 .Case("k6-3", CK_K6_3) 2715 .Case("athlon", CK_Athlon) 2716 .Case("athlon-tbird", CK_AthlonThunderbird) 2717 .Case("athlon-4", CK_Athlon4) 2718 .Case("athlon-xp", CK_AthlonXP) 2719 .Case("athlon-mp", CK_AthlonMP) 2720 .Case("athlon64", CK_Athlon64) 2721 .Case("athlon64-sse3", CK_Athlon64SSE3) 2722 .Case("athlon-fx", CK_AthlonFX) 2723 .Case("k8", CK_K8) 2724 .Case("k8-sse3", CK_K8SSE3) 2725 .Case("opteron", CK_Opteron) 2726 .Case("opteron-sse3", CK_OpteronSSE3) 2727 .Case("barcelona", CK_AMDFAM10) 2728 .Case("amdfam10", CK_AMDFAM10) 2729 .Case("btver1", CK_BTVER1) 2730 .Case("btver2", CK_BTVER2) 2731 .Case("bdver1", CK_BDVER1) 2732 .Case("bdver2", CK_BDVER2) 2733 .Case("bdver3", CK_BDVER3) 2734 .Case("bdver4", CK_BDVER4) 2735 .Case("x86-64", CK_x86_64) 2736 .Case("geode", CK_Geode) 2737 .Default(CK_Generic); 2738 } 2739 2740 enum FPMathKind { 2741 FP_Default, 2742 FP_SSE, 2743 FP_387 2744 } FPMath = FP_Default; 2745 2746 public: 2747 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2748 : TargetInfo(Triple) { 2749 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2750 } 2751 unsigned getFloatEvalMethod() const override { 2752 // X87 evaluates with 80 bits "long double" precision. 2753 return SSELevel == NoSSE ? 2 : 0; 2754 } 2755 ArrayRef<const char *> getGCCRegNames() const override { 2756 return llvm::makeArrayRef(GCCRegNames); 2757 } 2758 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2759 return None; 2760 } 2761 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2762 return llvm::makeArrayRef(AddlRegNames); 2763 } 2764 bool validateCpuSupports(StringRef Name) const override; 2765 bool validateAsmConstraint(const char *&Name, 2766 TargetInfo::ConstraintInfo &info) const override; 2767 2768 bool validateGlobalRegisterVariable(StringRef RegName, 2769 unsigned RegSize, 2770 bool &HasSizeMismatch) const override { 2771 // esp and ebp are the only 32-bit registers the x86 backend can currently 2772 // handle. 2773 if (RegName.equals("esp") || RegName.equals("ebp")) { 2774 // Check that the register size is 32-bit. 2775 HasSizeMismatch = RegSize != 32; 2776 return true; 2777 } 2778 2779 return false; 2780 } 2781 2782 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2783 2784 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2785 2786 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2787 2788 std::string convertConstraint(const char *&Constraint) const override; 2789 const char *getClobbers() const override { 2790 return "~{dirflag},~{fpsr},~{flags}"; 2791 } 2792 void getTargetDefines(const LangOptions &Opts, 2793 MacroBuilder &Builder) const override; 2794 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2795 bool Enabled); 2796 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2797 bool Enabled); 2798 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2799 bool Enabled); 2800 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2801 StringRef Name, bool Enabled) const override { 2802 setFeatureEnabledImpl(Features, Name, Enabled); 2803 } 2804 // This exists purely to cut down on the number of virtual calls in 2805 // initFeatureMap which calls this repeatedly. 2806 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2807 StringRef Name, bool Enabled); 2808 bool 2809 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2810 StringRef CPU, 2811 const std::vector<std::string> &FeaturesVec) const override; 2812 bool hasFeature(StringRef Feature) const override; 2813 bool handleTargetFeatures(std::vector<std::string> &Features, 2814 DiagnosticsEngine &Diags) override; 2815 StringRef getABI() const override { 2816 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2817 return "avx512"; 2818 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2819 return "avx"; 2820 if (getTriple().getArch() == llvm::Triple::x86 && 2821 MMX3DNowLevel == NoMMX3DNow) 2822 return "no-mmx"; 2823 return ""; 2824 } 2825 bool setCPU(const std::string &Name) override { 2826 CPU = getCPUKind(Name); 2827 2828 // Perform any per-CPU checks necessary to determine if this CPU is 2829 // acceptable. 2830 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2831 // invalid without explaining *why*. 2832 switch (CPU) { 2833 case CK_Generic: 2834 // No processor selected! 2835 return false; 2836 2837 case CK_i386: 2838 case CK_i486: 2839 case CK_WinChipC6: 2840 case CK_WinChip2: 2841 case CK_C3: 2842 case CK_i586: 2843 case CK_Pentium: 2844 case CK_PentiumMMX: 2845 case CK_i686: 2846 case CK_PentiumPro: 2847 case CK_Pentium2: 2848 case CK_Pentium3: 2849 case CK_Pentium3M: 2850 case CK_PentiumM: 2851 case CK_Yonah: 2852 case CK_C3_2: 2853 case CK_Pentium4: 2854 case CK_Pentium4M: 2855 case CK_Lakemont: 2856 case CK_Prescott: 2857 case CK_K6: 2858 case CK_K6_2: 2859 case CK_K6_3: 2860 case CK_Athlon: 2861 case CK_AthlonThunderbird: 2862 case CK_Athlon4: 2863 case CK_AthlonXP: 2864 case CK_AthlonMP: 2865 case CK_Geode: 2866 // Only accept certain architectures when compiling in 32-bit mode. 2867 if (getTriple().getArch() != llvm::Triple::x86) 2868 return false; 2869 2870 // Fallthrough 2871 case CK_Nocona: 2872 case CK_Core2: 2873 case CK_Penryn: 2874 case CK_Bonnell: 2875 case CK_Silvermont: 2876 case CK_Nehalem: 2877 case CK_Westmere: 2878 case CK_SandyBridge: 2879 case CK_IvyBridge: 2880 case CK_Haswell: 2881 case CK_Broadwell: 2882 case CK_SkylakeClient: 2883 case CK_SkylakeServer: 2884 case CK_Cannonlake: 2885 case CK_KNL: 2886 case CK_Athlon64: 2887 case CK_Athlon64SSE3: 2888 case CK_AthlonFX: 2889 case CK_K8: 2890 case CK_K8SSE3: 2891 case CK_Opteron: 2892 case CK_OpteronSSE3: 2893 case CK_AMDFAM10: 2894 case CK_BTVER1: 2895 case CK_BTVER2: 2896 case CK_BDVER1: 2897 case CK_BDVER2: 2898 case CK_BDVER3: 2899 case CK_BDVER4: 2900 case CK_x86_64: 2901 return true; 2902 } 2903 llvm_unreachable("Unhandled CPU kind"); 2904 } 2905 2906 bool setFPMath(StringRef Name) override; 2907 2908 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2909 // Most of the non-ARM calling conventions are i386 conventions. 2910 switch (CC) { 2911 case CC_X86ThisCall: 2912 case CC_X86FastCall: 2913 case CC_X86StdCall: 2914 case CC_X86VectorCall: 2915 case CC_X86RegCall: 2916 case CC_C: 2917 case CC_Swift: 2918 case CC_X86Pascal: 2919 case CC_IntelOclBicc: 2920 return CCCR_OK; 2921 default: 2922 return CCCR_Warning; 2923 } 2924 } 2925 2926 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2927 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2928 } 2929 2930 bool hasSjLjLowering() const override { 2931 return true; 2932 } 2933 2934 void setSupportedOpenCLOpts() override { 2935 getSupportedOpenCLOpts().setAll(); 2936 } 2937 }; 2938 2939 bool X86TargetInfo::setFPMath(StringRef Name) { 2940 if (Name == "387") { 2941 FPMath = FP_387; 2942 return true; 2943 } 2944 if (Name == "sse") { 2945 FPMath = FP_SSE; 2946 return true; 2947 } 2948 return false; 2949 } 2950 2951 bool X86TargetInfo::initFeatureMap( 2952 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2953 const std::vector<std::string> &FeaturesVec) const { 2954 // FIXME: This *really* should not be here. 2955 // X86_64 always has SSE2. 2956 if (getTriple().getArch() == llvm::Triple::x86_64) 2957 setFeatureEnabledImpl(Features, "sse2", true); 2958 2959 const CPUKind Kind = getCPUKind(CPU); 2960 2961 // Enable X87 for all X86 processors but Lakemont. 2962 if (Kind != CK_Lakemont) 2963 setFeatureEnabledImpl(Features, "x87", true); 2964 2965 switch (Kind) { 2966 case CK_Generic: 2967 case CK_i386: 2968 case CK_i486: 2969 case CK_i586: 2970 case CK_Pentium: 2971 case CK_i686: 2972 case CK_PentiumPro: 2973 case CK_Lakemont: 2974 break; 2975 case CK_PentiumMMX: 2976 case CK_Pentium2: 2977 case CK_K6: 2978 case CK_WinChipC6: 2979 setFeatureEnabledImpl(Features, "mmx", true); 2980 break; 2981 case CK_Pentium3: 2982 case CK_Pentium3M: 2983 case CK_C3_2: 2984 setFeatureEnabledImpl(Features, "sse", true); 2985 setFeatureEnabledImpl(Features, "fxsr", true); 2986 break; 2987 case CK_PentiumM: 2988 case CK_Pentium4: 2989 case CK_Pentium4M: 2990 case CK_x86_64: 2991 setFeatureEnabledImpl(Features, "sse2", true); 2992 setFeatureEnabledImpl(Features, "fxsr", true); 2993 break; 2994 case CK_Yonah: 2995 case CK_Prescott: 2996 case CK_Nocona: 2997 setFeatureEnabledImpl(Features, "sse3", true); 2998 setFeatureEnabledImpl(Features, "fxsr", true); 2999 setFeatureEnabledImpl(Features, "cx16", true); 3000 break; 3001 case CK_Core2: 3002 case CK_Bonnell: 3003 setFeatureEnabledImpl(Features, "ssse3", true); 3004 setFeatureEnabledImpl(Features, "fxsr", true); 3005 setFeatureEnabledImpl(Features, "cx16", true); 3006 break; 3007 case CK_Penryn: 3008 setFeatureEnabledImpl(Features, "sse4.1", true); 3009 setFeatureEnabledImpl(Features, "fxsr", true); 3010 setFeatureEnabledImpl(Features, "cx16", true); 3011 break; 3012 case CK_Cannonlake: 3013 setFeatureEnabledImpl(Features, "avx512ifma", true); 3014 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3015 setFeatureEnabledImpl(Features, "sha", true); 3016 setFeatureEnabledImpl(Features, "umip", true); 3017 // FALLTHROUGH 3018 case CK_SkylakeServer: 3019 setFeatureEnabledImpl(Features, "avx512f", true); 3020 setFeatureEnabledImpl(Features, "avx512cd", true); 3021 setFeatureEnabledImpl(Features, "avx512dq", true); 3022 setFeatureEnabledImpl(Features, "avx512bw", true); 3023 setFeatureEnabledImpl(Features, "avx512vl", true); 3024 setFeatureEnabledImpl(Features, "pku", true); 3025 setFeatureEnabledImpl(Features, "pcommit", true); 3026 setFeatureEnabledImpl(Features, "clwb", true); 3027 // FALLTHROUGH 3028 case CK_SkylakeClient: 3029 setFeatureEnabledImpl(Features, "xsavec", true); 3030 setFeatureEnabledImpl(Features, "xsaves", true); 3031 setFeatureEnabledImpl(Features, "mpx", true); 3032 setFeatureEnabledImpl(Features, "sgx", true); 3033 setFeatureEnabledImpl(Features, "clflushopt", true); 3034 // FALLTHROUGH 3035 case CK_Broadwell: 3036 setFeatureEnabledImpl(Features, "rdseed", true); 3037 setFeatureEnabledImpl(Features, "adx", true); 3038 // FALLTHROUGH 3039 case CK_Haswell: 3040 setFeatureEnabledImpl(Features, "avx2", true); 3041 setFeatureEnabledImpl(Features, "lzcnt", true); 3042 setFeatureEnabledImpl(Features, "bmi", true); 3043 setFeatureEnabledImpl(Features, "bmi2", true); 3044 setFeatureEnabledImpl(Features, "rtm", true); 3045 setFeatureEnabledImpl(Features, "fma", true); 3046 setFeatureEnabledImpl(Features, "movbe", true); 3047 // FALLTHROUGH 3048 case CK_IvyBridge: 3049 setFeatureEnabledImpl(Features, "rdrnd", true); 3050 setFeatureEnabledImpl(Features, "f16c", true); 3051 setFeatureEnabledImpl(Features, "fsgsbase", true); 3052 // FALLTHROUGH 3053 case CK_SandyBridge: 3054 setFeatureEnabledImpl(Features, "avx", true); 3055 setFeatureEnabledImpl(Features, "xsave", true); 3056 setFeatureEnabledImpl(Features, "xsaveopt", true); 3057 // FALLTHROUGH 3058 case CK_Westmere: 3059 case CK_Silvermont: 3060 setFeatureEnabledImpl(Features, "aes", true); 3061 setFeatureEnabledImpl(Features, "pclmul", true); 3062 // FALLTHROUGH 3063 case CK_Nehalem: 3064 setFeatureEnabledImpl(Features, "sse4.2", true); 3065 setFeatureEnabledImpl(Features, "fxsr", true); 3066 setFeatureEnabledImpl(Features, "cx16", true); 3067 break; 3068 case CK_KNL: 3069 setFeatureEnabledImpl(Features, "avx512f", true); 3070 setFeatureEnabledImpl(Features, "avx512cd", true); 3071 setFeatureEnabledImpl(Features, "avx512er", true); 3072 setFeatureEnabledImpl(Features, "avx512pf", true); 3073 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3074 setFeatureEnabledImpl(Features, "fxsr", true); 3075 setFeatureEnabledImpl(Features, "rdseed", true); 3076 setFeatureEnabledImpl(Features, "adx", true); 3077 setFeatureEnabledImpl(Features, "lzcnt", true); 3078 setFeatureEnabledImpl(Features, "bmi", true); 3079 setFeatureEnabledImpl(Features, "bmi2", true); 3080 setFeatureEnabledImpl(Features, "rtm", true); 3081 setFeatureEnabledImpl(Features, "fma", true); 3082 setFeatureEnabledImpl(Features, "rdrnd", true); 3083 setFeatureEnabledImpl(Features, "f16c", true); 3084 setFeatureEnabledImpl(Features, "fsgsbase", true); 3085 setFeatureEnabledImpl(Features, "aes", true); 3086 setFeatureEnabledImpl(Features, "pclmul", true); 3087 setFeatureEnabledImpl(Features, "cx16", true); 3088 setFeatureEnabledImpl(Features, "xsaveopt", true); 3089 setFeatureEnabledImpl(Features, "xsave", true); 3090 setFeatureEnabledImpl(Features, "movbe", true); 3091 break; 3092 case CK_K6_2: 3093 case CK_K6_3: 3094 case CK_WinChip2: 3095 case CK_C3: 3096 setFeatureEnabledImpl(Features, "3dnow", true); 3097 break; 3098 case CK_Athlon: 3099 case CK_AthlonThunderbird: 3100 case CK_Geode: 3101 setFeatureEnabledImpl(Features, "3dnowa", true); 3102 break; 3103 case CK_Athlon4: 3104 case CK_AthlonXP: 3105 case CK_AthlonMP: 3106 setFeatureEnabledImpl(Features, "sse", true); 3107 setFeatureEnabledImpl(Features, "3dnowa", true); 3108 setFeatureEnabledImpl(Features, "fxsr", true); 3109 break; 3110 case CK_K8: 3111 case CK_Opteron: 3112 case CK_Athlon64: 3113 case CK_AthlonFX: 3114 setFeatureEnabledImpl(Features, "sse2", true); 3115 setFeatureEnabledImpl(Features, "3dnowa", true); 3116 setFeatureEnabledImpl(Features, "fxsr", true); 3117 break; 3118 case CK_AMDFAM10: 3119 setFeatureEnabledImpl(Features, "sse4a", true); 3120 setFeatureEnabledImpl(Features, "lzcnt", true); 3121 setFeatureEnabledImpl(Features, "popcnt", true); 3122 // FALLTHROUGH 3123 case CK_K8SSE3: 3124 case CK_OpteronSSE3: 3125 case CK_Athlon64SSE3: 3126 setFeatureEnabledImpl(Features, "sse3", true); 3127 setFeatureEnabledImpl(Features, "3dnowa", true); 3128 setFeatureEnabledImpl(Features, "fxsr", true); 3129 break; 3130 case CK_BTVER2: 3131 setFeatureEnabledImpl(Features, "avx", true); 3132 setFeatureEnabledImpl(Features, "aes", true); 3133 setFeatureEnabledImpl(Features, "pclmul", true); 3134 setFeatureEnabledImpl(Features, "bmi", true); 3135 setFeatureEnabledImpl(Features, "f16c", true); 3136 setFeatureEnabledImpl(Features, "xsaveopt", true); 3137 // FALLTHROUGH 3138 case CK_BTVER1: 3139 setFeatureEnabledImpl(Features, "ssse3", true); 3140 setFeatureEnabledImpl(Features, "sse4a", true); 3141 setFeatureEnabledImpl(Features, "lzcnt", true); 3142 setFeatureEnabledImpl(Features, "popcnt", true); 3143 setFeatureEnabledImpl(Features, "prfchw", true); 3144 setFeatureEnabledImpl(Features, "cx16", true); 3145 setFeatureEnabledImpl(Features, "fxsr", true); 3146 break; 3147 case CK_BDVER4: 3148 setFeatureEnabledImpl(Features, "avx2", true); 3149 setFeatureEnabledImpl(Features, "bmi2", true); 3150 setFeatureEnabledImpl(Features, "mwaitx", true); 3151 // FALLTHROUGH 3152 case CK_BDVER3: 3153 setFeatureEnabledImpl(Features, "fsgsbase", true); 3154 setFeatureEnabledImpl(Features, "xsaveopt", true); 3155 // FALLTHROUGH 3156 case CK_BDVER2: 3157 setFeatureEnabledImpl(Features, "bmi", true); 3158 setFeatureEnabledImpl(Features, "fma", true); 3159 setFeatureEnabledImpl(Features, "f16c", true); 3160 setFeatureEnabledImpl(Features, "tbm", true); 3161 // FALLTHROUGH 3162 case CK_BDVER1: 3163 // xop implies avx, sse4a and fma4. 3164 setFeatureEnabledImpl(Features, "xop", true); 3165 setFeatureEnabledImpl(Features, "lzcnt", true); 3166 setFeatureEnabledImpl(Features, "aes", true); 3167 setFeatureEnabledImpl(Features, "pclmul", true); 3168 setFeatureEnabledImpl(Features, "prfchw", true); 3169 setFeatureEnabledImpl(Features, "cx16", true); 3170 setFeatureEnabledImpl(Features, "fxsr", true); 3171 setFeatureEnabledImpl(Features, "xsave", true); 3172 break; 3173 } 3174 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3175 return false; 3176 3177 // Can't do this earlier because we need to be able to explicitly enable 3178 // or disable these features and the things that they depend upon. 3179 3180 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3181 auto I = Features.find("sse4.2"); 3182 if (I != Features.end() && I->getValue() && 3183 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3184 FeaturesVec.end()) 3185 Features["popcnt"] = true; 3186 3187 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3188 I = Features.find("3dnow"); 3189 if (I != Features.end() && I->getValue() && 3190 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3191 FeaturesVec.end()) 3192 Features["prfchw"] = true; 3193 3194 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3195 // then enable MMX. 3196 I = Features.find("sse"); 3197 if (I != Features.end() && I->getValue() && 3198 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3199 FeaturesVec.end()) 3200 Features["mmx"] = true; 3201 3202 return true; 3203 } 3204 3205 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3206 X86SSEEnum Level, bool Enabled) { 3207 if (Enabled) { 3208 switch (Level) { 3209 case AVX512F: 3210 Features["avx512f"] = true; 3211 case AVX2: 3212 Features["avx2"] = true; 3213 case AVX: 3214 Features["avx"] = true; 3215 Features["xsave"] = true; 3216 case SSE42: 3217 Features["sse4.2"] = true; 3218 case SSE41: 3219 Features["sse4.1"] = true; 3220 case SSSE3: 3221 Features["ssse3"] = true; 3222 case SSE3: 3223 Features["sse3"] = true; 3224 case SSE2: 3225 Features["sse2"] = true; 3226 case SSE1: 3227 Features["sse"] = true; 3228 case NoSSE: 3229 break; 3230 } 3231 return; 3232 } 3233 3234 switch (Level) { 3235 case NoSSE: 3236 case SSE1: 3237 Features["sse"] = false; 3238 case SSE2: 3239 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3240 Features["sha"] = false; 3241 case SSE3: 3242 Features["sse3"] = false; 3243 setXOPLevel(Features, NoXOP, false); 3244 case SSSE3: 3245 Features["ssse3"] = false; 3246 case SSE41: 3247 Features["sse4.1"] = false; 3248 case SSE42: 3249 Features["sse4.2"] = false; 3250 case AVX: 3251 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3252 Features["xsaveopt"] = false; 3253 setXOPLevel(Features, FMA4, false); 3254 case AVX2: 3255 Features["avx2"] = false; 3256 case AVX512F: 3257 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3258 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3259 Features["avx512vl"] = Features["avx512vbmi"] = 3260 Features["avx512ifma"] = false; 3261 } 3262 } 3263 3264 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3265 MMX3DNowEnum Level, bool Enabled) { 3266 if (Enabled) { 3267 switch (Level) { 3268 case AMD3DNowAthlon: 3269 Features["3dnowa"] = true; 3270 case AMD3DNow: 3271 Features["3dnow"] = true; 3272 case MMX: 3273 Features["mmx"] = true; 3274 case NoMMX3DNow: 3275 break; 3276 } 3277 return; 3278 } 3279 3280 switch (Level) { 3281 case NoMMX3DNow: 3282 case MMX: 3283 Features["mmx"] = false; 3284 case AMD3DNow: 3285 Features["3dnow"] = false; 3286 case AMD3DNowAthlon: 3287 Features["3dnowa"] = false; 3288 } 3289 } 3290 3291 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3292 bool Enabled) { 3293 if (Enabled) { 3294 switch (Level) { 3295 case XOP: 3296 Features["xop"] = true; 3297 case FMA4: 3298 Features["fma4"] = true; 3299 setSSELevel(Features, AVX, true); 3300 case SSE4A: 3301 Features["sse4a"] = true; 3302 setSSELevel(Features, SSE3, true); 3303 case NoXOP: 3304 break; 3305 } 3306 return; 3307 } 3308 3309 switch (Level) { 3310 case NoXOP: 3311 case SSE4A: 3312 Features["sse4a"] = false; 3313 case FMA4: 3314 Features["fma4"] = false; 3315 case XOP: 3316 Features["xop"] = false; 3317 } 3318 } 3319 3320 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3321 StringRef Name, bool Enabled) { 3322 // This is a bit of a hack to deal with the sse4 target feature when used 3323 // as part of the target attribute. We handle sse4 correctly everywhere 3324 // else. See below for more information on how we handle the sse4 options. 3325 if (Name != "sse4") 3326 Features[Name] = Enabled; 3327 3328 if (Name == "mmx") { 3329 setMMXLevel(Features, MMX, Enabled); 3330 } else if (Name == "sse") { 3331 setSSELevel(Features, SSE1, Enabled); 3332 } else if (Name == "sse2") { 3333 setSSELevel(Features, SSE2, Enabled); 3334 } else if (Name == "sse3") { 3335 setSSELevel(Features, SSE3, Enabled); 3336 } else if (Name == "ssse3") { 3337 setSSELevel(Features, SSSE3, Enabled); 3338 } else if (Name == "sse4.2") { 3339 setSSELevel(Features, SSE42, Enabled); 3340 } else if (Name == "sse4.1") { 3341 setSSELevel(Features, SSE41, Enabled); 3342 } else if (Name == "3dnow") { 3343 setMMXLevel(Features, AMD3DNow, Enabled); 3344 } else if (Name == "3dnowa") { 3345 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3346 } else if (Name == "aes") { 3347 if (Enabled) 3348 setSSELevel(Features, SSE2, Enabled); 3349 } else if (Name == "pclmul") { 3350 if (Enabled) 3351 setSSELevel(Features, SSE2, Enabled); 3352 } else if (Name == "avx") { 3353 setSSELevel(Features, AVX, Enabled); 3354 } else if (Name == "avx2") { 3355 setSSELevel(Features, AVX2, Enabled); 3356 } else if (Name == "avx512f") { 3357 setSSELevel(Features, AVX512F, Enabled); 3358 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3359 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3360 Name == "avx512vbmi" || Name == "avx512ifma") { 3361 if (Enabled) 3362 setSSELevel(Features, AVX512F, Enabled); 3363 // Enable BWI instruction if VBMI is being enabled. 3364 if (Name == "avx512vbmi" && Enabled) 3365 Features["avx512bw"] = true; 3366 // Also disable VBMI if BWI is being disabled. 3367 if (Name == "avx512bw" && !Enabled) 3368 Features["avx512vbmi"] = false; 3369 } else if (Name == "fma") { 3370 if (Enabled) 3371 setSSELevel(Features, AVX, Enabled); 3372 } else if (Name == "fma4") { 3373 setXOPLevel(Features, FMA4, Enabled); 3374 } else if (Name == "xop") { 3375 setXOPLevel(Features, XOP, Enabled); 3376 } else if (Name == "sse4a") { 3377 setXOPLevel(Features, SSE4A, Enabled); 3378 } else if (Name == "f16c") { 3379 if (Enabled) 3380 setSSELevel(Features, AVX, Enabled); 3381 } else if (Name == "sha") { 3382 if (Enabled) 3383 setSSELevel(Features, SSE2, Enabled); 3384 } else if (Name == "sse4") { 3385 // We can get here via the __target__ attribute since that's not controlled 3386 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3387 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3388 // disabled. 3389 if (Enabled) 3390 setSSELevel(Features, SSE42, Enabled); 3391 else 3392 setSSELevel(Features, SSE41, Enabled); 3393 } else if (Name == "xsave") { 3394 if (!Enabled) 3395 Features["xsaveopt"] = false; 3396 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3397 if (Enabled) 3398 Features["xsave"] = true; 3399 } 3400 } 3401 3402 /// handleTargetFeatures - Perform initialization based on the user 3403 /// configured set of features. 3404 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3405 DiagnosticsEngine &Diags) { 3406 for (const auto &Feature : Features) { 3407 if (Feature[0] != '+') 3408 continue; 3409 3410 if (Feature == "+aes") { 3411 HasAES = true; 3412 } else if (Feature == "+pclmul") { 3413 HasPCLMUL = true; 3414 } else if (Feature == "+lzcnt") { 3415 HasLZCNT = true; 3416 } else if (Feature == "+rdrnd") { 3417 HasRDRND = true; 3418 } else if (Feature == "+fsgsbase") { 3419 HasFSGSBASE = true; 3420 } else if (Feature == "+bmi") { 3421 HasBMI = true; 3422 } else if (Feature == "+bmi2") { 3423 HasBMI2 = true; 3424 } else if (Feature == "+popcnt") { 3425 HasPOPCNT = true; 3426 } else if (Feature == "+rtm") { 3427 HasRTM = true; 3428 } else if (Feature == "+prfchw") { 3429 HasPRFCHW = true; 3430 } else if (Feature == "+rdseed") { 3431 HasRDSEED = true; 3432 } else if (Feature == "+adx") { 3433 HasADX = true; 3434 } else if (Feature == "+tbm") { 3435 HasTBM = true; 3436 } else if (Feature == "+fma") { 3437 HasFMA = true; 3438 } else if (Feature == "+f16c") { 3439 HasF16C = true; 3440 } else if (Feature == "+avx512cd") { 3441 HasAVX512CD = true; 3442 } else if (Feature == "+avx512er") { 3443 HasAVX512ER = true; 3444 } else if (Feature == "+avx512pf") { 3445 HasAVX512PF = true; 3446 } else if (Feature == "+avx512dq") { 3447 HasAVX512DQ = true; 3448 } else if (Feature == "+avx512bw") { 3449 HasAVX512BW = true; 3450 } else if (Feature == "+avx512vl") { 3451 HasAVX512VL = true; 3452 } else if (Feature == "+avx512vbmi") { 3453 HasAVX512VBMI = true; 3454 } else if (Feature == "+avx512ifma") { 3455 HasAVX512IFMA = true; 3456 } else if (Feature == "+sha") { 3457 HasSHA = true; 3458 } else if (Feature == "+mpx") { 3459 HasMPX = true; 3460 } else if (Feature == "+movbe") { 3461 HasMOVBE = true; 3462 } else if (Feature == "+sgx") { 3463 HasSGX = true; 3464 } else if (Feature == "+cx16") { 3465 HasCX16 = true; 3466 } else if (Feature == "+fxsr") { 3467 HasFXSR = true; 3468 } else if (Feature == "+xsave") { 3469 HasXSAVE = true; 3470 } else if (Feature == "+xsaveopt") { 3471 HasXSAVEOPT = true; 3472 } else if (Feature == "+xsavec") { 3473 HasXSAVEC = true; 3474 } else if (Feature == "+xsaves") { 3475 HasXSAVES = true; 3476 } else if (Feature == "+mwaitx") { 3477 HasMWAITX = true; 3478 } else if (Feature == "+pku") { 3479 HasPKU = true; 3480 } else if (Feature == "+clflushopt") { 3481 HasCLFLUSHOPT = true; 3482 } else if (Feature == "+pcommit") { 3483 HasPCOMMIT = true; 3484 } else if (Feature == "+clwb") { 3485 HasCLWB = true; 3486 } else if (Feature == "+umip") { 3487 HasUMIP = true; 3488 } else if (Feature == "+prefetchwt1") { 3489 HasPREFETCHWT1 = true; 3490 } 3491 3492 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3493 .Case("+avx512f", AVX512F) 3494 .Case("+avx2", AVX2) 3495 .Case("+avx", AVX) 3496 .Case("+sse4.2", SSE42) 3497 .Case("+sse4.1", SSE41) 3498 .Case("+ssse3", SSSE3) 3499 .Case("+sse3", SSE3) 3500 .Case("+sse2", SSE2) 3501 .Case("+sse", SSE1) 3502 .Default(NoSSE); 3503 SSELevel = std::max(SSELevel, Level); 3504 3505 MMX3DNowEnum ThreeDNowLevel = 3506 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3507 .Case("+3dnowa", AMD3DNowAthlon) 3508 .Case("+3dnow", AMD3DNow) 3509 .Case("+mmx", MMX) 3510 .Default(NoMMX3DNow); 3511 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3512 3513 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3514 .Case("+xop", XOP) 3515 .Case("+fma4", FMA4) 3516 .Case("+sse4a", SSE4A) 3517 .Default(NoXOP); 3518 XOPLevel = std::max(XOPLevel, XLevel); 3519 } 3520 3521 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3522 // matches the selected sse level. 3523 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3524 (FPMath == FP_387 && SSELevel >= SSE1)) { 3525 Diags.Report(diag::err_target_unsupported_fpmath) << 3526 (FPMath == FP_SSE ? "sse" : "387"); 3527 return false; 3528 } 3529 3530 SimdDefaultAlign = 3531 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3532 return true; 3533 } 3534 3535 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3536 /// definitions for this particular subtarget. 3537 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3538 MacroBuilder &Builder) const { 3539 // Target identification. 3540 if (getTriple().getArch() == llvm::Triple::x86_64) { 3541 Builder.defineMacro("__amd64__"); 3542 Builder.defineMacro("__amd64"); 3543 Builder.defineMacro("__x86_64"); 3544 Builder.defineMacro("__x86_64__"); 3545 if (getTriple().getArchName() == "x86_64h") { 3546 Builder.defineMacro("__x86_64h"); 3547 Builder.defineMacro("__x86_64h__"); 3548 } 3549 } else { 3550 DefineStd(Builder, "i386", Opts); 3551 } 3552 3553 // Subtarget options. 3554 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3555 // truly should be based on -mtune options. 3556 switch (CPU) { 3557 case CK_Generic: 3558 break; 3559 case CK_i386: 3560 // The rest are coming from the i386 define above. 3561 Builder.defineMacro("__tune_i386__"); 3562 break; 3563 case CK_i486: 3564 case CK_WinChipC6: 3565 case CK_WinChip2: 3566 case CK_C3: 3567 defineCPUMacros(Builder, "i486"); 3568 break; 3569 case CK_PentiumMMX: 3570 Builder.defineMacro("__pentium_mmx__"); 3571 Builder.defineMacro("__tune_pentium_mmx__"); 3572 // Fallthrough 3573 case CK_i586: 3574 case CK_Pentium: 3575 defineCPUMacros(Builder, "i586"); 3576 defineCPUMacros(Builder, "pentium"); 3577 break; 3578 case CK_Pentium3: 3579 case CK_Pentium3M: 3580 case CK_PentiumM: 3581 Builder.defineMacro("__tune_pentium3__"); 3582 // Fallthrough 3583 case CK_Pentium2: 3584 case CK_C3_2: 3585 Builder.defineMacro("__tune_pentium2__"); 3586 // Fallthrough 3587 case CK_PentiumPro: 3588 Builder.defineMacro("__tune_i686__"); 3589 Builder.defineMacro("__tune_pentiumpro__"); 3590 // Fallthrough 3591 case CK_i686: 3592 Builder.defineMacro("__i686"); 3593 Builder.defineMacro("__i686__"); 3594 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3595 Builder.defineMacro("__pentiumpro"); 3596 Builder.defineMacro("__pentiumpro__"); 3597 break; 3598 case CK_Pentium4: 3599 case CK_Pentium4M: 3600 defineCPUMacros(Builder, "pentium4"); 3601 break; 3602 case CK_Yonah: 3603 case CK_Prescott: 3604 case CK_Nocona: 3605 defineCPUMacros(Builder, "nocona"); 3606 break; 3607 case CK_Core2: 3608 case CK_Penryn: 3609 defineCPUMacros(Builder, "core2"); 3610 break; 3611 case CK_Bonnell: 3612 defineCPUMacros(Builder, "atom"); 3613 break; 3614 case CK_Silvermont: 3615 defineCPUMacros(Builder, "slm"); 3616 break; 3617 case CK_Nehalem: 3618 case CK_Westmere: 3619 case CK_SandyBridge: 3620 case CK_IvyBridge: 3621 case CK_Haswell: 3622 case CK_Broadwell: 3623 case CK_SkylakeClient: 3624 // FIXME: Historically, we defined this legacy name, it would be nice to 3625 // remove it at some point. We've never exposed fine-grained names for 3626 // recent primary x86 CPUs, and we should keep it that way. 3627 defineCPUMacros(Builder, "corei7"); 3628 break; 3629 case CK_SkylakeServer: 3630 defineCPUMacros(Builder, "skx"); 3631 break; 3632 case CK_Cannonlake: 3633 break; 3634 case CK_KNL: 3635 defineCPUMacros(Builder, "knl"); 3636 break; 3637 case CK_Lakemont: 3638 Builder.defineMacro("__tune_lakemont__"); 3639 break; 3640 case CK_K6_2: 3641 Builder.defineMacro("__k6_2__"); 3642 Builder.defineMacro("__tune_k6_2__"); 3643 // Fallthrough 3644 case CK_K6_3: 3645 if (CPU != CK_K6_2) { // In case of fallthrough 3646 // FIXME: GCC may be enabling these in cases where some other k6 3647 // architecture is specified but -m3dnow is explicitly provided. The 3648 // exact semantics need to be determined and emulated here. 3649 Builder.defineMacro("__k6_3__"); 3650 Builder.defineMacro("__tune_k6_3__"); 3651 } 3652 // Fallthrough 3653 case CK_K6: 3654 defineCPUMacros(Builder, "k6"); 3655 break; 3656 case CK_Athlon: 3657 case CK_AthlonThunderbird: 3658 case CK_Athlon4: 3659 case CK_AthlonXP: 3660 case CK_AthlonMP: 3661 defineCPUMacros(Builder, "athlon"); 3662 if (SSELevel != NoSSE) { 3663 Builder.defineMacro("__athlon_sse__"); 3664 Builder.defineMacro("__tune_athlon_sse__"); 3665 } 3666 break; 3667 case CK_K8: 3668 case CK_K8SSE3: 3669 case CK_x86_64: 3670 case CK_Opteron: 3671 case CK_OpteronSSE3: 3672 case CK_Athlon64: 3673 case CK_Athlon64SSE3: 3674 case CK_AthlonFX: 3675 defineCPUMacros(Builder, "k8"); 3676 break; 3677 case CK_AMDFAM10: 3678 defineCPUMacros(Builder, "amdfam10"); 3679 break; 3680 case CK_BTVER1: 3681 defineCPUMacros(Builder, "btver1"); 3682 break; 3683 case CK_BTVER2: 3684 defineCPUMacros(Builder, "btver2"); 3685 break; 3686 case CK_BDVER1: 3687 defineCPUMacros(Builder, "bdver1"); 3688 break; 3689 case CK_BDVER2: 3690 defineCPUMacros(Builder, "bdver2"); 3691 break; 3692 case CK_BDVER3: 3693 defineCPUMacros(Builder, "bdver3"); 3694 break; 3695 case CK_BDVER4: 3696 defineCPUMacros(Builder, "bdver4"); 3697 break; 3698 case CK_Geode: 3699 defineCPUMacros(Builder, "geode"); 3700 break; 3701 } 3702 3703 // Target properties. 3704 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3705 3706 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3707 // functions in glibc header files that use FP Stack inline asm which the 3708 // backend can't deal with (PR879). 3709 Builder.defineMacro("__NO_MATH_INLINES"); 3710 3711 if (HasAES) 3712 Builder.defineMacro("__AES__"); 3713 3714 if (HasPCLMUL) 3715 Builder.defineMacro("__PCLMUL__"); 3716 3717 if (HasLZCNT) 3718 Builder.defineMacro("__LZCNT__"); 3719 3720 if (HasRDRND) 3721 Builder.defineMacro("__RDRND__"); 3722 3723 if (HasFSGSBASE) 3724 Builder.defineMacro("__FSGSBASE__"); 3725 3726 if (HasBMI) 3727 Builder.defineMacro("__BMI__"); 3728 3729 if (HasBMI2) 3730 Builder.defineMacro("__BMI2__"); 3731 3732 if (HasPOPCNT) 3733 Builder.defineMacro("__POPCNT__"); 3734 3735 if (HasRTM) 3736 Builder.defineMacro("__RTM__"); 3737 3738 if (HasPRFCHW) 3739 Builder.defineMacro("__PRFCHW__"); 3740 3741 if (HasRDSEED) 3742 Builder.defineMacro("__RDSEED__"); 3743 3744 if (HasADX) 3745 Builder.defineMacro("__ADX__"); 3746 3747 if (HasTBM) 3748 Builder.defineMacro("__TBM__"); 3749 3750 if (HasMWAITX) 3751 Builder.defineMacro("__MWAITX__"); 3752 3753 switch (XOPLevel) { 3754 case XOP: 3755 Builder.defineMacro("__XOP__"); 3756 case FMA4: 3757 Builder.defineMacro("__FMA4__"); 3758 case SSE4A: 3759 Builder.defineMacro("__SSE4A__"); 3760 case NoXOP: 3761 break; 3762 } 3763 3764 if (HasFMA) 3765 Builder.defineMacro("__FMA__"); 3766 3767 if (HasF16C) 3768 Builder.defineMacro("__F16C__"); 3769 3770 if (HasAVX512CD) 3771 Builder.defineMacro("__AVX512CD__"); 3772 if (HasAVX512ER) 3773 Builder.defineMacro("__AVX512ER__"); 3774 if (HasAVX512PF) 3775 Builder.defineMacro("__AVX512PF__"); 3776 if (HasAVX512DQ) 3777 Builder.defineMacro("__AVX512DQ__"); 3778 if (HasAVX512BW) 3779 Builder.defineMacro("__AVX512BW__"); 3780 if (HasAVX512VL) 3781 Builder.defineMacro("__AVX512VL__"); 3782 if (HasAVX512VBMI) 3783 Builder.defineMacro("__AVX512VBMI__"); 3784 if (HasAVX512IFMA) 3785 Builder.defineMacro("__AVX512IFMA__"); 3786 3787 if (HasSHA) 3788 Builder.defineMacro("__SHA__"); 3789 3790 if (HasFXSR) 3791 Builder.defineMacro("__FXSR__"); 3792 if (HasXSAVE) 3793 Builder.defineMacro("__XSAVE__"); 3794 if (HasXSAVEOPT) 3795 Builder.defineMacro("__XSAVEOPT__"); 3796 if (HasXSAVEC) 3797 Builder.defineMacro("__XSAVEC__"); 3798 if (HasXSAVES) 3799 Builder.defineMacro("__XSAVES__"); 3800 if (HasPKU) 3801 Builder.defineMacro("__PKU__"); 3802 if (HasCX16) 3803 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3804 3805 // Each case falls through to the previous one here. 3806 switch (SSELevel) { 3807 case AVX512F: 3808 Builder.defineMacro("__AVX512F__"); 3809 case AVX2: 3810 Builder.defineMacro("__AVX2__"); 3811 case AVX: 3812 Builder.defineMacro("__AVX__"); 3813 case SSE42: 3814 Builder.defineMacro("__SSE4_2__"); 3815 case SSE41: 3816 Builder.defineMacro("__SSE4_1__"); 3817 case SSSE3: 3818 Builder.defineMacro("__SSSE3__"); 3819 case SSE3: 3820 Builder.defineMacro("__SSE3__"); 3821 case SSE2: 3822 Builder.defineMacro("__SSE2__"); 3823 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3824 case SSE1: 3825 Builder.defineMacro("__SSE__"); 3826 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3827 case NoSSE: 3828 break; 3829 } 3830 3831 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3832 switch (SSELevel) { 3833 case AVX512F: 3834 case AVX2: 3835 case AVX: 3836 case SSE42: 3837 case SSE41: 3838 case SSSE3: 3839 case SSE3: 3840 case SSE2: 3841 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3842 break; 3843 case SSE1: 3844 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3845 break; 3846 default: 3847 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3848 } 3849 } 3850 3851 // Each case falls through to the previous one here. 3852 switch (MMX3DNowLevel) { 3853 case AMD3DNowAthlon: 3854 Builder.defineMacro("__3dNOW_A__"); 3855 case AMD3DNow: 3856 Builder.defineMacro("__3dNOW__"); 3857 case MMX: 3858 Builder.defineMacro("__MMX__"); 3859 case NoMMX3DNow: 3860 break; 3861 } 3862 3863 if (CPU >= CK_i486) { 3864 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3865 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3866 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3867 } 3868 if (CPU >= CK_i586) 3869 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3870 } 3871 3872 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3873 return llvm::StringSwitch<bool>(Feature) 3874 .Case("aes", HasAES) 3875 .Case("avx", SSELevel >= AVX) 3876 .Case("avx2", SSELevel >= AVX2) 3877 .Case("avx512f", SSELevel >= AVX512F) 3878 .Case("avx512cd", HasAVX512CD) 3879 .Case("avx512er", HasAVX512ER) 3880 .Case("avx512pf", HasAVX512PF) 3881 .Case("avx512dq", HasAVX512DQ) 3882 .Case("avx512bw", HasAVX512BW) 3883 .Case("avx512vl", HasAVX512VL) 3884 .Case("avx512vbmi", HasAVX512VBMI) 3885 .Case("avx512ifma", HasAVX512IFMA) 3886 .Case("bmi", HasBMI) 3887 .Case("bmi2", HasBMI2) 3888 .Case("clflushopt", HasCLFLUSHOPT) 3889 .Case("clwb", HasCLWB) 3890 .Case("cx16", HasCX16) 3891 .Case("f16c", HasF16C) 3892 .Case("fma", HasFMA) 3893 .Case("fma4", XOPLevel >= FMA4) 3894 .Case("fsgsbase", HasFSGSBASE) 3895 .Case("fxsr", HasFXSR) 3896 .Case("lzcnt", HasLZCNT) 3897 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3898 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3899 .Case("mmx", MMX3DNowLevel >= MMX) 3900 .Case("movbe", HasMOVBE) 3901 .Case("mpx", HasMPX) 3902 .Case("pclmul", HasPCLMUL) 3903 .Case("pcommit", HasPCOMMIT) 3904 .Case("pku", HasPKU) 3905 .Case("popcnt", HasPOPCNT) 3906 .Case("prefetchwt1", HasPREFETCHWT1) 3907 .Case("prfchw", HasPRFCHW) 3908 .Case("rdrnd", HasRDRND) 3909 .Case("rdseed", HasRDSEED) 3910 .Case("rtm", HasRTM) 3911 .Case("sgx", HasSGX) 3912 .Case("sha", HasSHA) 3913 .Case("sse", SSELevel >= SSE1) 3914 .Case("sse2", SSELevel >= SSE2) 3915 .Case("sse3", SSELevel >= SSE3) 3916 .Case("ssse3", SSELevel >= SSSE3) 3917 .Case("sse4.1", SSELevel >= SSE41) 3918 .Case("sse4.2", SSELevel >= SSE42) 3919 .Case("sse4a", XOPLevel >= SSE4A) 3920 .Case("tbm", HasTBM) 3921 .Case("umip", HasUMIP) 3922 .Case("x86", true) 3923 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3924 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3925 .Case("xop", XOPLevel >= XOP) 3926 .Case("xsave", HasXSAVE) 3927 .Case("xsavec", HasXSAVEC) 3928 .Case("xsaves", HasXSAVES) 3929 .Case("xsaveopt", HasXSAVEOPT) 3930 .Default(false); 3931 } 3932 3933 // We can't use a generic validation scheme for the features accepted here 3934 // versus subtarget features accepted in the target attribute because the 3935 // bitfield structure that's initialized in the runtime only supports the 3936 // below currently rather than the full range of subtarget features. (See 3937 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3938 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3939 return llvm::StringSwitch<bool>(FeatureStr) 3940 .Case("cmov", true) 3941 .Case("mmx", true) 3942 .Case("popcnt", true) 3943 .Case("sse", true) 3944 .Case("sse2", true) 3945 .Case("sse3", true) 3946 .Case("ssse3", true) 3947 .Case("sse4.1", true) 3948 .Case("sse4.2", true) 3949 .Case("avx", true) 3950 .Case("avx2", true) 3951 .Case("sse4a", true) 3952 .Case("fma4", true) 3953 .Case("xop", true) 3954 .Case("fma", true) 3955 .Case("avx512f", true) 3956 .Case("bmi", true) 3957 .Case("bmi2", true) 3958 .Case("aes", true) 3959 .Case("pclmul", true) 3960 .Case("avx512vl", true) 3961 .Case("avx512bw", true) 3962 .Case("avx512dq", true) 3963 .Case("avx512cd", true) 3964 .Case("avx512er", true) 3965 .Case("avx512pf", true) 3966 .Case("avx512vbmi", true) 3967 .Case("avx512ifma", true) 3968 .Default(false); 3969 } 3970 3971 bool 3972 X86TargetInfo::validateAsmConstraint(const char *&Name, 3973 TargetInfo::ConstraintInfo &Info) const { 3974 switch (*Name) { 3975 default: return false; 3976 // Constant constraints. 3977 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3978 // instructions. 3979 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3980 // x86_64 instructions. 3981 case 's': 3982 Info.setRequiresImmediate(); 3983 return true; 3984 case 'I': 3985 Info.setRequiresImmediate(0, 31); 3986 return true; 3987 case 'J': 3988 Info.setRequiresImmediate(0, 63); 3989 return true; 3990 case 'K': 3991 Info.setRequiresImmediate(-128, 127); 3992 return true; 3993 case 'L': 3994 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3995 return true; 3996 case 'M': 3997 Info.setRequiresImmediate(0, 3); 3998 return true; 3999 case 'N': 4000 Info.setRequiresImmediate(0, 255); 4001 return true; 4002 case 'O': 4003 Info.setRequiresImmediate(0, 127); 4004 return true; 4005 // Register constraints. 4006 case 'Y': // 'Y' is the first character for several 2-character constraints. 4007 // Shift the pointer to the second character of the constraint. 4008 Name++; 4009 switch (*Name) { 4010 default: 4011 return false; 4012 case '0': // First SSE register. 4013 case 't': // Any SSE register, when SSE2 is enabled. 4014 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4015 case 'm': // Any MMX register, when inter-unit moves enabled. 4016 case 'k': // AVX512 arch mask registers: k1-k7. 4017 Info.setAllowsRegister(); 4018 return true; 4019 } 4020 case 'f': // Any x87 floating point stack register. 4021 // Constraint 'f' cannot be used for output operands. 4022 if (Info.ConstraintStr[0] == '=') 4023 return false; 4024 Info.setAllowsRegister(); 4025 return true; 4026 case 'a': // eax. 4027 case 'b': // ebx. 4028 case 'c': // ecx. 4029 case 'd': // edx. 4030 case 'S': // esi. 4031 case 'D': // edi. 4032 case 'A': // edx:eax. 4033 case 't': // Top of floating point stack. 4034 case 'u': // Second from top of floating point stack. 4035 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4036 case 'y': // Any MMX register. 4037 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4038 case 'x': // Any SSE register. 4039 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4040 // for intermideate k reg operations). 4041 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4042 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4043 case 'l': // "Index" registers: any general register that can be used as an 4044 // index in a base+index memory access. 4045 Info.setAllowsRegister(); 4046 return true; 4047 // Floating point constant constraints. 4048 case 'C': // SSE floating point constant. 4049 case 'G': // x87 floating point constant. 4050 return true; 4051 } 4052 } 4053 4054 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4055 unsigned Size) const { 4056 // Strip off constraint modifiers. 4057 while (Constraint[0] == '=' || 4058 Constraint[0] == '+' || 4059 Constraint[0] == '&') 4060 Constraint = Constraint.substr(1); 4061 4062 return validateOperandSize(Constraint, Size); 4063 } 4064 4065 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4066 unsigned Size) const { 4067 return validateOperandSize(Constraint, Size); 4068 } 4069 4070 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4071 unsigned Size) const { 4072 switch (Constraint[0]) { 4073 default: break; 4074 case 'k': 4075 // Registers k0-k7 (AVX512) size limit is 64 bit. 4076 case 'y': 4077 return Size <= 64; 4078 case 'f': 4079 case 't': 4080 case 'u': 4081 return Size <= 128; 4082 case 'v': 4083 case 'x': 4084 if (SSELevel >= AVX512F) 4085 // 512-bit zmm registers can be used if target supports AVX512F. 4086 return Size <= 512U; 4087 else if (SSELevel >= AVX) 4088 // 256-bit ymm registers can be used if target supports AVX. 4089 return Size <= 256U; 4090 return Size <= 128U; 4091 case 'Y': 4092 // 'Y' is the first character for several 2-character constraints. 4093 switch (Constraint[1]) { 4094 default: break; 4095 case 'm': 4096 // 'Ym' is synonymous with 'y'. 4097 case 'k': 4098 return Size <= 64; 4099 case 'i': 4100 case 't': 4101 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4102 if (SSELevel >= AVX512F) 4103 return Size <= 512U; 4104 else if (SSELevel >= AVX) 4105 return Size <= 256U; 4106 return SSELevel >= SSE2 && Size <= 128U; 4107 } 4108 4109 } 4110 4111 return true; 4112 } 4113 4114 std::string 4115 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4116 switch (*Constraint) { 4117 case 'a': return std::string("{ax}"); 4118 case 'b': return std::string("{bx}"); 4119 case 'c': return std::string("{cx}"); 4120 case 'd': return std::string("{dx}"); 4121 case 'S': return std::string("{si}"); 4122 case 'D': return std::string("{di}"); 4123 case 'p': // address 4124 return std::string("im"); 4125 case 't': // top of floating point stack. 4126 return std::string("{st}"); 4127 case 'u': // second from top of floating point stack. 4128 return std::string("{st(1)}"); // second from top of floating point stack. 4129 case 'Y': 4130 switch (Constraint[1]) { 4131 default: 4132 // Break from inner switch and fall through (copy single char), 4133 // continue parsing after copying the current constraint into 4134 // the return string. 4135 break; 4136 case 'k': 4137 // "^" hints llvm that this is a 2 letter constraint. 4138 // "Constraint++" is used to promote the string iterator 4139 // to the next constraint. 4140 return std::string("^") + std::string(Constraint++, 2); 4141 } 4142 LLVM_FALLTHROUGH; 4143 default: 4144 return std::string(1, *Constraint); 4145 } 4146 } 4147 4148 // X86-32 generic target 4149 class X86_32TargetInfo : public X86TargetInfo { 4150 public: 4151 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4152 : X86TargetInfo(Triple, Opts) { 4153 DoubleAlign = LongLongAlign = 32; 4154 LongDoubleWidth = 96; 4155 LongDoubleAlign = 32; 4156 SuitableAlign = 128; 4157 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4158 SizeType = UnsignedInt; 4159 PtrDiffType = SignedInt; 4160 IntPtrType = SignedInt; 4161 RegParmMax = 3; 4162 4163 // Use fpret for all types. 4164 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4165 (1 << TargetInfo::Double) | 4166 (1 << TargetInfo::LongDouble)); 4167 4168 // x86-32 has atomics up to 8 bytes 4169 // FIXME: Check that we actually have cmpxchg8b before setting 4170 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4171 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4172 } 4173 BuiltinVaListKind getBuiltinVaListKind() const override { 4174 return TargetInfo::CharPtrBuiltinVaList; 4175 } 4176 4177 int getEHDataRegisterNumber(unsigned RegNo) const override { 4178 if (RegNo == 0) return 0; 4179 if (RegNo == 1) return 2; 4180 return -1; 4181 } 4182 bool validateOperandSize(StringRef Constraint, 4183 unsigned Size) const override { 4184 switch (Constraint[0]) { 4185 default: break; 4186 case 'R': 4187 case 'q': 4188 case 'Q': 4189 case 'a': 4190 case 'b': 4191 case 'c': 4192 case 'd': 4193 case 'S': 4194 case 'D': 4195 return Size <= 32; 4196 case 'A': 4197 return Size <= 64; 4198 } 4199 4200 return X86TargetInfo::validateOperandSize(Constraint, Size); 4201 } 4202 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4203 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4204 Builtin::FirstTSBuiltin + 1); 4205 } 4206 }; 4207 4208 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4209 public: 4210 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4211 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4212 4213 unsigned getFloatEvalMethod() const override { 4214 unsigned Major, Minor, Micro; 4215 getTriple().getOSVersion(Major, Minor, Micro); 4216 // New NetBSD uses the default rounding mode. 4217 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4218 return X86_32TargetInfo::getFloatEvalMethod(); 4219 // NetBSD before 6.99.26 defaults to "double" rounding. 4220 return 1; 4221 } 4222 }; 4223 4224 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4225 public: 4226 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4227 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4228 SizeType = UnsignedLong; 4229 IntPtrType = SignedLong; 4230 PtrDiffType = SignedLong; 4231 } 4232 }; 4233 4234 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4235 public: 4236 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4237 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4238 SizeType = UnsignedLong; 4239 IntPtrType = SignedLong; 4240 PtrDiffType = SignedLong; 4241 } 4242 }; 4243 4244 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4245 public: 4246 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4247 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4248 LongDoubleWidth = 128; 4249 LongDoubleAlign = 128; 4250 SuitableAlign = 128; 4251 MaxVectorAlign = 256; 4252 // The watchOS simulator uses the builtin bool type for Objective-C. 4253 llvm::Triple T = llvm::Triple(Triple); 4254 if (T.isWatchOS()) 4255 UseSignedCharForObjCBool = false; 4256 SizeType = UnsignedLong; 4257 IntPtrType = SignedLong; 4258 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4259 HasAlignMac68kSupport = true; 4260 } 4261 4262 bool handleTargetFeatures(std::vector<std::string> &Features, 4263 DiagnosticsEngine &Diags) override { 4264 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4265 Diags)) 4266 return false; 4267 // We now know the features we have: we can decide how to align vectors. 4268 MaxVectorAlign = 4269 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4270 return true; 4271 } 4272 }; 4273 4274 // x86-32 Windows target 4275 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4276 public: 4277 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4278 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4279 WCharType = UnsignedShort; 4280 DoubleAlign = LongLongAlign = 64; 4281 bool IsWinCOFF = 4282 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4283 resetDataLayout(IsWinCOFF 4284 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4285 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4286 } 4287 void getTargetDefines(const LangOptions &Opts, 4288 MacroBuilder &Builder) const override { 4289 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4290 } 4291 }; 4292 4293 // x86-32 Windows Visual Studio target 4294 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4295 public: 4296 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4297 const TargetOptions &Opts) 4298 : WindowsX86_32TargetInfo(Triple, Opts) { 4299 LongDoubleWidth = LongDoubleAlign = 64; 4300 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4301 } 4302 void getTargetDefines(const LangOptions &Opts, 4303 MacroBuilder &Builder) const override { 4304 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4305 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4306 // The value of the following reflects processor type. 4307 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4308 // We lost the original triple, so we use the default. 4309 Builder.defineMacro("_M_IX86", "600"); 4310 } 4311 }; 4312 4313 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4314 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4315 // supports __declspec natively under -fms-extensions, but we define a no-op 4316 // __declspec macro anyway for pre-processor compatibility. 4317 if (Opts.MicrosoftExt) 4318 Builder.defineMacro("__declspec", "__declspec"); 4319 else 4320 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4321 4322 if (!Opts.MicrosoftExt) { 4323 // Provide macros for all the calling convention keywords. Provide both 4324 // single and double underscore prefixed variants. These are available on 4325 // x64 as well as x86, even though they have no effect. 4326 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4327 for (const char *CC : CCs) { 4328 std::string GCCSpelling = "__attribute__((__"; 4329 GCCSpelling += CC; 4330 GCCSpelling += "__))"; 4331 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4332 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4333 } 4334 } 4335 } 4336 4337 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4338 Builder.defineMacro("__MSVCRT__"); 4339 Builder.defineMacro("__MINGW32__"); 4340 addCygMingDefines(Opts, Builder); 4341 } 4342 4343 // x86-32 MinGW target 4344 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4345 public: 4346 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4347 : WindowsX86_32TargetInfo(Triple, Opts) {} 4348 void getTargetDefines(const LangOptions &Opts, 4349 MacroBuilder &Builder) const override { 4350 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4351 DefineStd(Builder, "WIN32", Opts); 4352 DefineStd(Builder, "WINNT", Opts); 4353 Builder.defineMacro("_X86_"); 4354 addMinGWDefines(Opts, Builder); 4355 } 4356 }; 4357 4358 // x86-32 Cygwin target 4359 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4360 public: 4361 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4362 : X86_32TargetInfo(Triple, Opts) { 4363 WCharType = UnsignedShort; 4364 DoubleAlign = LongLongAlign = 64; 4365 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4366 } 4367 void getTargetDefines(const LangOptions &Opts, 4368 MacroBuilder &Builder) const override { 4369 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4370 Builder.defineMacro("_X86_"); 4371 Builder.defineMacro("__CYGWIN__"); 4372 Builder.defineMacro("__CYGWIN32__"); 4373 addCygMingDefines(Opts, Builder); 4374 DefineStd(Builder, "unix", Opts); 4375 if (Opts.CPlusPlus) 4376 Builder.defineMacro("_GNU_SOURCE"); 4377 } 4378 }; 4379 4380 // x86-32 Haiku target 4381 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4382 public: 4383 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4384 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4385 } 4386 void getTargetDefines(const LangOptions &Opts, 4387 MacroBuilder &Builder) const override { 4388 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4389 Builder.defineMacro("__INTEL__"); 4390 } 4391 }; 4392 4393 // X86-32 MCU target 4394 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4395 public: 4396 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4397 : X86_32TargetInfo(Triple, Opts) { 4398 LongDoubleWidth = 64; 4399 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4400 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4401 WIntType = UnsignedInt; 4402 } 4403 4404 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4405 // On MCU we support only C calling convention. 4406 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4407 } 4408 4409 void getTargetDefines(const LangOptions &Opts, 4410 MacroBuilder &Builder) const override { 4411 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4412 Builder.defineMacro("__iamcu"); 4413 Builder.defineMacro("__iamcu__"); 4414 } 4415 4416 bool allowsLargerPreferedTypeAlignment() const override { 4417 return false; 4418 } 4419 }; 4420 4421 // RTEMS Target 4422 template<typename Target> 4423 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4424 protected: 4425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4426 MacroBuilder &Builder) const override { 4427 // RTEMS defines; list based off of gcc output 4428 4429 Builder.defineMacro("__rtems__"); 4430 Builder.defineMacro("__ELF__"); 4431 } 4432 4433 public: 4434 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4435 : OSTargetInfo<Target>(Triple, Opts) { 4436 switch (Triple.getArch()) { 4437 default: 4438 case llvm::Triple::x86: 4439 // this->MCountName = ".mcount"; 4440 break; 4441 case llvm::Triple::mips: 4442 case llvm::Triple::mipsel: 4443 case llvm::Triple::ppc: 4444 case llvm::Triple::ppc64: 4445 case llvm::Triple::ppc64le: 4446 // this->MCountName = "_mcount"; 4447 break; 4448 case llvm::Triple::arm: 4449 // this->MCountName = "__mcount"; 4450 break; 4451 } 4452 } 4453 }; 4454 4455 // x86-32 RTEMS target 4456 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4457 public: 4458 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4459 : X86_32TargetInfo(Triple, Opts) { 4460 SizeType = UnsignedLong; 4461 IntPtrType = SignedLong; 4462 PtrDiffType = SignedLong; 4463 } 4464 void getTargetDefines(const LangOptions &Opts, 4465 MacroBuilder &Builder) const override { 4466 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4467 Builder.defineMacro("__INTEL__"); 4468 Builder.defineMacro("__rtems__"); 4469 } 4470 }; 4471 4472 // x86-64 generic target 4473 class X86_64TargetInfo : public X86TargetInfo { 4474 public: 4475 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4476 : X86TargetInfo(Triple, Opts) { 4477 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4478 bool IsWinCOFF = 4479 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4480 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4481 LongDoubleWidth = 128; 4482 LongDoubleAlign = 128; 4483 LargeArrayMinWidth = 128; 4484 LargeArrayAlign = 128; 4485 SuitableAlign = 128; 4486 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4487 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4488 IntPtrType = IsX32 ? SignedInt : SignedLong; 4489 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4490 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4491 RegParmMax = 6; 4492 4493 // Pointers are 32-bit in x32. 4494 resetDataLayout(IsX32 4495 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4496 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4497 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4498 4499 // Use fpret only for long double. 4500 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4501 4502 // Use fp2ret for _Complex long double. 4503 ComplexLongDoubleUsesFP2Ret = true; 4504 4505 // Make __builtin_ms_va_list available. 4506 HasBuiltinMSVaList = true; 4507 4508 // x86-64 has atomics up to 16 bytes. 4509 MaxAtomicPromoteWidth = 128; 4510 MaxAtomicInlineWidth = 128; 4511 } 4512 BuiltinVaListKind getBuiltinVaListKind() const override { 4513 return TargetInfo::X86_64ABIBuiltinVaList; 4514 } 4515 4516 int getEHDataRegisterNumber(unsigned RegNo) const override { 4517 if (RegNo == 0) return 0; 4518 if (RegNo == 1) return 1; 4519 return -1; 4520 } 4521 4522 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4523 switch (CC) { 4524 case CC_C: 4525 case CC_Swift: 4526 case CC_X86VectorCall: 4527 case CC_IntelOclBicc: 4528 case CC_X86_64Win64: 4529 case CC_PreserveMost: 4530 case CC_PreserveAll: 4531 case CC_X86RegCall: 4532 return CCCR_OK; 4533 default: 4534 return CCCR_Warning; 4535 } 4536 } 4537 4538 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4539 return CC_C; 4540 } 4541 4542 // for x32 we need it here explicitly 4543 bool hasInt128Type() const override { return true; } 4544 unsigned getUnwindWordWidth() const override { return 64; } 4545 unsigned getRegisterWidth() const override { return 64; } 4546 4547 bool validateGlobalRegisterVariable(StringRef RegName, 4548 unsigned RegSize, 4549 bool &HasSizeMismatch) const override { 4550 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4551 // handle. 4552 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4553 // Check that the register size is 64-bit. 4554 HasSizeMismatch = RegSize != 64; 4555 return true; 4556 } 4557 4558 // Check if the register is a 32-bit register the backend can handle. 4559 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4560 HasSizeMismatch); 4561 } 4562 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4563 return llvm::makeArrayRef(BuiltinInfoX86, 4564 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4565 } 4566 }; 4567 4568 // x86-64 Windows target 4569 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4570 public: 4571 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4572 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4573 WCharType = UnsignedShort; 4574 LongWidth = LongAlign = 32; 4575 DoubleAlign = LongLongAlign = 64; 4576 IntMaxType = SignedLongLong; 4577 Int64Type = SignedLongLong; 4578 SizeType = UnsignedLongLong; 4579 PtrDiffType = SignedLongLong; 4580 IntPtrType = SignedLongLong; 4581 } 4582 4583 void getTargetDefines(const LangOptions &Opts, 4584 MacroBuilder &Builder) const override { 4585 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4586 Builder.defineMacro("_WIN64"); 4587 } 4588 4589 BuiltinVaListKind getBuiltinVaListKind() const override { 4590 return TargetInfo::CharPtrBuiltinVaList; 4591 } 4592 4593 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4594 switch (CC) { 4595 case CC_X86StdCall: 4596 case CC_X86ThisCall: 4597 case CC_X86FastCall: 4598 return CCCR_Ignore; 4599 case CC_C: 4600 case CC_X86VectorCall: 4601 case CC_IntelOclBicc: 4602 case CC_X86_64SysV: 4603 case CC_Swift: 4604 case CC_X86RegCall: 4605 return CCCR_OK; 4606 default: 4607 return CCCR_Warning; 4608 } 4609 } 4610 }; 4611 4612 // x86-64 Windows Visual Studio target 4613 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4614 public: 4615 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4616 const TargetOptions &Opts) 4617 : WindowsX86_64TargetInfo(Triple, Opts) { 4618 LongDoubleWidth = LongDoubleAlign = 64; 4619 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4620 } 4621 void getTargetDefines(const LangOptions &Opts, 4622 MacroBuilder &Builder) const override { 4623 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4624 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4625 Builder.defineMacro("_M_X64", "100"); 4626 Builder.defineMacro("_M_AMD64", "100"); 4627 } 4628 }; 4629 4630 // x86-64 MinGW target 4631 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4632 public: 4633 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4634 : WindowsX86_64TargetInfo(Triple, Opts) { 4635 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4636 // with x86 FP ops. Weird. 4637 LongDoubleWidth = LongDoubleAlign = 128; 4638 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4639 } 4640 4641 void getTargetDefines(const LangOptions &Opts, 4642 MacroBuilder &Builder) const override { 4643 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4644 DefineStd(Builder, "WIN64", Opts); 4645 Builder.defineMacro("__MINGW64__"); 4646 addMinGWDefines(Opts, Builder); 4647 4648 // GCC defines this macro when it is using __gxx_personality_seh0. 4649 if (!Opts.SjLjExceptions) 4650 Builder.defineMacro("__SEH__"); 4651 } 4652 }; 4653 4654 // x86-64 Cygwin target 4655 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4656 public: 4657 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4658 : X86_64TargetInfo(Triple, Opts) { 4659 TLSSupported = false; 4660 WCharType = UnsignedShort; 4661 } 4662 void getTargetDefines(const LangOptions &Opts, 4663 MacroBuilder &Builder) const override { 4664 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4665 Builder.defineMacro("__x86_64__"); 4666 Builder.defineMacro("__CYGWIN__"); 4667 Builder.defineMacro("__CYGWIN64__"); 4668 addCygMingDefines(Opts, Builder); 4669 DefineStd(Builder, "unix", Opts); 4670 if (Opts.CPlusPlus) 4671 Builder.defineMacro("_GNU_SOURCE"); 4672 4673 // GCC defines this macro when it is using __gxx_personality_seh0. 4674 if (!Opts.SjLjExceptions) 4675 Builder.defineMacro("__SEH__"); 4676 } 4677 }; 4678 4679 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4680 public: 4681 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4682 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4683 Int64Type = SignedLongLong; 4684 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4685 llvm::Triple T = llvm::Triple(Triple); 4686 if (T.isiOS()) 4687 UseSignedCharForObjCBool = false; 4688 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4689 } 4690 4691 bool handleTargetFeatures(std::vector<std::string> &Features, 4692 DiagnosticsEngine &Diags) override { 4693 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4694 Diags)) 4695 return false; 4696 // We now know the features we have: we can decide how to align vectors. 4697 MaxVectorAlign = 4698 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4699 return true; 4700 } 4701 }; 4702 4703 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4704 public: 4705 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4706 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4707 IntMaxType = SignedLongLong; 4708 Int64Type = SignedLongLong; 4709 } 4710 }; 4711 4712 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4713 public: 4714 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4715 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4716 IntMaxType = SignedLongLong; 4717 Int64Type = SignedLongLong; 4718 } 4719 }; 4720 4721 class ARMTargetInfo : public TargetInfo { 4722 // Possible FPU choices. 4723 enum FPUMode { 4724 VFP2FPU = (1 << 0), 4725 VFP3FPU = (1 << 1), 4726 VFP4FPU = (1 << 2), 4727 NeonFPU = (1 << 3), 4728 FPARMV8 = (1 << 4) 4729 }; 4730 4731 // Possible HWDiv features. 4732 enum HWDivMode { 4733 HWDivThumb = (1 << 0), 4734 HWDivARM = (1 << 1) 4735 }; 4736 4737 static bool FPUModeIsVFP(FPUMode Mode) { 4738 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4739 } 4740 4741 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4742 static const char * const GCCRegNames[]; 4743 4744 std::string ABI, CPU; 4745 4746 StringRef CPUProfile; 4747 StringRef CPUAttr; 4748 4749 enum { 4750 FP_Default, 4751 FP_VFP, 4752 FP_Neon 4753 } FPMath; 4754 4755 unsigned ArchISA; 4756 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4757 unsigned ArchProfile; 4758 unsigned ArchVersion; 4759 4760 unsigned FPU : 5; 4761 4762 unsigned IsAAPCS : 1; 4763 unsigned HWDiv : 2; 4764 4765 // Initialized via features. 4766 unsigned SoftFloat : 1; 4767 unsigned SoftFloatABI : 1; 4768 4769 unsigned CRC : 1; 4770 unsigned Crypto : 1; 4771 unsigned DSP : 1; 4772 unsigned Unaligned : 1; 4773 4774 enum { 4775 LDREX_B = (1 << 0), /// byte (8-bit) 4776 LDREX_H = (1 << 1), /// half (16-bit) 4777 LDREX_W = (1 << 2), /// word (32-bit) 4778 LDREX_D = (1 << 3), /// double (64-bit) 4779 }; 4780 4781 uint32_t LDREX; 4782 4783 // ACLE 6.5.1 Hardware floating point 4784 enum { 4785 HW_FP_HP = (1 << 1), /// half (16-bit) 4786 HW_FP_SP = (1 << 2), /// single (32-bit) 4787 HW_FP_DP = (1 << 3), /// double (64-bit) 4788 }; 4789 uint32_t HW_FP; 4790 4791 static const Builtin::Info BuiltinInfo[]; 4792 4793 void setABIAAPCS() { 4794 IsAAPCS = true; 4795 4796 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4797 const llvm::Triple &T = getTriple(); 4798 4799 // size_t is unsigned long on MachO-derived environments, NetBSD, 4800 // OpenBSD and Bitrig. 4801 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4802 T.getOS() == llvm::Triple::OpenBSD || 4803 T.getOS() == llvm::Triple::Bitrig) 4804 SizeType = UnsignedLong; 4805 else 4806 SizeType = UnsignedInt; 4807 4808 switch (T.getOS()) { 4809 case llvm::Triple::NetBSD: 4810 case llvm::Triple::OpenBSD: 4811 WCharType = SignedInt; 4812 break; 4813 case llvm::Triple::Win32: 4814 WCharType = UnsignedShort; 4815 break; 4816 case llvm::Triple::Linux: 4817 default: 4818 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4819 WCharType = UnsignedInt; 4820 break; 4821 } 4822 4823 UseBitFieldTypeAlignment = true; 4824 4825 ZeroLengthBitfieldBoundary = 0; 4826 4827 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4828 // so set preferred for small types to 32. 4829 if (T.isOSBinFormatMachO()) { 4830 resetDataLayout(BigEndian 4831 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4832 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4833 } else if (T.isOSWindows()) { 4834 assert(!BigEndian && "Windows on ARM does not support big endian"); 4835 resetDataLayout("e" 4836 "-m:w" 4837 "-p:32:32" 4838 "-i64:64" 4839 "-v128:64:128" 4840 "-a:0:32" 4841 "-n32" 4842 "-S64"); 4843 } else if (T.isOSNaCl()) { 4844 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4845 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4846 } else { 4847 resetDataLayout(BigEndian 4848 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4849 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4850 } 4851 4852 // FIXME: Enumerated types are variable width in straight AAPCS. 4853 } 4854 4855 void setABIAPCS(bool IsAAPCS16) { 4856 const llvm::Triple &T = getTriple(); 4857 4858 IsAAPCS = false; 4859 4860 if (IsAAPCS16) 4861 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4862 else 4863 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4864 4865 // size_t is unsigned int on FreeBSD. 4866 if (T.getOS() == llvm::Triple::FreeBSD) 4867 SizeType = UnsignedInt; 4868 else 4869 SizeType = UnsignedLong; 4870 4871 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4872 WCharType = SignedInt; 4873 4874 // Do not respect the alignment of bit-field types when laying out 4875 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4876 UseBitFieldTypeAlignment = false; 4877 4878 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4879 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4880 /// gcc. 4881 ZeroLengthBitfieldBoundary = 32; 4882 4883 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4884 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4885 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4886 } else if (T.isOSBinFormatMachO()) 4887 resetDataLayout( 4888 BigEndian 4889 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4890 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4891 else 4892 resetDataLayout( 4893 BigEndian 4894 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4895 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4896 4897 // FIXME: Override "preferred align" for double and long long. 4898 } 4899 4900 void setArchInfo() { 4901 StringRef ArchName = getTriple().getArchName(); 4902 4903 ArchISA = llvm::ARM::parseArchISA(ArchName); 4904 CPU = llvm::ARM::getDefaultCPU(ArchName); 4905 unsigned AK = llvm::ARM::parseArch(ArchName); 4906 if (AK != llvm::ARM::AK_INVALID) 4907 ArchKind = AK; 4908 setArchInfo(ArchKind); 4909 } 4910 4911 void setArchInfo(unsigned Kind) { 4912 StringRef SubArch; 4913 4914 // cache TargetParser info 4915 ArchKind = Kind; 4916 SubArch = llvm::ARM::getSubArch(ArchKind); 4917 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4918 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4919 4920 // cache CPU related strings 4921 CPUAttr = getCPUAttr(); 4922 CPUProfile = getCPUProfile(); 4923 } 4924 4925 void setAtomic() { 4926 // when triple does not specify a sub arch, 4927 // then we are not using inline atomics 4928 bool ShouldUseInlineAtomic = 4929 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4930 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4931 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4932 if (ArchProfile == llvm::ARM::PK_M) { 4933 MaxAtomicPromoteWidth = 32; 4934 if (ShouldUseInlineAtomic) 4935 MaxAtomicInlineWidth = 32; 4936 } 4937 else { 4938 MaxAtomicPromoteWidth = 64; 4939 if (ShouldUseInlineAtomic) 4940 MaxAtomicInlineWidth = 64; 4941 } 4942 } 4943 4944 bool isThumb() const { 4945 return (ArchISA == llvm::ARM::IK_THUMB); 4946 } 4947 4948 bool supportsThumb() const { 4949 return CPUAttr.count('T') || ArchVersion >= 6; 4950 } 4951 4952 bool supportsThumb2() const { 4953 return CPUAttr.equals("6T2") || 4954 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4955 } 4956 4957 StringRef getCPUAttr() const { 4958 // For most sub-arches, the build attribute CPU name is enough. 4959 // For Cortex variants, it's slightly different. 4960 switch(ArchKind) { 4961 default: 4962 return llvm::ARM::getCPUAttr(ArchKind); 4963 case llvm::ARM::AK_ARMV6M: 4964 return "6M"; 4965 case llvm::ARM::AK_ARMV7S: 4966 return "7S"; 4967 case llvm::ARM::AK_ARMV7A: 4968 return "7A"; 4969 case llvm::ARM::AK_ARMV7R: 4970 return "7R"; 4971 case llvm::ARM::AK_ARMV7M: 4972 return "7M"; 4973 case llvm::ARM::AK_ARMV7EM: 4974 return "7EM"; 4975 case llvm::ARM::AK_ARMV8A: 4976 return "8A"; 4977 case llvm::ARM::AK_ARMV8_1A: 4978 return "8_1A"; 4979 case llvm::ARM::AK_ARMV8_2A: 4980 return "8_2A"; 4981 case llvm::ARM::AK_ARMV8MBaseline: 4982 return "8M_BASE"; 4983 case llvm::ARM::AK_ARMV8MMainline: 4984 return "8M_MAIN"; 4985 case llvm::ARM::AK_ARMV8R: 4986 return "8R"; 4987 } 4988 } 4989 4990 StringRef getCPUProfile() const { 4991 switch(ArchProfile) { 4992 case llvm::ARM::PK_A: 4993 return "A"; 4994 case llvm::ARM::PK_R: 4995 return "R"; 4996 case llvm::ARM::PK_M: 4997 return "M"; 4998 default: 4999 return ""; 5000 } 5001 } 5002 5003 public: 5004 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5005 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5006 HW_FP(0) { 5007 5008 switch (getTriple().getOS()) { 5009 case llvm::Triple::NetBSD: 5010 case llvm::Triple::OpenBSD: 5011 PtrDiffType = SignedLong; 5012 break; 5013 default: 5014 PtrDiffType = SignedInt; 5015 break; 5016 } 5017 5018 // Cache arch related info. 5019 setArchInfo(); 5020 5021 // {} in inline assembly are neon specifiers, not assembly variant 5022 // specifiers. 5023 NoAsmVariants = true; 5024 5025 // FIXME: This duplicates code from the driver that sets the -target-abi 5026 // option - this code is used if -target-abi isn't passed and should 5027 // be unified in some way. 5028 if (Triple.isOSBinFormatMachO()) { 5029 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5030 // the frontend matches that. 5031 if (Triple.getEnvironment() == llvm::Triple::EABI || 5032 Triple.getOS() == llvm::Triple::UnknownOS || 5033 ArchProfile == llvm::ARM::PK_M) { 5034 setABI("aapcs"); 5035 } else if (Triple.isWatchABI()) { 5036 setABI("aapcs16"); 5037 } else { 5038 setABI("apcs-gnu"); 5039 } 5040 } else if (Triple.isOSWindows()) { 5041 // FIXME: this is invalid for WindowsCE 5042 setABI("aapcs"); 5043 } else { 5044 // Select the default based on the platform. 5045 switch (Triple.getEnvironment()) { 5046 case llvm::Triple::Android: 5047 case llvm::Triple::GNUEABI: 5048 case llvm::Triple::GNUEABIHF: 5049 case llvm::Triple::MuslEABI: 5050 case llvm::Triple::MuslEABIHF: 5051 setABI("aapcs-linux"); 5052 break; 5053 case llvm::Triple::EABIHF: 5054 case llvm::Triple::EABI: 5055 setABI("aapcs"); 5056 break; 5057 case llvm::Triple::GNU: 5058 setABI("apcs-gnu"); 5059 break; 5060 default: 5061 if (Triple.getOS() == llvm::Triple::NetBSD) 5062 setABI("apcs-gnu"); 5063 else 5064 setABI("aapcs"); 5065 break; 5066 } 5067 } 5068 5069 // ARM targets default to using the ARM C++ ABI. 5070 TheCXXABI.set(TargetCXXABI::GenericARM); 5071 5072 // ARM has atomics up to 8 bytes 5073 setAtomic(); 5074 5075 // Do force alignment of members that follow zero length bitfields. If 5076 // the alignment of the zero-length bitfield is greater than the member 5077 // that follows it, `bar', `bar' will be aligned as the type of the 5078 // zero length bitfield. 5079 UseZeroLengthBitfieldAlignment = true; 5080 5081 if (Triple.getOS() == llvm::Triple::Linux || 5082 Triple.getOS() == llvm::Triple::UnknownOS) 5083 this->MCountName = 5084 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5085 } 5086 5087 StringRef getABI() const override { return ABI; } 5088 5089 bool setABI(const std::string &Name) override { 5090 ABI = Name; 5091 5092 // The defaults (above) are for AAPCS, check if we need to change them. 5093 // 5094 // FIXME: We need support for -meabi... we could just mangle it into the 5095 // name. 5096 if (Name == "apcs-gnu" || Name == "aapcs16") { 5097 setABIAPCS(Name == "aapcs16"); 5098 return true; 5099 } 5100 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5101 setABIAAPCS(); 5102 return true; 5103 } 5104 return false; 5105 } 5106 5107 // FIXME: This should be based on Arch attributes, not CPU names. 5108 bool 5109 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5110 StringRef CPU, 5111 const std::vector<std::string> &FeaturesVec) const override { 5112 5113 std::vector<StringRef> TargetFeatures; 5114 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5115 5116 // get default FPU features 5117 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5118 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5119 5120 // get default Extension features 5121 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5122 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5123 5124 for (auto Feature : TargetFeatures) 5125 if (Feature[0] == '+') 5126 Features[Feature.drop_front(1)] = true; 5127 5128 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5129 } 5130 5131 bool handleTargetFeatures(std::vector<std::string> &Features, 5132 DiagnosticsEngine &Diags) override { 5133 FPU = 0; 5134 CRC = 0; 5135 Crypto = 0; 5136 DSP = 0; 5137 Unaligned = 1; 5138 SoftFloat = SoftFloatABI = false; 5139 HWDiv = 0; 5140 5141 // This does not diagnose illegal cases like having both 5142 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5143 uint32_t HW_FP_remove = 0; 5144 for (const auto &Feature : Features) { 5145 if (Feature == "+soft-float") { 5146 SoftFloat = true; 5147 } else if (Feature == "+soft-float-abi") { 5148 SoftFloatABI = true; 5149 } else if (Feature == "+vfp2") { 5150 FPU |= VFP2FPU; 5151 HW_FP |= HW_FP_SP | HW_FP_DP; 5152 } else if (Feature == "+vfp3") { 5153 FPU |= VFP3FPU; 5154 HW_FP |= HW_FP_SP | HW_FP_DP; 5155 } else if (Feature == "+vfp4") { 5156 FPU |= VFP4FPU; 5157 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5158 } else if (Feature == "+fp-armv8") { 5159 FPU |= FPARMV8; 5160 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5161 } else if (Feature == "+neon") { 5162 FPU |= NeonFPU; 5163 HW_FP |= HW_FP_SP | HW_FP_DP; 5164 } else if (Feature == "+hwdiv") { 5165 HWDiv |= HWDivThumb; 5166 } else if (Feature == "+hwdiv-arm") { 5167 HWDiv |= HWDivARM; 5168 } else if (Feature == "+crc") { 5169 CRC = 1; 5170 } else if (Feature == "+crypto") { 5171 Crypto = 1; 5172 } else if (Feature == "+dsp") { 5173 DSP = 1; 5174 } else if (Feature == "+fp-only-sp") { 5175 HW_FP_remove |= HW_FP_DP; 5176 } else if (Feature == "+strict-align") { 5177 Unaligned = 0; 5178 } else if (Feature == "+fp16") { 5179 HW_FP |= HW_FP_HP; 5180 } 5181 } 5182 HW_FP &= ~HW_FP_remove; 5183 5184 switch (ArchVersion) { 5185 case 6: 5186 if (ArchProfile == llvm::ARM::PK_M) 5187 LDREX = 0; 5188 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5189 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5190 else 5191 LDREX = LDREX_W; 5192 break; 5193 case 7: 5194 if (ArchProfile == llvm::ARM::PK_M) 5195 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5196 else 5197 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5198 break; 5199 case 8: 5200 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5201 } 5202 5203 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5204 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5205 return false; 5206 } 5207 5208 if (FPMath == FP_Neon) 5209 Features.push_back("+neonfp"); 5210 else if (FPMath == FP_VFP) 5211 Features.push_back("-neonfp"); 5212 5213 // Remove front-end specific options which the backend handles differently. 5214 auto Feature = 5215 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5216 if (Feature != Features.end()) 5217 Features.erase(Feature); 5218 5219 return true; 5220 } 5221 5222 bool hasFeature(StringRef Feature) const override { 5223 return llvm::StringSwitch<bool>(Feature) 5224 .Case("arm", true) 5225 .Case("aarch32", true) 5226 .Case("softfloat", SoftFloat) 5227 .Case("thumb", isThumb()) 5228 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5229 .Case("hwdiv", HWDiv & HWDivThumb) 5230 .Case("hwdiv-arm", HWDiv & HWDivARM) 5231 .Default(false); 5232 } 5233 5234 bool setCPU(const std::string &Name) override { 5235 if (Name != "generic") 5236 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5237 5238 if (ArchKind == llvm::ARM::AK_INVALID) 5239 return false; 5240 setAtomic(); 5241 CPU = Name; 5242 return true; 5243 } 5244 5245 bool setFPMath(StringRef Name) override; 5246 5247 void getTargetDefines(const LangOptions &Opts, 5248 MacroBuilder &Builder) const override { 5249 // Target identification. 5250 Builder.defineMacro("__arm"); 5251 Builder.defineMacro("__arm__"); 5252 // For bare-metal none-eabi. 5253 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5254 getTriple().getEnvironment() == llvm::Triple::EABI) 5255 Builder.defineMacro("__ELF__"); 5256 5257 // Target properties. 5258 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5259 5260 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5261 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5262 if (getTriple().isWatchABI()) 5263 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5264 5265 if (!CPUAttr.empty()) 5266 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5267 5268 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5269 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5270 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5271 5272 if (ArchVersion >= 8) { 5273 // ACLE 6.5.7 Crypto Extension 5274 if (Crypto) 5275 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5276 // ACLE 6.5.8 CRC32 Extension 5277 if (CRC) 5278 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5279 // ACLE 6.5.10 Numeric Maximum and Minimum 5280 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5281 // ACLE 6.5.9 Directed Rounding 5282 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5283 } 5284 5285 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5286 // is not defined for the M-profile. 5287 // NOTE that the default profile is assumed to be 'A' 5288 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5289 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5290 5291 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5292 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5293 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5294 // v7 and v8 architectures excluding v8-M Baseline. 5295 if (supportsThumb2()) 5296 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5297 else if (supportsThumb()) 5298 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5299 5300 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5301 // instruction set such as ARM or Thumb. 5302 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5303 5304 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5305 5306 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5307 if (!CPUProfile.empty()) 5308 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5309 5310 // ACLE 6.4.3 Unaligned access supported in hardware 5311 if (Unaligned) 5312 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5313 5314 // ACLE 6.4.4 LDREX/STREX 5315 if (LDREX) 5316 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5317 5318 // ACLE 6.4.5 CLZ 5319 if (ArchVersion == 5 || 5320 (ArchVersion == 6 && CPUProfile != "M") || 5321 ArchVersion > 6) 5322 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5323 5324 // ACLE 6.5.1 Hardware Floating Point 5325 if (HW_FP) 5326 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5327 5328 // ACLE predefines. 5329 Builder.defineMacro("__ARM_ACLE", "200"); 5330 5331 // FP16 support (we currently only support IEEE format). 5332 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5333 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5334 5335 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5336 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5337 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5338 5339 // Subtarget options. 5340 5341 // FIXME: It's more complicated than this and we don't really support 5342 // interworking. 5343 // Windows on ARM does not "support" interworking 5344 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5345 Builder.defineMacro("__THUMB_INTERWORK__"); 5346 5347 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5348 // Embedded targets on Darwin follow AAPCS, but not EABI. 5349 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5350 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5351 Builder.defineMacro("__ARM_EABI__"); 5352 Builder.defineMacro("__ARM_PCS", "1"); 5353 } 5354 5355 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5356 ABI == "aapcs16") 5357 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5358 5359 if (SoftFloat) 5360 Builder.defineMacro("__SOFTFP__"); 5361 5362 if (ArchKind == llvm::ARM::AK_XSCALE) 5363 Builder.defineMacro("__XSCALE__"); 5364 5365 if (isThumb()) { 5366 Builder.defineMacro("__THUMBEL__"); 5367 Builder.defineMacro("__thumb__"); 5368 if (supportsThumb2()) 5369 Builder.defineMacro("__thumb2__"); 5370 } 5371 5372 // ACLE 6.4.9 32-bit SIMD instructions 5373 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5374 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5375 5376 // ACLE 6.4.10 Hardware Integer Divide 5377 if (((HWDiv & HWDivThumb) && isThumb()) || 5378 ((HWDiv & HWDivARM) && !isThumb())) { 5379 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5380 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5381 } 5382 5383 // Note, this is always on in gcc, even though it doesn't make sense. 5384 Builder.defineMacro("__APCS_32__"); 5385 5386 if (FPUModeIsVFP((FPUMode) FPU)) { 5387 Builder.defineMacro("__VFP_FP__"); 5388 if (FPU & VFP2FPU) 5389 Builder.defineMacro("__ARM_VFPV2__"); 5390 if (FPU & VFP3FPU) 5391 Builder.defineMacro("__ARM_VFPV3__"); 5392 if (FPU & VFP4FPU) 5393 Builder.defineMacro("__ARM_VFPV4__"); 5394 } 5395 5396 // This only gets set when Neon instructions are actually available, unlike 5397 // the VFP define, hence the soft float and arch check. This is subtly 5398 // different from gcc, we follow the intent which was that it should be set 5399 // when Neon instructions are actually available. 5400 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5401 Builder.defineMacro("__ARM_NEON", "1"); 5402 Builder.defineMacro("__ARM_NEON__"); 5403 // current AArch32 NEON implementations do not support double-precision 5404 // floating-point even when it is present in VFP. 5405 Builder.defineMacro("__ARM_NEON_FP", 5406 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5407 } 5408 5409 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5410 Opts.ShortWChar ? "2" : "4"); 5411 5412 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5413 Opts.ShortEnums ? "1" : "4"); 5414 5415 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5416 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5417 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5418 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5419 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5420 } 5421 5422 // ACLE 6.4.7 DSP instructions 5423 if (DSP) { 5424 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5425 } 5426 5427 // ACLE 6.4.8 Saturation instructions 5428 bool SAT = false; 5429 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5430 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5431 SAT = true; 5432 } 5433 5434 // ACLE 6.4.6 Q (saturation) flag 5435 if (DSP || SAT) 5436 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5437 5438 if (Opts.UnsafeFPMath) 5439 Builder.defineMacro("__ARM_FP_FAST", "1"); 5440 5441 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5442 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5443 } 5444 5445 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5446 return llvm::makeArrayRef(BuiltinInfo, 5447 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5448 } 5449 bool isCLZForZeroUndef() const override { return false; } 5450 BuiltinVaListKind getBuiltinVaListKind() const override { 5451 return IsAAPCS 5452 ? AAPCSABIBuiltinVaList 5453 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5454 : TargetInfo::VoidPtrBuiltinVaList); 5455 } 5456 ArrayRef<const char *> getGCCRegNames() const override; 5457 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5458 bool validateAsmConstraint(const char *&Name, 5459 TargetInfo::ConstraintInfo &Info) const override { 5460 switch (*Name) { 5461 default: break; 5462 case 'l': // r0-r7 5463 case 'h': // r8-r15 5464 case 't': // VFP Floating point register single precision 5465 case 'w': // VFP Floating point register double precision 5466 Info.setAllowsRegister(); 5467 return true; 5468 case 'I': 5469 case 'J': 5470 case 'K': 5471 case 'L': 5472 case 'M': 5473 // FIXME 5474 return true; 5475 case 'Q': // A memory address that is a single base register. 5476 Info.setAllowsMemory(); 5477 return true; 5478 case 'U': // a memory reference... 5479 switch (Name[1]) { 5480 case 'q': // ...ARMV4 ldrsb 5481 case 'v': // ...VFP load/store (reg+constant offset) 5482 case 'y': // ...iWMMXt load/store 5483 case 't': // address valid for load/store opaque types wider 5484 // than 128-bits 5485 case 'n': // valid address for Neon doubleword vector load/store 5486 case 'm': // valid address for Neon element and structure load/store 5487 case 's': // valid address for non-offset loads/stores of quad-word 5488 // values in four ARM registers 5489 Info.setAllowsMemory(); 5490 Name++; 5491 return true; 5492 } 5493 } 5494 return false; 5495 } 5496 std::string convertConstraint(const char *&Constraint) const override { 5497 std::string R; 5498 switch (*Constraint) { 5499 case 'U': // Two-character constraint; add "^" hint for later parsing. 5500 R = std::string("^") + std::string(Constraint, 2); 5501 Constraint++; 5502 break; 5503 case 'p': // 'p' should be translated to 'r' by default. 5504 R = std::string("r"); 5505 break; 5506 default: 5507 return std::string(1, *Constraint); 5508 } 5509 return R; 5510 } 5511 bool 5512 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5513 std::string &SuggestedModifier) const override { 5514 bool isOutput = (Constraint[0] == '='); 5515 bool isInOut = (Constraint[0] == '+'); 5516 5517 // Strip off constraint modifiers. 5518 while (Constraint[0] == '=' || 5519 Constraint[0] == '+' || 5520 Constraint[0] == '&') 5521 Constraint = Constraint.substr(1); 5522 5523 switch (Constraint[0]) { 5524 default: break; 5525 case 'r': { 5526 switch (Modifier) { 5527 default: 5528 return (isInOut || isOutput || Size <= 64); 5529 case 'q': 5530 // A register of size 32 cannot fit a vector type. 5531 return false; 5532 } 5533 } 5534 } 5535 5536 return true; 5537 } 5538 const char *getClobbers() const override { 5539 // FIXME: Is this really right? 5540 return ""; 5541 } 5542 5543 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5544 switch (CC) { 5545 case CC_AAPCS: 5546 case CC_AAPCS_VFP: 5547 case CC_Swift: 5548 return CCCR_OK; 5549 default: 5550 return CCCR_Warning; 5551 } 5552 } 5553 5554 int getEHDataRegisterNumber(unsigned RegNo) const override { 5555 if (RegNo == 0) return 0; 5556 if (RegNo == 1) return 1; 5557 return -1; 5558 } 5559 5560 bool hasSjLjLowering() const override { 5561 return true; 5562 } 5563 }; 5564 5565 bool ARMTargetInfo::setFPMath(StringRef Name) { 5566 if (Name == "neon") { 5567 FPMath = FP_Neon; 5568 return true; 5569 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5570 Name == "vfp4") { 5571 FPMath = FP_VFP; 5572 return true; 5573 } 5574 return false; 5575 } 5576 5577 const char * const ARMTargetInfo::GCCRegNames[] = { 5578 // Integer registers 5579 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5580 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5581 5582 // Float registers 5583 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5584 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5585 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5586 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5587 5588 // Double registers 5589 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5590 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5591 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5592 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5593 5594 // Quad registers 5595 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5596 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5597 }; 5598 5599 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5600 return llvm::makeArrayRef(GCCRegNames); 5601 } 5602 5603 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5604 { { "a1" }, "r0" }, 5605 { { "a2" }, "r1" }, 5606 { { "a3" }, "r2" }, 5607 { { "a4" }, "r3" }, 5608 { { "v1" }, "r4" }, 5609 { { "v2" }, "r5" }, 5610 { { "v3" }, "r6" }, 5611 { { "v4" }, "r7" }, 5612 { { "v5" }, "r8" }, 5613 { { "v6", "rfp" }, "r9" }, 5614 { { "sl" }, "r10" }, 5615 { { "fp" }, "r11" }, 5616 { { "ip" }, "r12" }, 5617 { { "r13" }, "sp" }, 5618 { { "r14" }, "lr" }, 5619 { { "r15" }, "pc" }, 5620 // The S, D and Q registers overlap, but aren't really aliases; we 5621 // don't want to substitute one of these for a different-sized one. 5622 }; 5623 5624 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5625 return llvm::makeArrayRef(GCCRegAliases); 5626 } 5627 5628 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5629 #define BUILTIN(ID, TYPE, ATTRS) \ 5630 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5631 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5632 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5633 #include "clang/Basic/BuiltinsNEON.def" 5634 5635 #define BUILTIN(ID, TYPE, ATTRS) \ 5636 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5637 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5638 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5639 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5640 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5641 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5642 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5643 #include "clang/Basic/BuiltinsARM.def" 5644 }; 5645 5646 class ARMleTargetInfo : public ARMTargetInfo { 5647 public: 5648 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5649 : ARMTargetInfo(Triple, Opts) {} 5650 void getTargetDefines(const LangOptions &Opts, 5651 MacroBuilder &Builder) const override { 5652 Builder.defineMacro("__ARMEL__"); 5653 ARMTargetInfo::getTargetDefines(Opts, Builder); 5654 } 5655 }; 5656 5657 class ARMbeTargetInfo : public ARMTargetInfo { 5658 public: 5659 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5660 : ARMTargetInfo(Triple, Opts) {} 5661 void getTargetDefines(const LangOptions &Opts, 5662 MacroBuilder &Builder) const override { 5663 Builder.defineMacro("__ARMEB__"); 5664 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5665 ARMTargetInfo::getTargetDefines(Opts, Builder); 5666 } 5667 }; 5668 5669 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5670 const llvm::Triple Triple; 5671 public: 5672 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5673 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5674 WCharType = UnsignedShort; 5675 SizeType = UnsignedInt; 5676 } 5677 void getVisualStudioDefines(const LangOptions &Opts, 5678 MacroBuilder &Builder) const { 5679 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5680 5681 // FIXME: this is invalid for WindowsCE 5682 Builder.defineMacro("_M_ARM_NT", "1"); 5683 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5684 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5685 5686 assert((Triple.getArch() == llvm::Triple::arm || 5687 Triple.getArch() == llvm::Triple::thumb) && 5688 "invalid architecture for Windows ARM target info"); 5689 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5690 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5691 5692 // TODO map the complete set of values 5693 // 31: VFPv3 40: VFPv4 5694 Builder.defineMacro("_M_ARM_FP", "31"); 5695 } 5696 BuiltinVaListKind getBuiltinVaListKind() const override { 5697 return TargetInfo::CharPtrBuiltinVaList; 5698 } 5699 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5700 switch (CC) { 5701 case CC_X86StdCall: 5702 case CC_X86ThisCall: 5703 case CC_X86FastCall: 5704 case CC_X86VectorCall: 5705 return CCCR_Ignore; 5706 case CC_C: 5707 return CCCR_OK; 5708 default: 5709 return CCCR_Warning; 5710 } 5711 } 5712 }; 5713 5714 // Windows ARM + Itanium C++ ABI Target 5715 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5716 public: 5717 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5718 const TargetOptions &Opts) 5719 : WindowsARMTargetInfo(Triple, Opts) { 5720 TheCXXABI.set(TargetCXXABI::GenericARM); 5721 } 5722 5723 void getTargetDefines(const LangOptions &Opts, 5724 MacroBuilder &Builder) const override { 5725 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5726 5727 if (Opts.MSVCCompat) 5728 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5729 } 5730 }; 5731 5732 // Windows ARM, MS (C++) ABI 5733 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5734 public: 5735 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5736 const TargetOptions &Opts) 5737 : WindowsARMTargetInfo(Triple, Opts) { 5738 TheCXXABI.set(TargetCXXABI::Microsoft); 5739 } 5740 5741 void getTargetDefines(const LangOptions &Opts, 5742 MacroBuilder &Builder) const override { 5743 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5744 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5745 } 5746 }; 5747 5748 // ARM MinGW target 5749 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5750 public: 5751 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5752 : WindowsARMTargetInfo(Triple, Opts) { 5753 TheCXXABI.set(TargetCXXABI::GenericARM); 5754 } 5755 5756 void getTargetDefines(const LangOptions &Opts, 5757 MacroBuilder &Builder) const override { 5758 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5759 DefineStd(Builder, "WIN32", Opts); 5760 DefineStd(Builder, "WINNT", Opts); 5761 Builder.defineMacro("_ARM_"); 5762 addMinGWDefines(Opts, Builder); 5763 } 5764 }; 5765 5766 // ARM Cygwin target 5767 class CygwinARMTargetInfo : public ARMleTargetInfo { 5768 public: 5769 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5770 : ARMleTargetInfo(Triple, Opts) { 5771 TLSSupported = false; 5772 WCharType = UnsignedShort; 5773 DoubleAlign = LongLongAlign = 64; 5774 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5775 } 5776 void getTargetDefines(const LangOptions &Opts, 5777 MacroBuilder &Builder) const override { 5778 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5779 Builder.defineMacro("_ARM_"); 5780 Builder.defineMacro("__CYGWIN__"); 5781 Builder.defineMacro("__CYGWIN32__"); 5782 DefineStd(Builder, "unix", Opts); 5783 if (Opts.CPlusPlus) 5784 Builder.defineMacro("_GNU_SOURCE"); 5785 } 5786 }; 5787 5788 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5789 protected: 5790 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5791 MacroBuilder &Builder) const override { 5792 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5793 } 5794 5795 public: 5796 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5797 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5798 HasAlignMac68kSupport = true; 5799 // iOS always has 64-bit atomic instructions. 5800 // FIXME: This should be based off of the target features in 5801 // ARMleTargetInfo. 5802 MaxAtomicInlineWidth = 64; 5803 5804 if (Triple.isWatchABI()) { 5805 // Darwin on iOS uses a variant of the ARM C++ ABI. 5806 TheCXXABI.set(TargetCXXABI::WatchOS); 5807 5808 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5809 // size_t is long, it's a bit weird for it to be int. 5810 PtrDiffType = SignedLong; 5811 5812 // BOOL should be a real boolean on the new ABI 5813 UseSignedCharForObjCBool = false; 5814 } else 5815 TheCXXABI.set(TargetCXXABI::iOS); 5816 } 5817 }; 5818 5819 class AArch64TargetInfo : public TargetInfo { 5820 virtual void setDataLayout() = 0; 5821 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5822 static const char *const GCCRegNames[]; 5823 5824 enum FPUModeEnum { 5825 FPUMode, 5826 NeonMode 5827 }; 5828 5829 unsigned FPU; 5830 unsigned CRC; 5831 unsigned Crypto; 5832 unsigned Unaligned; 5833 unsigned V8_1A; 5834 5835 static const Builtin::Info BuiltinInfo[]; 5836 5837 std::string ABI; 5838 5839 public: 5840 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5841 : TargetInfo(Triple), ABI("aapcs") { 5842 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5843 WCharType = SignedInt; 5844 5845 // NetBSD apparently prefers consistency across ARM targets to consistency 5846 // across 64-bit targets. 5847 Int64Type = SignedLongLong; 5848 IntMaxType = SignedLongLong; 5849 } else { 5850 WCharType = UnsignedInt; 5851 Int64Type = SignedLong; 5852 IntMaxType = SignedLong; 5853 } 5854 5855 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5856 MaxVectorAlign = 128; 5857 MaxAtomicInlineWidth = 128; 5858 MaxAtomicPromoteWidth = 128; 5859 5860 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5861 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 5862 5863 // {} in inline assembly are neon specifiers, not assembly variant 5864 // specifiers. 5865 NoAsmVariants = true; 5866 5867 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5868 // contributes to the alignment of the containing aggregate in the same way 5869 // a plain (non bit-field) member of that type would, without exception for 5870 // zero-sized or anonymous bit-fields." 5871 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5872 UseZeroLengthBitfieldAlignment = true; 5873 5874 // AArch64 targets default to using the ARM C++ ABI. 5875 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5876 5877 if (Triple.getOS() == llvm::Triple::Linux || 5878 Triple.getOS() == llvm::Triple::UnknownOS) 5879 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5880 } 5881 5882 StringRef getABI() const override { return ABI; } 5883 bool setABI(const std::string &Name) override { 5884 if (Name != "aapcs" && Name != "darwinpcs") 5885 return false; 5886 5887 ABI = Name; 5888 return true; 5889 } 5890 5891 bool setCPU(const std::string &Name) override { 5892 return Name == "generic" || 5893 llvm::AArch64::parseCPUArch(Name) != 5894 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 5895 } 5896 5897 void getTargetDefines(const LangOptions &Opts, 5898 MacroBuilder &Builder) const override { 5899 // Target identification. 5900 Builder.defineMacro("__aarch64__"); 5901 5902 // Target properties. 5903 Builder.defineMacro("_LP64"); 5904 Builder.defineMacro("__LP64__"); 5905 5906 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5907 Builder.defineMacro("__ARM_ACLE", "200"); 5908 Builder.defineMacro("__ARM_ARCH", "8"); 5909 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5910 5911 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5912 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5913 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5914 5915 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5916 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5917 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5918 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5919 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5920 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5921 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5922 5923 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5924 5925 // 0xe implies support for half, single and double precision operations. 5926 Builder.defineMacro("__ARM_FP", "0xE"); 5927 5928 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5929 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5930 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5931 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5932 5933 if (Opts.UnsafeFPMath) 5934 Builder.defineMacro("__ARM_FP_FAST", "1"); 5935 5936 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5937 5938 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5939 Opts.ShortEnums ? "1" : "4"); 5940 5941 if (FPU == NeonMode) { 5942 Builder.defineMacro("__ARM_NEON", "1"); 5943 // 64-bit NEON supports half, single and double precision operations. 5944 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5945 } 5946 5947 if (CRC) 5948 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5949 5950 if (Crypto) 5951 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5952 5953 if (Unaligned) 5954 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5955 5956 if (V8_1A) 5957 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5958 5959 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5960 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5961 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5962 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5963 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5964 } 5965 5966 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5967 return llvm::makeArrayRef(BuiltinInfo, 5968 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5969 } 5970 5971 bool hasFeature(StringRef Feature) const override { 5972 return Feature == "aarch64" || 5973 Feature == "arm64" || 5974 Feature == "arm" || 5975 (Feature == "neon" && FPU == NeonMode); 5976 } 5977 5978 bool handleTargetFeatures(std::vector<std::string> &Features, 5979 DiagnosticsEngine &Diags) override { 5980 FPU = FPUMode; 5981 CRC = 0; 5982 Crypto = 0; 5983 Unaligned = 1; 5984 V8_1A = 0; 5985 5986 for (const auto &Feature : Features) { 5987 if (Feature == "+neon") 5988 FPU = NeonMode; 5989 if (Feature == "+crc") 5990 CRC = 1; 5991 if (Feature == "+crypto") 5992 Crypto = 1; 5993 if (Feature == "+strict-align") 5994 Unaligned = 0; 5995 if (Feature == "+v8.1a") 5996 V8_1A = 1; 5997 } 5998 5999 setDataLayout(); 6000 6001 return true; 6002 } 6003 6004 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6005 switch (CC) { 6006 case CC_C: 6007 case CC_Swift: 6008 case CC_PreserveMost: 6009 case CC_PreserveAll: 6010 return CCCR_OK; 6011 default: 6012 return CCCR_Warning; 6013 } 6014 } 6015 6016 bool isCLZForZeroUndef() const override { return false; } 6017 6018 BuiltinVaListKind getBuiltinVaListKind() const override { 6019 return TargetInfo::AArch64ABIBuiltinVaList; 6020 } 6021 6022 ArrayRef<const char *> getGCCRegNames() const override; 6023 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6024 6025 bool validateAsmConstraint(const char *&Name, 6026 TargetInfo::ConstraintInfo &Info) const override { 6027 switch (*Name) { 6028 default: 6029 return false; 6030 case 'w': // Floating point and SIMD registers (V0-V31) 6031 Info.setAllowsRegister(); 6032 return true; 6033 case 'I': // Constant that can be used with an ADD instruction 6034 case 'J': // Constant that can be used with a SUB instruction 6035 case 'K': // Constant that can be used with a 32-bit logical instruction 6036 case 'L': // Constant that can be used with a 64-bit logical instruction 6037 case 'M': // Constant that can be used as a 32-bit MOV immediate 6038 case 'N': // Constant that can be used as a 64-bit MOV immediate 6039 case 'Y': // Floating point constant zero 6040 case 'Z': // Integer constant zero 6041 return true; 6042 case 'Q': // A memory reference with base register and no offset 6043 Info.setAllowsMemory(); 6044 return true; 6045 case 'S': // A symbolic address 6046 Info.setAllowsRegister(); 6047 return true; 6048 case 'U': 6049 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6050 // Utf: A memory address suitable for ldp/stp in TF mode. 6051 // Usa: An absolute symbolic address. 6052 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6053 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6054 case 'z': // Zero register, wzr or xzr 6055 Info.setAllowsRegister(); 6056 return true; 6057 case 'x': // Floating point and SIMD registers (V0-V15) 6058 Info.setAllowsRegister(); 6059 return true; 6060 } 6061 return false; 6062 } 6063 6064 bool 6065 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6066 std::string &SuggestedModifier) const override { 6067 // Strip off constraint modifiers. 6068 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6069 Constraint = Constraint.substr(1); 6070 6071 switch (Constraint[0]) { 6072 default: 6073 return true; 6074 case 'z': 6075 case 'r': { 6076 switch (Modifier) { 6077 case 'x': 6078 case 'w': 6079 // For now assume that the person knows what they're 6080 // doing with the modifier. 6081 return true; 6082 default: 6083 // By default an 'r' constraint will be in the 'x' 6084 // registers. 6085 if (Size == 64) 6086 return true; 6087 6088 SuggestedModifier = "w"; 6089 return false; 6090 } 6091 } 6092 } 6093 } 6094 6095 const char *getClobbers() const override { return ""; } 6096 6097 int getEHDataRegisterNumber(unsigned RegNo) const override { 6098 if (RegNo == 0) 6099 return 0; 6100 if (RegNo == 1) 6101 return 1; 6102 return -1; 6103 } 6104 }; 6105 6106 const char *const AArch64TargetInfo::GCCRegNames[] = { 6107 // 32-bit Integer registers 6108 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6109 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6110 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6111 6112 // 64-bit Integer registers 6113 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6114 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6115 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6116 6117 // 32-bit floating point regsisters 6118 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6119 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6120 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6121 6122 // 64-bit floating point regsisters 6123 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6124 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6125 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6126 6127 // Vector registers 6128 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6129 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6130 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6131 }; 6132 6133 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6134 return llvm::makeArrayRef(GCCRegNames); 6135 } 6136 6137 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6138 { { "w31" }, "wsp" }, 6139 { { "x29" }, "fp" }, 6140 { { "x30" }, "lr" }, 6141 { { "x31" }, "sp" }, 6142 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6143 // don't want to substitute one of these for a different-sized one. 6144 }; 6145 6146 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6147 return llvm::makeArrayRef(GCCRegAliases); 6148 } 6149 6150 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6151 #define BUILTIN(ID, TYPE, ATTRS) \ 6152 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6153 #include "clang/Basic/BuiltinsNEON.def" 6154 6155 #define BUILTIN(ID, TYPE, ATTRS) \ 6156 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6157 #include "clang/Basic/BuiltinsAArch64.def" 6158 }; 6159 6160 class AArch64leTargetInfo : public AArch64TargetInfo { 6161 void setDataLayout() override { 6162 if (getTriple().isOSBinFormatMachO()) 6163 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6164 else 6165 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6166 } 6167 6168 public: 6169 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6170 : AArch64TargetInfo(Triple, Opts) { 6171 } 6172 void getTargetDefines(const LangOptions &Opts, 6173 MacroBuilder &Builder) const override { 6174 Builder.defineMacro("__AARCH64EL__"); 6175 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6176 } 6177 }; 6178 6179 class AArch64beTargetInfo : public AArch64TargetInfo { 6180 void setDataLayout() override { 6181 assert(!getTriple().isOSBinFormatMachO()); 6182 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6183 } 6184 6185 public: 6186 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6187 : AArch64TargetInfo(Triple, Opts) {} 6188 void getTargetDefines(const LangOptions &Opts, 6189 MacroBuilder &Builder) const override { 6190 Builder.defineMacro("__AARCH64EB__"); 6191 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6192 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6193 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6194 } 6195 }; 6196 6197 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6198 protected: 6199 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6200 MacroBuilder &Builder) const override { 6201 Builder.defineMacro("__AARCH64_SIMD__"); 6202 Builder.defineMacro("__ARM64_ARCH_8__"); 6203 Builder.defineMacro("__ARM_NEON__"); 6204 Builder.defineMacro("__LITTLE_ENDIAN__"); 6205 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6206 Builder.defineMacro("__arm64", "1"); 6207 Builder.defineMacro("__arm64__", "1"); 6208 6209 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6210 } 6211 6212 public: 6213 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6214 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6215 Int64Type = SignedLongLong; 6216 WCharType = SignedInt; 6217 UseSignedCharForObjCBool = false; 6218 6219 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6220 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6221 6222 TheCXXABI.set(TargetCXXABI::iOS64); 6223 } 6224 6225 BuiltinVaListKind getBuiltinVaListKind() const override { 6226 return TargetInfo::CharPtrBuiltinVaList; 6227 } 6228 }; 6229 6230 // Hexagon abstract base class 6231 class HexagonTargetInfo : public TargetInfo { 6232 static const Builtin::Info BuiltinInfo[]; 6233 static const char * const GCCRegNames[]; 6234 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6235 std::string CPU; 6236 bool HasHVX, HasHVXDouble; 6237 bool UseLongCalls; 6238 6239 public: 6240 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6241 : TargetInfo(Triple) { 6242 // Specify the vector alignment explicitly. For v512x1, the calculated 6243 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6244 // the required minimum of 64 bytes. 6245 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6246 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6247 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6248 SizeType = UnsignedInt; 6249 PtrDiffType = SignedInt; 6250 IntPtrType = SignedInt; 6251 6252 // {} in inline assembly are packet specifiers, not assembly variant 6253 // specifiers. 6254 NoAsmVariants = true; 6255 6256 LargeArrayMinWidth = 64; 6257 LargeArrayAlign = 64; 6258 UseBitFieldTypeAlignment = true; 6259 ZeroLengthBitfieldBoundary = 32; 6260 HasHVX = HasHVXDouble = false; 6261 UseLongCalls = false; 6262 } 6263 6264 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6265 return llvm::makeArrayRef(BuiltinInfo, 6266 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6267 } 6268 6269 bool validateAsmConstraint(const char *&Name, 6270 TargetInfo::ConstraintInfo &Info) const override { 6271 switch (*Name) { 6272 case 'v': 6273 case 'q': 6274 if (HasHVX) { 6275 Info.setAllowsRegister(); 6276 return true; 6277 } 6278 break; 6279 case 's': 6280 // Relocatable constant. 6281 return true; 6282 } 6283 return false; 6284 } 6285 6286 void getTargetDefines(const LangOptions &Opts, 6287 MacroBuilder &Builder) const override; 6288 6289 bool isCLZForZeroUndef() const override { return false; } 6290 6291 bool hasFeature(StringRef Feature) const override { 6292 return llvm::StringSwitch<bool>(Feature) 6293 .Case("hexagon", true) 6294 .Case("hvx", HasHVX) 6295 .Case("hvx-double", HasHVXDouble) 6296 .Case("long-calls", UseLongCalls) 6297 .Default(false); 6298 } 6299 6300 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6301 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6302 const override; 6303 6304 bool handleTargetFeatures(std::vector<std::string> &Features, 6305 DiagnosticsEngine &Diags) override; 6306 6307 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6308 bool Enabled) const override; 6309 6310 BuiltinVaListKind getBuiltinVaListKind() const override { 6311 return TargetInfo::CharPtrBuiltinVaList; 6312 } 6313 ArrayRef<const char *> getGCCRegNames() const override; 6314 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6315 const char *getClobbers() const override { 6316 return ""; 6317 } 6318 6319 static const char *getHexagonCPUSuffix(StringRef Name) { 6320 return llvm::StringSwitch<const char*>(Name) 6321 .Case("hexagonv4", "4") 6322 .Case("hexagonv5", "5") 6323 .Case("hexagonv55", "55") 6324 .Case("hexagonv60", "60") 6325 .Default(nullptr); 6326 } 6327 6328 bool setCPU(const std::string &Name) override { 6329 if (!getHexagonCPUSuffix(Name)) 6330 return false; 6331 CPU = Name; 6332 return true; 6333 } 6334 6335 int getEHDataRegisterNumber(unsigned RegNo) const override { 6336 return RegNo < 2 ? RegNo : -1; 6337 } 6338 }; 6339 6340 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6341 MacroBuilder &Builder) const { 6342 Builder.defineMacro("__qdsp6__", "1"); 6343 Builder.defineMacro("__hexagon__", "1"); 6344 6345 if (CPU == "hexagonv4") { 6346 Builder.defineMacro("__HEXAGON_V4__"); 6347 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6348 if (Opts.HexagonQdsp6Compat) { 6349 Builder.defineMacro("__QDSP6_V4__"); 6350 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6351 } 6352 } else if (CPU == "hexagonv5") { 6353 Builder.defineMacro("__HEXAGON_V5__"); 6354 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6355 if(Opts.HexagonQdsp6Compat) { 6356 Builder.defineMacro("__QDSP6_V5__"); 6357 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6358 } 6359 } else if (CPU == "hexagonv55") { 6360 Builder.defineMacro("__HEXAGON_V55__"); 6361 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6362 Builder.defineMacro("__QDSP6_V55__"); 6363 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6364 } else if (CPU == "hexagonv60") { 6365 Builder.defineMacro("__HEXAGON_V60__"); 6366 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6367 Builder.defineMacro("__QDSP6_V60__"); 6368 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6369 } 6370 6371 if (hasFeature("hvx")) { 6372 Builder.defineMacro("__HVX__"); 6373 if (hasFeature("hvx-double")) 6374 Builder.defineMacro("__HVXDBL__"); 6375 } 6376 } 6377 6378 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6379 DiagnosticsEngine &Diags, StringRef CPU, 6380 const std::vector<std::string> &FeaturesVec) const { 6381 // Default for v60: -hvx, -hvx-double. 6382 Features["hvx"] = false; 6383 Features["hvx-double"] = false; 6384 Features["long-calls"] = false; 6385 6386 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6387 } 6388 6389 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6390 DiagnosticsEngine &Diags) { 6391 for (auto &F : Features) { 6392 if (F == "+hvx") 6393 HasHVX = true; 6394 else if (F == "-hvx") 6395 HasHVX = HasHVXDouble = false; 6396 else if (F == "+hvx-double") 6397 HasHVX = HasHVXDouble = true; 6398 else if (F == "-hvx-double") 6399 HasHVXDouble = false; 6400 6401 if (F == "+long-calls") 6402 UseLongCalls = true; 6403 else if (F == "-long-calls") 6404 UseLongCalls = false; 6405 } 6406 return true; 6407 } 6408 6409 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6410 StringRef Name, bool Enabled) const { 6411 if (Enabled) { 6412 if (Name == "hvx-double") 6413 Features["hvx"] = true; 6414 } else { 6415 if (Name == "hvx") 6416 Features["hvx-double"] = false; 6417 } 6418 Features[Name] = Enabled; 6419 } 6420 6421 const char *const HexagonTargetInfo::GCCRegNames[] = { 6422 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6423 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6424 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6425 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6426 "p0", "p1", "p2", "p3", 6427 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6428 }; 6429 6430 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6431 return llvm::makeArrayRef(GCCRegNames); 6432 } 6433 6434 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6435 { { "sp" }, "r29" }, 6436 { { "fp" }, "r30" }, 6437 { { "lr" }, "r31" }, 6438 }; 6439 6440 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6441 return llvm::makeArrayRef(GCCRegAliases); 6442 } 6443 6444 6445 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6446 #define BUILTIN(ID, TYPE, ATTRS) \ 6447 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6448 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6449 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6450 #include "clang/Basic/BuiltinsHexagon.def" 6451 }; 6452 6453 class LanaiTargetInfo : public TargetInfo { 6454 // Class for Lanai (32-bit). 6455 // The CPU profiles supported by the Lanai backend 6456 enum CPUKind { 6457 CK_NONE, 6458 CK_V11, 6459 } CPU; 6460 6461 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6462 static const char *const GCCRegNames[]; 6463 6464 public: 6465 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6466 : TargetInfo(Triple) { 6467 // Description string has to be kept in sync with backend. 6468 resetDataLayout("E" // Big endian 6469 "-m:e" // ELF name manging 6470 "-p:32:32" // 32 bit pointers, 32 bit aligned 6471 "-i64:64" // 64 bit integers, 64 bit aligned 6472 "-a:0:32" // 32 bit alignment of objects of aggregate type 6473 "-n32" // 32 bit native integer width 6474 "-S64" // 64 bit natural stack alignment 6475 ); 6476 6477 // Setting RegParmMax equal to what mregparm was set to in the old 6478 // toolchain 6479 RegParmMax = 4; 6480 6481 // Set the default CPU to V11 6482 CPU = CK_V11; 6483 6484 // Temporary approach to make everything at least word-aligned and allow for 6485 // safely casting between pointers with different alignment requirements. 6486 // TODO: Remove this when there are no more cast align warnings on the 6487 // firmware. 6488 MinGlobalAlign = 32; 6489 } 6490 6491 void getTargetDefines(const LangOptions &Opts, 6492 MacroBuilder &Builder) const override { 6493 // Define __lanai__ when building for target lanai. 6494 Builder.defineMacro("__lanai__"); 6495 6496 // Set define for the CPU specified. 6497 switch (CPU) { 6498 case CK_V11: 6499 Builder.defineMacro("__LANAI_V11__"); 6500 break; 6501 case CK_NONE: 6502 llvm_unreachable("Unhandled target CPU"); 6503 } 6504 } 6505 6506 bool setCPU(const std::string &Name) override { 6507 CPU = llvm::StringSwitch<CPUKind>(Name) 6508 .Case("v11", CK_V11) 6509 .Default(CK_NONE); 6510 6511 return CPU != CK_NONE; 6512 } 6513 6514 bool hasFeature(StringRef Feature) const override { 6515 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6516 } 6517 6518 ArrayRef<const char *> getGCCRegNames() const override; 6519 6520 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6521 6522 BuiltinVaListKind getBuiltinVaListKind() const override { 6523 return TargetInfo::VoidPtrBuiltinVaList; 6524 } 6525 6526 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6527 6528 bool validateAsmConstraint(const char *&Name, 6529 TargetInfo::ConstraintInfo &info) const override { 6530 return false; 6531 } 6532 6533 const char *getClobbers() const override { return ""; } 6534 }; 6535 6536 const char *const LanaiTargetInfo::GCCRegNames[] = { 6537 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6538 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6539 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6540 6541 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6542 return llvm::makeArrayRef(GCCRegNames); 6543 } 6544 6545 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6546 {{"pc"}, "r2"}, 6547 {{"sp"}, "r4"}, 6548 {{"fp"}, "r5"}, 6549 {{"rv"}, "r8"}, 6550 {{"rr1"}, "r10"}, 6551 {{"rr2"}, "r11"}, 6552 {{"rca"}, "r15"}, 6553 }; 6554 6555 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6556 return llvm::makeArrayRef(GCCRegAliases); 6557 } 6558 6559 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6560 class SparcTargetInfo : public TargetInfo { 6561 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6562 static const char * const GCCRegNames[]; 6563 bool SoftFloat; 6564 public: 6565 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6566 : TargetInfo(Triple), SoftFloat(false) {} 6567 6568 int getEHDataRegisterNumber(unsigned RegNo) const override { 6569 if (RegNo == 0) return 24; 6570 if (RegNo == 1) return 25; 6571 return -1; 6572 } 6573 6574 bool handleTargetFeatures(std::vector<std::string> &Features, 6575 DiagnosticsEngine &Diags) override { 6576 // Check if software floating point is enabled 6577 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6578 if (Feature != Features.end()) { 6579 SoftFloat = true; 6580 } 6581 return true; 6582 } 6583 void getTargetDefines(const LangOptions &Opts, 6584 MacroBuilder &Builder) const override { 6585 DefineStd(Builder, "sparc", Opts); 6586 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6587 6588 if (SoftFloat) 6589 Builder.defineMacro("SOFT_FLOAT", "1"); 6590 } 6591 6592 bool hasFeature(StringRef Feature) const override { 6593 return llvm::StringSwitch<bool>(Feature) 6594 .Case("softfloat", SoftFloat) 6595 .Case("sparc", true) 6596 .Default(false); 6597 } 6598 6599 bool hasSjLjLowering() const override { 6600 return true; 6601 } 6602 6603 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6604 // FIXME: Implement! 6605 return None; 6606 } 6607 BuiltinVaListKind getBuiltinVaListKind() const override { 6608 return TargetInfo::VoidPtrBuiltinVaList; 6609 } 6610 ArrayRef<const char *> getGCCRegNames() const override; 6611 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6612 bool validateAsmConstraint(const char *&Name, 6613 TargetInfo::ConstraintInfo &info) const override { 6614 // FIXME: Implement! 6615 switch (*Name) { 6616 case 'I': // Signed 13-bit constant 6617 case 'J': // Zero 6618 case 'K': // 32-bit constant with the low 12 bits clear 6619 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6620 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6621 case 'N': // Same as 'K' but zext (required for SIMode) 6622 case 'O': // The constant 4096 6623 return true; 6624 } 6625 return false; 6626 } 6627 const char *getClobbers() const override { 6628 // FIXME: Implement! 6629 return ""; 6630 } 6631 6632 // No Sparc V7 for now, the backend doesn't support it anyway. 6633 enum CPUKind { 6634 CK_GENERIC, 6635 CK_V8, 6636 CK_SUPERSPARC, 6637 CK_SPARCLITE, 6638 CK_F934, 6639 CK_HYPERSPARC, 6640 CK_SPARCLITE86X, 6641 CK_SPARCLET, 6642 CK_TSC701, 6643 CK_V9, 6644 CK_ULTRASPARC, 6645 CK_ULTRASPARC3, 6646 CK_NIAGARA, 6647 CK_NIAGARA2, 6648 CK_NIAGARA3, 6649 CK_NIAGARA4, 6650 CK_MYRIAD2100, 6651 CK_MYRIAD2150, 6652 CK_MYRIAD2450, 6653 CK_LEON2, 6654 CK_LEON2_AT697E, 6655 CK_LEON2_AT697F, 6656 CK_LEON3, 6657 CK_LEON3_UT699, 6658 CK_LEON3_GR712RC, 6659 CK_LEON4, 6660 CK_LEON4_GR740 6661 } CPU = CK_GENERIC; 6662 6663 enum CPUGeneration { 6664 CG_V8, 6665 CG_V9, 6666 }; 6667 6668 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6669 switch (Kind) { 6670 case CK_GENERIC: 6671 case CK_V8: 6672 case CK_SUPERSPARC: 6673 case CK_SPARCLITE: 6674 case CK_F934: 6675 case CK_HYPERSPARC: 6676 case CK_SPARCLITE86X: 6677 case CK_SPARCLET: 6678 case CK_TSC701: 6679 case CK_MYRIAD2100: 6680 case CK_MYRIAD2150: 6681 case CK_MYRIAD2450: 6682 case CK_LEON2: 6683 case CK_LEON2_AT697E: 6684 case CK_LEON2_AT697F: 6685 case CK_LEON3: 6686 case CK_LEON3_UT699: 6687 case CK_LEON3_GR712RC: 6688 case CK_LEON4: 6689 case CK_LEON4_GR740: 6690 return CG_V8; 6691 case CK_V9: 6692 case CK_ULTRASPARC: 6693 case CK_ULTRASPARC3: 6694 case CK_NIAGARA: 6695 case CK_NIAGARA2: 6696 case CK_NIAGARA3: 6697 case CK_NIAGARA4: 6698 return CG_V9; 6699 } 6700 llvm_unreachable("Unexpected CPU kind"); 6701 } 6702 6703 CPUKind getCPUKind(StringRef Name) const { 6704 return llvm::StringSwitch<CPUKind>(Name) 6705 .Case("v8", CK_V8) 6706 .Case("supersparc", CK_SUPERSPARC) 6707 .Case("sparclite", CK_SPARCLITE) 6708 .Case("f934", CK_F934) 6709 .Case("hypersparc", CK_HYPERSPARC) 6710 .Case("sparclite86x", CK_SPARCLITE86X) 6711 .Case("sparclet", CK_SPARCLET) 6712 .Case("tsc701", CK_TSC701) 6713 .Case("v9", CK_V9) 6714 .Case("ultrasparc", CK_ULTRASPARC) 6715 .Case("ultrasparc3", CK_ULTRASPARC3) 6716 .Case("niagara", CK_NIAGARA) 6717 .Case("niagara2", CK_NIAGARA2) 6718 .Case("niagara3", CK_NIAGARA3) 6719 .Case("niagara4", CK_NIAGARA4) 6720 .Case("ma2100", CK_MYRIAD2100) 6721 .Case("ma2150", CK_MYRIAD2150) 6722 .Case("ma2450", CK_MYRIAD2450) 6723 // FIXME: the myriad2[.n] spellings are obsolete, 6724 // but a grace period is needed to allow updating dependent builds. 6725 .Case("myriad2", CK_MYRIAD2100) 6726 .Case("myriad2.1", CK_MYRIAD2100) 6727 .Case("myriad2.2", CK_MYRIAD2150) 6728 .Case("leon2", CK_LEON2) 6729 .Case("at697e", CK_LEON2_AT697E) 6730 .Case("at697f", CK_LEON2_AT697F) 6731 .Case("leon3", CK_LEON3) 6732 .Case("ut699", CK_LEON3_UT699) 6733 .Case("gr712rc", CK_LEON3_GR712RC) 6734 .Case("leon4", CK_LEON4) 6735 .Case("gr740", CK_LEON4_GR740) 6736 .Default(CK_GENERIC); 6737 } 6738 6739 bool setCPU(const std::string &Name) override { 6740 CPU = getCPUKind(Name); 6741 return CPU != CK_GENERIC; 6742 } 6743 }; 6744 6745 const char * const SparcTargetInfo::GCCRegNames[] = { 6746 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6747 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6748 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6749 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6750 }; 6751 6752 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6753 return llvm::makeArrayRef(GCCRegNames); 6754 } 6755 6756 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6757 { { "g0" }, "r0" }, 6758 { { "g1" }, "r1" }, 6759 { { "g2" }, "r2" }, 6760 { { "g3" }, "r3" }, 6761 { { "g4" }, "r4" }, 6762 { { "g5" }, "r5" }, 6763 { { "g6" }, "r6" }, 6764 { { "g7" }, "r7" }, 6765 { { "o0" }, "r8" }, 6766 { { "o1" }, "r9" }, 6767 { { "o2" }, "r10" }, 6768 { { "o3" }, "r11" }, 6769 { { "o4" }, "r12" }, 6770 { { "o5" }, "r13" }, 6771 { { "o6", "sp" }, "r14" }, 6772 { { "o7" }, "r15" }, 6773 { { "l0" }, "r16" }, 6774 { { "l1" }, "r17" }, 6775 { { "l2" }, "r18" }, 6776 { { "l3" }, "r19" }, 6777 { { "l4" }, "r20" }, 6778 { { "l5" }, "r21" }, 6779 { { "l6" }, "r22" }, 6780 { { "l7" }, "r23" }, 6781 { { "i0" }, "r24" }, 6782 { { "i1" }, "r25" }, 6783 { { "i2" }, "r26" }, 6784 { { "i3" }, "r27" }, 6785 { { "i4" }, "r28" }, 6786 { { "i5" }, "r29" }, 6787 { { "i6", "fp" }, "r30" }, 6788 { { "i7" }, "r31" }, 6789 }; 6790 6791 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6792 return llvm::makeArrayRef(GCCRegAliases); 6793 } 6794 6795 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6796 class SparcV8TargetInfo : public SparcTargetInfo { 6797 public: 6798 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6799 : SparcTargetInfo(Triple, Opts) { 6800 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6801 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6802 switch (getTriple().getOS()) { 6803 default: 6804 SizeType = UnsignedInt; 6805 IntPtrType = SignedInt; 6806 PtrDiffType = SignedInt; 6807 break; 6808 case llvm::Triple::NetBSD: 6809 case llvm::Triple::OpenBSD: 6810 SizeType = UnsignedLong; 6811 IntPtrType = SignedLong; 6812 PtrDiffType = SignedLong; 6813 break; 6814 } 6815 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 6816 // on up to 64 bits. 6817 MaxAtomicPromoteWidth = 64; 6818 MaxAtomicInlineWidth = 32; 6819 } 6820 6821 void getTargetDefines(const LangOptions &Opts, 6822 MacroBuilder &Builder) const override { 6823 SparcTargetInfo::getTargetDefines(Opts, Builder); 6824 switch (getCPUGeneration(CPU)) { 6825 case CG_V8: 6826 Builder.defineMacro("__sparcv8"); 6827 if (getTriple().getOS() != llvm::Triple::Solaris) 6828 Builder.defineMacro("__sparcv8__"); 6829 break; 6830 case CG_V9: 6831 Builder.defineMacro("__sparcv9"); 6832 if (getTriple().getOS() != llvm::Triple::Solaris) { 6833 Builder.defineMacro("__sparcv9__"); 6834 Builder.defineMacro("__sparc_v9__"); 6835 } 6836 break; 6837 } 6838 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6839 std::string MyriadArchValue, Myriad2Value; 6840 Builder.defineMacro("__sparc_v8__"); 6841 Builder.defineMacro("__leon__"); 6842 switch (CPU) { 6843 case CK_MYRIAD2150: 6844 MyriadArchValue = "__ma2150"; 6845 Myriad2Value = "2"; 6846 break; 6847 case CK_MYRIAD2450: 6848 MyriadArchValue = "__ma2450"; 6849 Myriad2Value = "2"; 6850 break; 6851 default: 6852 MyriadArchValue = "__ma2100"; 6853 Myriad2Value = "1"; 6854 break; 6855 } 6856 Builder.defineMacro(MyriadArchValue, "1"); 6857 Builder.defineMacro(MyriadArchValue+"__", "1"); 6858 Builder.defineMacro("__myriad2__", Myriad2Value); 6859 Builder.defineMacro("__myriad2", Myriad2Value); 6860 } 6861 } 6862 6863 bool hasSjLjLowering() const override { 6864 return true; 6865 } 6866 }; 6867 6868 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6869 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6870 public: 6871 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6872 : SparcV8TargetInfo(Triple, Opts) { 6873 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6874 } 6875 }; 6876 6877 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6878 class SparcV9TargetInfo : public SparcTargetInfo { 6879 public: 6880 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6881 : SparcTargetInfo(Triple, Opts) { 6882 // FIXME: Support Sparc quad-precision long double? 6883 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6884 // This is an LP64 platform. 6885 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6886 6887 // OpenBSD uses long long for int64_t and intmax_t. 6888 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6889 IntMaxType = SignedLongLong; 6890 else 6891 IntMaxType = SignedLong; 6892 Int64Type = IntMaxType; 6893 6894 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6895 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6896 LongDoubleWidth = 128; 6897 LongDoubleAlign = 128; 6898 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6899 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6900 } 6901 6902 void getTargetDefines(const LangOptions &Opts, 6903 MacroBuilder &Builder) const override { 6904 SparcTargetInfo::getTargetDefines(Opts, Builder); 6905 Builder.defineMacro("__sparcv9"); 6906 Builder.defineMacro("__arch64__"); 6907 // Solaris doesn't need these variants, but the BSDs do. 6908 if (getTriple().getOS() != llvm::Triple::Solaris) { 6909 Builder.defineMacro("__sparc64__"); 6910 Builder.defineMacro("__sparc_v9__"); 6911 Builder.defineMacro("__sparcv9__"); 6912 } 6913 } 6914 6915 bool setCPU(const std::string &Name) override { 6916 if (!SparcTargetInfo::setCPU(Name)) 6917 return false; 6918 return getCPUGeneration(CPU) == CG_V9; 6919 } 6920 }; 6921 6922 class SystemZTargetInfo : public TargetInfo { 6923 static const Builtin::Info BuiltinInfo[]; 6924 static const char *const GCCRegNames[]; 6925 std::string CPU; 6926 bool HasTransactionalExecution; 6927 bool HasVector; 6928 6929 public: 6930 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6931 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6932 HasVector(false) { 6933 IntMaxType = SignedLong; 6934 Int64Type = SignedLong; 6935 TLSSupported = true; 6936 IntWidth = IntAlign = 32; 6937 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6938 PointerWidth = PointerAlign = 64; 6939 LongDoubleWidth = 128; 6940 LongDoubleAlign = 64; 6941 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6942 DefaultAlignForAttributeAligned = 64; 6943 MinGlobalAlign = 16; 6944 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6945 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6946 } 6947 void getTargetDefines(const LangOptions &Opts, 6948 MacroBuilder &Builder) const override { 6949 Builder.defineMacro("__s390__"); 6950 Builder.defineMacro("__s390x__"); 6951 Builder.defineMacro("__zarch__"); 6952 Builder.defineMacro("__LONG_DOUBLE_128__"); 6953 6954 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6955 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6956 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6957 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6958 6959 if (HasTransactionalExecution) 6960 Builder.defineMacro("__HTM__"); 6961 if (Opts.ZVector) 6962 Builder.defineMacro("__VEC__", "10301"); 6963 } 6964 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6965 return llvm::makeArrayRef(BuiltinInfo, 6966 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6967 } 6968 6969 ArrayRef<const char *> getGCCRegNames() const override; 6970 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6971 // No aliases. 6972 return None; 6973 } 6974 bool validateAsmConstraint(const char *&Name, 6975 TargetInfo::ConstraintInfo &info) const override; 6976 const char *getClobbers() const override { 6977 // FIXME: Is this really right? 6978 return ""; 6979 } 6980 BuiltinVaListKind getBuiltinVaListKind() const override { 6981 return TargetInfo::SystemZBuiltinVaList; 6982 } 6983 bool setCPU(const std::string &Name) override { 6984 CPU = Name; 6985 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6986 .Case("z10", true) 6987 .Case("arch8", true) 6988 .Case("z196", true) 6989 .Case("arch9", true) 6990 .Case("zEC12", true) 6991 .Case("arch10", true) 6992 .Case("z13", true) 6993 .Case("arch11", true) 6994 .Default(false); 6995 6996 return CPUKnown; 6997 } 6998 bool 6999 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7000 StringRef CPU, 7001 const std::vector<std::string> &FeaturesVec) const override { 7002 if (CPU == "zEC12" || CPU == "arch10") 7003 Features["transactional-execution"] = true; 7004 if (CPU == "z13" || CPU == "arch11") { 7005 Features["transactional-execution"] = true; 7006 Features["vector"] = true; 7007 } 7008 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7009 } 7010 7011 bool handleTargetFeatures(std::vector<std::string> &Features, 7012 DiagnosticsEngine &Diags) override { 7013 HasTransactionalExecution = false; 7014 for (const auto &Feature : Features) { 7015 if (Feature == "+transactional-execution") 7016 HasTransactionalExecution = true; 7017 else if (Feature == "+vector") 7018 HasVector = true; 7019 } 7020 // If we use the vector ABI, vector types are 64-bit aligned. 7021 if (HasVector) { 7022 MaxVectorAlign = 64; 7023 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7024 "-v128:64-a:8:16-n32:64"); 7025 } 7026 return true; 7027 } 7028 7029 bool hasFeature(StringRef Feature) const override { 7030 return llvm::StringSwitch<bool>(Feature) 7031 .Case("systemz", true) 7032 .Case("htm", HasTransactionalExecution) 7033 .Case("vx", HasVector) 7034 .Default(false); 7035 } 7036 7037 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7038 switch (CC) { 7039 case CC_C: 7040 case CC_Swift: 7041 return CCCR_OK; 7042 default: 7043 return CCCR_Warning; 7044 } 7045 } 7046 7047 StringRef getABI() const override { 7048 if (HasVector) 7049 return "vector"; 7050 return ""; 7051 } 7052 7053 bool useFloat128ManglingForLongDouble() const override { 7054 return true; 7055 } 7056 }; 7057 7058 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7059 #define BUILTIN(ID, TYPE, ATTRS) \ 7060 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7061 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7062 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7063 #include "clang/Basic/BuiltinsSystemZ.def" 7064 }; 7065 7066 const char *const SystemZTargetInfo::GCCRegNames[] = { 7067 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7068 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7069 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7070 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7071 }; 7072 7073 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7074 return llvm::makeArrayRef(GCCRegNames); 7075 } 7076 7077 bool SystemZTargetInfo:: 7078 validateAsmConstraint(const char *&Name, 7079 TargetInfo::ConstraintInfo &Info) const { 7080 switch (*Name) { 7081 default: 7082 return false; 7083 7084 case 'a': // Address register 7085 case 'd': // Data register (equivalent to 'r') 7086 case 'f': // Floating-point register 7087 Info.setAllowsRegister(); 7088 return true; 7089 7090 case 'I': // Unsigned 8-bit constant 7091 case 'J': // Unsigned 12-bit constant 7092 case 'K': // Signed 16-bit constant 7093 case 'L': // Signed 20-bit displacement (on all targets we support) 7094 case 'M': // 0x7fffffff 7095 return true; 7096 7097 case 'Q': // Memory with base and unsigned 12-bit displacement 7098 case 'R': // Likewise, plus an index 7099 case 'S': // Memory with base and signed 20-bit displacement 7100 case 'T': // Likewise, plus an index 7101 Info.setAllowsMemory(); 7102 return true; 7103 } 7104 } 7105 7106 class MSP430TargetInfo : public TargetInfo { 7107 static const char *const GCCRegNames[]; 7108 7109 public: 7110 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7111 : TargetInfo(Triple) { 7112 TLSSupported = false; 7113 IntWidth = 16; 7114 IntAlign = 16; 7115 LongWidth = 32; 7116 LongLongWidth = 64; 7117 LongAlign = LongLongAlign = 16; 7118 PointerWidth = 16; 7119 PointerAlign = 16; 7120 SuitableAlign = 16; 7121 SizeType = UnsignedInt; 7122 IntMaxType = SignedLongLong; 7123 IntPtrType = SignedInt; 7124 PtrDiffType = SignedInt; 7125 SigAtomicType = SignedLong; 7126 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7127 } 7128 void getTargetDefines(const LangOptions &Opts, 7129 MacroBuilder &Builder) const override { 7130 Builder.defineMacro("MSP430"); 7131 Builder.defineMacro("__MSP430__"); 7132 // FIXME: defines for different 'flavours' of MCU 7133 } 7134 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7135 // FIXME: Implement. 7136 return None; 7137 } 7138 bool hasFeature(StringRef Feature) const override { 7139 return Feature == "msp430"; 7140 } 7141 ArrayRef<const char *> getGCCRegNames() const override; 7142 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7143 // No aliases. 7144 return None; 7145 } 7146 bool validateAsmConstraint(const char *&Name, 7147 TargetInfo::ConstraintInfo &info) const override { 7148 // FIXME: implement 7149 switch (*Name) { 7150 case 'K': // the constant 1 7151 case 'L': // constant -1^20 .. 1^19 7152 case 'M': // constant 1-4: 7153 return true; 7154 } 7155 // No target constraints for now. 7156 return false; 7157 } 7158 const char *getClobbers() const override { 7159 // FIXME: Is this really right? 7160 return ""; 7161 } 7162 BuiltinVaListKind getBuiltinVaListKind() const override { 7163 // FIXME: implement 7164 return TargetInfo::CharPtrBuiltinVaList; 7165 } 7166 }; 7167 7168 const char *const MSP430TargetInfo::GCCRegNames[] = { 7169 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7170 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7171 7172 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7173 return llvm::makeArrayRef(GCCRegNames); 7174 } 7175 7176 // LLVM and Clang cannot be used directly to output native binaries for 7177 // target, but is used to compile C code to llvm bitcode with correct 7178 // type and alignment information. 7179 // 7180 // TCE uses the llvm bitcode as input and uses it for generating customized 7181 // target processor and program binary. TCE co-design environment is 7182 // publicly available in http://tce.cs.tut.fi 7183 7184 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7185 3, // opencl_global 7186 4, // opencl_local 7187 5, // opencl_constant 7188 // FIXME: generic has to be added to the target 7189 0, // opencl_generic 7190 0, // cuda_device 7191 0, // cuda_constant 7192 0 // cuda_shared 7193 }; 7194 7195 class TCETargetInfo : public TargetInfo { 7196 public: 7197 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7198 : TargetInfo(Triple) { 7199 TLSSupported = false; 7200 IntWidth = 32; 7201 LongWidth = LongLongWidth = 32; 7202 PointerWidth = 32; 7203 IntAlign = 32; 7204 LongAlign = LongLongAlign = 32; 7205 PointerAlign = 32; 7206 SuitableAlign = 32; 7207 SizeType = UnsignedInt; 7208 IntMaxType = SignedLong; 7209 IntPtrType = SignedInt; 7210 PtrDiffType = SignedInt; 7211 FloatWidth = 32; 7212 FloatAlign = 32; 7213 DoubleWidth = 32; 7214 DoubleAlign = 32; 7215 LongDoubleWidth = 32; 7216 LongDoubleAlign = 32; 7217 FloatFormat = &llvm::APFloat::IEEEsingle(); 7218 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7219 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7220 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7221 "i16:16:32-i32:32:32-i64:32:32-" 7222 "f32:32:32-f64:32:32-v64:32:32-" 7223 "v128:32:32-v256:32:32-v512:32:32-" 7224 "v1024:32:32-a0:0:32-n32"); 7225 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7226 UseAddrSpaceMapMangling = true; 7227 } 7228 7229 void getTargetDefines(const LangOptions &Opts, 7230 MacroBuilder &Builder) const override { 7231 DefineStd(Builder, "tce", Opts); 7232 Builder.defineMacro("__TCE__"); 7233 Builder.defineMacro("__TCE_V1__"); 7234 } 7235 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7236 7237 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7238 const char *getClobbers() const override { return ""; } 7239 BuiltinVaListKind getBuiltinVaListKind() const override { 7240 return TargetInfo::VoidPtrBuiltinVaList; 7241 } 7242 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7243 bool validateAsmConstraint(const char *&Name, 7244 TargetInfo::ConstraintInfo &info) const override { 7245 return true; 7246 } 7247 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7248 return None; 7249 } 7250 }; 7251 7252 class TCELETargetInfo : public TCETargetInfo { 7253 public: 7254 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7255 : TCETargetInfo(Triple, Opts) { 7256 BigEndian = false; 7257 7258 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7259 "i16:16:32-i32:32:32-i64:32:32-" 7260 "f32:32:32-f64:32:32-v64:32:32-" 7261 "v128:32:32-v256:32:32-v512:32:32-" 7262 "v1024:32:32-a0:0:32-n32"); 7263 7264 } 7265 7266 virtual void getTargetDefines(const LangOptions &Opts, 7267 MacroBuilder &Builder) const { 7268 DefineStd(Builder, "tcele", Opts); 7269 Builder.defineMacro("__TCE__"); 7270 Builder.defineMacro("__TCE_V1__"); 7271 Builder.defineMacro("__TCELE__"); 7272 Builder.defineMacro("__TCELE_V1__"); 7273 } 7274 7275 }; 7276 7277 class BPFTargetInfo : public TargetInfo { 7278 public: 7279 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7280 : TargetInfo(Triple) { 7281 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7282 SizeType = UnsignedLong; 7283 PtrDiffType = SignedLong; 7284 IntPtrType = SignedLong; 7285 IntMaxType = SignedLong; 7286 Int64Type = SignedLong; 7287 RegParmMax = 5; 7288 if (Triple.getArch() == llvm::Triple::bpfeb) { 7289 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7290 } else { 7291 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7292 } 7293 MaxAtomicPromoteWidth = 64; 7294 MaxAtomicInlineWidth = 64; 7295 TLSSupported = false; 7296 } 7297 void getTargetDefines(const LangOptions &Opts, 7298 MacroBuilder &Builder) const override { 7299 DefineStd(Builder, "bpf", Opts); 7300 Builder.defineMacro("__BPF__"); 7301 } 7302 bool hasFeature(StringRef Feature) const override { 7303 return Feature == "bpf"; 7304 } 7305 7306 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7307 const char *getClobbers() const override { 7308 return ""; 7309 } 7310 BuiltinVaListKind getBuiltinVaListKind() const override { 7311 return TargetInfo::VoidPtrBuiltinVaList; 7312 } 7313 ArrayRef<const char *> getGCCRegNames() const override { 7314 return None; 7315 } 7316 bool validateAsmConstraint(const char *&Name, 7317 TargetInfo::ConstraintInfo &info) const override { 7318 return true; 7319 } 7320 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7321 return None; 7322 } 7323 }; 7324 7325 class MipsTargetInfo : public TargetInfo { 7326 void setDataLayout() { 7327 StringRef Layout; 7328 7329 if (ABI == "o32") 7330 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7331 else if (ABI == "n32") 7332 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7333 else if (ABI == "n64") 7334 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7335 else 7336 llvm_unreachable("Invalid ABI"); 7337 7338 if (BigEndian) 7339 resetDataLayout(("E-" + Layout).str()); 7340 else 7341 resetDataLayout(("e-" + Layout).str()); 7342 } 7343 7344 7345 static const Builtin::Info BuiltinInfo[]; 7346 std::string CPU; 7347 bool IsMips16; 7348 bool IsMicromips; 7349 bool IsNan2008; 7350 bool IsSingleFloat; 7351 enum MipsFloatABI { 7352 HardFloat, SoftFloat 7353 } FloatABI; 7354 enum DspRevEnum { 7355 NoDSP, DSP1, DSP2 7356 } DspRev; 7357 bool HasMSA; 7358 7359 protected: 7360 bool HasFP64; 7361 std::string ABI; 7362 7363 public: 7364 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7365 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7366 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7367 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7368 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7369 7370 setABI((getTriple().getArch() == llvm::Triple::mips || 7371 getTriple().getArch() == llvm::Triple::mipsel) 7372 ? "o32" 7373 : "n64"); 7374 7375 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7376 } 7377 7378 bool isNaN2008Default() const { 7379 return CPU == "mips32r6" || CPU == "mips64r6"; 7380 } 7381 7382 bool isFP64Default() const { 7383 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7384 } 7385 7386 bool isNan2008() const override { 7387 return IsNan2008; 7388 } 7389 7390 bool processorSupportsGPR64() const { 7391 return llvm::StringSwitch<bool>(CPU) 7392 .Case("mips3", true) 7393 .Case("mips4", true) 7394 .Case("mips5", true) 7395 .Case("mips64", true) 7396 .Case("mips64r2", true) 7397 .Case("mips64r3", true) 7398 .Case("mips64r5", true) 7399 .Case("mips64r6", true) 7400 .Case("octeon", true) 7401 .Default(false); 7402 return false; 7403 } 7404 7405 StringRef getABI() const override { return ABI; } 7406 bool setABI(const std::string &Name) override { 7407 if (Name == "o32") { 7408 setO32ABITypes(); 7409 ABI = Name; 7410 return true; 7411 } 7412 7413 if (Name == "n32") { 7414 setN32ABITypes(); 7415 ABI = Name; 7416 return true; 7417 } 7418 if (Name == "n64") { 7419 setN64ABITypes(); 7420 ABI = Name; 7421 return true; 7422 } 7423 return false; 7424 } 7425 7426 void setO32ABITypes() { 7427 Int64Type = SignedLongLong; 7428 IntMaxType = Int64Type; 7429 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7430 LongDoubleWidth = LongDoubleAlign = 64; 7431 LongWidth = LongAlign = 32; 7432 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7433 PointerWidth = PointerAlign = 32; 7434 PtrDiffType = SignedInt; 7435 SizeType = UnsignedInt; 7436 SuitableAlign = 64; 7437 } 7438 7439 void setN32N64ABITypes() { 7440 LongDoubleWidth = LongDoubleAlign = 128; 7441 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7442 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7443 LongDoubleWidth = LongDoubleAlign = 64; 7444 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7445 } 7446 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7447 SuitableAlign = 128; 7448 } 7449 7450 void setN64ABITypes() { 7451 setN32N64ABITypes(); 7452 Int64Type = SignedLong; 7453 IntMaxType = Int64Type; 7454 LongWidth = LongAlign = 64; 7455 PointerWidth = PointerAlign = 64; 7456 PtrDiffType = SignedLong; 7457 SizeType = UnsignedLong; 7458 } 7459 7460 void setN32ABITypes() { 7461 setN32N64ABITypes(); 7462 Int64Type = SignedLongLong; 7463 IntMaxType = Int64Type; 7464 LongWidth = LongAlign = 32; 7465 PointerWidth = PointerAlign = 32; 7466 PtrDiffType = SignedInt; 7467 SizeType = UnsignedInt; 7468 } 7469 7470 bool setCPU(const std::string &Name) override { 7471 CPU = Name; 7472 return llvm::StringSwitch<bool>(Name) 7473 .Case("mips1", true) 7474 .Case("mips2", true) 7475 .Case("mips3", true) 7476 .Case("mips4", true) 7477 .Case("mips5", true) 7478 .Case("mips32", true) 7479 .Case("mips32r2", true) 7480 .Case("mips32r3", true) 7481 .Case("mips32r5", true) 7482 .Case("mips32r6", true) 7483 .Case("mips64", true) 7484 .Case("mips64r2", true) 7485 .Case("mips64r3", true) 7486 .Case("mips64r5", true) 7487 .Case("mips64r6", true) 7488 .Case("octeon", true) 7489 .Case("p5600", true) 7490 .Default(false); 7491 } 7492 const std::string& getCPU() const { return CPU; } 7493 bool 7494 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7495 StringRef CPU, 7496 const std::vector<std::string> &FeaturesVec) const override { 7497 if (CPU.empty()) 7498 CPU = getCPU(); 7499 if (CPU == "octeon") 7500 Features["mips64r2"] = Features["cnmips"] = true; 7501 else 7502 Features[CPU] = true; 7503 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7504 } 7505 7506 void getTargetDefines(const LangOptions &Opts, 7507 MacroBuilder &Builder) const override { 7508 if (BigEndian) { 7509 DefineStd(Builder, "MIPSEB", Opts); 7510 Builder.defineMacro("_MIPSEB"); 7511 } else { 7512 DefineStd(Builder, "MIPSEL", Opts); 7513 Builder.defineMacro("_MIPSEL"); 7514 } 7515 7516 Builder.defineMacro("__mips__"); 7517 Builder.defineMacro("_mips"); 7518 if (Opts.GNUMode) 7519 Builder.defineMacro("mips"); 7520 7521 if (ABI == "o32") { 7522 Builder.defineMacro("__mips", "32"); 7523 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7524 } else { 7525 Builder.defineMacro("__mips", "64"); 7526 Builder.defineMacro("__mips64"); 7527 Builder.defineMacro("__mips64__"); 7528 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7529 } 7530 7531 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7532 .Cases("mips32", "mips64", "1") 7533 .Cases("mips32r2", "mips64r2", "2") 7534 .Cases("mips32r3", "mips64r3", "3") 7535 .Cases("mips32r5", "mips64r5", "5") 7536 .Cases("mips32r6", "mips64r6", "6") 7537 .Default(""); 7538 if (!ISARev.empty()) 7539 Builder.defineMacro("__mips_isa_rev", ISARev); 7540 7541 if (ABI == "o32") { 7542 Builder.defineMacro("__mips_o32"); 7543 Builder.defineMacro("_ABIO32", "1"); 7544 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7545 } else if (ABI == "n32") { 7546 Builder.defineMacro("__mips_n32"); 7547 Builder.defineMacro("_ABIN32", "2"); 7548 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7549 } else if (ABI == "n64") { 7550 Builder.defineMacro("__mips_n64"); 7551 Builder.defineMacro("_ABI64", "3"); 7552 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7553 } else 7554 llvm_unreachable("Invalid ABI."); 7555 7556 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7557 7558 switch (FloatABI) { 7559 case HardFloat: 7560 Builder.defineMacro("__mips_hard_float", Twine(1)); 7561 break; 7562 case SoftFloat: 7563 Builder.defineMacro("__mips_soft_float", Twine(1)); 7564 break; 7565 } 7566 7567 if (IsSingleFloat) 7568 Builder.defineMacro("__mips_single_float", Twine(1)); 7569 7570 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7571 Builder.defineMacro("_MIPS_FPSET", 7572 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7573 7574 if (IsMips16) 7575 Builder.defineMacro("__mips16", Twine(1)); 7576 7577 if (IsMicromips) 7578 Builder.defineMacro("__mips_micromips", Twine(1)); 7579 7580 if (IsNan2008) 7581 Builder.defineMacro("__mips_nan2008", Twine(1)); 7582 7583 switch (DspRev) { 7584 default: 7585 break; 7586 case DSP1: 7587 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7588 Builder.defineMacro("__mips_dsp", Twine(1)); 7589 break; 7590 case DSP2: 7591 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7592 Builder.defineMacro("__mips_dspr2", Twine(1)); 7593 Builder.defineMacro("__mips_dsp", Twine(1)); 7594 break; 7595 } 7596 7597 if (HasMSA) 7598 Builder.defineMacro("__mips_msa", Twine(1)); 7599 7600 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7601 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7602 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7603 7604 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7605 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7606 7607 // These shouldn't be defined for MIPS-I but there's no need to check 7608 // for that since MIPS-I isn't supported. 7609 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7610 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7611 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7612 7613 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7614 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7615 // the instructions exist but using them violates the ABI since they 7616 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7617 if (ABI == "n32" || ABI == "n64") 7618 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7619 } 7620 7621 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7622 return llvm::makeArrayRef(BuiltinInfo, 7623 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7624 } 7625 bool hasFeature(StringRef Feature) const override { 7626 return llvm::StringSwitch<bool>(Feature) 7627 .Case("mips", true) 7628 .Case("fp64", HasFP64) 7629 .Default(false); 7630 } 7631 BuiltinVaListKind getBuiltinVaListKind() const override { 7632 return TargetInfo::VoidPtrBuiltinVaList; 7633 } 7634 ArrayRef<const char *> getGCCRegNames() const override { 7635 static const char *const GCCRegNames[] = { 7636 // CPU register names 7637 // Must match second column of GCCRegAliases 7638 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7639 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7640 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7641 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7642 // Floating point register names 7643 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7644 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7645 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7646 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7647 // Hi/lo and condition register names 7648 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7649 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7650 "$ac3hi","$ac3lo", 7651 // MSA register names 7652 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7653 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7654 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7655 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7656 // MSA control register names 7657 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7658 "$msarequest", "$msamap", "$msaunmap" 7659 }; 7660 return llvm::makeArrayRef(GCCRegNames); 7661 } 7662 bool validateAsmConstraint(const char *&Name, 7663 TargetInfo::ConstraintInfo &Info) const override { 7664 switch (*Name) { 7665 default: 7666 return false; 7667 case 'r': // CPU registers. 7668 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7669 case 'y': // Equivalent to "r", backward compatibility only. 7670 case 'f': // floating-point registers. 7671 case 'c': // $25 for indirect jumps 7672 case 'l': // lo register 7673 case 'x': // hilo register pair 7674 Info.setAllowsRegister(); 7675 return true; 7676 case 'I': // Signed 16-bit constant 7677 case 'J': // Integer 0 7678 case 'K': // Unsigned 16-bit constant 7679 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7680 case 'M': // Constants not loadable via lui, addiu, or ori 7681 case 'N': // Constant -1 to -65535 7682 case 'O': // A signed 15-bit constant 7683 case 'P': // A constant between 1 go 65535 7684 return true; 7685 case 'R': // An address that can be used in a non-macro load or store 7686 Info.setAllowsMemory(); 7687 return true; 7688 case 'Z': 7689 if (Name[1] == 'C') { // An address usable by ll, and sc. 7690 Info.setAllowsMemory(); 7691 Name++; // Skip over 'Z'. 7692 return true; 7693 } 7694 return false; 7695 } 7696 } 7697 7698 std::string convertConstraint(const char *&Constraint) const override { 7699 std::string R; 7700 switch (*Constraint) { 7701 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7702 if (Constraint[1] == 'C') { 7703 R = std::string("^") + std::string(Constraint, 2); 7704 Constraint++; 7705 return R; 7706 } 7707 break; 7708 } 7709 return TargetInfo::convertConstraint(Constraint); 7710 } 7711 7712 const char *getClobbers() const override { 7713 // In GCC, $1 is not widely used in generated code (it's used only in a few 7714 // specific situations), so there is no real need for users to add it to 7715 // the clobbers list if they want to use it in their inline assembly code. 7716 // 7717 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7718 // code generation, so using it in inline assembly without adding it to the 7719 // clobbers list can cause conflicts between the inline assembly code and 7720 // the surrounding generated code. 7721 // 7722 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7723 // operands, which will conflict with the ".set at" assembler option (which 7724 // we use only for inline assembly, in order to maintain compatibility with 7725 // GCC) and will also conflict with the user's usage of $1. 7726 // 7727 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7728 // register for generated code is to automatically clobber $1 for all inline 7729 // assembly code. 7730 // 7731 // FIXME: We should automatically clobber $1 only for inline assembly code 7732 // which actually uses it. This would allow LLVM to use $1 for inline 7733 // assembly operands if the user's assembly code doesn't use it. 7734 return "~{$1}"; 7735 } 7736 7737 bool handleTargetFeatures(std::vector<std::string> &Features, 7738 DiagnosticsEngine &Diags) override { 7739 IsMips16 = false; 7740 IsMicromips = false; 7741 IsNan2008 = isNaN2008Default(); 7742 IsSingleFloat = false; 7743 FloatABI = HardFloat; 7744 DspRev = NoDSP; 7745 HasFP64 = isFP64Default(); 7746 7747 for (const auto &Feature : Features) { 7748 if (Feature == "+single-float") 7749 IsSingleFloat = true; 7750 else if (Feature == "+soft-float") 7751 FloatABI = SoftFloat; 7752 else if (Feature == "+mips16") 7753 IsMips16 = true; 7754 else if (Feature == "+micromips") 7755 IsMicromips = true; 7756 else if (Feature == "+dsp") 7757 DspRev = std::max(DspRev, DSP1); 7758 else if (Feature == "+dspr2") 7759 DspRev = std::max(DspRev, DSP2); 7760 else if (Feature == "+msa") 7761 HasMSA = true; 7762 else if (Feature == "+fp64") 7763 HasFP64 = true; 7764 else if (Feature == "-fp64") 7765 HasFP64 = false; 7766 else if (Feature == "+nan2008") 7767 IsNan2008 = true; 7768 else if (Feature == "-nan2008") 7769 IsNan2008 = false; 7770 } 7771 7772 setDataLayout(); 7773 7774 return true; 7775 } 7776 7777 int getEHDataRegisterNumber(unsigned RegNo) const override { 7778 if (RegNo == 0) return 4; 7779 if (RegNo == 1) return 5; 7780 return -1; 7781 } 7782 7783 bool isCLZForZeroUndef() const override { return false; } 7784 7785 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7786 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7787 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7788 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7789 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7790 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7791 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7792 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7793 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7794 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7795 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7796 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7797 {{"ra"}, "$31"}}; 7798 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7799 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7800 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7801 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7802 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7803 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7804 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7805 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7806 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7807 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7808 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7809 {{"ra"}, "$31"}}; 7810 if (ABI == "o32") 7811 return llvm::makeArrayRef(O32RegAliases); 7812 return llvm::makeArrayRef(NewABIRegAliases); 7813 } 7814 7815 bool hasInt128Type() const override { 7816 return ABI == "n32" || ABI == "n64"; 7817 } 7818 7819 bool validateTarget(DiagnosticsEngine &Diags) const override { 7820 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7821 // this yet. It's better to fail here than on the backend assertion. 7822 if (processorSupportsGPR64() && ABI == "o32") { 7823 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7824 return false; 7825 } 7826 7827 // 64-bit ABI's require 64-bit CPU's. 7828 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7829 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7830 return false; 7831 } 7832 7833 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7834 // can't handle this yet. It's better to fail here than on the 7835 // backend assertion. 7836 if ((getTriple().getArch() == llvm::Triple::mips64 || 7837 getTriple().getArch() == llvm::Triple::mips64el) && 7838 ABI == "o32") { 7839 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7840 << ABI << getTriple().str(); 7841 return false; 7842 } 7843 7844 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7845 // can't handle this yet. It's better to fail here than on the 7846 // backend assertion. 7847 if ((getTriple().getArch() == llvm::Triple::mips || 7848 getTriple().getArch() == llvm::Triple::mipsel) && 7849 (ABI == "n32" || ABI == "n64")) { 7850 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7851 << ABI << getTriple().str(); 7852 return false; 7853 } 7854 7855 return true; 7856 } 7857 }; 7858 7859 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7860 #define BUILTIN(ID, TYPE, ATTRS) \ 7861 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7862 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7863 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7864 #include "clang/Basic/BuiltinsMips.def" 7865 }; 7866 7867 class PNaClTargetInfo : public TargetInfo { 7868 public: 7869 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7870 : TargetInfo(Triple) { 7871 this->LongAlign = 32; 7872 this->LongWidth = 32; 7873 this->PointerAlign = 32; 7874 this->PointerWidth = 32; 7875 this->IntMaxType = TargetInfo::SignedLongLong; 7876 this->Int64Type = TargetInfo::SignedLongLong; 7877 this->DoubleAlign = 64; 7878 this->LongDoubleWidth = 64; 7879 this->LongDoubleAlign = 64; 7880 this->SizeType = TargetInfo::UnsignedInt; 7881 this->PtrDiffType = TargetInfo::SignedInt; 7882 this->IntPtrType = TargetInfo::SignedInt; 7883 this->RegParmMax = 0; // Disallow regparm 7884 } 7885 7886 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7887 Builder.defineMacro("__le32__"); 7888 Builder.defineMacro("__pnacl__"); 7889 } 7890 void getTargetDefines(const LangOptions &Opts, 7891 MacroBuilder &Builder) const override { 7892 getArchDefines(Opts, Builder); 7893 } 7894 bool hasFeature(StringRef Feature) const override { 7895 return Feature == "pnacl"; 7896 } 7897 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7898 BuiltinVaListKind getBuiltinVaListKind() const override { 7899 return TargetInfo::PNaClABIBuiltinVaList; 7900 } 7901 ArrayRef<const char *> getGCCRegNames() const override; 7902 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7903 bool validateAsmConstraint(const char *&Name, 7904 TargetInfo::ConstraintInfo &Info) const override { 7905 return false; 7906 } 7907 7908 const char *getClobbers() const override { 7909 return ""; 7910 } 7911 }; 7912 7913 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7914 return None; 7915 } 7916 7917 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7918 return None; 7919 } 7920 7921 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7922 class NaClMips32TargetInfo : public MipsTargetInfo { 7923 public: 7924 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7925 : MipsTargetInfo(Triple, Opts) {} 7926 7927 BuiltinVaListKind getBuiltinVaListKind() const override { 7928 return TargetInfo::PNaClABIBuiltinVaList; 7929 } 7930 }; 7931 7932 class Le64TargetInfo : public TargetInfo { 7933 static const Builtin::Info BuiltinInfo[]; 7934 7935 public: 7936 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7937 : TargetInfo(Triple) { 7938 NoAsmVariants = true; 7939 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7940 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7941 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7942 } 7943 7944 void getTargetDefines(const LangOptions &Opts, 7945 MacroBuilder &Builder) const override { 7946 DefineStd(Builder, "unix", Opts); 7947 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7948 Builder.defineMacro("__ELF__"); 7949 } 7950 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7951 return llvm::makeArrayRef(BuiltinInfo, 7952 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7953 } 7954 BuiltinVaListKind getBuiltinVaListKind() const override { 7955 return TargetInfo::PNaClABIBuiltinVaList; 7956 } 7957 const char *getClobbers() const override { return ""; } 7958 ArrayRef<const char *> getGCCRegNames() const override { 7959 return None; 7960 } 7961 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7962 return None; 7963 } 7964 bool validateAsmConstraint(const char *&Name, 7965 TargetInfo::ConstraintInfo &Info) const override { 7966 return false; 7967 } 7968 7969 bool hasProtectedVisibility() const override { return false; } 7970 }; 7971 7972 class WebAssemblyTargetInfo : public TargetInfo { 7973 static const Builtin::Info BuiltinInfo[]; 7974 7975 enum SIMDEnum { 7976 NoSIMD, 7977 SIMD128, 7978 } SIMDLevel; 7979 7980 public: 7981 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7982 : TargetInfo(T), SIMDLevel(NoSIMD) { 7983 NoAsmVariants = true; 7984 SuitableAlign = 128; 7985 LargeArrayMinWidth = 128; 7986 LargeArrayAlign = 128; 7987 SimdDefaultAlign = 128; 7988 SigAtomicType = SignedLong; 7989 LongDoubleWidth = LongDoubleAlign = 128; 7990 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7991 SizeType = UnsignedInt; 7992 PtrDiffType = SignedInt; 7993 IntPtrType = SignedInt; 7994 } 7995 7996 protected: 7997 void getTargetDefines(const LangOptions &Opts, 7998 MacroBuilder &Builder) const override { 7999 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8000 if (SIMDLevel >= SIMD128) 8001 Builder.defineMacro("__wasm_simd128__"); 8002 } 8003 8004 private: 8005 bool 8006 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8007 StringRef CPU, 8008 const std::vector<std::string> &FeaturesVec) const override { 8009 if (CPU == "bleeding-edge") 8010 Features["simd128"] = true; 8011 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8012 } 8013 bool hasFeature(StringRef Feature) const final { 8014 return llvm::StringSwitch<bool>(Feature) 8015 .Case("simd128", SIMDLevel >= SIMD128) 8016 .Default(false); 8017 } 8018 bool handleTargetFeatures(std::vector<std::string> &Features, 8019 DiagnosticsEngine &Diags) final { 8020 for (const auto &Feature : Features) { 8021 if (Feature == "+simd128") { 8022 SIMDLevel = std::max(SIMDLevel, SIMD128); 8023 continue; 8024 } 8025 if (Feature == "-simd128") { 8026 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8027 continue; 8028 } 8029 8030 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8031 << "-target-feature"; 8032 return false; 8033 } 8034 return true; 8035 } 8036 bool setCPU(const std::string &Name) final { 8037 return llvm::StringSwitch<bool>(Name) 8038 .Case("mvp", true) 8039 .Case("bleeding-edge", true) 8040 .Case("generic", true) 8041 .Default(false); 8042 } 8043 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8044 return llvm::makeArrayRef(BuiltinInfo, 8045 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8046 } 8047 BuiltinVaListKind getBuiltinVaListKind() const final { 8048 return VoidPtrBuiltinVaList; 8049 } 8050 ArrayRef<const char *> getGCCRegNames() const final { 8051 return None; 8052 } 8053 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8054 return None; 8055 } 8056 bool 8057 validateAsmConstraint(const char *&Name, 8058 TargetInfo::ConstraintInfo &Info) const final { 8059 return false; 8060 } 8061 const char *getClobbers() const final { return ""; } 8062 bool isCLZForZeroUndef() const final { return false; } 8063 bool hasInt128Type() const final { return true; } 8064 IntType getIntTypeByWidth(unsigned BitWidth, 8065 bool IsSigned) const final { 8066 // WebAssembly prefers long long for explicitly 64-bit integers. 8067 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8068 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8069 } 8070 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8071 bool IsSigned) const final { 8072 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8073 return BitWidth == 64 8074 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8075 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8076 } 8077 }; 8078 8079 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8080 #define BUILTIN(ID, TYPE, ATTRS) \ 8081 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8082 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8083 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8084 #include "clang/Basic/BuiltinsWebAssembly.def" 8085 }; 8086 8087 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8088 public: 8089 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8090 const TargetOptions &Opts) 8091 : WebAssemblyTargetInfo(T, Opts) { 8092 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8093 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8094 } 8095 8096 protected: 8097 void getTargetDefines(const LangOptions &Opts, 8098 MacroBuilder &Builder) const override { 8099 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8100 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8101 } 8102 }; 8103 8104 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8105 public: 8106 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8107 const TargetOptions &Opts) 8108 : WebAssemblyTargetInfo(T, Opts) { 8109 LongAlign = LongWidth = 64; 8110 PointerAlign = PointerWidth = 64; 8111 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8112 SizeType = UnsignedLong; 8113 PtrDiffType = SignedLong; 8114 IntPtrType = SignedLong; 8115 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8116 } 8117 8118 protected: 8119 void getTargetDefines(const LangOptions &Opts, 8120 MacroBuilder &Builder) const override { 8121 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8122 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8123 } 8124 }; 8125 8126 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8127 #define BUILTIN(ID, TYPE, ATTRS) \ 8128 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8129 #include "clang/Basic/BuiltinsLe64.def" 8130 }; 8131 8132 static const unsigned SPIRAddrSpaceMap[] = { 8133 1, // opencl_global 8134 3, // opencl_local 8135 2, // opencl_constant 8136 4, // opencl_generic 8137 0, // cuda_device 8138 0, // cuda_constant 8139 0 // cuda_shared 8140 }; 8141 class SPIRTargetInfo : public TargetInfo { 8142 public: 8143 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8144 : TargetInfo(Triple) { 8145 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8146 "SPIR target must use unknown OS"); 8147 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8148 "SPIR target must use unknown environment type"); 8149 TLSSupported = false; 8150 LongWidth = LongAlign = 64; 8151 AddrSpaceMap = &SPIRAddrSpaceMap; 8152 UseAddrSpaceMapMangling = true; 8153 // Define available target features 8154 // These must be defined in sorted order! 8155 NoAsmVariants = true; 8156 } 8157 void getTargetDefines(const LangOptions &Opts, 8158 MacroBuilder &Builder) const override { 8159 DefineStd(Builder, "SPIR", Opts); 8160 } 8161 bool hasFeature(StringRef Feature) const override { 8162 return Feature == "spir"; 8163 } 8164 8165 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8166 const char *getClobbers() const override { return ""; } 8167 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8168 bool validateAsmConstraint(const char *&Name, 8169 TargetInfo::ConstraintInfo &info) const override { 8170 return true; 8171 } 8172 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8173 return None; 8174 } 8175 BuiltinVaListKind getBuiltinVaListKind() const override { 8176 return TargetInfo::VoidPtrBuiltinVaList; 8177 } 8178 8179 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8180 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8181 : CCCR_Warning; 8182 } 8183 8184 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8185 return CC_SpirFunction; 8186 } 8187 8188 void setSupportedOpenCLOpts() override { 8189 // Assume all OpenCL extensions and optional core features are supported 8190 // for SPIR since it is a generic target. 8191 getSupportedOpenCLOpts().setAll(); 8192 } 8193 }; 8194 8195 class SPIR32TargetInfo : public SPIRTargetInfo { 8196 public: 8197 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8198 : SPIRTargetInfo(Triple, Opts) { 8199 PointerWidth = PointerAlign = 32; 8200 SizeType = TargetInfo::UnsignedInt; 8201 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8202 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8203 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8204 } 8205 void getTargetDefines(const LangOptions &Opts, 8206 MacroBuilder &Builder) const override { 8207 DefineStd(Builder, "SPIR32", Opts); 8208 } 8209 }; 8210 8211 class SPIR64TargetInfo : public SPIRTargetInfo { 8212 public: 8213 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8214 : SPIRTargetInfo(Triple, Opts) { 8215 PointerWidth = PointerAlign = 64; 8216 SizeType = TargetInfo::UnsignedLong; 8217 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8218 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8219 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8220 } 8221 void getTargetDefines(const LangOptions &Opts, 8222 MacroBuilder &Builder) const override { 8223 DefineStd(Builder, "SPIR64", Opts); 8224 } 8225 }; 8226 8227 class XCoreTargetInfo : public TargetInfo { 8228 static const Builtin::Info BuiltinInfo[]; 8229 public: 8230 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8231 : TargetInfo(Triple) { 8232 NoAsmVariants = true; 8233 LongLongAlign = 32; 8234 SuitableAlign = 32; 8235 DoubleAlign = LongDoubleAlign = 32; 8236 SizeType = UnsignedInt; 8237 PtrDiffType = SignedInt; 8238 IntPtrType = SignedInt; 8239 WCharType = UnsignedChar; 8240 WIntType = UnsignedInt; 8241 UseZeroLengthBitfieldAlignment = true; 8242 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8243 "-f64:32-a:0:32-n32"); 8244 } 8245 void getTargetDefines(const LangOptions &Opts, 8246 MacroBuilder &Builder) const override { 8247 Builder.defineMacro("__XS1B__"); 8248 } 8249 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8250 return llvm::makeArrayRef(BuiltinInfo, 8251 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8252 } 8253 BuiltinVaListKind getBuiltinVaListKind() const override { 8254 return TargetInfo::VoidPtrBuiltinVaList; 8255 } 8256 const char *getClobbers() const override { 8257 return ""; 8258 } 8259 ArrayRef<const char *> getGCCRegNames() const override { 8260 static const char * const GCCRegNames[] = { 8261 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8262 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8263 }; 8264 return llvm::makeArrayRef(GCCRegNames); 8265 } 8266 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8267 return None; 8268 } 8269 bool validateAsmConstraint(const char *&Name, 8270 TargetInfo::ConstraintInfo &Info) const override { 8271 return false; 8272 } 8273 int getEHDataRegisterNumber(unsigned RegNo) const override { 8274 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8275 return (RegNo < 2)? RegNo : -1; 8276 } 8277 bool allowsLargerPreferedTypeAlignment() const override { 8278 return false; 8279 } 8280 }; 8281 8282 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8283 #define BUILTIN(ID, TYPE, ATTRS) \ 8284 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8285 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8286 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8287 #include "clang/Basic/BuiltinsXCore.def" 8288 }; 8289 8290 // x86_32 Android target 8291 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8292 public: 8293 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8294 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8295 SuitableAlign = 32; 8296 LongDoubleWidth = 64; 8297 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8298 } 8299 }; 8300 8301 // x86_64 Android target 8302 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8303 public: 8304 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8305 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8306 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8307 } 8308 8309 bool useFloat128ManglingForLongDouble() const override { 8310 return true; 8311 } 8312 }; 8313 8314 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8315 class RenderScript32TargetInfo : public ARMleTargetInfo { 8316 public: 8317 RenderScript32TargetInfo(const llvm::Triple &Triple, 8318 const TargetOptions &Opts) 8319 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8320 Triple.getOSName(), 8321 Triple.getEnvironmentName()), 8322 Opts) { 8323 IsRenderScriptTarget = true; 8324 LongWidth = LongAlign = 64; 8325 } 8326 void getTargetDefines(const LangOptions &Opts, 8327 MacroBuilder &Builder) const override { 8328 Builder.defineMacro("__RENDERSCRIPT__"); 8329 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8330 } 8331 }; 8332 8333 // 64-bit RenderScript is aarch64 8334 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8335 public: 8336 RenderScript64TargetInfo(const llvm::Triple &Triple, 8337 const TargetOptions &Opts) 8338 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8339 Triple.getOSName(), 8340 Triple.getEnvironmentName()), 8341 Opts) { 8342 IsRenderScriptTarget = true; 8343 } 8344 8345 void getTargetDefines(const LangOptions &Opts, 8346 MacroBuilder &Builder) const override { 8347 Builder.defineMacro("__RENDERSCRIPT__"); 8348 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8349 } 8350 }; 8351 8352 } // end anonymous namespace 8353 8354 //===----------------------------------------------------------------------===// 8355 // Driver code 8356 //===----------------------------------------------------------------------===// 8357 8358 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8359 const TargetOptions &Opts) { 8360 llvm::Triple::OSType os = Triple.getOS(); 8361 8362 switch (Triple.getArch()) { 8363 default: 8364 return nullptr; 8365 8366 case llvm::Triple::xcore: 8367 return new XCoreTargetInfo(Triple, Opts); 8368 8369 case llvm::Triple::hexagon: 8370 return new HexagonTargetInfo(Triple, Opts); 8371 8372 case llvm::Triple::lanai: 8373 return new LanaiTargetInfo(Triple, Opts); 8374 8375 case llvm::Triple::aarch64: 8376 if (Triple.isOSDarwin()) 8377 return new DarwinAArch64TargetInfo(Triple, Opts); 8378 8379 switch (os) { 8380 case llvm::Triple::CloudABI: 8381 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8382 case llvm::Triple::FreeBSD: 8383 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8384 case llvm::Triple::Fuchsia: 8385 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8386 case llvm::Triple::Linux: 8387 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8388 case llvm::Triple::NetBSD: 8389 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8390 default: 8391 return new AArch64leTargetInfo(Triple, Opts); 8392 } 8393 8394 case llvm::Triple::aarch64_be: 8395 switch (os) { 8396 case llvm::Triple::FreeBSD: 8397 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8398 case llvm::Triple::Fuchsia: 8399 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8400 case llvm::Triple::Linux: 8401 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8402 case llvm::Triple::NetBSD: 8403 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8404 default: 8405 return new AArch64beTargetInfo(Triple, Opts); 8406 } 8407 8408 case llvm::Triple::arm: 8409 case llvm::Triple::thumb: 8410 if (Triple.isOSBinFormatMachO()) 8411 return new DarwinARMTargetInfo(Triple, Opts); 8412 8413 switch (os) { 8414 case llvm::Triple::CloudABI: 8415 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 8416 case llvm::Triple::Linux: 8417 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8418 case llvm::Triple::FreeBSD: 8419 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8420 case llvm::Triple::Fuchsia: 8421 return new FuchsiaTargetInfo<ARMleTargetInfo>(Triple, Opts); 8422 case llvm::Triple::NetBSD: 8423 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8424 case llvm::Triple::OpenBSD: 8425 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8426 case llvm::Triple::Bitrig: 8427 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8428 case llvm::Triple::RTEMS: 8429 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8430 case llvm::Triple::NaCl: 8431 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8432 case llvm::Triple::Win32: 8433 switch (Triple.getEnvironment()) { 8434 case llvm::Triple::Cygnus: 8435 return new CygwinARMTargetInfo(Triple, Opts); 8436 case llvm::Triple::GNU: 8437 return new MinGWARMTargetInfo(Triple, Opts); 8438 case llvm::Triple::Itanium: 8439 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8440 case llvm::Triple::MSVC: 8441 default: // Assume MSVC for unknown environments 8442 return new MicrosoftARMleTargetInfo(Triple, Opts); 8443 } 8444 default: 8445 return new ARMleTargetInfo(Triple, Opts); 8446 } 8447 8448 case llvm::Triple::armeb: 8449 case llvm::Triple::thumbeb: 8450 if (Triple.isOSDarwin()) 8451 return new DarwinARMTargetInfo(Triple, Opts); 8452 8453 switch (os) { 8454 case llvm::Triple::Linux: 8455 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8456 case llvm::Triple::FreeBSD: 8457 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8458 case llvm::Triple::Fuchsia: 8459 return new FuchsiaTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8460 case llvm::Triple::NetBSD: 8461 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8462 case llvm::Triple::OpenBSD: 8463 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8464 case llvm::Triple::Bitrig: 8465 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8466 case llvm::Triple::RTEMS: 8467 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8468 case llvm::Triple::NaCl: 8469 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8470 default: 8471 return new ARMbeTargetInfo(Triple, Opts); 8472 } 8473 8474 case llvm::Triple::bpfeb: 8475 case llvm::Triple::bpfel: 8476 return new BPFTargetInfo(Triple, Opts); 8477 8478 case llvm::Triple::msp430: 8479 return new MSP430TargetInfo(Triple, Opts); 8480 8481 case llvm::Triple::mips: 8482 switch (os) { 8483 case llvm::Triple::Linux: 8484 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8485 case llvm::Triple::RTEMS: 8486 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8487 case llvm::Triple::FreeBSD: 8488 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8489 case llvm::Triple::NetBSD: 8490 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8491 default: 8492 return new MipsTargetInfo(Triple, Opts); 8493 } 8494 8495 case llvm::Triple::mipsel: 8496 switch (os) { 8497 case llvm::Triple::Linux: 8498 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8499 case llvm::Triple::RTEMS: 8500 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8501 case llvm::Triple::FreeBSD: 8502 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8503 case llvm::Triple::NetBSD: 8504 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8505 case llvm::Triple::NaCl: 8506 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8507 default: 8508 return new MipsTargetInfo(Triple, Opts); 8509 } 8510 8511 case llvm::Triple::mips64: 8512 switch (os) { 8513 case llvm::Triple::Linux: 8514 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8515 case llvm::Triple::RTEMS: 8516 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8517 case llvm::Triple::FreeBSD: 8518 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8519 case llvm::Triple::NetBSD: 8520 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8521 case llvm::Triple::OpenBSD: 8522 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8523 default: 8524 return new MipsTargetInfo(Triple, Opts); 8525 } 8526 8527 case llvm::Triple::mips64el: 8528 switch (os) { 8529 case llvm::Triple::Linux: 8530 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8531 case llvm::Triple::RTEMS: 8532 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8533 case llvm::Triple::FreeBSD: 8534 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8535 case llvm::Triple::NetBSD: 8536 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8537 case llvm::Triple::OpenBSD: 8538 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8539 default: 8540 return new MipsTargetInfo(Triple, Opts); 8541 } 8542 8543 case llvm::Triple::le32: 8544 switch (os) { 8545 case llvm::Triple::NaCl: 8546 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8547 default: 8548 return nullptr; 8549 } 8550 8551 case llvm::Triple::le64: 8552 return new Le64TargetInfo(Triple, Opts); 8553 8554 case llvm::Triple::ppc: 8555 if (Triple.isOSDarwin()) 8556 return new DarwinPPC32TargetInfo(Triple, Opts); 8557 switch (os) { 8558 case llvm::Triple::Linux: 8559 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8560 case llvm::Triple::FreeBSD: 8561 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8562 case llvm::Triple::NetBSD: 8563 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8564 case llvm::Triple::OpenBSD: 8565 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8566 case llvm::Triple::RTEMS: 8567 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8568 default: 8569 return new PPC32TargetInfo(Triple, Opts); 8570 } 8571 8572 case llvm::Triple::ppc64: 8573 if (Triple.isOSDarwin()) 8574 return new DarwinPPC64TargetInfo(Triple, Opts); 8575 switch (os) { 8576 case llvm::Triple::Linux: 8577 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8578 case llvm::Triple::Lv2: 8579 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8580 case llvm::Triple::FreeBSD: 8581 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8582 case llvm::Triple::NetBSD: 8583 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8584 default: 8585 return new PPC64TargetInfo(Triple, Opts); 8586 } 8587 8588 case llvm::Triple::ppc64le: 8589 switch (os) { 8590 case llvm::Triple::Linux: 8591 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8592 case llvm::Triple::NetBSD: 8593 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8594 default: 8595 return new PPC64TargetInfo(Triple, Opts); 8596 } 8597 8598 case llvm::Triple::nvptx: 8599 return new NVPTX32TargetInfo(Triple, Opts); 8600 case llvm::Triple::nvptx64: 8601 return new NVPTX64TargetInfo(Triple, Opts); 8602 8603 case llvm::Triple::amdgcn: 8604 case llvm::Triple::r600: 8605 return new AMDGPUTargetInfo(Triple, Opts); 8606 8607 case llvm::Triple::sparc: 8608 switch (os) { 8609 case llvm::Triple::Linux: 8610 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8611 case llvm::Triple::Solaris: 8612 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8613 case llvm::Triple::NetBSD: 8614 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8615 case llvm::Triple::OpenBSD: 8616 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8617 case llvm::Triple::RTEMS: 8618 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8619 default: 8620 return new SparcV8TargetInfo(Triple, Opts); 8621 } 8622 8623 // The 'sparcel' architecture copies all the above cases except for Solaris. 8624 case llvm::Triple::sparcel: 8625 switch (os) { 8626 case llvm::Triple::Linux: 8627 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8628 case llvm::Triple::NetBSD: 8629 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8630 case llvm::Triple::OpenBSD: 8631 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8632 case llvm::Triple::RTEMS: 8633 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8634 default: 8635 return new SparcV8elTargetInfo(Triple, Opts); 8636 } 8637 8638 case llvm::Triple::sparcv9: 8639 switch (os) { 8640 case llvm::Triple::Linux: 8641 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8642 case llvm::Triple::Solaris: 8643 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8644 case llvm::Triple::NetBSD: 8645 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8646 case llvm::Triple::OpenBSD: 8647 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8648 case llvm::Triple::FreeBSD: 8649 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8650 default: 8651 return new SparcV9TargetInfo(Triple, Opts); 8652 } 8653 8654 case llvm::Triple::systemz: 8655 switch (os) { 8656 case llvm::Triple::Linux: 8657 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8658 default: 8659 return new SystemZTargetInfo(Triple, Opts); 8660 } 8661 8662 case llvm::Triple::tce: 8663 return new TCETargetInfo(Triple, Opts); 8664 8665 case llvm::Triple::tcele: 8666 return new TCELETargetInfo(Triple, Opts); 8667 8668 case llvm::Triple::x86: 8669 if (Triple.isOSDarwin()) 8670 return new DarwinI386TargetInfo(Triple, Opts); 8671 8672 switch (os) { 8673 case llvm::Triple::CloudABI: 8674 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8675 case llvm::Triple::Linux: { 8676 switch (Triple.getEnvironment()) { 8677 default: 8678 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8679 case llvm::Triple::Android: 8680 return new AndroidX86_32TargetInfo(Triple, Opts); 8681 } 8682 } 8683 case llvm::Triple::DragonFly: 8684 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8685 case llvm::Triple::NetBSD: 8686 return new NetBSDI386TargetInfo(Triple, Opts); 8687 case llvm::Triple::OpenBSD: 8688 return new OpenBSDI386TargetInfo(Triple, Opts); 8689 case llvm::Triple::Bitrig: 8690 return new BitrigI386TargetInfo(Triple, Opts); 8691 case llvm::Triple::FreeBSD: 8692 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8693 case llvm::Triple::Fuchsia: 8694 return new FuchsiaTargetInfo<X86_32TargetInfo>(Triple, Opts); 8695 case llvm::Triple::KFreeBSD: 8696 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8697 case llvm::Triple::Minix: 8698 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8699 case llvm::Triple::Solaris: 8700 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8701 case llvm::Triple::Win32: { 8702 switch (Triple.getEnvironment()) { 8703 case llvm::Triple::Cygnus: 8704 return new CygwinX86_32TargetInfo(Triple, Opts); 8705 case llvm::Triple::GNU: 8706 return new MinGWX86_32TargetInfo(Triple, Opts); 8707 case llvm::Triple::Itanium: 8708 case llvm::Triple::MSVC: 8709 default: // Assume MSVC for unknown environments 8710 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8711 } 8712 } 8713 case llvm::Triple::Haiku: 8714 return new HaikuX86_32TargetInfo(Triple, Opts); 8715 case llvm::Triple::RTEMS: 8716 return new RTEMSX86_32TargetInfo(Triple, Opts); 8717 case llvm::Triple::NaCl: 8718 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8719 case llvm::Triple::ELFIAMCU: 8720 return new MCUX86_32TargetInfo(Triple, Opts); 8721 default: 8722 return new X86_32TargetInfo(Triple, Opts); 8723 } 8724 8725 case llvm::Triple::x86_64: 8726 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8727 return new DarwinX86_64TargetInfo(Triple, Opts); 8728 8729 switch (os) { 8730 case llvm::Triple::CloudABI: 8731 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8732 case llvm::Triple::Linux: { 8733 switch (Triple.getEnvironment()) { 8734 default: 8735 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8736 case llvm::Triple::Android: 8737 return new AndroidX86_64TargetInfo(Triple, Opts); 8738 } 8739 } 8740 case llvm::Triple::DragonFly: 8741 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8742 case llvm::Triple::NetBSD: 8743 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8744 case llvm::Triple::OpenBSD: 8745 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8746 case llvm::Triple::Bitrig: 8747 return new BitrigX86_64TargetInfo(Triple, Opts); 8748 case llvm::Triple::FreeBSD: 8749 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8750 case llvm::Triple::Fuchsia: 8751 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 8752 case llvm::Triple::KFreeBSD: 8753 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8754 case llvm::Triple::Solaris: 8755 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8756 case llvm::Triple::Win32: { 8757 switch (Triple.getEnvironment()) { 8758 case llvm::Triple::Cygnus: 8759 return new CygwinX86_64TargetInfo(Triple, Opts); 8760 case llvm::Triple::GNU: 8761 return new MinGWX86_64TargetInfo(Triple, Opts); 8762 case llvm::Triple::MSVC: 8763 default: // Assume MSVC for unknown environments 8764 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8765 } 8766 } 8767 case llvm::Triple::Haiku: 8768 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8769 case llvm::Triple::NaCl: 8770 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8771 case llvm::Triple::PS4: 8772 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8773 default: 8774 return new X86_64TargetInfo(Triple, Opts); 8775 } 8776 8777 case llvm::Triple::spir: { 8778 if (Triple.getOS() != llvm::Triple::UnknownOS || 8779 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8780 return nullptr; 8781 return new SPIR32TargetInfo(Triple, Opts); 8782 } 8783 case llvm::Triple::spir64: { 8784 if (Triple.getOS() != llvm::Triple::UnknownOS || 8785 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8786 return nullptr; 8787 return new SPIR64TargetInfo(Triple, Opts); 8788 } 8789 case llvm::Triple::wasm32: 8790 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8791 return nullptr; 8792 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8793 case llvm::Triple::wasm64: 8794 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8795 return nullptr; 8796 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8797 8798 case llvm::Triple::renderscript32: 8799 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8800 case llvm::Triple::renderscript64: 8801 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8802 } 8803 } 8804 8805 /// CreateTargetInfo - Return the target info object for the specified target 8806 /// options. 8807 TargetInfo * 8808 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8809 const std::shared_ptr<TargetOptions> &Opts) { 8810 llvm::Triple Triple(Opts->Triple); 8811 8812 // Construct the target 8813 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8814 if (!Target) { 8815 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8816 return nullptr; 8817 } 8818 Target->TargetOpts = Opts; 8819 8820 // Set the target CPU if specified. 8821 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8822 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8823 return nullptr; 8824 } 8825 8826 // Set the target ABI if specified. 8827 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8828 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8829 return nullptr; 8830 } 8831 8832 // Set the fp math unit. 8833 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8834 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8835 return nullptr; 8836 } 8837 8838 // Compute the default target features, we need the target to handle this 8839 // because features may have dependencies on one another. 8840 llvm::StringMap<bool> Features; 8841 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8842 Opts->FeaturesAsWritten)) 8843 return nullptr; 8844 8845 // Add the features to the compile options. 8846 Opts->Features.clear(); 8847 for (const auto &F : Features) 8848 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8849 8850 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8851 return nullptr; 8852 8853 Target->setSupportedOpenCLOpts(); 8854 Target->setOpenCLExtensionOpts(); 8855 8856 if (!Target->validateTarget(Diags)) 8857 return nullptr; 8858 8859 return Target.release(); 8860 } 8861