1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include <algorithm>
32 using namespace clang;
33 
34 //===----------------------------------------------------------------------===//
35 //  Common code shared among targets.
36 //===----------------------------------------------------------------------===//
37 
38 /// DefineStd - Define a macro name and standard variants.  For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40 /// when in GNU mode.
41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                       const LangOptions &Opts) {
43   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44 
45   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46   // in the user's namespace.
47   if (Opts.GNUMode)
48     Builder.defineMacro(MacroName);
49 
50   // Define __unix.
51   Builder.defineMacro("__" + MacroName);
52 
53   // Define __unix__.
54   Builder.defineMacro("__" + MacroName + "__");
55 }
56 
57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                             bool Tuning = true) {
59   Builder.defineMacro("__" + CPUName);
60   Builder.defineMacro("__" + CPUName + "__");
61   if (Tuning)
62     Builder.defineMacro("__tune_" + CPUName + "__");
63 }
64 
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
68 
69 namespace {
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
72 protected:
73   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                             MacroBuilder &Builder) const=0;
75 public:
76   OSTargetInfo(const std::string& triple) : TgtInfo(triple) {}
77   virtual void getTargetDefines(const LangOptions &Opts,
78                                 MacroBuilder &Builder) const {
79     TgtInfo::getTargetDefines(Opts, Builder);
80     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81   }
82 
83 };
84 } // end anonymous namespace
85 
86 
87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                              const llvm::Triple &Triple,
89                              StringRef &PlatformName,
90                              VersionTuple &PlatformMinVersion) {
91   Builder.defineMacro("__APPLE_CC__", "5621");
92   Builder.defineMacro("__APPLE__");
93   Builder.defineMacro("__MACH__");
94   Builder.defineMacro("OBJC_NEW_PROPERTIES");
95   // AddressSanitizer doesn't play well with source fortification, which is on
96   // by default on Darwin.
97   if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98 
99   if (!Opts.ObjCAutoRefCount) {
100     // __weak is always defined, for use in blocks and with objc pointers.
101     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102 
103     // Darwin defines __strong even in C mode (just to nothing).
104     if (Opts.getGC() != LangOptions::NonGC)
105       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106     else
107       Builder.defineMacro("__strong", "");
108 
109     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110     // allow this in C, since one might have block pointers in structs that
111     // are used in pure C code and in Objective-C ARC.
112     Builder.defineMacro("__unsafe_unretained", "");
113   }
114 
115   if (Opts.Static)
116     Builder.defineMacro("__STATIC__");
117   else
118     Builder.defineMacro("__DYNAMIC__");
119 
120   if (Opts.POSIXThreads)
121     Builder.defineMacro("_REENTRANT");
122 
123   // Get the platform type and version number from the triple.
124   unsigned Maj, Min, Rev;
125   if (Triple.isMacOSX()) {
126     Triple.getMacOSXVersion(Maj, Min, Rev);
127     PlatformName = "macosx";
128   } else {
129     Triple.getOSVersion(Maj, Min, Rev);
130     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131   }
132 
133   // If -target arch-pc-win32-macho option specified, we're
134   // generating code for Win32 ABI. No need to emit
135   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136   if (PlatformName == "win32") {
137     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138     return;
139   }
140 
141   // Set the appropriate OS version define.
142   if (Triple.getOS() == llvm::Triple::IOS) {
143     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144     char Str[6];
145     Str[0] = '0' + Maj;
146     Str[1] = '0' + (Min / 10);
147     Str[2] = '0' + (Min % 10);
148     Str[3] = '0' + (Rev / 10);
149     Str[4] = '0' + (Rev % 10);
150     Str[5] = '\0';
151     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152   } else {
153     // Note that the Driver allows versions which aren't representable in the
154     // define (because we only get a single digit for the minor and micro
155     // revision numbers). So, we limit them to the maximum representable
156     // version.
157     assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159     char Str[5];
160     Str[0] = '0' + (Maj / 10);
161     Str[1] = '0' + (Maj % 10);
162     Str[2] = '0' + std::min(Min, 9U);
163     Str[3] = '0' + std::min(Rev, 9U);
164     Str[4] = '\0';
165     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166   }
167 
168   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169 }
170 
171 namespace {
172 template<typename Target>
173 class DarwinTargetInfo : public OSTargetInfo<Target> {
174 protected:
175   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                             MacroBuilder &Builder) const {
177     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                      this->PlatformMinVersion);
179   }
180 
181 public:
182   DarwinTargetInfo(const std::string& triple) :
183     OSTargetInfo<Target>(triple) {
184       llvm::Triple T = llvm::Triple(triple);
185       this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7);
186       this->MCountName = "\01mcount";
187     }
188 
189   virtual std::string isValidSectionSpecifier(StringRef SR) const {
190     // Let MCSectionMachO validate this.
191     StringRef Segment, Section;
192     unsigned TAA, StubSize;
193     bool HasTAA;
194     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195                                                        TAA, HasTAA, StubSize);
196   }
197 
198   virtual const char *getStaticInitSectionSpecifier() const {
199     // FIXME: We should return 0 when building kexts.
200     return "__TEXT,__StaticInit,regular,pure_instructions";
201   }
202 
203   /// Darwin does not support protected visibility.  Darwin's "default"
204   /// is very similar to ELF's "protected";  Darwin requires a "weak"
205   /// attribute on declarations that can be dynamically replaced.
206   virtual bool hasProtectedVisibility() const {
207     return false;
208   }
209 };
210 
211 
212 // DragonFlyBSD Target
213 template<typename Target>
214 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
215 protected:
216   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217                             MacroBuilder &Builder) const {
218     // DragonFly defines; list based off of gcc output
219     Builder.defineMacro("__DragonFly__");
220     Builder.defineMacro("__DragonFly_cc_version", "100001");
221     Builder.defineMacro("__ELF__");
222     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223     Builder.defineMacro("__tune_i386__");
224     DefineStd(Builder, "unix", Opts);
225   }
226 public:
227   DragonFlyBSDTargetInfo(const std::string &triple)
228     : OSTargetInfo<Target>(triple) {
229       this->UserLabelPrefix = "";
230 
231       llvm::Triple Triple(triple);
232       switch (Triple.getArch()) {
233         default:
234         case llvm::Triple::x86:
235         case llvm::Triple::x86_64:
236           this->MCountName = ".mcount";
237           break;
238       }
239   }
240 };
241 
242 // FreeBSD Target
243 template<typename Target>
244 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
245 protected:
246   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247                             MacroBuilder &Builder) const {
248     // FreeBSD defines; list based off of gcc output
249 
250     unsigned Release = Triple.getOSMajorVersion();
251     if (Release == 0U)
252       Release = 8;
253 
254     Builder.defineMacro("__FreeBSD__", Twine(Release));
255     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
256     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
257     DefineStd(Builder, "unix", Opts);
258     Builder.defineMacro("__ELF__");
259   }
260 public:
261   FreeBSDTargetInfo(const std::string &triple)
262     : OSTargetInfo<Target>(triple) {
263       this->UserLabelPrefix = "";
264 
265       llvm::Triple Triple(triple);
266       switch (Triple.getArch()) {
267         default:
268         case llvm::Triple::x86:
269         case llvm::Triple::x86_64:
270           this->MCountName = ".mcount";
271           break;
272         case llvm::Triple::mips:
273         case llvm::Triple::mipsel:
274         case llvm::Triple::ppc:
275         case llvm::Triple::ppc64:
276           this->MCountName = "_mcount";
277           break;
278         case llvm::Triple::arm:
279           this->MCountName = "__mcount";
280           break;
281       }
282 
283     }
284 };
285 
286 // Minix Target
287 template<typename Target>
288 class MinixTargetInfo : public OSTargetInfo<Target> {
289 protected:
290   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
291                             MacroBuilder &Builder) const {
292     // Minix defines
293 
294     Builder.defineMacro("__minix", "3");
295     Builder.defineMacro("_EM_WSIZE", "4");
296     Builder.defineMacro("_EM_PSIZE", "4");
297     Builder.defineMacro("_EM_SSIZE", "2");
298     Builder.defineMacro("_EM_LSIZE", "4");
299     Builder.defineMacro("_EM_FSIZE", "4");
300     Builder.defineMacro("_EM_DSIZE", "8");
301     Builder.defineMacro("__ELF__");
302     DefineStd(Builder, "unix", Opts);
303   }
304 public:
305   MinixTargetInfo(const std::string &triple)
306     : OSTargetInfo<Target>(triple) {
307       this->UserLabelPrefix = "";
308     }
309 };
310 
311 // Linux target
312 template<typename Target>
313 class LinuxTargetInfo : public OSTargetInfo<Target> {
314 protected:
315   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316                             MacroBuilder &Builder) const {
317     // Linux defines; list based off of gcc output
318     DefineStd(Builder, "unix", Opts);
319     DefineStd(Builder, "linux", Opts);
320     Builder.defineMacro("__gnu_linux__");
321     Builder.defineMacro("__ELF__");
322     if (Triple.getEnvironment() == llvm::Triple::Android)
323       Builder.defineMacro("__ANDROID__", "1");
324     if (Opts.POSIXThreads)
325       Builder.defineMacro("_REENTRANT");
326     if (Opts.CPlusPlus)
327       Builder.defineMacro("_GNU_SOURCE");
328   }
329 public:
330   LinuxTargetInfo(const std::string& triple)
331     : OSTargetInfo<Target>(triple) {
332     this->UserLabelPrefix = "";
333     this->WIntType = TargetInfo::UnsignedInt;
334   }
335 
336   virtual const char *getStaticInitSectionSpecifier() const {
337     return ".text.startup";
338   }
339 };
340 
341 // NetBSD Target
342 template<typename Target>
343 class NetBSDTargetInfo : public OSTargetInfo<Target> {
344 protected:
345   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
346                             MacroBuilder &Builder) const {
347     // NetBSD defines; list based off of gcc output
348     Builder.defineMacro("__NetBSD__");
349     Builder.defineMacro("__unix__");
350     Builder.defineMacro("__ELF__");
351     if (Opts.POSIXThreads)
352       Builder.defineMacro("_POSIX_THREADS");
353   }
354 public:
355   NetBSDTargetInfo(const std::string &triple)
356     : OSTargetInfo<Target>(triple) {
357       this->UserLabelPrefix = "";
358     }
359 };
360 
361 // OpenBSD Target
362 template<typename Target>
363 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
364 protected:
365   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
366                             MacroBuilder &Builder) const {
367     // OpenBSD defines; list based off of gcc output
368 
369     Builder.defineMacro("__OpenBSD__");
370     DefineStd(Builder, "unix", Opts);
371     Builder.defineMacro("__ELF__");
372     if (Opts.POSIXThreads)
373       Builder.defineMacro("_REENTRANT");
374   }
375 public:
376   OpenBSDTargetInfo(const std::string &triple)
377     : OSTargetInfo<Target>(triple) {
378       this->UserLabelPrefix = "";
379       this->TLSSupported = false;
380 
381       llvm::Triple Triple(triple);
382       switch (Triple.getArch()) {
383         default:
384         case llvm::Triple::x86:
385         case llvm::Triple::x86_64:
386         case llvm::Triple::arm:
387         case llvm::Triple::sparc:
388           this->MCountName = "__mcount";
389           break;
390         case llvm::Triple::mips64:
391         case llvm::Triple::mips64el:
392         case llvm::Triple::ppc:
393         case llvm::Triple::sparcv9:
394           this->MCountName = "_mcount";
395           break;
396       }
397   }
398 };
399 
400 // Bitrig Target
401 template<typename Target>
402 class BitrigTargetInfo : public OSTargetInfo<Target> {
403 protected:
404   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
405                             MacroBuilder &Builder) const {
406     // Bitrig defines; list based off of gcc output
407 
408     Builder.defineMacro("__Bitrig__");
409     DefineStd(Builder, "unix", Opts);
410     Builder.defineMacro("__ELF__");
411     if (Opts.POSIXThreads)
412       Builder.defineMacro("_REENTRANT");
413   }
414 public:
415   BitrigTargetInfo(const std::string &triple)
416     : OSTargetInfo<Target>(triple) {
417       this->UserLabelPrefix = "";
418       this->TLSSupported = false;
419       this->MCountName = "__mcount";
420   }
421 };
422 
423 // PSP Target
424 template<typename Target>
425 class PSPTargetInfo : public OSTargetInfo<Target> {
426 protected:
427   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
428                             MacroBuilder &Builder) const {
429     // PSP defines; list based on the output of the pspdev gcc toolchain.
430     Builder.defineMacro("PSP");
431     Builder.defineMacro("_PSP");
432     Builder.defineMacro("__psp__");
433     Builder.defineMacro("__ELF__");
434   }
435 public:
436   PSPTargetInfo(const std::string& triple)
437     : OSTargetInfo<Target>(triple) {
438     this->UserLabelPrefix = "";
439   }
440 };
441 
442 // PS3 PPU Target
443 template<typename Target>
444 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
445 protected:
446   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447                             MacroBuilder &Builder) const {
448     // PS3 PPU defines.
449     Builder.defineMacro("__PPC__");
450     Builder.defineMacro("__PPU__");
451     Builder.defineMacro("__CELLOS_LV2__");
452     Builder.defineMacro("__ELF__");
453     Builder.defineMacro("__LP32__");
454     Builder.defineMacro("_ARCH_PPC64");
455     Builder.defineMacro("__powerpc64__");
456   }
457 public:
458   PS3PPUTargetInfo(const std::string& triple)
459     : OSTargetInfo<Target>(triple) {
460     this->UserLabelPrefix = "";
461     this->LongWidth = this->LongAlign = 32;
462     this->PointerWidth = this->PointerAlign = 32;
463     this->IntMaxType = TargetInfo::SignedLongLong;
464     this->UIntMaxType = TargetInfo::UnsignedLongLong;
465     this->Int64Type = TargetInfo::SignedLongLong;
466     this->SizeType = TargetInfo::UnsignedInt;
467     this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
468                               "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
469   }
470 };
471 
472 // FIXME: Need a real SPU target.
473 // PS3 SPU Target
474 template<typename Target>
475 class PS3SPUTargetInfo : public OSTargetInfo<Target> {
476 protected:
477   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
478                             MacroBuilder &Builder) const {
479     // PS3 PPU defines.
480     Builder.defineMacro("__SPU__");
481     Builder.defineMacro("__ELF__");
482   }
483 public:
484   PS3SPUTargetInfo(const std::string& triple)
485     : OSTargetInfo<Target>(triple) {
486     this->UserLabelPrefix = "";
487   }
488 };
489 
490 // AuroraUX target
491 template<typename Target>
492 class AuroraUXTargetInfo : public OSTargetInfo<Target> {
493 protected:
494   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495                             MacroBuilder &Builder) const {
496     DefineStd(Builder, "sun", Opts);
497     DefineStd(Builder, "unix", Opts);
498     Builder.defineMacro("__ELF__");
499     Builder.defineMacro("__svr4__");
500     Builder.defineMacro("__SVR4");
501   }
502 public:
503   AuroraUXTargetInfo(const std::string& triple)
504     : OSTargetInfo<Target>(triple) {
505     this->UserLabelPrefix = "";
506     this->WCharType = this->SignedLong;
507     // FIXME: WIntType should be SignedLong
508   }
509 };
510 
511 // Solaris target
512 template<typename Target>
513 class SolarisTargetInfo : public OSTargetInfo<Target> {
514 protected:
515   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
516                             MacroBuilder &Builder) const {
517     DefineStd(Builder, "sun", Opts);
518     DefineStd(Builder, "unix", Opts);
519     Builder.defineMacro("__ELF__");
520     Builder.defineMacro("__svr4__");
521     Builder.defineMacro("__SVR4");
522     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
523     // newer, but to 500 for everything else.  feature_test.h has a check to
524     // ensure that you are not using C99 with an old version of X/Open or C89
525     // with a new version.
526     if (Opts.C99 || Opts.C11)
527       Builder.defineMacro("_XOPEN_SOURCE", "600");
528     else
529       Builder.defineMacro("_XOPEN_SOURCE", "500");
530     if (Opts.CPlusPlus)
531       Builder.defineMacro("__C99FEATURES__");
532     Builder.defineMacro("_LARGEFILE_SOURCE");
533     Builder.defineMacro("_LARGEFILE64_SOURCE");
534     Builder.defineMacro("__EXTENSIONS__");
535     Builder.defineMacro("_REENTRANT");
536   }
537 public:
538   SolarisTargetInfo(const std::string& triple)
539     : OSTargetInfo<Target>(triple) {
540     this->UserLabelPrefix = "";
541     this->WCharType = this->SignedInt;
542     // FIXME: WIntType should be SignedLong
543   }
544 };
545 
546 // Windows target
547 template<typename Target>
548 class WindowsTargetInfo : public OSTargetInfo<Target> {
549 protected:
550   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
551                             MacroBuilder &Builder) const {
552     Builder.defineMacro("_WIN32");
553   }
554   void getVisualStudioDefines(const LangOptions &Opts,
555                               MacroBuilder &Builder) const {
556     if (Opts.CPlusPlus) {
557       if (Opts.RTTI)
558         Builder.defineMacro("_CPPRTTI");
559 
560       if (Opts.Exceptions)
561         Builder.defineMacro("_CPPUNWIND");
562     }
563 
564     if (!Opts.CharIsSigned)
565       Builder.defineMacro("_CHAR_UNSIGNED");
566 
567     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
568     //        but it works for now.
569     if (Opts.POSIXThreads)
570       Builder.defineMacro("_MT");
571 
572     if (Opts.MSCVersion != 0)
573       Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
574 
575     if (Opts.MicrosoftExt) {
576       Builder.defineMacro("_MSC_EXTENSIONS");
577 
578       if (Opts.CPlusPlus11) {
579         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
580         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
581         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
582       }
583     }
584 
585     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
586   }
587 
588 public:
589   WindowsTargetInfo(const std::string &triple)
590     : OSTargetInfo<Target>(triple) {}
591 };
592 
593 template <typename Target>
594 class NaClTargetInfo : public OSTargetInfo<Target> {
595  protected:
596   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
597                             MacroBuilder &Builder) const {
598     if (Opts.POSIXThreads)
599       Builder.defineMacro("_REENTRANT");
600     if (Opts.CPlusPlus)
601       Builder.defineMacro("_GNU_SOURCE");
602 
603     DefineStd(Builder, "unix", Opts);
604     Builder.defineMacro("__ELF__");
605     Builder.defineMacro("__native_client__");
606   }
607  public:
608   NaClTargetInfo(const std::string &triple)
609     : OSTargetInfo<Target>(triple) {
610     this->UserLabelPrefix = "";
611     this->LongAlign = 32;
612     this->LongWidth = 32;
613     this->PointerAlign = 32;
614     this->PointerWidth = 32;
615     this->IntMaxType = TargetInfo::SignedLongLong;
616     this->UIntMaxType = TargetInfo::UnsignedLongLong;
617     this->Int64Type = TargetInfo::SignedLongLong;
618     this->DoubleAlign = 64;
619     this->LongDoubleWidth = 64;
620     this->LongDoubleAlign = 64;
621     this->SizeType = TargetInfo::UnsignedInt;
622     this->PtrDiffType = TargetInfo::SignedInt;
623     this->IntPtrType = TargetInfo::SignedInt;
624     // RegParmMax is inherited from the underlying architecture
625     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
626     this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
627                               "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
628   }
629   virtual typename Target::CallingConvCheckResult checkCallingConvention(
630       CallingConv CC) const {
631     return CC == CC_PnaclCall ? Target::CCCR_OK :
632         Target::checkCallingConvention(CC);
633   }
634 };
635 } // end anonymous namespace.
636 
637 //===----------------------------------------------------------------------===//
638 // Specific target implementations.
639 //===----------------------------------------------------------------------===//
640 
641 namespace {
642 // PPC abstract base class
643 class PPCTargetInfo : public TargetInfo {
644   static const Builtin::Info BuiltinInfo[];
645   static const char * const GCCRegNames[];
646   static const TargetInfo::GCCRegAlias GCCRegAliases[];
647   std::string CPU;
648 public:
649   PPCTargetInfo(const std::string& triple) : TargetInfo(triple) {
650     LongDoubleWidth = LongDoubleAlign = 128;
651     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
652   }
653 
654   /// \brief Flags for architecture specific defines.
655   typedef enum {
656     ArchDefineNone  = 0,
657     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
658     ArchDefinePpcgr = 1 << 1,
659     ArchDefinePpcsq = 1 << 2,
660     ArchDefine440   = 1 << 3,
661     ArchDefine603   = 1 << 4,
662     ArchDefine604   = 1 << 5,
663     ArchDefinePwr4  = 1 << 6,
664     ArchDefinePwr5  = 1 << 7,
665     ArchDefinePwr5x = 1 << 8,
666     ArchDefinePwr6  = 1 << 9,
667     ArchDefinePwr6x = 1 << 10,
668     ArchDefinePwr7  = 1 << 11,
669     ArchDefineA2    = 1 << 12,
670     ArchDefineA2q   = 1 << 13
671   } ArchDefineTypes;
672 
673   // Note: GCC recognizes the following additional cpus:
674   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
675   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
676   //  titan, rs64.
677   virtual bool setCPU(const std::string &Name) {
678     bool CPUKnown = llvm::StringSwitch<bool>(Name)
679       .Case("generic", true)
680       .Case("440", true)
681       .Case("450", true)
682       .Case("601", true)
683       .Case("602", true)
684       .Case("603", true)
685       .Case("603e", true)
686       .Case("603ev", true)
687       .Case("604", true)
688       .Case("604e", true)
689       .Case("620", true)
690       .Case("630", true)
691       .Case("g3", true)
692       .Case("7400", true)
693       .Case("g4", true)
694       .Case("7450", true)
695       .Case("g4+", true)
696       .Case("750", true)
697       .Case("970", true)
698       .Case("g5", true)
699       .Case("a2", true)
700       .Case("a2q", true)
701       .Case("e500mc", true)
702       .Case("e5500", true)
703       .Case("power3", true)
704       .Case("pwr3", true)
705       .Case("power4", true)
706       .Case("pwr4", true)
707       .Case("power5", true)
708       .Case("pwr5", true)
709       .Case("power5x", true)
710       .Case("pwr5x", true)
711       .Case("power6", true)
712       .Case("pwr6", true)
713       .Case("power6x", true)
714       .Case("pwr6x", true)
715       .Case("power7", true)
716       .Case("pwr7", true)
717       .Case("powerpc", true)
718       .Case("ppc", true)
719       .Case("powerpc64", true)
720       .Case("ppc64", true)
721       .Default(false);
722 
723     if (CPUKnown)
724       CPU = Name;
725 
726     return CPUKnown;
727   }
728 
729   virtual void getTargetBuiltins(const Builtin::Info *&Records,
730                                  unsigned &NumRecords) const {
731     Records = BuiltinInfo;
732     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
733   }
734 
735   virtual bool isCLZForZeroUndef() const { return false; }
736 
737   virtual void getTargetDefines(const LangOptions &Opts,
738                                 MacroBuilder &Builder) const;
739 
740   virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
741 
742   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
743                                  StringRef Name,
744                                  bool Enabled) const;
745 
746   virtual bool hasFeature(StringRef Feature) const;
747 
748   virtual void getGCCRegNames(const char * const *&Names,
749                               unsigned &NumNames) const;
750   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
751                                 unsigned &NumAliases) const;
752   virtual bool validateAsmConstraint(const char *&Name,
753                                      TargetInfo::ConstraintInfo &Info) const {
754     switch (*Name) {
755     default: return false;
756     case 'O': // Zero
757       break;
758     case 'b': // Base register
759     case 'f': // Floating point register
760       Info.setAllowsRegister();
761       break;
762     // FIXME: The following are added to allow parsing.
763     // I just took a guess at what the actions should be.
764     // Also, is more specific checking needed?  I.e. specific registers?
765     case 'd': // Floating point register (containing 64-bit value)
766     case 'v': // Altivec vector register
767       Info.setAllowsRegister();
768       break;
769     case 'w':
770       switch (Name[1]) {
771         case 'd':// VSX vector register to hold vector double data
772         case 'f':// VSX vector register to hold vector float data
773         case 's':// VSX vector register to hold scalar float data
774         case 'a':// Any VSX register
775           break;
776         default:
777           return false;
778       }
779       Info.setAllowsRegister();
780       Name++; // Skip over 'w'.
781       break;
782     case 'h': // `MQ', `CTR', or `LINK' register
783     case 'q': // `MQ' register
784     case 'c': // `CTR' register
785     case 'l': // `LINK' register
786     case 'x': // `CR' register (condition register) number 0
787     case 'y': // `CR' register (condition register)
788     case 'z': // `XER[CA]' carry bit (part of the XER register)
789       Info.setAllowsRegister();
790       break;
791     case 'I': // Signed 16-bit constant
792     case 'J': // Unsigned 16-bit constant shifted left 16 bits
793               //  (use `L' instead for SImode constants)
794     case 'K': // Unsigned 16-bit constant
795     case 'L': // Signed 16-bit constant shifted left 16 bits
796     case 'M': // Constant larger than 31
797     case 'N': // Exact power of 2
798     case 'P': // Constant whose negation is a signed 16-bit constant
799     case 'G': // Floating point constant that can be loaded into a
800               // register with one instruction per word
801     case 'H': // Integer/Floating point constant that can be loaded
802               // into a register using three instructions
803       break;
804     case 'm': // Memory operand. Note that on PowerPC targets, m can
805               // include addresses that update the base register. It
806               // is therefore only safe to use `m' in an asm statement
807               // if that asm statement accesses the operand exactly once.
808               // The asm statement must also use `%U<opno>' as a
809               // placeholder for the "update" flag in the corresponding
810               // load or store instruction. For example:
811               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
812               // is correct but:
813               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
814               // is not. Use es rather than m if you don't want the base
815               // register to be updated.
816     case 'e':
817       if (Name[1] != 's')
818           return false;
819               // es: A "stable" memory operand; that is, one which does not
820               // include any automodification of the base register. Unlike
821               // `m', this constraint can be used in asm statements that
822               // might access the operand several times, or that might not
823               // access it at all.
824       Info.setAllowsMemory();
825       Name++; // Skip over 'e'.
826       break;
827     case 'Q': // Memory operand that is an offset from a register (it is
828               // usually better to use `m' or `es' in asm statements)
829     case 'Z': // Memory operand that is an indexed or indirect from a
830               // register (it is usually better to use `m' or `es' in
831               // asm statements)
832       Info.setAllowsMemory();
833       Info.setAllowsRegister();
834       break;
835     case 'R': // AIX TOC entry
836     case 'a': // Address operand that is an indexed or indirect from a
837               // register (`p' is preferable for asm statements)
838     case 'S': // Constant suitable as a 64-bit mask operand
839     case 'T': // Constant suitable as a 32-bit mask operand
840     case 'U': // System V Release 4 small data area reference
841     case 't': // AND masks that can be performed by two rldic{l, r}
842               // instructions
843     case 'W': // Vector constant that does not require memory
844     case 'j': // Vector constant that is all zeros.
845       break;
846     // End FIXME.
847     }
848     return true;
849   }
850   virtual const char *getClobbers() const {
851     return "";
852   }
853   int getEHDataRegisterNumber(unsigned RegNo) const {
854     if (RegNo == 0) return 3;
855     if (RegNo == 1) return 4;
856     return -1;
857   }
858 };
859 
860 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
861 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
862 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
863                                               ALL_LANGUAGES },
864 #include "clang/Basic/BuiltinsPPC.def"
865 };
866 
867 
868 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
869 /// #defines that are not tied to a specific subtarget.
870 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
871                                      MacroBuilder &Builder) const {
872   // Target identification.
873   Builder.defineMacro("__ppc__");
874   Builder.defineMacro("__PPC__");
875   Builder.defineMacro("_ARCH_PPC");
876   Builder.defineMacro("__powerpc__");
877   Builder.defineMacro("__POWERPC__");
878   if (PointerWidth == 64) {
879     Builder.defineMacro("_ARCH_PPC64");
880     Builder.defineMacro("__powerpc64__");
881     Builder.defineMacro("__ppc64__");
882     Builder.defineMacro("__PPC64__");
883   }
884 
885   // Target properties.
886   if (getTriple().getOS() != llvm::Triple::NetBSD &&
887       getTriple().getOS() != llvm::Triple::OpenBSD)
888     Builder.defineMacro("_BIG_ENDIAN");
889   Builder.defineMacro("__BIG_ENDIAN__");
890 
891   // Subtarget options.
892   Builder.defineMacro("__NATURAL_ALIGNMENT__");
893   Builder.defineMacro("__REGISTER_PREFIX__", "");
894 
895   // FIXME: Should be controlled by command line option.
896   Builder.defineMacro("__LONG_DOUBLE_128__");
897 
898   if (Opts.AltiVec) {
899     Builder.defineMacro("__VEC__", "10206");
900     Builder.defineMacro("__ALTIVEC__");
901   }
902 
903   // CPU identification.
904   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
905     .Case("440",   ArchDefineName)
906     .Case("450",   ArchDefineName | ArchDefine440)
907     .Case("601",   ArchDefineName)
908     .Case("602",   ArchDefineName | ArchDefinePpcgr)
909     .Case("603",   ArchDefineName | ArchDefinePpcgr)
910     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
911     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
912     .Case("604",   ArchDefineName | ArchDefinePpcgr)
913     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
914     .Case("620",   ArchDefineName | ArchDefinePpcgr)
915     .Case("630",   ArchDefineName | ArchDefinePpcgr)
916     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
917     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
918     .Case("750",   ArchDefineName | ArchDefinePpcgr)
919     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
920                      | ArchDefinePpcsq)
921     .Case("a2",    ArchDefineA2)
922     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
923     .Case("pwr3",  ArchDefinePpcgr)
924     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
925     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
926                      | ArchDefinePpcsq)
927     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
928                      | ArchDefinePpcgr | ArchDefinePpcsq)
929     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
930                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
931     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
932                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
933                      | ArchDefinePpcsq)
934     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
935                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
936                      | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
937     .Case("power3",  ArchDefinePpcgr)
938     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
939     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
940                        | ArchDefinePpcsq)
941     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
942                        | ArchDefinePpcgr | ArchDefinePpcsq)
943     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
944                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
945     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
946                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
947                        | ArchDefinePpcsq)
948     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
949                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
950                        | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
951     .Default(ArchDefineNone);
952 
953   if (defs & ArchDefineName)
954     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
955   if (defs & ArchDefinePpcgr)
956     Builder.defineMacro("_ARCH_PPCGR");
957   if (defs & ArchDefinePpcsq)
958     Builder.defineMacro("_ARCH_PPCSQ");
959   if (defs & ArchDefine440)
960     Builder.defineMacro("_ARCH_440");
961   if (defs & ArchDefine603)
962     Builder.defineMacro("_ARCH_603");
963   if (defs & ArchDefine604)
964     Builder.defineMacro("_ARCH_604");
965   if (defs & ArchDefinePwr4)
966     Builder.defineMacro("_ARCH_PWR4");
967   if (defs & ArchDefinePwr5)
968     Builder.defineMacro("_ARCH_PWR5");
969   if (defs & ArchDefinePwr5x)
970     Builder.defineMacro("_ARCH_PWR5X");
971   if (defs & ArchDefinePwr6)
972     Builder.defineMacro("_ARCH_PWR6");
973   if (defs & ArchDefinePwr6x)
974     Builder.defineMacro("_ARCH_PWR6X");
975   if (defs & ArchDefinePwr7)
976     Builder.defineMacro("_ARCH_PWR7");
977   if (defs & ArchDefineA2)
978     Builder.defineMacro("_ARCH_A2");
979   if (defs & ArchDefineA2q) {
980     Builder.defineMacro("_ARCH_A2Q");
981     Builder.defineMacro("_ARCH_QP");
982   }
983 
984   if (getTriple().getVendor() == llvm::Triple::BGQ) {
985     Builder.defineMacro("__bg__");
986     Builder.defineMacro("__THW_BLUEGENE__");
987     Builder.defineMacro("__bgq__");
988     Builder.defineMacro("__TOS_BGQ__");
989   }
990 
991   // FIXME: The following are not yet generated here by Clang, but are
992   //        generated by GCC:
993   //
994   //   _SOFT_FLOAT_
995   //   __RECIP_PRECISION__
996   //   __APPLE_ALTIVEC__
997   //   __VSX__
998   //   __RECIP__
999   //   __RECIPF__
1000   //   __RSQRTE__
1001   //   __RSQRTEF__
1002   //   _SOFT_DOUBLE_
1003   //   __NO_LWSYNC__
1004   //   __HAVE_BSWAP__
1005   //   __LONGDOUBLE128
1006   //   __CMODEL_MEDIUM__
1007   //   __CMODEL_LARGE__
1008   //   _CALL_SYSV
1009   //   _CALL_DARWIN
1010   //   __NO_FPRS__
1011 }
1012 
1013 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1014   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1015     .Case("7400", true)
1016     .Case("g4", true)
1017     .Case("7450", true)
1018     .Case("g4+", true)
1019     .Case("970", true)
1020     .Case("g5", true)
1021     .Case("pwr6", true)
1022     .Case("pwr7", true)
1023     .Case("ppc64", true)
1024     .Default(false);
1025 
1026   Features["qpx"] = (CPU == "a2q");
1027 }
1028 
1029 bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1030                                          StringRef Name,
1031                                          bool Enabled) const {
1032   if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" ||
1033       Name == "popcntd" || Name == "qpx") {
1034     Features[Name] = Enabled;
1035     return true;
1036   }
1037 
1038   return false;
1039 }
1040 
1041 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1042   return Feature == "powerpc";
1043 }
1044 
1045 
1046 const char * const PPCTargetInfo::GCCRegNames[] = {
1047   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1048   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1049   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1050   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1051   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1052   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1053   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1054   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1055   "mq", "lr", "ctr", "ap",
1056   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1057   "xer",
1058   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1059   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1060   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1061   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1062   "vrsave", "vscr",
1063   "spe_acc", "spefscr",
1064   "sfp"
1065 };
1066 
1067 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1068                                    unsigned &NumNames) const {
1069   Names = GCCRegNames;
1070   NumNames = llvm::array_lengthof(GCCRegNames);
1071 }
1072 
1073 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1074   // While some of these aliases do map to different registers
1075   // they still share the same register name.
1076   { { "0" }, "r0" },
1077   { { "1"}, "r1" },
1078   { { "2" }, "r2" },
1079   { { "3" }, "r3" },
1080   { { "4" }, "r4" },
1081   { { "5" }, "r5" },
1082   { { "6" }, "r6" },
1083   { { "7" }, "r7" },
1084   { { "8" }, "r8" },
1085   { { "9" }, "r9" },
1086   { { "10" }, "r10" },
1087   { { "11" }, "r11" },
1088   { { "12" }, "r12" },
1089   { { "13" }, "r13" },
1090   { { "14" }, "r14" },
1091   { { "15" }, "r15" },
1092   { { "16" }, "r16" },
1093   { { "17" }, "r17" },
1094   { { "18" }, "r18" },
1095   { { "19" }, "r19" },
1096   { { "20" }, "r20" },
1097   { { "21" }, "r21" },
1098   { { "22" }, "r22" },
1099   { { "23" }, "r23" },
1100   { { "24" }, "r24" },
1101   { { "25" }, "r25" },
1102   { { "26" }, "r26" },
1103   { { "27" }, "r27" },
1104   { { "28" }, "r28" },
1105   { { "29" }, "r29" },
1106   { { "30" }, "r30" },
1107   { { "31" }, "r31" },
1108   { { "fr0" }, "f0" },
1109   { { "fr1" }, "f1" },
1110   { { "fr2" }, "f2" },
1111   { { "fr3" }, "f3" },
1112   { { "fr4" }, "f4" },
1113   { { "fr5" }, "f5" },
1114   { { "fr6" }, "f6" },
1115   { { "fr7" }, "f7" },
1116   { { "fr8" }, "f8" },
1117   { { "fr9" }, "f9" },
1118   { { "fr10" }, "f10" },
1119   { { "fr11" }, "f11" },
1120   { { "fr12" }, "f12" },
1121   { { "fr13" }, "f13" },
1122   { { "fr14" }, "f14" },
1123   { { "fr15" }, "f15" },
1124   { { "fr16" }, "f16" },
1125   { { "fr17" }, "f17" },
1126   { { "fr18" }, "f18" },
1127   { { "fr19" }, "f19" },
1128   { { "fr20" }, "f20" },
1129   { { "fr21" }, "f21" },
1130   { { "fr22" }, "f22" },
1131   { { "fr23" }, "f23" },
1132   { { "fr24" }, "f24" },
1133   { { "fr25" }, "f25" },
1134   { { "fr26" }, "f26" },
1135   { { "fr27" }, "f27" },
1136   { { "fr28" }, "f28" },
1137   { { "fr29" }, "f29" },
1138   { { "fr30" }, "f30" },
1139   { { "fr31" }, "f31" },
1140   { { "cc" }, "cr0" },
1141 };
1142 
1143 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1144                                      unsigned &NumAliases) const {
1145   Aliases = GCCRegAliases;
1146   NumAliases = llvm::array_lengthof(GCCRegAliases);
1147 }
1148 } // end anonymous namespace.
1149 
1150 namespace {
1151 class PPC32TargetInfo : public PPCTargetInfo {
1152 public:
1153   PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) {
1154     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1155                         "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1156 
1157     switch (getTriple().getOS()) {
1158     case llvm::Triple::Linux:
1159     case llvm::Triple::FreeBSD:
1160     case llvm::Triple::NetBSD:
1161       SizeType = UnsignedInt;
1162       PtrDiffType = SignedInt;
1163       IntPtrType = SignedInt;
1164       break;
1165     default:
1166       break;
1167     }
1168 
1169     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1170       LongDoubleWidth = LongDoubleAlign = 64;
1171       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1172     }
1173 
1174     // PPC32 supports atomics up to 4 bytes.
1175     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1176   }
1177 
1178   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1179     // This is the ELF definition, and is overridden by the Darwin sub-target
1180     return TargetInfo::PowerABIBuiltinVaList;
1181   }
1182 };
1183 } // end anonymous namespace.
1184 
1185 namespace {
1186 class PPC64TargetInfo : public PPCTargetInfo {
1187 public:
1188   PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) {
1189     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1190     IntMaxType = SignedLong;
1191     UIntMaxType = UnsignedLong;
1192     Int64Type = SignedLong;
1193 
1194     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1195       LongDoubleWidth = LongDoubleAlign = 64;
1196       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1197       DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1198                           "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1199                           "v128:128:128-n32:64";
1200     } else
1201       DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1202                           "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1203                           "v128:128:128-n32:64";
1204 
1205     // PPC64 supports atomics up to 8 bytes.
1206     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1207   }
1208   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1209     return TargetInfo::CharPtrBuiltinVaList;
1210   }
1211 };
1212 } // end anonymous namespace.
1213 
1214 
1215 namespace {
1216 class DarwinPPC32TargetInfo :
1217   public DarwinTargetInfo<PPC32TargetInfo> {
1218 public:
1219   DarwinPPC32TargetInfo(const std::string& triple)
1220     : DarwinTargetInfo<PPC32TargetInfo>(triple) {
1221     HasAlignMac68kSupport = true;
1222     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1223     PtrDiffType = SignedInt;	// for http://llvm.org/bugs/show_bug.cgi?id=15726
1224     LongLongAlign = 32;
1225     SuitableAlign = 128;
1226     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1227                         "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1228   }
1229   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1230     return TargetInfo::CharPtrBuiltinVaList;
1231   }
1232 };
1233 
1234 class DarwinPPC64TargetInfo :
1235   public DarwinTargetInfo<PPC64TargetInfo> {
1236 public:
1237   DarwinPPC64TargetInfo(const std::string& triple)
1238     : DarwinTargetInfo<PPC64TargetInfo>(triple) {
1239     HasAlignMac68kSupport = true;
1240     SuitableAlign = 128;
1241     DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1242                         "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1243   }
1244 };
1245 } // end anonymous namespace.
1246 
1247 namespace {
1248   static const unsigned NVPTXAddrSpaceMap[] = {
1249     1,    // opencl_global
1250     3,    // opencl_local
1251     4,    // opencl_constant
1252     1,    // cuda_device
1253     4,    // cuda_constant
1254     3,    // cuda_shared
1255   };
1256   class NVPTXTargetInfo : public TargetInfo {
1257     static const char * const GCCRegNames[];
1258     static const Builtin::Info BuiltinInfo[];
1259     std::vector<StringRef> AvailableFeatures;
1260   public:
1261     NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) {
1262       BigEndian = false;
1263       TLSSupported = false;
1264       LongWidth = LongAlign = 64;
1265       AddrSpaceMap = &NVPTXAddrSpaceMap;
1266       // Define available target features
1267       // These must be defined in sorted order!
1268       NoAsmVariants = true;
1269     }
1270     virtual void getTargetDefines(const LangOptions &Opts,
1271                                   MacroBuilder &Builder) const {
1272       Builder.defineMacro("__PTX__");
1273       Builder.defineMacro("__NVPTX__");
1274     }
1275     virtual void getTargetBuiltins(const Builtin::Info *&Records,
1276                                    unsigned &NumRecords) const {
1277       Records = BuiltinInfo;
1278       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1279     }
1280     virtual bool hasFeature(StringRef Feature) const {
1281       return Feature == "ptx" || Feature == "nvptx";
1282     }
1283 
1284     virtual void getGCCRegNames(const char * const *&Names,
1285                                 unsigned &NumNames) const;
1286     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1287                                   unsigned &NumAliases) const {
1288       // No aliases.
1289       Aliases = 0;
1290       NumAliases = 0;
1291     }
1292     virtual bool validateAsmConstraint(const char *&Name,
1293                                        TargetInfo::ConstraintInfo &Info) const {
1294       switch (*Name) {
1295       default: return false;
1296       case 'c':
1297       case 'h':
1298       case 'r':
1299       case 'l':
1300       case 'f':
1301       case 'd':
1302         Info.setAllowsRegister();
1303         return true;
1304       }
1305     }
1306     virtual const char *getClobbers() const {
1307       // FIXME: Is this really right?
1308       return "";
1309     }
1310     virtual BuiltinVaListKind getBuiltinVaListKind() const {
1311       // FIXME: implement
1312       return TargetInfo::CharPtrBuiltinVaList;
1313     }
1314     virtual bool setCPU(const std::string &Name) {
1315       bool Valid = llvm::StringSwitch<bool>(Name)
1316         .Case("sm_20", true)
1317         .Case("sm_21", true)
1318         .Case("sm_30", true)
1319         .Case("sm_35", true)
1320         .Default(false);
1321 
1322       return Valid;
1323     }
1324     virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1325                                    StringRef Name,
1326                                    bool Enabled) const;
1327   };
1328 
1329   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1330 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1331 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1332                                               ALL_LANGUAGES },
1333 #include "clang/Basic/BuiltinsNVPTX.def"
1334   };
1335 
1336   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1337     "r0"
1338   };
1339 
1340   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1341                                      unsigned &NumNames) const {
1342     Names = GCCRegNames;
1343     NumNames = llvm::array_lengthof(GCCRegNames);
1344   }
1345 
1346   bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1347                                           StringRef Name,
1348                                           bool Enabled) const {
1349     if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1350                           Name)) {
1351       Features[Name] = Enabled;
1352       return true;
1353     } else {
1354       return false;
1355     }
1356   }
1357 
1358   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1359   public:
1360     NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1361       PointerWidth = PointerAlign = 32;
1362       SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1363       DescriptionString
1364         = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1365           "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1366           "n16:32:64";
1367   }
1368   };
1369 
1370   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1371   public:
1372     NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1373       PointerWidth = PointerAlign = 64;
1374       SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1375       DescriptionString
1376         = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1377           "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1378           "n16:32:64";
1379   }
1380   };
1381 }
1382 
1383 namespace {
1384 
1385 static const unsigned R600AddrSpaceMap[] = {
1386   1,    // opencl_global
1387   3,    // opencl_local
1388   2,    // opencl_constant
1389   1,    // cuda_device
1390   2,    // cuda_constant
1391   3     // cuda_shared
1392 };
1393 
1394 static const char *DescriptionStringR600 =
1395   "e"
1396   "-p:32:32:32"
1397   "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1398   "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1399   "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1400   "-n32:64";
1401 
1402 static const char *DescriptionStringR600DoubleOps =
1403   "e"
1404   "-p:32:32:32"
1405   "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1406   "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1407   "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1408   "-n32:64";
1409 
1410 static const char *DescriptionStringSI =
1411   "e"
1412   "-p:64:64:64"
1413   "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1414   "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1415   "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1416   "-n32:64";
1417 
1418 class R600TargetInfo : public TargetInfo {
1419   /// \brief The GPU profiles supported by the R600 target.
1420   enum GPUKind {
1421     GK_NONE,
1422     GK_R600,
1423     GK_R600_DOUBLE_OPS,
1424     GK_R700,
1425     GK_R700_DOUBLE_OPS,
1426     GK_EVERGREEN,
1427     GK_EVERGREEN_DOUBLE_OPS,
1428     GK_NORTHERN_ISLANDS,
1429     GK_CAYMAN,
1430     GK_SOUTHERN_ISLANDS
1431   } GPU;
1432 
1433 public:
1434   R600TargetInfo(const std::string& triple)
1435     : TargetInfo(triple),
1436       GPU(GK_R600) {
1437     DescriptionString = DescriptionStringR600;
1438     AddrSpaceMap = &R600AddrSpaceMap;
1439   }
1440 
1441   virtual const char * getClobbers() const {
1442     return "";
1443   }
1444 
1445   virtual void getGCCRegNames(const char * const *&Names,
1446                               unsigned &numNames) const  {
1447     Names = NULL;
1448     numNames = 0;
1449   }
1450 
1451   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1452                                 unsigned &NumAliases) const {
1453     Aliases = NULL;
1454     NumAliases = 0;
1455   }
1456 
1457   virtual bool validateAsmConstraint(const char *&Name,
1458                                      TargetInfo::ConstraintInfo &info) const {
1459     return true;
1460   }
1461 
1462   virtual void getTargetBuiltins(const Builtin::Info *&Records,
1463                                  unsigned &NumRecords) const {
1464     Records = NULL;
1465     NumRecords = 0;
1466   }
1467 
1468 
1469   virtual void getTargetDefines(const LangOptions &Opts,
1470                                 MacroBuilder &Builder) const {
1471     Builder.defineMacro("__R600__");
1472   }
1473 
1474   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1475     return TargetInfo::CharPtrBuiltinVaList;
1476   }
1477 
1478   virtual bool setCPU(const std::string &Name) {
1479     GPU = llvm::StringSwitch<GPUKind>(Name)
1480       .Case("r600" ,    GK_R600)
1481       .Case("rv610",    GK_R600)
1482       .Case("rv620",    GK_R600)
1483       .Case("rv630",    GK_R600)
1484       .Case("rv635",    GK_R600)
1485       .Case("rs780",    GK_R600)
1486       .Case("rs880",    GK_R600)
1487       .Case("rv670",    GK_R600_DOUBLE_OPS)
1488       .Case("rv710",    GK_R700)
1489       .Case("rv730",    GK_R700)
1490       .Case("rv740",    GK_R700_DOUBLE_OPS)
1491       .Case("rv770",    GK_R700_DOUBLE_OPS)
1492       .Case("palm",     GK_EVERGREEN)
1493       .Case("cedar",    GK_EVERGREEN)
1494       .Case("sumo",     GK_EVERGREEN)
1495       .Case("sumo2",    GK_EVERGREEN)
1496       .Case("redwood",  GK_EVERGREEN)
1497       .Case("juniper",  GK_EVERGREEN)
1498       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1499       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1500       .Case("barts",    GK_NORTHERN_ISLANDS)
1501       .Case("turks",    GK_NORTHERN_ISLANDS)
1502       .Case("caicos",   GK_NORTHERN_ISLANDS)
1503       .Case("cayman",   GK_CAYMAN)
1504       .Case("aruba",    GK_CAYMAN)
1505       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1506       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1507       .Case("verde",    GK_SOUTHERN_ISLANDS)
1508       .Case("oland",    GK_SOUTHERN_ISLANDS)
1509       .Default(GK_NONE);
1510 
1511     if (GPU == GK_NONE) {
1512       return false;
1513     }
1514 
1515     // Set the correct data layout
1516     switch (GPU) {
1517     case GK_NONE:
1518     case GK_R600:
1519     case GK_R700:
1520     case GK_EVERGREEN:
1521     case GK_NORTHERN_ISLANDS:
1522       DescriptionString = DescriptionStringR600;
1523       break;
1524     case GK_R600_DOUBLE_OPS:
1525     case GK_R700_DOUBLE_OPS:
1526     case GK_EVERGREEN_DOUBLE_OPS:
1527     case GK_CAYMAN:
1528       DescriptionString = DescriptionStringR600DoubleOps;
1529       break;
1530     case GK_SOUTHERN_ISLANDS:
1531       DescriptionString = DescriptionStringSI;
1532       break;
1533     }
1534 
1535     return true;
1536   }
1537 };
1538 
1539 } // end anonymous namespace
1540 
1541 namespace {
1542 // MBlaze abstract base class
1543 class MBlazeTargetInfo : public TargetInfo {
1544   static const char * const GCCRegNames[];
1545   static const TargetInfo::GCCRegAlias GCCRegAliases[];
1546 
1547 public:
1548   MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) {
1549     DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1550   }
1551 
1552   virtual void getTargetBuiltins(const Builtin::Info *&Records,
1553                                  unsigned &NumRecords) const {
1554     // FIXME: Implement.
1555     Records = 0;
1556     NumRecords = 0;
1557   }
1558 
1559   virtual void getTargetDefines(const LangOptions &Opts,
1560                                 MacroBuilder &Builder) const;
1561 
1562   virtual bool hasFeature(StringRef Feature) const {
1563     return Feature == "mblaze";
1564   }
1565 
1566   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1567     return TargetInfo::CharPtrBuiltinVaList;
1568   }
1569   virtual const char *getTargetPrefix() const {
1570     return "mblaze";
1571   }
1572   virtual void getGCCRegNames(const char * const *&Names,
1573                               unsigned &NumNames) const;
1574   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1575                                 unsigned &NumAliases) const;
1576   virtual bool validateAsmConstraint(const char *&Name,
1577                                      TargetInfo::ConstraintInfo &Info) const {
1578     switch (*Name) {
1579     default: return false;
1580     case 'O': // Zero
1581       return true;
1582     case 'b': // Base register
1583     case 'f': // Floating point register
1584       Info.setAllowsRegister();
1585       return true;
1586     }
1587   }
1588   virtual const char *getClobbers() const {
1589     return "";
1590   }
1591 };
1592 
1593 /// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1594 /// #defines that are not tied to a specific subtarget.
1595 void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1596                                      MacroBuilder &Builder) const {
1597   // Target identification.
1598   Builder.defineMacro("__microblaze__");
1599   Builder.defineMacro("_ARCH_MICROBLAZE");
1600   Builder.defineMacro("__MICROBLAZE__");
1601 
1602   // Target properties.
1603   Builder.defineMacro("_BIG_ENDIAN");
1604   Builder.defineMacro("__BIG_ENDIAN__");
1605 
1606   // Subtarget options.
1607   Builder.defineMacro("__REGISTER_PREFIX__", "");
1608 }
1609 
1610 
1611 const char * const MBlazeTargetInfo::GCCRegNames[] = {
1612   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
1613   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
1614   "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
1615   "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
1616   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
1617   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1618   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1619   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1620   "hi",   "lo",   "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1621   "$fcc5","$fcc6","$fcc7","$ap",  "$rap", "$frp"
1622 };
1623 
1624 void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1625                                    unsigned &NumNames) const {
1626   Names = GCCRegNames;
1627   NumNames = llvm::array_lengthof(GCCRegNames);
1628 }
1629 
1630 const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1631   { {"f0"},  "r0" },
1632   { {"f1"},  "r1" },
1633   { {"f2"},  "r2" },
1634   { {"f3"},  "r3" },
1635   { {"f4"},  "r4" },
1636   { {"f5"},  "r5" },
1637   { {"f6"},  "r6" },
1638   { {"f7"},  "r7" },
1639   { {"f8"},  "r8" },
1640   { {"f9"},  "r9" },
1641   { {"f10"}, "r10" },
1642   { {"f11"}, "r11" },
1643   { {"f12"}, "r12" },
1644   { {"f13"}, "r13" },
1645   { {"f14"}, "r14" },
1646   { {"f15"}, "r15" },
1647   { {"f16"}, "r16" },
1648   { {"f17"}, "r17" },
1649   { {"f18"}, "r18" },
1650   { {"f19"}, "r19" },
1651   { {"f20"}, "r20" },
1652   { {"f21"}, "r21" },
1653   { {"f22"}, "r22" },
1654   { {"f23"}, "r23" },
1655   { {"f24"}, "r24" },
1656   { {"f25"}, "r25" },
1657   { {"f26"}, "r26" },
1658   { {"f27"}, "r27" },
1659   { {"f28"}, "r28" },
1660   { {"f29"}, "r29" },
1661   { {"f30"}, "r30" },
1662   { {"f31"}, "r31" },
1663 };
1664 
1665 void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1666                                      unsigned &NumAliases) const {
1667   Aliases = GCCRegAliases;
1668   NumAliases = llvm::array_lengthof(GCCRegAliases);
1669 }
1670 } // end anonymous namespace.
1671 
1672 namespace {
1673 // Namespace for x86 abstract base class
1674 const Builtin::Info BuiltinInfo[] = {
1675 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1676 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1677                                               ALL_LANGUAGES },
1678 #include "clang/Basic/BuiltinsX86.def"
1679 };
1680 
1681 static const char* const GCCRegNames[] = {
1682   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1683   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1684   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1685   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1686   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1687   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1688   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1689   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1690   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1691 };
1692 
1693 const TargetInfo::AddlRegName AddlRegNames[] = {
1694   { { "al", "ah", "eax", "rax" }, 0 },
1695   { { "bl", "bh", "ebx", "rbx" }, 3 },
1696   { { "cl", "ch", "ecx", "rcx" }, 2 },
1697   { { "dl", "dh", "edx", "rdx" }, 1 },
1698   { { "esi", "rsi" }, 4 },
1699   { { "edi", "rdi" }, 5 },
1700   { { "esp", "rsp" }, 7 },
1701   { { "ebp", "rbp" }, 6 },
1702 };
1703 
1704 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1705 // most of the implementation can be shared.
1706 class X86TargetInfo : public TargetInfo {
1707   enum X86SSEEnum {
1708     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1709   } SSELevel;
1710   enum MMX3DNowEnum {
1711     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1712   } MMX3DNowLevel;
1713 
1714   bool HasAES;
1715   bool HasPCLMUL;
1716   bool HasLZCNT;
1717   bool HasRDRND;
1718   bool HasBMI;
1719   bool HasBMI2;
1720   bool HasPOPCNT;
1721   bool HasRTM;
1722   bool HasPRFCHW;
1723   bool HasRDSEED;
1724   bool HasSSE4a;
1725   bool HasFMA4;
1726   bool HasFMA;
1727   bool HasXOP;
1728   bool HasF16C;
1729 
1730   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1731   ///
1732   /// Each enumeration represents a particular CPU supported by Clang. These
1733   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1734   enum CPUKind {
1735     CK_Generic,
1736 
1737     /// \name i386
1738     /// i386-generation processors.
1739     //@{
1740     CK_i386,
1741     //@}
1742 
1743     /// \name i486
1744     /// i486-generation processors.
1745     //@{
1746     CK_i486,
1747     CK_WinChipC6,
1748     CK_WinChip2,
1749     CK_C3,
1750     //@}
1751 
1752     /// \name i586
1753     /// i586-generation processors, P5 microarchitecture based.
1754     //@{
1755     CK_i586,
1756     CK_Pentium,
1757     CK_PentiumMMX,
1758     //@}
1759 
1760     /// \name i686
1761     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1762     //@{
1763     CK_i686,
1764     CK_PentiumPro,
1765     CK_Pentium2,
1766     CK_Pentium3,
1767     CK_Pentium3M,
1768     CK_PentiumM,
1769     CK_C3_2,
1770 
1771     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1772     /// Clang however has some logic to suport this.
1773     // FIXME: Warn, deprecate, and potentially remove this.
1774     CK_Yonah,
1775     //@}
1776 
1777     /// \name Netburst
1778     /// Netburst microarchitecture based processors.
1779     //@{
1780     CK_Pentium4,
1781     CK_Pentium4M,
1782     CK_Prescott,
1783     CK_Nocona,
1784     //@}
1785 
1786     /// \name Core
1787     /// Core microarchitecture based processors.
1788     //@{
1789     CK_Core2,
1790 
1791     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1792     /// codename which GCC no longer accepts as an option to -march, but Clang
1793     /// has some logic for recognizing it.
1794     // FIXME: Warn, deprecate, and potentially remove this.
1795     CK_Penryn,
1796     //@}
1797 
1798     /// \name Atom
1799     /// Atom processors
1800     //@{
1801     CK_Atom,
1802     //@}
1803 
1804     /// \name Nehalem
1805     /// Nehalem microarchitecture based processors.
1806     //@{
1807     CK_Corei7,
1808     CK_Corei7AVX,
1809     CK_CoreAVXi,
1810     CK_CoreAVX2,
1811     //@}
1812 
1813     /// \name K6
1814     /// K6 architecture processors.
1815     //@{
1816     CK_K6,
1817     CK_K6_2,
1818     CK_K6_3,
1819     //@}
1820 
1821     /// \name K7
1822     /// K7 architecture processors.
1823     //@{
1824     CK_Athlon,
1825     CK_AthlonThunderbird,
1826     CK_Athlon4,
1827     CK_AthlonXP,
1828     CK_AthlonMP,
1829     //@}
1830 
1831     /// \name K8
1832     /// K8 architecture processors.
1833     //@{
1834     CK_Athlon64,
1835     CK_Athlon64SSE3,
1836     CK_AthlonFX,
1837     CK_K8,
1838     CK_K8SSE3,
1839     CK_Opteron,
1840     CK_OpteronSSE3,
1841     CK_AMDFAM10,
1842     //@}
1843 
1844     /// \name Bobcat
1845     /// Bobcat architecture processors.
1846     //@{
1847     CK_BTVER1,
1848     CK_BTVER2,
1849     //@}
1850 
1851     /// \name Bulldozer
1852     /// Bulldozer architecture processors.
1853     //@{
1854     CK_BDVER1,
1855     CK_BDVER2,
1856     //@}
1857 
1858     /// This specification is deprecated and will be removed in the future.
1859     /// Users should prefer \see CK_K8.
1860     // FIXME: Warn on this when the CPU is set to it.
1861     CK_x86_64,
1862     //@}
1863 
1864     /// \name Geode
1865     /// Geode processors.
1866     //@{
1867     CK_Geode
1868     //@}
1869   } CPU;
1870 
1871 public:
1872   X86TargetInfo(const std::string& triple)
1873     : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1874       HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1875       HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1876       HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false),
1877       HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) {
1878     BigEndian = false;
1879     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1880   }
1881   virtual unsigned getFloatEvalMethod() const {
1882     // X87 evaluates with 80 bits "long double" precision.
1883     return SSELevel == NoSSE ? 2 : 0;
1884   }
1885   virtual void getTargetBuiltins(const Builtin::Info *&Records,
1886                                  unsigned &NumRecords) const {
1887     Records = BuiltinInfo;
1888     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1889   }
1890   virtual void getGCCRegNames(const char * const *&Names,
1891                               unsigned &NumNames) const {
1892     Names = GCCRegNames;
1893     NumNames = llvm::array_lengthof(GCCRegNames);
1894   }
1895   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1896                                 unsigned &NumAliases) const {
1897     Aliases = 0;
1898     NumAliases = 0;
1899   }
1900   virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1901                                   unsigned &NumNames) const {
1902     Names = AddlRegNames;
1903     NumNames = llvm::array_lengthof(AddlRegNames);
1904   }
1905   virtual bool validateAsmConstraint(const char *&Name,
1906                                      TargetInfo::ConstraintInfo &info) const;
1907   virtual std::string convertConstraint(const char *&Constraint) const;
1908   virtual const char *getClobbers() const {
1909     return "~{dirflag},~{fpsr},~{flags}";
1910   }
1911   virtual void getTargetDefines(const LangOptions &Opts,
1912                                 MacroBuilder &Builder) const;
1913   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1914                                  StringRef Name,
1915                                  bool Enabled) const;
1916   virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1917   virtual bool hasFeature(StringRef Feature) const;
1918   virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1919   virtual const char* getABI() const {
1920     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1921       return "avx";
1922     else if (getTriple().getArch() == llvm::Triple::x86 &&
1923              MMX3DNowLevel == NoMMX3DNow)
1924       return "no-mmx";
1925     return "";
1926   }
1927   virtual bool setCPU(const std::string &Name) {
1928     CPU = llvm::StringSwitch<CPUKind>(Name)
1929       .Case("i386", CK_i386)
1930       .Case("i486", CK_i486)
1931       .Case("winchip-c6", CK_WinChipC6)
1932       .Case("winchip2", CK_WinChip2)
1933       .Case("c3", CK_C3)
1934       .Case("i586", CK_i586)
1935       .Case("pentium", CK_Pentium)
1936       .Case("pentium-mmx", CK_PentiumMMX)
1937       .Case("i686", CK_i686)
1938       .Case("pentiumpro", CK_PentiumPro)
1939       .Case("pentium2", CK_Pentium2)
1940       .Case("pentium3", CK_Pentium3)
1941       .Case("pentium3m", CK_Pentium3M)
1942       .Case("pentium-m", CK_PentiumM)
1943       .Case("c3-2", CK_C3_2)
1944       .Case("yonah", CK_Yonah)
1945       .Case("pentium4", CK_Pentium4)
1946       .Case("pentium4m", CK_Pentium4M)
1947       .Case("prescott", CK_Prescott)
1948       .Case("nocona", CK_Nocona)
1949       .Case("core2", CK_Core2)
1950       .Case("penryn", CK_Penryn)
1951       .Case("atom", CK_Atom)
1952       .Case("corei7", CK_Corei7)
1953       .Case("corei7-avx", CK_Corei7AVX)
1954       .Case("core-avx-i", CK_CoreAVXi)
1955       .Case("core-avx2", CK_CoreAVX2)
1956       .Case("k6", CK_K6)
1957       .Case("k6-2", CK_K6_2)
1958       .Case("k6-3", CK_K6_3)
1959       .Case("athlon", CK_Athlon)
1960       .Case("athlon-tbird", CK_AthlonThunderbird)
1961       .Case("athlon-4", CK_Athlon4)
1962       .Case("athlon-xp", CK_AthlonXP)
1963       .Case("athlon-mp", CK_AthlonMP)
1964       .Case("athlon64", CK_Athlon64)
1965       .Case("athlon64-sse3", CK_Athlon64SSE3)
1966       .Case("athlon-fx", CK_AthlonFX)
1967       .Case("k8", CK_K8)
1968       .Case("k8-sse3", CK_K8SSE3)
1969       .Case("opteron", CK_Opteron)
1970       .Case("opteron-sse3", CK_OpteronSSE3)
1971       .Case("amdfam10", CK_AMDFAM10)
1972       .Case("btver1", CK_BTVER1)
1973       .Case("btver2", CK_BTVER2)
1974       .Case("bdver1", CK_BDVER1)
1975       .Case("bdver2", CK_BDVER2)
1976       .Case("x86-64", CK_x86_64)
1977       .Case("geode", CK_Geode)
1978       .Default(CK_Generic);
1979 
1980     // Perform any per-CPU checks necessary to determine if this CPU is
1981     // acceptable.
1982     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1983     // invalid without explaining *why*.
1984     switch (CPU) {
1985     case CK_Generic:
1986       // No processor selected!
1987       return false;
1988 
1989     case CK_i386:
1990     case CK_i486:
1991     case CK_WinChipC6:
1992     case CK_WinChip2:
1993     case CK_C3:
1994     case CK_i586:
1995     case CK_Pentium:
1996     case CK_PentiumMMX:
1997     case CK_i686:
1998     case CK_PentiumPro:
1999     case CK_Pentium2:
2000     case CK_Pentium3:
2001     case CK_Pentium3M:
2002     case CK_PentiumM:
2003     case CK_Yonah:
2004     case CK_C3_2:
2005     case CK_Pentium4:
2006     case CK_Pentium4M:
2007     case CK_Prescott:
2008     case CK_K6:
2009     case CK_K6_2:
2010     case CK_K6_3:
2011     case CK_Athlon:
2012     case CK_AthlonThunderbird:
2013     case CK_Athlon4:
2014     case CK_AthlonXP:
2015     case CK_AthlonMP:
2016     case CK_Geode:
2017       // Only accept certain architectures when compiling in 32-bit mode.
2018       if (getTriple().getArch() != llvm::Triple::x86)
2019         return false;
2020 
2021       // Fallthrough
2022     case CK_Nocona:
2023     case CK_Core2:
2024     case CK_Penryn:
2025     case CK_Atom:
2026     case CK_Corei7:
2027     case CK_Corei7AVX:
2028     case CK_CoreAVXi:
2029     case CK_CoreAVX2:
2030     case CK_Athlon64:
2031     case CK_Athlon64SSE3:
2032     case CK_AthlonFX:
2033     case CK_K8:
2034     case CK_K8SSE3:
2035     case CK_Opteron:
2036     case CK_OpteronSSE3:
2037     case CK_AMDFAM10:
2038     case CK_BTVER1:
2039     case CK_BTVER2:
2040     case CK_BDVER1:
2041     case CK_BDVER2:
2042     case CK_x86_64:
2043       return true;
2044     }
2045     llvm_unreachable("Unhandled CPU kind");
2046   }
2047 
2048   virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2049     // We accept all non-ARM calling conventions
2050     return (CC == CC_X86ThisCall ||
2051             CC == CC_X86FastCall ||
2052             CC == CC_X86StdCall ||
2053             CC == CC_C ||
2054             CC == CC_X86Pascal ||
2055             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2056   }
2057 
2058   virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2059     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2060   }
2061 };
2062 
2063 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2064   // FIXME: This should not be here.
2065   Features["3dnow"] = false;
2066   Features["3dnowa"] = false;
2067   Features["mmx"] = false;
2068   Features["sse"] = false;
2069   Features["sse2"] = false;
2070   Features["sse3"] = false;
2071   Features["ssse3"] = false;
2072   Features["sse41"] = false;
2073   Features["sse42"] = false;
2074   Features["sse4a"] = false;
2075   Features["aes"] = false;
2076   Features["pclmul"] = false;
2077   Features["avx"] = false;
2078   Features["avx2"] = false;
2079   Features["lzcnt"] = false;
2080   Features["rdrand"] = false;
2081   Features["bmi"] = false;
2082   Features["bmi2"] = false;
2083   Features["popcnt"] = false;
2084   Features["rtm"] = false;
2085   Features["prfchw"] = false;
2086   Features["rdseed"] = false;
2087   Features["fma4"] = false;
2088   Features["fma"] = false;
2089   Features["xop"] = false;
2090   Features["f16c"] = false;
2091 
2092   // FIXME: This *really* should not be here.
2093 
2094   // X86_64 always has SSE2.
2095   if (getTriple().getArch() == llvm::Triple::x86_64)
2096     setFeatureEnabled(Features, "sse2", true);
2097 
2098   switch (CPU) {
2099   case CK_Generic:
2100   case CK_i386:
2101   case CK_i486:
2102   case CK_i586:
2103   case CK_Pentium:
2104   case CK_i686:
2105   case CK_PentiumPro:
2106     break;
2107   case CK_PentiumMMX:
2108   case CK_Pentium2:
2109     setFeatureEnabled(Features, "mmx", true);
2110     break;
2111   case CK_Pentium3:
2112   case CK_Pentium3M:
2113     setFeatureEnabled(Features, "sse", true);
2114     break;
2115   case CK_PentiumM:
2116   case CK_Pentium4:
2117   case CK_Pentium4M:
2118   case CK_x86_64:
2119     setFeatureEnabled(Features, "sse2", true);
2120     break;
2121   case CK_Yonah:
2122   case CK_Prescott:
2123   case CK_Nocona:
2124     setFeatureEnabled(Features, "sse3", true);
2125     break;
2126   case CK_Core2:
2127     setFeatureEnabled(Features, "ssse3", true);
2128     break;
2129   case CK_Penryn:
2130     setFeatureEnabled(Features, "sse4.1", true);
2131     break;
2132   case CK_Atom:
2133     setFeatureEnabled(Features, "ssse3", true);
2134     break;
2135   case CK_Corei7:
2136     setFeatureEnabled(Features, "sse4", true);
2137     break;
2138   case CK_Corei7AVX:
2139     setFeatureEnabled(Features, "avx", true);
2140     setFeatureEnabled(Features, "aes", true);
2141     setFeatureEnabled(Features, "pclmul", true);
2142     break;
2143   case CK_CoreAVXi:
2144     setFeatureEnabled(Features, "avx", true);
2145     setFeatureEnabled(Features, "aes", true);
2146     setFeatureEnabled(Features, "pclmul", true);
2147     setFeatureEnabled(Features, "rdrnd", true);
2148     setFeatureEnabled(Features, "f16c", true);
2149     break;
2150   case CK_CoreAVX2:
2151     setFeatureEnabled(Features, "avx2", true);
2152     setFeatureEnabled(Features, "aes", true);
2153     setFeatureEnabled(Features, "pclmul", true);
2154     setFeatureEnabled(Features, "lzcnt", true);
2155     setFeatureEnabled(Features, "rdrnd", true);
2156     setFeatureEnabled(Features, "f16c", true);
2157     setFeatureEnabled(Features, "bmi", true);
2158     setFeatureEnabled(Features, "bmi2", true);
2159     setFeatureEnabled(Features, "rtm", true);
2160     setFeatureEnabled(Features, "fma", true);
2161     break;
2162   case CK_K6:
2163   case CK_WinChipC6:
2164     setFeatureEnabled(Features, "mmx", true);
2165     break;
2166   case CK_K6_2:
2167   case CK_K6_3:
2168   case CK_WinChip2:
2169   case CK_C3:
2170     setFeatureEnabled(Features, "3dnow", true);
2171     break;
2172   case CK_Athlon:
2173   case CK_AthlonThunderbird:
2174   case CK_Geode:
2175     setFeatureEnabled(Features, "3dnowa", true);
2176     break;
2177   case CK_Athlon4:
2178   case CK_AthlonXP:
2179   case CK_AthlonMP:
2180     setFeatureEnabled(Features, "sse", true);
2181     setFeatureEnabled(Features, "3dnowa", true);
2182     break;
2183   case CK_K8:
2184   case CK_Opteron:
2185   case CK_Athlon64:
2186   case CK_AthlonFX:
2187     setFeatureEnabled(Features, "sse2", true);
2188     setFeatureEnabled(Features, "3dnowa", true);
2189     break;
2190   case CK_K8SSE3:
2191   case CK_OpteronSSE3:
2192   case CK_Athlon64SSE3:
2193     setFeatureEnabled(Features, "sse3", true);
2194     setFeatureEnabled(Features, "3dnowa", true);
2195     break;
2196   case CK_AMDFAM10:
2197     setFeatureEnabled(Features, "sse3", true);
2198     setFeatureEnabled(Features, "sse4a", true);
2199     setFeatureEnabled(Features, "3dnowa", true);
2200     setFeatureEnabled(Features, "lzcnt", true);
2201     setFeatureEnabled(Features, "popcnt", true);
2202     break;
2203   case CK_BTVER1:
2204     setFeatureEnabled(Features, "ssse3", true);
2205     setFeatureEnabled(Features, "sse4a", true);
2206     setFeatureEnabled(Features, "lzcnt", true);
2207     setFeatureEnabled(Features, "popcnt", true);
2208     break;
2209   case CK_BTVER2:
2210     setFeatureEnabled(Features, "avx", true);
2211     setFeatureEnabled(Features, "sse4a", true);
2212     setFeatureEnabled(Features, "lzcnt", true);
2213     setFeatureEnabled(Features, "aes", true);
2214     setFeatureEnabled(Features, "pclmul", true);
2215     setFeatureEnabled(Features, "bmi", true);
2216     setFeatureEnabled(Features, "f16c", true);
2217     break;
2218   case CK_BDVER1:
2219     setFeatureEnabled(Features, "xop", true);
2220     setFeatureEnabled(Features, "lzcnt", true);
2221     setFeatureEnabled(Features, "aes", true);
2222     setFeatureEnabled(Features, "pclmul", true);
2223     break;
2224   case CK_BDVER2:
2225     setFeatureEnabled(Features, "xop", true);
2226     setFeatureEnabled(Features, "lzcnt", true);
2227     setFeatureEnabled(Features, "aes", true);
2228     setFeatureEnabled(Features, "pclmul", true);
2229     setFeatureEnabled(Features, "bmi", true);
2230     setFeatureEnabled(Features, "fma", true);
2231     setFeatureEnabled(Features, "f16c", true);
2232     break;
2233   case CK_C3_2:
2234     setFeatureEnabled(Features, "sse", true);
2235     break;
2236   }
2237 }
2238 
2239 bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2240                                       StringRef Name,
2241                                       bool Enabled) const {
2242   // FIXME: This *really* should not be here.  We need some way of translating
2243   // options into llvm subtarget features.
2244   if (!Features.count(Name) &&
2245       (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2246        Name != "rdrnd"))
2247     return false;
2248 
2249   // FIXME: this should probably use a switch with fall through.
2250 
2251   if (Enabled) {
2252     if (Name == "mmx")
2253       Features["mmx"] = true;
2254     else if (Name == "sse")
2255       Features["mmx"] = Features["sse"] = true;
2256     else if (Name == "sse2")
2257       Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2258     else if (Name == "sse3")
2259       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2260         true;
2261     else if (Name == "ssse3")
2262       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2263         Features["ssse3"] = true;
2264     else if (Name == "sse4" || Name == "sse4.2")
2265       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2266         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2267         Features["popcnt"] = true;
2268     else if (Name == "sse4.1")
2269       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2270         Features["ssse3"] = Features["sse41"] = true;
2271     else if (Name == "3dnow")
2272       Features["mmx"] = Features["3dnow"] = true;
2273     else if (Name == "3dnowa")
2274       Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2275     else if (Name == "aes")
2276       Features["sse"] = Features["sse2"] = Features["aes"] = true;
2277     else if (Name == "pclmul")
2278       Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2279     else if (Name == "avx")
2280       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2281         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2282         Features["popcnt"] = Features["avx"] = true;
2283     else if (Name == "avx2")
2284       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2285         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2286         Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2287     else if (Name == "fma")
2288       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2289         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2290         Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2291     else if (Name == "fma4")
2292       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2293         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2294         Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2295         Features["fma4"] = true;
2296     else if (Name == "xop")
2297       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2298         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2299         Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2300         Features["fma4"] = Features["xop"] = true;
2301     else if (Name == "sse4a")
2302       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2303         Features["sse4a"] = true;
2304     else if (Name == "lzcnt")
2305       Features["lzcnt"] = true;
2306     else if (Name == "rdrnd")
2307       Features["rdrand"] = true;
2308     else if (Name == "bmi")
2309       Features["bmi"] = true;
2310     else if (Name == "bmi2")
2311       Features["bmi2"] = true;
2312     else if (Name == "popcnt")
2313       Features["popcnt"] = true;
2314     else if (Name == "f16c")
2315       Features["f16c"] = true;
2316     else if (Name == "rtm")
2317       Features["rtm"] = true;
2318     else if (Name == "prfchw")
2319       Features["prfchw"] = true;
2320     else if (Name == "rdseed")
2321       Features["rdseed"] = true;
2322   } else {
2323     if (Name == "mmx")
2324       Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2325     else if (Name == "sse")
2326       Features["sse"] = Features["sse2"] = Features["sse3"] =
2327         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2328         Features["sse4a"] = Features["avx"] = Features["avx2"] =
2329         Features["fma"] = Features["fma4"] = Features["aes"] =
2330         Features["pclmul"] = Features["xop"] = false;
2331     else if (Name == "sse2")
2332       Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2333         Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2334         Features["avx"] = Features["avx2"] = Features["fma"] =
2335         Features["fma4"] = Features["aes"] = Features["pclmul"] =
2336         Features["xop"] = false;
2337     else if (Name == "sse3")
2338       Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2339         Features["sse42"] = Features["sse4a"] = Features["avx"] =
2340         Features["avx2"] = Features["fma"] = Features["fma4"] =
2341         Features["xop"] = false;
2342     else if (Name == "ssse3")
2343       Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2344         Features["avx"] = Features["avx2"] = Features["fma"] = false;
2345     else if (Name == "sse4" || Name == "sse4.1")
2346       Features["sse41"] = Features["sse42"] = Features["avx"] =
2347         Features["avx2"] = Features["fma"] = false;
2348     else if (Name == "sse4.2")
2349       Features["sse42"] = Features["avx"] = Features["avx2"] =
2350         Features["fma"] = false;
2351     else if (Name == "3dnow")
2352       Features["3dnow"] = Features["3dnowa"] = false;
2353     else if (Name == "3dnowa")
2354       Features["3dnowa"] = false;
2355     else if (Name == "aes")
2356       Features["aes"] = false;
2357     else if (Name == "pclmul")
2358       Features["pclmul"] = false;
2359     else if (Name == "avx")
2360       Features["avx"] = Features["avx2"] = Features["fma"] =
2361         Features["fma4"] = Features["xop"] = false;
2362     else if (Name == "avx2")
2363       Features["avx2"] = false;
2364     else if (Name == "fma")
2365       Features["fma"] = false;
2366     else if (Name == "sse4a")
2367       Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2368     else if (Name == "lzcnt")
2369       Features["lzcnt"] = false;
2370     else if (Name == "rdrnd")
2371       Features["rdrand"] = false;
2372     else if (Name == "bmi")
2373       Features["bmi"] = false;
2374     else if (Name == "bmi2")
2375       Features["bmi2"] = false;
2376     else if (Name == "popcnt")
2377       Features["popcnt"] = false;
2378     else if (Name == "fma4")
2379       Features["fma4"] = Features["xop"] = false;
2380     else if (Name == "xop")
2381       Features["xop"] = false;
2382     else if (Name == "f16c")
2383       Features["f16c"] = false;
2384     else if (Name == "rtm")
2385       Features["rtm"] = false;
2386     else if (Name == "prfchw")
2387       Features["prfchw"] = false;
2388     else if (Name == "rdseed")
2389       Features["rdseed"] = false;
2390   }
2391 
2392   return true;
2393 }
2394 
2395 /// HandleTargetOptions - Perform initialization based on the user
2396 /// configured set of features.
2397 void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2398   // Remember the maximum enabled sselevel.
2399   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2400     // Ignore disabled features.
2401     if (Features[i][0] == '-')
2402       continue;
2403 
2404     StringRef Feature = StringRef(Features[i]).substr(1);
2405 
2406     if (Feature == "aes") {
2407       HasAES = true;
2408       continue;
2409     }
2410 
2411     if (Feature == "pclmul") {
2412       HasPCLMUL = true;
2413       continue;
2414     }
2415 
2416     if (Feature == "lzcnt") {
2417       HasLZCNT = true;
2418       continue;
2419     }
2420 
2421     if (Feature == "rdrand") {
2422       HasRDRND = true;
2423       continue;
2424     }
2425 
2426     if (Feature == "bmi") {
2427       HasBMI = true;
2428       continue;
2429     }
2430 
2431     if (Feature == "bmi2") {
2432       HasBMI2 = true;
2433       continue;
2434     }
2435 
2436     if (Feature == "popcnt") {
2437       HasPOPCNT = true;
2438       continue;
2439     }
2440 
2441     if (Feature == "rtm") {
2442       HasRTM = true;
2443       continue;
2444     }
2445 
2446     if (Feature == "prfchw") {
2447       HasPRFCHW = true;
2448       continue;
2449     }
2450 
2451     if (Feature == "rdseed") {
2452       HasRDSEED = true;
2453       continue;
2454     }
2455 
2456     if (Feature == "sse4a") {
2457       HasSSE4a = true;
2458       continue;
2459     }
2460 
2461     if (Feature == "fma4") {
2462       HasFMA4 = true;
2463       continue;
2464     }
2465 
2466     if (Feature == "fma") {
2467       HasFMA = true;
2468       continue;
2469     }
2470 
2471     if (Feature == "xop") {
2472       HasXOP = true;
2473       continue;
2474     }
2475 
2476     if (Feature == "f16c") {
2477       HasF16C = true;
2478       continue;
2479     }
2480 
2481     assert(Features[i][0] == '+' && "Invalid target feature!");
2482     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2483       .Case("avx2", AVX2)
2484       .Case("avx", AVX)
2485       .Case("sse42", SSE42)
2486       .Case("sse41", SSE41)
2487       .Case("ssse3", SSSE3)
2488       .Case("sse3", SSE3)
2489       .Case("sse2", SSE2)
2490       .Case("sse", SSE1)
2491       .Default(NoSSE);
2492     SSELevel = std::max(SSELevel, Level);
2493 
2494     MMX3DNowEnum ThreeDNowLevel =
2495       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2496         .Case("3dnowa", AMD3DNowAthlon)
2497         .Case("3dnow", AMD3DNow)
2498         .Case("mmx", MMX)
2499         .Default(NoMMX3DNow);
2500 
2501     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2502   }
2503 
2504   // Don't tell the backend if we're turning off mmx; it will end up disabling
2505   // SSE, which we don't want.
2506   std::vector<std::string>::iterator it;
2507   it = std::find(Features.begin(), Features.end(), "-mmx");
2508   if (it != Features.end())
2509     Features.erase(it);
2510 }
2511 
2512 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2513 /// definitions for this particular subtarget.
2514 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2515                                      MacroBuilder &Builder) const {
2516   // Target identification.
2517   if (getTriple().getArch() == llvm::Triple::x86_64) {
2518     Builder.defineMacro("__amd64__");
2519     Builder.defineMacro("__amd64");
2520     Builder.defineMacro("__x86_64");
2521     Builder.defineMacro("__x86_64__");
2522   } else {
2523     DefineStd(Builder, "i386", Opts);
2524   }
2525 
2526   // Subtarget options.
2527   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2528   // truly should be based on -mtune options.
2529   switch (CPU) {
2530   case CK_Generic:
2531     break;
2532   case CK_i386:
2533     // The rest are coming from the i386 define above.
2534     Builder.defineMacro("__tune_i386__");
2535     break;
2536   case CK_i486:
2537   case CK_WinChipC6:
2538   case CK_WinChip2:
2539   case CK_C3:
2540     defineCPUMacros(Builder, "i486");
2541     break;
2542   case CK_PentiumMMX:
2543     Builder.defineMacro("__pentium_mmx__");
2544     Builder.defineMacro("__tune_pentium_mmx__");
2545     // Fallthrough
2546   case CK_i586:
2547   case CK_Pentium:
2548     defineCPUMacros(Builder, "i586");
2549     defineCPUMacros(Builder, "pentium");
2550     break;
2551   case CK_Pentium3:
2552   case CK_Pentium3M:
2553   case CK_PentiumM:
2554     Builder.defineMacro("__tune_pentium3__");
2555     // Fallthrough
2556   case CK_Pentium2:
2557   case CK_C3_2:
2558     Builder.defineMacro("__tune_pentium2__");
2559     // Fallthrough
2560   case CK_PentiumPro:
2561     Builder.defineMacro("__tune_i686__");
2562     Builder.defineMacro("__tune_pentiumpro__");
2563     // Fallthrough
2564   case CK_i686:
2565     Builder.defineMacro("__i686");
2566     Builder.defineMacro("__i686__");
2567     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2568     Builder.defineMacro("__pentiumpro");
2569     Builder.defineMacro("__pentiumpro__");
2570     break;
2571   case CK_Pentium4:
2572   case CK_Pentium4M:
2573     defineCPUMacros(Builder, "pentium4");
2574     break;
2575   case CK_Yonah:
2576   case CK_Prescott:
2577   case CK_Nocona:
2578     defineCPUMacros(Builder, "nocona");
2579     break;
2580   case CK_Core2:
2581   case CK_Penryn:
2582     defineCPUMacros(Builder, "core2");
2583     break;
2584   case CK_Atom:
2585     defineCPUMacros(Builder, "atom");
2586     break;
2587   case CK_Corei7:
2588   case CK_Corei7AVX:
2589   case CK_CoreAVXi:
2590   case CK_CoreAVX2:
2591     defineCPUMacros(Builder, "corei7");
2592     break;
2593   case CK_K6_2:
2594     Builder.defineMacro("__k6_2__");
2595     Builder.defineMacro("__tune_k6_2__");
2596     // Fallthrough
2597   case CK_K6_3:
2598     if (CPU != CK_K6_2) {  // In case of fallthrough
2599       // FIXME: GCC may be enabling these in cases where some other k6
2600       // architecture is specified but -m3dnow is explicitly provided. The
2601       // exact semantics need to be determined and emulated here.
2602       Builder.defineMacro("__k6_3__");
2603       Builder.defineMacro("__tune_k6_3__");
2604     }
2605     // Fallthrough
2606   case CK_K6:
2607     defineCPUMacros(Builder, "k6");
2608     break;
2609   case CK_Athlon:
2610   case CK_AthlonThunderbird:
2611   case CK_Athlon4:
2612   case CK_AthlonXP:
2613   case CK_AthlonMP:
2614     defineCPUMacros(Builder, "athlon");
2615     if (SSELevel != NoSSE) {
2616       Builder.defineMacro("__athlon_sse__");
2617       Builder.defineMacro("__tune_athlon_sse__");
2618     }
2619     break;
2620   case CK_K8:
2621   case CK_K8SSE3:
2622   case CK_x86_64:
2623   case CK_Opteron:
2624   case CK_OpteronSSE3:
2625   case CK_Athlon64:
2626   case CK_Athlon64SSE3:
2627   case CK_AthlonFX:
2628     defineCPUMacros(Builder, "k8");
2629     break;
2630   case CK_AMDFAM10:
2631     defineCPUMacros(Builder, "amdfam10");
2632     break;
2633   case CK_BTVER1:
2634     defineCPUMacros(Builder, "btver1");
2635     break;
2636   case CK_BTVER2:
2637     defineCPUMacros(Builder, "btver2");
2638     break;
2639   case CK_BDVER1:
2640     defineCPUMacros(Builder, "bdver1");
2641     break;
2642   case CK_BDVER2:
2643     defineCPUMacros(Builder, "bdver2");
2644     break;
2645   case CK_Geode:
2646     defineCPUMacros(Builder, "geode");
2647     break;
2648   }
2649 
2650   // Target properties.
2651   Builder.defineMacro("__LITTLE_ENDIAN__");
2652   Builder.defineMacro("__REGISTER_PREFIX__", "");
2653 
2654   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2655   // functions in glibc header files that use FP Stack inline asm which the
2656   // backend can't deal with (PR879).
2657   Builder.defineMacro("__NO_MATH_INLINES");
2658 
2659   if (HasAES)
2660     Builder.defineMacro("__AES__");
2661 
2662   if (HasPCLMUL)
2663     Builder.defineMacro("__PCLMUL__");
2664 
2665   if (HasLZCNT)
2666     Builder.defineMacro("__LZCNT__");
2667 
2668   if (HasRDRND)
2669     Builder.defineMacro("__RDRND__");
2670 
2671   if (HasBMI)
2672     Builder.defineMacro("__BMI__");
2673 
2674   if (HasBMI2)
2675     Builder.defineMacro("__BMI2__");
2676 
2677   if (HasPOPCNT)
2678     Builder.defineMacro("__POPCNT__");
2679 
2680   if (HasRTM)
2681     Builder.defineMacro("__RTM__");
2682 
2683   if (HasPRFCHW)
2684     Builder.defineMacro("__PRFCHW__");
2685 
2686   if (HasRDSEED)
2687     Builder.defineMacro("__RDSEED__");
2688 
2689   if (HasSSE4a)
2690     Builder.defineMacro("__SSE4A__");
2691 
2692   if (HasFMA4)
2693     Builder.defineMacro("__FMA4__");
2694 
2695   if (HasFMA)
2696     Builder.defineMacro("__FMA__");
2697 
2698   if (HasXOP)
2699     Builder.defineMacro("__XOP__");
2700 
2701   if (HasF16C)
2702     Builder.defineMacro("__F16C__");
2703 
2704   // Each case falls through to the previous one here.
2705   switch (SSELevel) {
2706   case AVX2:
2707     Builder.defineMacro("__AVX2__");
2708   case AVX:
2709     Builder.defineMacro("__AVX__");
2710   case SSE42:
2711     Builder.defineMacro("__SSE4_2__");
2712   case SSE41:
2713     Builder.defineMacro("__SSE4_1__");
2714   case SSSE3:
2715     Builder.defineMacro("__SSSE3__");
2716   case SSE3:
2717     Builder.defineMacro("__SSE3__");
2718   case SSE2:
2719     Builder.defineMacro("__SSE2__");
2720     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2721   case SSE1:
2722     Builder.defineMacro("__SSE__");
2723     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2724   case NoSSE:
2725     break;
2726   }
2727 
2728   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2729     switch (SSELevel) {
2730     case AVX2:
2731     case AVX:
2732     case SSE42:
2733     case SSE41:
2734     case SSSE3:
2735     case SSE3:
2736     case SSE2:
2737       Builder.defineMacro("_M_IX86_FP", Twine(2));
2738       break;
2739     case SSE1:
2740       Builder.defineMacro("_M_IX86_FP", Twine(1));
2741       break;
2742     default:
2743       Builder.defineMacro("_M_IX86_FP", Twine(0));
2744     }
2745   }
2746 
2747   // Each case falls through to the previous one here.
2748   switch (MMX3DNowLevel) {
2749   case AMD3DNowAthlon:
2750     Builder.defineMacro("__3dNOW_A__");
2751   case AMD3DNow:
2752     Builder.defineMacro("__3dNOW__");
2753   case MMX:
2754     Builder.defineMacro("__MMX__");
2755   case NoMMX3DNow:
2756     break;
2757   }
2758 
2759   if (CPU >= CK_i486) {
2760     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2761     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2762     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2763   }
2764   if (CPU >= CK_i586)
2765     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2766 }
2767 
2768 bool X86TargetInfo::hasFeature(StringRef Feature) const {
2769   return llvm::StringSwitch<bool>(Feature)
2770       .Case("aes", HasAES)
2771       .Case("avx", SSELevel >= AVX)
2772       .Case("avx2", SSELevel >= AVX2)
2773       .Case("bmi", HasBMI)
2774       .Case("bmi2", HasBMI2)
2775       .Case("fma", HasFMA)
2776       .Case("fma4", HasFMA4)
2777       .Case("lzcnt", HasLZCNT)
2778       .Case("rdrnd", HasRDRND)
2779       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2780       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2781       .Case("mmx", MMX3DNowLevel >= MMX)
2782       .Case("pclmul", HasPCLMUL)
2783       .Case("popcnt", HasPOPCNT)
2784       .Case("rtm", HasRTM)
2785       .Case("prfchw", HasPRFCHW)
2786       .Case("rdseed", HasRDSEED)
2787       .Case("sse", SSELevel >= SSE1)
2788       .Case("sse2", SSELevel >= SSE2)
2789       .Case("sse3", SSELevel >= SSE3)
2790       .Case("ssse3", SSELevel >= SSSE3)
2791       .Case("sse41", SSELevel >= SSE41)
2792       .Case("sse42", SSELevel >= SSE42)
2793       .Case("sse4a", HasSSE4a)
2794       .Case("x86", true)
2795       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2796       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2797       .Case("xop", HasXOP)
2798       .Case("f16c", HasF16C)
2799       .Default(false);
2800 }
2801 
2802 bool
2803 X86TargetInfo::validateAsmConstraint(const char *&Name,
2804                                      TargetInfo::ConstraintInfo &Info) const {
2805   switch (*Name) {
2806   default: return false;
2807   case 'Y': // first letter of a pair:
2808     switch (*(Name+1)) {
2809     default: return false;
2810     case '0':  // First SSE register.
2811     case 't':  // Any SSE register, when SSE2 is enabled.
2812     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2813     case 'm':  // any MMX register, when inter-unit moves enabled.
2814       break;   // falls through to setAllowsRegister.
2815   }
2816   case 'a': // eax.
2817   case 'b': // ebx.
2818   case 'c': // ecx.
2819   case 'd': // edx.
2820   case 'S': // esi.
2821   case 'D': // edi.
2822   case 'A': // edx:eax.
2823   case 'f': // any x87 floating point stack register.
2824   case 't': // top of floating point stack.
2825   case 'u': // second from top of floating point stack.
2826   case 'q': // Any register accessible as [r]l: a, b, c, and d.
2827   case 'y': // Any MMX register.
2828   case 'x': // Any SSE register.
2829   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2830   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2831   case 'l': // "Index" registers: any general register that can be used as an
2832             // index in a base+index memory access.
2833     Info.setAllowsRegister();
2834     return true;
2835   case 'C': // SSE floating point constant.
2836   case 'G': // x87 floating point constant.
2837   case 'e': // 32-bit signed integer constant for use with zero-extending
2838             // x86_64 instructions.
2839   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2840             // x86_64 instructions.
2841     return true;
2842   }
2843 }
2844 
2845 
2846 std::string
2847 X86TargetInfo::convertConstraint(const char *&Constraint) const {
2848   switch (*Constraint) {
2849   case 'a': return std::string("{ax}");
2850   case 'b': return std::string("{bx}");
2851   case 'c': return std::string("{cx}");
2852   case 'd': return std::string("{dx}");
2853   case 'S': return std::string("{si}");
2854   case 'D': return std::string("{di}");
2855   case 'p': // address
2856     return std::string("im");
2857   case 't': // top of floating point stack.
2858     return std::string("{st}");
2859   case 'u': // second from top of floating point stack.
2860     return std::string("{st(1)}"); // second from top of floating point stack.
2861   default:
2862     return std::string(1, *Constraint);
2863   }
2864 }
2865 } // end anonymous namespace
2866 
2867 namespace {
2868 // X86-32 generic target
2869 class X86_32TargetInfo : public X86TargetInfo {
2870 public:
2871   X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) {
2872     DoubleAlign = LongLongAlign = 32;
2873     LongDoubleWidth = 96;
2874     LongDoubleAlign = 32;
2875     SuitableAlign = 128;
2876     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2877                         "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2878                         "a0:0:64-f80:32:32-n8:16:32-S128";
2879     SizeType = UnsignedInt;
2880     PtrDiffType = SignedInt;
2881     IntPtrType = SignedInt;
2882     RegParmMax = 3;
2883 
2884     // Use fpret for all types.
2885     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2886                              (1 << TargetInfo::Double) |
2887                              (1 << TargetInfo::LongDouble));
2888 
2889     // x86-32 has atomics up to 8 bytes
2890     // FIXME: Check that we actually have cmpxchg8b before setting
2891     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2892     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2893   }
2894   virtual BuiltinVaListKind getBuiltinVaListKind() const {
2895     return TargetInfo::CharPtrBuiltinVaList;
2896   }
2897 
2898   int getEHDataRegisterNumber(unsigned RegNo) const {
2899     if (RegNo == 0) return 0;
2900     if (RegNo == 1) return 2;
2901     return -1;
2902   }
2903   virtual bool validateInputSize(StringRef Constraint,
2904                                  unsigned Size) const {
2905     switch (Constraint[0]) {
2906     default: break;
2907     case 'a':
2908     case 'b':
2909     case 'c':
2910     case 'd':
2911       return Size <= 32;
2912     }
2913 
2914     return true;
2915   }
2916 };
2917 } // end anonymous namespace
2918 
2919 namespace {
2920 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2921 public:
2922   NetBSDI386TargetInfo(const std::string &triple) :
2923     NetBSDTargetInfo<X86_32TargetInfo>(triple) {
2924   }
2925 
2926   virtual unsigned getFloatEvalMethod() const {
2927     // NetBSD defaults to "double" rounding
2928     return 1;
2929   }
2930 };
2931 } // end anonymous namespace
2932 
2933 namespace {
2934 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2935 public:
2936   OpenBSDI386TargetInfo(const std::string& triple) :
2937     OpenBSDTargetInfo<X86_32TargetInfo>(triple) {
2938     SizeType = UnsignedLong;
2939     IntPtrType = SignedLong;
2940     PtrDiffType = SignedLong;
2941   }
2942 };
2943 } // end anonymous namespace
2944 
2945 namespace {
2946 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2947 public:
2948   BitrigI386TargetInfo(const std::string& triple) :
2949     BitrigTargetInfo<X86_32TargetInfo>(triple) {
2950     SizeType = UnsignedLong;
2951     IntPtrType = SignedLong;
2952     PtrDiffType = SignedLong;
2953   }
2954 };
2955 } // end anonymous namespace
2956 
2957 namespace {
2958 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2959 public:
2960   DarwinI386TargetInfo(const std::string& triple) :
2961     DarwinTargetInfo<X86_32TargetInfo>(triple) {
2962     LongDoubleWidth = 128;
2963     LongDoubleAlign = 128;
2964     SuitableAlign = 128;
2965     MaxVectorAlign = 256;
2966     SizeType = UnsignedLong;
2967     IntPtrType = SignedLong;
2968     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2969                         "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2970                         "a0:0:64-f80:128:128-n8:16:32-S128";
2971     HasAlignMac68kSupport = true;
2972   }
2973 
2974 };
2975 } // end anonymous namespace
2976 
2977 namespace {
2978 // x86-32 Windows target
2979 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2980 public:
2981   WindowsX86_32TargetInfo(const std::string& triple)
2982     : WindowsTargetInfo<X86_32TargetInfo>(triple) {
2983     TLSSupported = false;
2984     WCharType = UnsignedShort;
2985     DoubleAlign = LongLongAlign = 64;
2986     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2987                         "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2988                         "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2989   }
2990   virtual void getTargetDefines(const LangOptions &Opts,
2991                                 MacroBuilder &Builder) const {
2992     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2993   }
2994 };
2995 } // end anonymous namespace
2996 
2997 namespace {
2998 
2999 // x86-32 Windows Visual Studio target
3000 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
3001 public:
3002   VisualStudioWindowsX86_32TargetInfo(const std::string& triple)
3003     : WindowsX86_32TargetInfo(triple) {
3004     LongDoubleWidth = LongDoubleAlign = 64;
3005     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3006   }
3007   virtual void getTargetDefines(const LangOptions &Opts,
3008                                 MacroBuilder &Builder) const {
3009     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3010     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3011     // The value of the following reflects processor type.
3012     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3013     // We lost the original triple, so we use the default.
3014     Builder.defineMacro("_M_IX86", "600");
3015   }
3016 };
3017 } // end anonymous namespace
3018 
3019 namespace {
3020 // x86-32 MinGW target
3021 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3022 public:
3023   MinGWX86_32TargetInfo(const std::string& triple)
3024     : WindowsX86_32TargetInfo(triple) {
3025   }
3026   virtual void getTargetDefines(const LangOptions &Opts,
3027                                 MacroBuilder &Builder) const {
3028     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3029     DefineStd(Builder, "WIN32", Opts);
3030     DefineStd(Builder, "WINNT", Opts);
3031     Builder.defineMacro("_X86_");
3032     Builder.defineMacro("__MSVCRT__");
3033     Builder.defineMacro("__MINGW32__");
3034 
3035     // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3036     // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3037     if (Opts.MicrosoftExt)
3038       // Provide "as-is" __declspec.
3039       Builder.defineMacro("__declspec", "__declspec");
3040     else
3041       // Provide alias of __attribute__ like mingw32-gcc.
3042       Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3043   }
3044 };
3045 } // end anonymous namespace
3046 
3047 namespace {
3048 // x86-32 Cygwin target
3049 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3050 public:
3051   CygwinX86_32TargetInfo(const std::string& triple)
3052     : X86_32TargetInfo(triple) {
3053     TLSSupported = false;
3054     WCharType = UnsignedShort;
3055     DoubleAlign = LongLongAlign = 64;
3056     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3057                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3058                         "a0:0:64-f80:32:32-n8:16:32-S32";
3059   }
3060   virtual void getTargetDefines(const LangOptions &Opts,
3061                                 MacroBuilder &Builder) const {
3062     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3063     Builder.defineMacro("_X86_");
3064     Builder.defineMacro("__CYGWIN__");
3065     Builder.defineMacro("__CYGWIN32__");
3066     DefineStd(Builder, "unix", Opts);
3067     if (Opts.CPlusPlus)
3068       Builder.defineMacro("_GNU_SOURCE");
3069   }
3070 };
3071 } // end anonymous namespace
3072 
3073 namespace {
3074 // x86-32 Haiku target
3075 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3076 public:
3077   HaikuX86_32TargetInfo(const std::string& triple)
3078     : X86_32TargetInfo(triple) {
3079     SizeType = UnsignedLong;
3080     IntPtrType = SignedLong;
3081     PtrDiffType = SignedLong;
3082     ProcessIDType = SignedLong;
3083     this->UserLabelPrefix = "";
3084     this->TLSSupported = false;
3085   }
3086   virtual void getTargetDefines(const LangOptions &Opts,
3087                                 MacroBuilder &Builder) const {
3088     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3089     Builder.defineMacro("__INTEL__");
3090     Builder.defineMacro("__HAIKU__");
3091   }
3092 };
3093 } // end anonymous namespace
3094 
3095 // RTEMS Target
3096 template<typename Target>
3097 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3098 protected:
3099   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3100                             MacroBuilder &Builder) const {
3101     // RTEMS defines; list based off of gcc output
3102 
3103     Builder.defineMacro("__rtems__");
3104     Builder.defineMacro("__ELF__");
3105   }
3106 public:
3107   RTEMSTargetInfo(const std::string &triple)
3108     : OSTargetInfo<Target>(triple) {
3109       this->UserLabelPrefix = "";
3110 
3111       llvm::Triple Triple(triple);
3112       switch (Triple.getArch()) {
3113         default:
3114         case llvm::Triple::x86:
3115           // this->MCountName = ".mcount";
3116           break;
3117         case llvm::Triple::mips:
3118         case llvm::Triple::mipsel:
3119         case llvm::Triple::ppc:
3120         case llvm::Triple::ppc64:
3121           // this->MCountName = "_mcount";
3122           break;
3123         case llvm::Triple::arm:
3124           // this->MCountName = "__mcount";
3125           break;
3126       }
3127 
3128     }
3129 };
3130 
3131 namespace {
3132 // x86-32 RTEMS target
3133 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3134 public:
3135   RTEMSX86_32TargetInfo(const std::string& triple)
3136     : X86_32TargetInfo(triple) {
3137     SizeType = UnsignedLong;
3138     IntPtrType = SignedLong;
3139     PtrDiffType = SignedLong;
3140     this->UserLabelPrefix = "";
3141   }
3142   virtual void getTargetDefines(const LangOptions &Opts,
3143                                 MacroBuilder &Builder) const {
3144     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3145     Builder.defineMacro("__INTEL__");
3146     Builder.defineMacro("__rtems__");
3147   }
3148 };
3149 } // end anonymous namespace
3150 
3151 namespace {
3152 // x86-64 generic target
3153 class X86_64TargetInfo : public X86TargetInfo {
3154 public:
3155   X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) {
3156     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3157     LongDoubleWidth = 128;
3158     LongDoubleAlign = 128;
3159     LargeArrayMinWidth = 128;
3160     LargeArrayAlign = 128;
3161     SuitableAlign = 128;
3162     IntMaxType = SignedLong;
3163     UIntMaxType = UnsignedLong;
3164     Int64Type = SignedLong;
3165     RegParmMax = 6;
3166 
3167     DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3168                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3169                         "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3170 
3171     // Use fpret only for long double.
3172     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3173 
3174     // Use fp2ret for _Complex long double.
3175     ComplexLongDoubleUsesFP2Ret = true;
3176 
3177     // x86-64 has atomics up to 16 bytes.
3178     // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3179     // on CPUs with cmpxchg16b
3180     MaxAtomicPromoteWidth = 128;
3181     MaxAtomicInlineWidth = 64;
3182   }
3183   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3184     return TargetInfo::X86_64ABIBuiltinVaList;
3185   }
3186 
3187   int getEHDataRegisterNumber(unsigned RegNo) const {
3188     if (RegNo == 0) return 0;
3189     if (RegNo == 1) return 1;
3190     return -1;
3191   }
3192 
3193   virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3194     return (CC == CC_Default ||
3195             CC == CC_C ||
3196             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
3197   }
3198 
3199   virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3200     return CC_C;
3201   }
3202 
3203 };
3204 } // end anonymous namespace
3205 
3206 namespace {
3207 // x86-64 Windows target
3208 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3209 public:
3210   WindowsX86_64TargetInfo(const std::string& triple)
3211     : WindowsTargetInfo<X86_64TargetInfo>(triple) {
3212     TLSSupported = false;
3213     WCharType = UnsignedShort;
3214     LongWidth = LongAlign = 32;
3215     DoubleAlign = LongLongAlign = 64;
3216     IntMaxType = SignedLongLong;
3217     UIntMaxType = UnsignedLongLong;
3218     Int64Type = SignedLongLong;
3219     SizeType = UnsignedLongLong;
3220     PtrDiffType = SignedLongLong;
3221     IntPtrType = SignedLongLong;
3222     this->UserLabelPrefix = "";
3223   }
3224   virtual void getTargetDefines(const LangOptions &Opts,
3225                                 MacroBuilder &Builder) const {
3226     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3227     Builder.defineMacro("_WIN64");
3228   }
3229   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3230     return TargetInfo::CharPtrBuiltinVaList;
3231   }
3232 };
3233 } // end anonymous namespace
3234 
3235 namespace {
3236 // x86-64 Windows Visual Studio target
3237 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3238 public:
3239   VisualStudioWindowsX86_64TargetInfo(const std::string& triple)
3240     : WindowsX86_64TargetInfo(triple) {
3241     LongDoubleWidth = LongDoubleAlign = 64;
3242     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3243   }
3244   virtual void getTargetDefines(const LangOptions &Opts,
3245                                 MacroBuilder &Builder) const {
3246     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3247     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3248     Builder.defineMacro("_M_X64");
3249     Builder.defineMacro("_M_AMD64");
3250   }
3251 };
3252 } // end anonymous namespace
3253 
3254 namespace {
3255 // x86-64 MinGW target
3256 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3257 public:
3258   MinGWX86_64TargetInfo(const std::string& triple)
3259     : WindowsX86_64TargetInfo(triple) {
3260   }
3261   virtual void getTargetDefines(const LangOptions &Opts,
3262                                 MacroBuilder &Builder) const {
3263     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3264     DefineStd(Builder, "WIN64", Opts);
3265     Builder.defineMacro("__MSVCRT__");
3266     Builder.defineMacro("__MINGW32__");
3267     Builder.defineMacro("__MINGW64__");
3268 
3269     // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3270     // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3271     if (Opts.MicrosoftExt)
3272       // Provide "as-is" __declspec.
3273       Builder.defineMacro("__declspec", "__declspec");
3274     else
3275       // Provide alias of __attribute__ like mingw32-gcc.
3276       Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3277   }
3278 };
3279 } // end anonymous namespace
3280 
3281 namespace {
3282 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3283 public:
3284   DarwinX86_64TargetInfo(const std::string& triple)
3285       : DarwinTargetInfo<X86_64TargetInfo>(triple) {
3286     Int64Type = SignedLongLong;
3287     MaxVectorAlign = 256;
3288   }
3289 };
3290 } // end anonymous namespace
3291 
3292 namespace {
3293 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3294 public:
3295   OpenBSDX86_64TargetInfo(const std::string& triple)
3296       : OpenBSDTargetInfo<X86_64TargetInfo>(triple) {
3297     IntMaxType = SignedLongLong;
3298     UIntMaxType = UnsignedLongLong;
3299     Int64Type = SignedLongLong;
3300   }
3301 };
3302 } // end anonymous namespace
3303 
3304 namespace {
3305 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3306 public:
3307   BitrigX86_64TargetInfo(const std::string& triple)
3308       : BitrigTargetInfo<X86_64TargetInfo>(triple) {
3309      IntMaxType = SignedLongLong;
3310      UIntMaxType = UnsignedLongLong;
3311      Int64Type = SignedLongLong;
3312   }
3313 };
3314 }
3315 
3316 namespace {
3317 class AArch64TargetInfo : public TargetInfo {
3318   static const char * const GCCRegNames[];
3319   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3320 
3321   static const Builtin::Info BuiltinInfo[];
3322 public:
3323   AArch64TargetInfo(const std::string& triple) : TargetInfo(triple) {
3324     BigEndian = false;
3325     LongWidth = LongAlign = 64;
3326     LongDoubleWidth = LongDoubleAlign = 128;
3327     PointerWidth = PointerAlign = 64;
3328     SuitableAlign = 128;
3329     DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3330                         "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3331                         "f128:128:128-n32:64-S128";
3332 
3333     WCharType = UnsignedInt;
3334     LongDoubleFormat = &llvm::APFloat::IEEEquad;
3335 
3336     // AArch64 backend supports 64-bit operations at the moment. In principle
3337     // 128-bit is possible if register-pairs are used.
3338     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3339 
3340     TheCXXABI.set(TargetCXXABI::GenericAArch64);
3341   }
3342   virtual void getTargetDefines(const LangOptions &Opts,
3343                                 MacroBuilder &Builder) const {
3344     // GCC defines theses currently
3345     Builder.defineMacro("__aarch64__");
3346     Builder.defineMacro("__AARCH64EL__");
3347 
3348     // ACLE predefines. Many can only have one possible value on v8 AArch64.
3349 
3350     // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3351     // which was intended to be compatible with a 64-bit implementation. They
3352     // will need updating when a real 64-bit ACLE exists. Particularly pressing
3353     // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS.
3354     Builder.defineMacro("__ARM_ACLE",         "101");
3355     Builder.defineMacro("__ARM_ARCH",         "8");
3356     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
3357 
3358     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
3359     Builder.defineMacro("__ARM_FEATURE_CLZ");
3360     Builder.defineMacro("__ARM_FEATURE_FMA");
3361 
3362     // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3363     // 128-bit LDXP present, at which point this becomes 0x1f.
3364     Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf");
3365 
3366     // 0xe implies support for half, single and double precision operations.
3367     Builder.defineMacro("__ARM_FP", "0xe");
3368 
3369     // PCS specifies this for SysV variants, which is all we support. Other ABIs
3370     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
3371     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
3372 
3373     if (Opts.FastMath || Opts.FiniteMathOnly)
3374       Builder.defineMacro("__ARM_FP_FAST");
3375 
3376     if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3377       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
3378 
3379     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3380                         Opts.ShortWChar ? "2" : "4");
3381 
3382     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3383                         Opts.ShortEnums ? "1" : "4");
3384 
3385     if (BigEndian)
3386       Builder.defineMacro("__ARM_BIG_ENDIAN");
3387   }
3388   virtual void getTargetBuiltins(const Builtin::Info *&Records,
3389                                  unsigned &NumRecords) const {
3390     Records = BuiltinInfo;
3391     NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
3392   }
3393   virtual bool hasFeature(StringRef Feature) const {
3394     return Feature == "aarch64";
3395   }
3396   virtual void getGCCRegNames(const char * const *&Names,
3397                               unsigned &NumNames) const;
3398   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3399                                 unsigned &NumAliases) const;
3400 
3401   virtual bool isCLZForZeroUndef() const { return false; }
3402 
3403   virtual bool validateAsmConstraint(const char *&Name,
3404                                      TargetInfo::ConstraintInfo &Info) const {
3405     switch (*Name) {
3406     default: return false;
3407     case 'w': // An FP/SIMD vector register
3408       Info.setAllowsRegister();
3409       return true;
3410     case 'I': // Constant that can be used with an ADD instruction
3411     case 'J': // Constant that can be used with a SUB instruction
3412     case 'K': // Constant that can be used with a 32-bit logical instruction
3413     case 'L': // Constant that can be used with a 64-bit logical instruction
3414     case 'M': // Constant that can be used as a 32-bit MOV immediate
3415     case 'N': // Constant that can be used as a 64-bit MOV immediate
3416     case 'Y': // Floating point constant zero
3417     case 'Z': // Integer constant zero
3418       return true;
3419     case 'Q': // A memory reference with base register and no offset
3420       Info.setAllowsMemory();
3421       return true;
3422     case 'S': // A symbolic address
3423       Info.setAllowsRegister();
3424       return true;
3425     case 'U':
3426       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3427       // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3428       // Usa: An absolute symbolic address
3429       // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3430       llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3431     }
3432   }
3433 
3434   virtual const char *getClobbers() const {
3435     // There are no AArch64 clobbers shared by all asm statements.
3436     return "";
3437   }
3438 
3439   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3440     return TargetInfo::AArch64ABIBuiltinVaList;
3441   }
3442 };
3443 
3444 const char * const AArch64TargetInfo::GCCRegNames[] = {
3445   "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3446   "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3447   "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3448   "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3449 
3450   "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3451   "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3452   "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3453   "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3454 
3455   "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3456   "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3457   "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3458   "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3459 
3460   "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3461   "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3462   "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3463   "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3464 
3465   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3466   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3467   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3468   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3469 
3470   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3471   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3472   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3473   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3474 
3475   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3476   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3477   "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3478   "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3479 };
3480 
3481 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3482                                        unsigned &NumNames) const {
3483   Names = GCCRegNames;
3484   NumNames = llvm::array_lengthof(GCCRegNames);
3485 }
3486 
3487 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3488   { { "x16" }, "ip0"},
3489   { { "x17" }, "ip1"},
3490   { { "x29" }, "fp" },
3491   { { "x30" }, "lr" }
3492 };
3493 
3494 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3495                                          unsigned &NumAliases) const {
3496   Aliases = GCCRegAliases;
3497   NumAliases = llvm::array_lengthof(GCCRegAliases);
3498 
3499 }
3500 
3501 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
3502 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3503 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3504                                               ALL_LANGUAGES },
3505 #include "clang/Basic/BuiltinsAArch64.def"
3506 };
3507 
3508 } // end anonymous namespace
3509 
3510 namespace {
3511 class ARMTargetInfo : public TargetInfo {
3512   // Possible FPU choices.
3513   enum FPUMode {
3514     VFP2FPU = (1 << 0),
3515     VFP3FPU = (1 << 1),
3516     VFP4FPU = (1 << 2),
3517     NeonFPU = (1 << 3)
3518   };
3519 
3520   static bool FPUModeIsVFP(FPUMode Mode) {
3521     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3522   }
3523 
3524   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3525   static const char * const GCCRegNames[];
3526 
3527   std::string ABI, CPU;
3528 
3529   unsigned FPU : 4;
3530 
3531   unsigned IsAAPCS : 1;
3532   unsigned IsThumb : 1;
3533 
3534   // Initialized via features.
3535   unsigned SoftFloat : 1;
3536   unsigned SoftFloatABI : 1;
3537 
3538   static const Builtin::Info BuiltinInfo[];
3539 
3540   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3541     // On linux, binaries targeting old cpus call functions in libgcc to
3542     // perform atomic operations. The implementation in libgcc then calls into
3543     // the kernel which on armv6 and newer uses ldrex and strex. The net result
3544     // is that if we assume the kernel is at least as recent as the hardware,
3545     // it is safe to use atomic instructions on armv6 and newer.
3546     if (T.getOS() != llvm::Triple::Linux &&
3547         T.getOS() != llvm::Triple::FreeBSD &&
3548         T.getOS() != llvm::Triple::Bitrig)
3549       return false;
3550     StringRef ArchName = T.getArchName();
3551     if (T.getArch() == llvm::Triple::arm) {
3552       if (!ArchName.startswith("armv"))
3553         return false;
3554       StringRef VersionStr = ArchName.substr(4);
3555       unsigned Version;
3556       if (VersionStr.getAsInteger(10, Version))
3557         return false;
3558       return Version >= 6;
3559     }
3560     assert(T.getArch() == llvm::Triple::thumb);
3561     if (!ArchName.startswith("thumbv"))
3562       return false;
3563     StringRef VersionStr = ArchName.substr(6);
3564     unsigned Version;
3565     if (VersionStr.getAsInteger(10, Version))
3566       return false;
3567     return Version >= 7;
3568   }
3569 
3570 public:
3571   ARMTargetInfo(const std::string &TripleStr)
3572     : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true)
3573   {
3574     BigEndian = false;
3575     SizeType = UnsignedInt;
3576     PtrDiffType = SignedInt;
3577     // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3578     WCharType = UnsignedInt;
3579 
3580     // {} in inline assembly are neon specifiers, not assembly variant
3581     // specifiers.
3582     NoAsmVariants = true;
3583 
3584     // FIXME: Should we just treat this as a feature?
3585     IsThumb = getTriple().getArchName().startswith("thumb");
3586     if (IsThumb) {
3587       // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3588       // so set preferred for small types to 32.
3589       DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3590                            "i64:64:64-f32:32:32-f64:64:64-"
3591                            "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3592     } else {
3593       DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3594                            "i64:64:64-f32:32:32-f64:64:64-"
3595                            "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3596     }
3597 
3598     // ARM targets default to using the ARM C++ ABI.
3599     TheCXXABI.set(TargetCXXABI::GenericARM);
3600 
3601     // ARM has atomics up to 8 bytes
3602     MaxAtomicPromoteWidth = 64;
3603     if (shouldUseInlineAtomic(getTriple()))
3604       MaxAtomicInlineWidth = 64;
3605 
3606     // Do force alignment of members that follow zero length bitfields.  If
3607     // the alignment of the zero-length bitfield is greater than the member
3608     // that follows it, `bar', `bar' will be aligned as the  type of the
3609     // zero length bitfield.
3610     UseZeroLengthBitfieldAlignment = true;
3611   }
3612   virtual const char *getABI() const { return ABI.c_str(); }
3613   virtual bool setABI(const std::string &Name) {
3614     ABI = Name;
3615 
3616     // The defaults (above) are for AAPCS, check if we need to change them.
3617     //
3618     // FIXME: We need support for -meabi... we could just mangle it into the
3619     // name.
3620     if (Name == "apcs-gnu") {
3621       DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3622       // size_t is unsigned int on FreeBSD.
3623       if (getTriple().getOS() != llvm::Triple::FreeBSD)
3624         SizeType = UnsignedLong;
3625 
3626       // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3627       WCharType = SignedInt;
3628 
3629       // Do not respect the alignment of bit-field types when laying out
3630       // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3631       UseBitFieldTypeAlignment = false;
3632 
3633       /// gcc forces the alignment to 4 bytes, regardless of the type of the
3634       /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3635       /// gcc.
3636       ZeroLengthBitfieldBoundary = 32;
3637 
3638       IsAAPCS = false;
3639 
3640       if (IsThumb) {
3641         // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3642         // so set preferred for small types to 32.
3643         DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3644                              "i64:32:64-f32:32:32-f64:32:64-"
3645                              "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3646       } else {
3647         DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3648                              "i64:32:64-f32:32:32-f64:32:64-"
3649                              "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3650       }
3651 
3652       // FIXME: Override "preferred align" for double and long long.
3653     } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3654       // size_t is unsigned long on Darwin.
3655       if (getTriple().isOSDarwin())
3656         SizeType = UnsignedLong;
3657       IsAAPCS = true;
3658       // FIXME: Enumerated types are variable width in straight AAPCS.
3659     } else if (Name == "aapcs-linux") {
3660       IsAAPCS = true;
3661     } else
3662       return false;
3663 
3664     return true;
3665   }
3666 
3667   void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3668     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3669       Features["vfp2"] = true;
3670     else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3671              CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3672       Features["neon"] = true;
3673     else if (CPU == "swift" || CPU == "cortex-a7") {
3674       Features["vfp4"] = true;
3675       Features["neon"] = true;
3676     }
3677   }
3678 
3679   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3680                                  StringRef Name,
3681                                  bool Enabled) const {
3682     if (Name == "soft-float" || Name == "soft-float-abi" ||
3683         Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3684         Name == "d16" || Name == "neonfp") {
3685       Features[Name] = Enabled;
3686     } else
3687       return false;
3688 
3689     return true;
3690   }
3691 
3692   virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3693     FPU = 0;
3694     SoftFloat = SoftFloatABI = false;
3695     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3696       if (Features[i] == "+soft-float")
3697         SoftFloat = true;
3698       else if (Features[i] == "+soft-float-abi")
3699         SoftFloatABI = true;
3700       else if (Features[i] == "+vfp2")
3701         FPU |= VFP2FPU;
3702       else if (Features[i] == "+vfp3")
3703         FPU |= VFP3FPU;
3704       else if (Features[i] == "+vfp4")
3705         FPU |= VFP4FPU;
3706       else if (Features[i] == "+neon")
3707         FPU |= NeonFPU;
3708     }
3709 
3710     // Remove front-end specific options which the backend handles differently.
3711     std::vector<std::string>::iterator it;
3712     it = std::find(Features.begin(), Features.end(), "+soft-float");
3713     if (it != Features.end())
3714       Features.erase(it);
3715     it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3716     if (it != Features.end())
3717       Features.erase(it);
3718   }
3719 
3720   virtual bool hasFeature(StringRef Feature) const {
3721     return llvm::StringSwitch<bool>(Feature)
3722         .Case("arm", true)
3723         .Case("softfloat", SoftFloat)
3724         .Case("thumb", IsThumb)
3725         .Case("neon", FPU == NeonFPU && !SoftFloat &&
3726               StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3727         .Default(false);
3728   }
3729   // FIXME: Should we actually have some table instead of these switches?
3730   static const char *getCPUDefineSuffix(StringRef Name) {
3731     return llvm::StringSwitch<const char*>(Name)
3732       .Cases("arm8", "arm810", "4")
3733       .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3734       .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3735       .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3736       .Case("ep9312", "4T")
3737       .Cases("arm10tdmi", "arm1020t", "5T")
3738       .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3739       .Case("arm926ej-s", "5TEJ")
3740       .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3741       .Cases("xscale", "iwmmxt", "5TE")
3742       .Case("arm1136j-s", "6J")
3743       .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3744       .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3745       .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3746       .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3747       .Cases("cortex-a9", "cortex-a15", "7A")
3748       .Case("cortex-r5", "7R")
3749       .Case("cortex-a9-mp", "7F")
3750       .Case("swift", "7S")
3751       .Cases("cortex-m3", "cortex-m4", "7M")
3752       .Case("cortex-m0", "6M")
3753       .Case("cortex-a53", "8A")
3754       .Default(0);
3755   }
3756   static const char *getCPUProfile(StringRef Name) {
3757     return llvm::StringSwitch<const char*>(Name)
3758       .Cases("cortex-a8", "cortex-a9", "A")
3759       .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3760       .Case("cortex-r5", "R")
3761       .Default("");
3762   }
3763   virtual bool setCPU(const std::string &Name) {
3764     if (!getCPUDefineSuffix(Name))
3765       return false;
3766 
3767     CPU = Name;
3768     return true;
3769   }
3770   virtual void getTargetDefines(const LangOptions &Opts,
3771                                 MacroBuilder &Builder) const {
3772     // Target identification.
3773     Builder.defineMacro("__arm");
3774     Builder.defineMacro("__arm__");
3775 
3776     // Target properties.
3777     Builder.defineMacro("__ARMEL__");
3778     Builder.defineMacro("__LITTLE_ENDIAN__");
3779     Builder.defineMacro("__REGISTER_PREFIX__", "");
3780 
3781     StringRef CPUArch = getCPUDefineSuffix(CPU);
3782     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3783     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3784     StringRef CPUProfile = getCPUProfile(CPU);
3785     if (!CPUProfile.empty())
3786       Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3787 
3788     // Subtarget options.
3789 
3790     // FIXME: It's more complicated than this and we don't really support
3791     // interworking.
3792     if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3793       Builder.defineMacro("__THUMB_INTERWORK__");
3794 
3795     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3796       // M-class CPUs on Darwin follow AAPCS, but not EABI.
3797       if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3798         Builder.defineMacro("__ARM_EABI__");
3799       Builder.defineMacro("__ARM_PCS", "1");
3800 
3801       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3802         Builder.defineMacro("__ARM_PCS_VFP", "1");
3803     }
3804 
3805     if (SoftFloat)
3806       Builder.defineMacro("__SOFTFP__");
3807 
3808     if (CPU == "xscale")
3809       Builder.defineMacro("__XSCALE__");
3810 
3811     bool IsARMv7 = CPUArch.startswith("7");
3812     if (IsThumb) {
3813       Builder.defineMacro("__THUMBEL__");
3814       Builder.defineMacro("__thumb__");
3815       if (CPUArch == "6T2" || IsARMv7)
3816         Builder.defineMacro("__thumb2__");
3817     }
3818 
3819     // Note, this is always on in gcc, even though it doesn't make sense.
3820     Builder.defineMacro("__APCS_32__");
3821 
3822     if (FPUModeIsVFP((FPUMode) FPU)) {
3823       Builder.defineMacro("__VFP_FP__");
3824       if (FPU & VFP2FPU)
3825         Builder.defineMacro("__ARM_VFPV2__");
3826       if (FPU & VFP3FPU)
3827         Builder.defineMacro("__ARM_VFPV3__");
3828       if (FPU & VFP4FPU)
3829         Builder.defineMacro("__ARM_VFPV4__");
3830     }
3831 
3832     // This only gets set when Neon instructions are actually available, unlike
3833     // the VFP define, hence the soft float and arch check. This is subtly
3834     // different from gcc, we follow the intent which was that it should be set
3835     // when Neon instructions are actually available.
3836     if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3837       Builder.defineMacro("__ARM_NEON__");
3838   }
3839   virtual void getTargetBuiltins(const Builtin::Info *&Records,
3840                                  unsigned &NumRecords) const {
3841     Records = BuiltinInfo;
3842     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3843   }
3844   virtual bool isCLZForZeroUndef() const { return false; }
3845   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3846     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3847   }
3848   virtual void getGCCRegNames(const char * const *&Names,
3849                               unsigned &NumNames) const;
3850   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3851                                 unsigned &NumAliases) const;
3852   virtual bool validateAsmConstraint(const char *&Name,
3853                                      TargetInfo::ConstraintInfo &Info) const {
3854     switch (*Name) {
3855     default: break;
3856     case 'l': // r0-r7
3857     case 'h': // r8-r15
3858     case 'w': // VFP Floating point register single precision
3859     case 'P': // VFP Floating point register double precision
3860       Info.setAllowsRegister();
3861       return true;
3862     case 'Q': // A memory address that is a single base register.
3863       Info.setAllowsMemory();
3864       return true;
3865     case 'U': // a memory reference...
3866       switch (Name[1]) {
3867       case 'q': // ...ARMV4 ldrsb
3868       case 'v': // ...VFP load/store (reg+constant offset)
3869       case 'y': // ...iWMMXt load/store
3870       case 't': // address valid for load/store opaque types wider
3871                 // than 128-bits
3872       case 'n': // valid address for Neon doubleword vector load/store
3873       case 'm': // valid address for Neon element and structure load/store
3874       case 's': // valid address for non-offset loads/stores of quad-word
3875                 // values in four ARM registers
3876         Info.setAllowsMemory();
3877         Name++;
3878         return true;
3879       }
3880     }
3881     return false;
3882   }
3883   virtual std::string convertConstraint(const char *&Constraint) const {
3884     std::string R;
3885     switch (*Constraint) {
3886     case 'U':   // Two-character constraint; add "^" hint for later parsing.
3887       R = std::string("^") + std::string(Constraint, 2);
3888       Constraint++;
3889       break;
3890     case 'p': // 'p' should be translated to 'r' by default.
3891       R = std::string("r");
3892       break;
3893     default:
3894       return std::string(1, *Constraint);
3895     }
3896     return R;
3897   }
3898   virtual bool validateConstraintModifier(StringRef Constraint,
3899                                           const char Modifier,
3900                                           unsigned Size) const {
3901     bool isOutput = (Constraint[0] == '=');
3902     bool isInOut = (Constraint[0] == '+');
3903 
3904     // Strip off constraint modifiers.
3905     while (Constraint[0] == '=' ||
3906            Constraint[0] == '+' ||
3907            Constraint[0] == '&')
3908       Constraint = Constraint.substr(1);
3909 
3910     switch (Constraint[0]) {
3911     default: break;
3912     case 'r': {
3913       switch (Modifier) {
3914       default:
3915         return (isInOut || isOutput || Size <= 32);
3916       case 'q':
3917         // A register of size 32 cannot fit a vector type.
3918         return false;
3919       }
3920     }
3921     }
3922 
3923     return true;
3924   }
3925   virtual const char *getClobbers() const {
3926     // FIXME: Is this really right?
3927     return "";
3928   }
3929 
3930   virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3931     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3932   }
3933 
3934   virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3935     if (RegNo == 0) return 0;
3936     if (RegNo == 1) return 1;
3937     return -1;
3938   }
3939 };
3940 
3941 const char * const ARMTargetInfo::GCCRegNames[] = {
3942   // Integer registers
3943   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3944   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3945 
3946   // Float registers
3947   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3948   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3949   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3950   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3951 
3952   // Double registers
3953   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3954   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3955   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3956   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3957 
3958   // Quad registers
3959   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3960   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3961 };
3962 
3963 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3964                                    unsigned &NumNames) const {
3965   Names = GCCRegNames;
3966   NumNames = llvm::array_lengthof(GCCRegNames);
3967 }
3968 
3969 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3970   { { "a1" }, "r0" },
3971   { { "a2" }, "r1" },
3972   { { "a3" }, "r2" },
3973   { { "a4" }, "r3" },
3974   { { "v1" }, "r4" },
3975   { { "v2" }, "r5" },
3976   { { "v3" }, "r6" },
3977   { { "v4" }, "r7" },
3978   { { "v5" }, "r8" },
3979   { { "v6", "rfp" }, "r9" },
3980   { { "sl" }, "r10" },
3981   { { "fp" }, "r11" },
3982   { { "ip" }, "r12" },
3983   { { "r13" }, "sp" },
3984   { { "r14" }, "lr" },
3985   { { "r15" }, "pc" },
3986   // The S, D and Q registers overlap, but aren't really aliases; we
3987   // don't want to substitute one of these for a different-sized one.
3988 };
3989 
3990 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3991                                        unsigned &NumAliases) const {
3992   Aliases = GCCRegAliases;
3993   NumAliases = llvm::array_lengthof(GCCRegAliases);
3994 }
3995 
3996 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3997 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3998 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3999                                               ALL_LANGUAGES },
4000 #include "clang/Basic/BuiltinsARM.def"
4001 };
4002 } // end anonymous namespace.
4003 
4004 namespace {
4005 class DarwinARMTargetInfo :
4006   public DarwinTargetInfo<ARMTargetInfo> {
4007 protected:
4008   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4009                             MacroBuilder &Builder) const {
4010     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4011   }
4012 
4013 public:
4014   DarwinARMTargetInfo(const std::string& triple)
4015     : DarwinTargetInfo<ARMTargetInfo>(triple) {
4016     HasAlignMac68kSupport = true;
4017     // iOS always has 64-bit atomic instructions.
4018     // FIXME: This should be based off of the target features in ARMTargetInfo.
4019     MaxAtomicInlineWidth = 64;
4020 
4021     // Darwin on iOS uses a variant of the ARM C++ ABI.
4022     TheCXXABI.set(TargetCXXABI::iOS);
4023   }
4024 };
4025 } // end anonymous namespace.
4026 
4027 
4028 namespace {
4029 // Hexagon abstract base class
4030 class HexagonTargetInfo : public TargetInfo {
4031   static const Builtin::Info BuiltinInfo[];
4032   static const char * const GCCRegNames[];
4033   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4034   std::string CPU;
4035 public:
4036   HexagonTargetInfo(const std::string& triple) : TargetInfo(triple)  {
4037     BigEndian = false;
4038     DescriptionString = ("e-p:32:32:32-"
4039                          "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
4040                          "f64:64:64-f32:32:32-a0:0-n32");
4041 
4042     // {} in inline assembly are packet specifiers, not assembly variant
4043     // specifiers.
4044     NoAsmVariants = true;
4045   }
4046 
4047   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4048                                  unsigned &NumRecords) const {
4049     Records = BuiltinInfo;
4050     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4051   }
4052 
4053   virtual bool validateAsmConstraint(const char *&Name,
4054                                      TargetInfo::ConstraintInfo &Info) const {
4055     return true;
4056   }
4057 
4058   virtual void getTargetDefines(const LangOptions &Opts,
4059                                 MacroBuilder &Builder) const;
4060 
4061   virtual bool hasFeature(StringRef Feature) const {
4062     return Feature == "hexagon";
4063   }
4064 
4065   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4066     return TargetInfo::CharPtrBuiltinVaList;
4067   }
4068   virtual void getGCCRegNames(const char * const *&Names,
4069                               unsigned &NumNames) const;
4070   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4071                                 unsigned &NumAliases) const;
4072   virtual const char *getClobbers() const {
4073     return "";
4074   }
4075 
4076   static const char *getHexagonCPUSuffix(StringRef Name) {
4077     return llvm::StringSwitch<const char*>(Name)
4078       .Case("hexagonv4", "4")
4079       .Case("hexagonv5", "5")
4080       .Default(0);
4081   }
4082 
4083   virtual bool setCPU(const std::string &Name) {
4084     if (!getHexagonCPUSuffix(Name))
4085       return false;
4086 
4087     CPU = Name;
4088     return true;
4089   }
4090 };
4091 
4092 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4093                                 MacroBuilder &Builder) const {
4094   Builder.defineMacro("qdsp6");
4095   Builder.defineMacro("__qdsp6", "1");
4096   Builder.defineMacro("__qdsp6__", "1");
4097 
4098   Builder.defineMacro("hexagon");
4099   Builder.defineMacro("__hexagon", "1");
4100   Builder.defineMacro("__hexagon__", "1");
4101 
4102   if(CPU == "hexagonv1") {
4103     Builder.defineMacro("__HEXAGON_V1__");
4104     Builder.defineMacro("__HEXAGON_ARCH__", "1");
4105     if(Opts.HexagonQdsp6Compat) {
4106       Builder.defineMacro("__QDSP6_V1__");
4107       Builder.defineMacro("__QDSP6_ARCH__", "1");
4108     }
4109   }
4110   else if(CPU == "hexagonv2") {
4111     Builder.defineMacro("__HEXAGON_V2__");
4112     Builder.defineMacro("__HEXAGON_ARCH__", "2");
4113     if(Opts.HexagonQdsp6Compat) {
4114       Builder.defineMacro("__QDSP6_V2__");
4115       Builder.defineMacro("__QDSP6_ARCH__", "2");
4116     }
4117   }
4118   else if(CPU == "hexagonv3") {
4119     Builder.defineMacro("__HEXAGON_V3__");
4120     Builder.defineMacro("__HEXAGON_ARCH__", "3");
4121     if(Opts.HexagonQdsp6Compat) {
4122       Builder.defineMacro("__QDSP6_V3__");
4123       Builder.defineMacro("__QDSP6_ARCH__", "3");
4124     }
4125   }
4126   else if(CPU == "hexagonv4") {
4127     Builder.defineMacro("__HEXAGON_V4__");
4128     Builder.defineMacro("__HEXAGON_ARCH__", "4");
4129     if(Opts.HexagonQdsp6Compat) {
4130       Builder.defineMacro("__QDSP6_V4__");
4131       Builder.defineMacro("__QDSP6_ARCH__", "4");
4132     }
4133   }
4134   else if(CPU == "hexagonv5") {
4135     Builder.defineMacro("__HEXAGON_V5__");
4136     Builder.defineMacro("__HEXAGON_ARCH__", "5");
4137     if(Opts.HexagonQdsp6Compat) {
4138       Builder.defineMacro("__QDSP6_V5__");
4139       Builder.defineMacro("__QDSP6_ARCH__", "5");
4140     }
4141   }
4142 }
4143 
4144 const char * const HexagonTargetInfo::GCCRegNames[] = {
4145   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4146   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4147   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4148   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4149   "p0", "p1", "p2", "p3",
4150   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4151 };
4152 
4153 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4154                                    unsigned &NumNames) const {
4155   Names = GCCRegNames;
4156   NumNames = llvm::array_lengthof(GCCRegNames);
4157 }
4158 
4159 
4160 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4161   { { "sp" }, "r29" },
4162   { { "fp" }, "r30" },
4163   { { "lr" }, "r31" },
4164  };
4165 
4166 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4167                                      unsigned &NumAliases) const {
4168   Aliases = GCCRegAliases;
4169   NumAliases = llvm::array_lengthof(GCCRegAliases);
4170 }
4171 
4172 
4173 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4174 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4175 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4176                                               ALL_LANGUAGES },
4177 #include "clang/Basic/BuiltinsHexagon.def"
4178 };
4179 }
4180 
4181 
4182 namespace {
4183 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4184 class SparcTargetInfo : public TargetInfo {
4185   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4186   static const char * const GCCRegNames[];
4187   bool SoftFloat;
4188 public:
4189   SparcTargetInfo(const std::string &triple) : TargetInfo(triple) {}
4190 
4191   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4192                                  StringRef Name,
4193                                  bool Enabled) const {
4194     if (Name == "soft-float")
4195       Features[Name] = Enabled;
4196     else
4197       return false;
4198 
4199     return true;
4200   }
4201   virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4202     SoftFloat = false;
4203     for (unsigned i = 0, e = Features.size(); i != e; ++i)
4204       if (Features[i] == "+soft-float")
4205         SoftFloat = true;
4206   }
4207   virtual void getTargetDefines(const LangOptions &Opts,
4208                                 MacroBuilder &Builder) const {
4209     DefineStd(Builder, "sparc", Opts);
4210     Builder.defineMacro("__REGISTER_PREFIX__", "");
4211 
4212     if (SoftFloat)
4213       Builder.defineMacro("SOFT_FLOAT", "1");
4214   }
4215 
4216   virtual bool hasFeature(StringRef Feature) const {
4217     return llvm::StringSwitch<bool>(Feature)
4218              .Case("softfloat", SoftFloat)
4219              .Case("sparc", true)
4220              .Default(false);
4221   }
4222 
4223   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4224                                  unsigned &NumRecords) const {
4225     // FIXME: Implement!
4226   }
4227   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4228     return TargetInfo::VoidPtrBuiltinVaList;
4229   }
4230   virtual void getGCCRegNames(const char * const *&Names,
4231                               unsigned &NumNames) const;
4232   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4233                                 unsigned &NumAliases) const;
4234   virtual bool validateAsmConstraint(const char *&Name,
4235                                      TargetInfo::ConstraintInfo &info) const {
4236     // FIXME: Implement!
4237     return false;
4238   }
4239   virtual const char *getClobbers() const {
4240     // FIXME: Implement!
4241     return "";
4242   }
4243 };
4244 
4245 const char * const SparcTargetInfo::GCCRegNames[] = {
4246   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4247   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4248   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4249   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4250 };
4251 
4252 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4253                                      unsigned &NumNames) const {
4254   Names = GCCRegNames;
4255   NumNames = llvm::array_lengthof(GCCRegNames);
4256 }
4257 
4258 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4259   { { "g0" }, "r0" },
4260   { { "g1" }, "r1" },
4261   { { "g2" }, "r2" },
4262   { { "g3" }, "r3" },
4263   { { "g4" }, "r4" },
4264   { { "g5" }, "r5" },
4265   { { "g6" }, "r6" },
4266   { { "g7" }, "r7" },
4267   { { "o0" }, "r8" },
4268   { { "o1" }, "r9" },
4269   { { "o2" }, "r10" },
4270   { { "o3" }, "r11" },
4271   { { "o4" }, "r12" },
4272   { { "o5" }, "r13" },
4273   { { "o6", "sp" }, "r14" },
4274   { { "o7" }, "r15" },
4275   { { "l0" }, "r16" },
4276   { { "l1" }, "r17" },
4277   { { "l2" }, "r18" },
4278   { { "l3" }, "r19" },
4279   { { "l4" }, "r20" },
4280   { { "l5" }, "r21" },
4281   { { "l6" }, "r22" },
4282   { { "l7" }, "r23" },
4283   { { "i0" }, "r24" },
4284   { { "i1" }, "r25" },
4285   { { "i2" }, "r26" },
4286   { { "i3" }, "r27" },
4287   { { "i4" }, "r28" },
4288   { { "i5" }, "r29" },
4289   { { "i6", "fp" }, "r30" },
4290   { { "i7" }, "r31" },
4291 };
4292 
4293 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4294                                        unsigned &NumAliases) const {
4295   Aliases = GCCRegAliases;
4296   NumAliases = llvm::array_lengthof(GCCRegAliases);
4297 }
4298 
4299 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
4300 class SparcV8TargetInfo : public SparcTargetInfo {
4301 public:
4302   SparcV8TargetInfo(const std::string& triple) : SparcTargetInfo(triple) {
4303     // FIXME: Support Sparc quad-precision long double?
4304     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4305                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4306   }
4307 
4308   virtual void getTargetDefines(const LangOptions &Opts,
4309                                 MacroBuilder &Builder) const {
4310     SparcTargetInfo::getTargetDefines(Opts, Builder);
4311     Builder.defineMacro("__sparcv8");
4312   }
4313 };
4314 
4315 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4316 class SparcV9TargetInfo : public SparcTargetInfo {
4317 public:
4318   SparcV9TargetInfo(const std::string& triple) : SparcTargetInfo(triple) {
4319     // FIXME: Support Sparc quad-precision long double?
4320     DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4321                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128";
4322     // This is an LP64 platform.
4323     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4324 
4325     // OpenBSD uses long long for int64_t and intmax_t.
4326     if (getTriple().getOS() == llvm::Triple::OpenBSD) {
4327       IntMaxType = SignedLongLong;
4328       UIntMaxType = UnsignedLongLong;
4329     } else {
4330       IntMaxType = SignedLong;
4331       UIntMaxType = UnsignedLong;
4332     }
4333     Int64Type = IntMaxType;
4334   }
4335 
4336   virtual void getTargetDefines(const LangOptions &Opts,
4337                                 MacroBuilder &Builder) const {
4338     SparcTargetInfo::getTargetDefines(Opts, Builder);
4339     Builder.defineMacro("__sparcv9");
4340     Builder.defineMacro("__arch64__");
4341     // Solaris and its derivative AuroraUX don't need these variants, but the
4342     // BSDs do.
4343     if (getTriple().getOS() != llvm::Triple::Solaris &&
4344         getTriple().getOS() != llvm::Triple::AuroraUX) {
4345       Builder.defineMacro("__sparc64__");
4346       Builder.defineMacro("__sparc_v9__");
4347       Builder.defineMacro("__sparcv9__");
4348     }
4349   }
4350 };
4351 
4352 } // end anonymous namespace.
4353 
4354 namespace {
4355 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4356 public:
4357   AuroraUXSparcV8TargetInfo(const std::string& triple) :
4358       AuroraUXTargetInfo<SparcV8TargetInfo>(triple) {
4359     SizeType = UnsignedInt;
4360     PtrDiffType = SignedInt;
4361   }
4362 };
4363 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4364 public:
4365   SolarisSparcV8TargetInfo(const std::string& triple) :
4366       SolarisTargetInfo<SparcV8TargetInfo>(triple) {
4367     SizeType = UnsignedInt;
4368     PtrDiffType = SignedInt;
4369   }
4370 };
4371 } // end anonymous namespace.
4372 
4373 namespace {
4374   class SystemZTargetInfo : public TargetInfo {
4375     static const char *const GCCRegNames[];
4376 
4377   public:
4378     SystemZTargetInfo(const std::string& triple) : TargetInfo(triple) {
4379       TLSSupported = true;
4380       IntWidth = IntAlign = 32;
4381       LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
4382       PointerWidth = PointerAlign = 64;
4383       LongDoubleWidth = 128;
4384       LongDoubleAlign = 64;
4385       LongDoubleFormat = &llvm::APFloat::IEEEquad;
4386       MinGlobalAlign = 16;
4387       DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64"
4388        "-f32:32-f64:64-f128:64-a0:8:16-n32:64";
4389       MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4390     }
4391     virtual void getTargetDefines(const LangOptions &Opts,
4392                                   MacroBuilder &Builder) const {
4393       Builder.defineMacro("__s390__");
4394       Builder.defineMacro("__s390x__");
4395       Builder.defineMacro("__zarch__");
4396       Builder.defineMacro("__LONG_DOUBLE_128__");
4397     }
4398     virtual void getTargetBuiltins(const Builtin::Info *&Records,
4399                                    unsigned &NumRecords) const {
4400       // FIXME: Implement.
4401       Records = 0;
4402       NumRecords = 0;
4403     }
4404 
4405     virtual void getGCCRegNames(const char *const *&Names,
4406                                 unsigned &NumNames) const;
4407     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4408                                   unsigned &NumAliases) const {
4409       // No aliases.
4410       Aliases = 0;
4411       NumAliases = 0;
4412     }
4413     virtual bool validateAsmConstraint(const char *&Name,
4414                                        TargetInfo::ConstraintInfo &info) const;
4415     virtual const char *getClobbers() const {
4416       // FIXME: Is this really right?
4417       return "";
4418     }
4419     virtual BuiltinVaListKind getBuiltinVaListKind() const {
4420       return TargetInfo::SystemZBuiltinVaList;
4421     }
4422   };
4423 
4424   const char *const SystemZTargetInfo::GCCRegNames[] = {
4425     "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
4426     "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
4427     "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
4428     "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
4429   };
4430 
4431   void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
4432                                          unsigned &NumNames) const {
4433     Names = GCCRegNames;
4434     NumNames = llvm::array_lengthof(GCCRegNames);
4435   }
4436 
4437   bool SystemZTargetInfo::
4438   validateAsmConstraint(const char *&Name,
4439                         TargetInfo::ConstraintInfo &Info) const {
4440     switch (*Name) {
4441     default:
4442       return false;
4443 
4444     case 'a': // Address register
4445     case 'd': // Data register (equivalent to 'r')
4446     case 'f': // Floating-point register
4447       Info.setAllowsRegister();
4448       return true;
4449 
4450     case 'I': // Unsigned 8-bit constant
4451     case 'J': // Unsigned 12-bit constant
4452     case 'K': // Signed 16-bit constant
4453     case 'L': // Signed 20-bit displacement (on all targets we support)
4454     case 'M': // 0x7fffffff
4455       return true;
4456 
4457     case 'Q': // Memory with base and unsigned 12-bit displacement
4458     case 'R': // Likewise, plus an index
4459     case 'S': // Memory with base and signed 20-bit displacement
4460     case 'T': // Likewise, plus an index
4461       Info.setAllowsMemory();
4462       return true;
4463     }
4464   }
4465 }
4466 
4467 namespace {
4468   class MSP430TargetInfo : public TargetInfo {
4469     static const char * const GCCRegNames[];
4470   public:
4471     MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) {
4472       BigEndian = false;
4473       TLSSupported = false;
4474       IntWidth = 16; IntAlign = 16;
4475       LongWidth = 32; LongLongWidth = 64;
4476       LongAlign = LongLongAlign = 16;
4477       PointerWidth = 16; PointerAlign = 16;
4478       SuitableAlign = 16;
4479       SizeType = UnsignedInt;
4480       IntMaxType = SignedLong;
4481       UIntMaxType = UnsignedLong;
4482       IntPtrType = SignedShort;
4483       PtrDiffType = SignedInt;
4484       SigAtomicType = SignedLong;
4485       DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4486    }
4487     virtual void getTargetDefines(const LangOptions &Opts,
4488                                   MacroBuilder &Builder) const {
4489       Builder.defineMacro("MSP430");
4490       Builder.defineMacro("__MSP430__");
4491       // FIXME: defines for different 'flavours' of MCU
4492     }
4493     virtual void getTargetBuiltins(const Builtin::Info *&Records,
4494                                    unsigned &NumRecords) const {
4495      // FIXME: Implement.
4496       Records = 0;
4497       NumRecords = 0;
4498     }
4499     virtual bool hasFeature(StringRef Feature) const {
4500       return Feature == "msp430";
4501     }
4502     virtual void getGCCRegNames(const char * const *&Names,
4503                                 unsigned &NumNames) const;
4504     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4505                                   unsigned &NumAliases) const {
4506       // No aliases.
4507       Aliases = 0;
4508       NumAliases = 0;
4509     }
4510     virtual bool validateAsmConstraint(const char *&Name,
4511                                        TargetInfo::ConstraintInfo &info) const {
4512       // No target constraints for now.
4513       return false;
4514     }
4515     virtual const char *getClobbers() const {
4516       // FIXME: Is this really right?
4517       return "";
4518     }
4519     virtual BuiltinVaListKind getBuiltinVaListKind() const {
4520       // FIXME: implement
4521       return TargetInfo::CharPtrBuiltinVaList;
4522    }
4523   };
4524 
4525   const char * const MSP430TargetInfo::GCCRegNames[] = {
4526     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4527     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4528   };
4529 
4530   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4531                                         unsigned &NumNames) const {
4532     Names = GCCRegNames;
4533     NumNames = llvm::array_lengthof(GCCRegNames);
4534   }
4535 }
4536 
4537 namespace {
4538 
4539   // LLVM and Clang cannot be used directly to output native binaries for
4540   // target, but is used to compile C code to llvm bitcode with correct
4541   // type and alignment information.
4542   //
4543   // TCE uses the llvm bitcode as input and uses it for generating customized
4544   // target processor and program binary. TCE co-design environment is
4545   // publicly available in http://tce.cs.tut.fi
4546 
4547   static const unsigned TCEOpenCLAddrSpaceMap[] = {
4548       3, // opencl_global
4549       4, // opencl_local
4550       5, // opencl_constant
4551       0, // cuda_device
4552       0, // cuda_constant
4553       0  // cuda_shared
4554   };
4555 
4556   class TCETargetInfo : public TargetInfo{
4557   public:
4558     TCETargetInfo(const std::string& triple) : TargetInfo(triple) {
4559       TLSSupported = false;
4560       IntWidth = 32;
4561       LongWidth = LongLongWidth = 32;
4562       PointerWidth = 32;
4563       IntAlign = 32;
4564       LongAlign = LongLongAlign = 32;
4565       PointerAlign = 32;
4566       SuitableAlign = 32;
4567       SizeType = UnsignedInt;
4568       IntMaxType = SignedLong;
4569       UIntMaxType = UnsignedLong;
4570       IntPtrType = SignedInt;
4571       PtrDiffType = SignedInt;
4572       FloatWidth = 32;
4573       FloatAlign = 32;
4574       DoubleWidth = 32;
4575       DoubleAlign = 32;
4576       LongDoubleWidth = 32;
4577       LongDoubleAlign = 32;
4578       FloatFormat = &llvm::APFloat::IEEEsingle;
4579       DoubleFormat = &llvm::APFloat::IEEEsingle;
4580       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4581       DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4582                           "i16:16:32-i32:32:32-i64:32:32-"
4583                           "f32:32:32-f64:32:32-v64:32:32-"
4584                           "v128:32:32-a0:0:32-n32";
4585       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4586     }
4587 
4588     virtual void getTargetDefines(const LangOptions &Opts,
4589                                   MacroBuilder &Builder) const {
4590       DefineStd(Builder, "tce", Opts);
4591       Builder.defineMacro("__TCE__");
4592       Builder.defineMacro("__TCE_V1__");
4593     }
4594     virtual bool hasFeature(StringRef Feature) const {
4595       return Feature == "tce";
4596     }
4597 
4598     virtual void getTargetBuiltins(const Builtin::Info *&Records,
4599                                    unsigned &NumRecords) const {}
4600     virtual const char *getClobbers() const {
4601       return "";
4602     }
4603     virtual BuiltinVaListKind getBuiltinVaListKind() const {
4604       return TargetInfo::VoidPtrBuiltinVaList;
4605     }
4606     virtual void getGCCRegNames(const char * const *&Names,
4607                                 unsigned &NumNames) const {}
4608     virtual bool validateAsmConstraint(const char *&Name,
4609                                        TargetInfo::ConstraintInfo &info) const {
4610       return true;
4611     }
4612     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4613                                   unsigned &NumAliases) const {}
4614   };
4615 }
4616 
4617 namespace {
4618 class MipsTargetInfoBase : public TargetInfo {
4619   static const Builtin::Info BuiltinInfo[];
4620   std::string CPU;
4621   bool IsMips16;
4622   bool IsMicromips;
4623   bool IsSingleFloat;
4624   enum MipsFloatABI {
4625     HardFloat, SoftFloat
4626   } FloatABI;
4627   enum DspRevEnum {
4628     NoDSP, DSP1, DSP2
4629   } DspRev;
4630 
4631 protected:
4632   std::string ABI;
4633 
4634 public:
4635   MipsTargetInfoBase(const std::string& triple,
4636                      const std::string& ABIStr,
4637                      const std::string& CPUStr)
4638     : TargetInfo(triple),
4639       CPU(CPUStr),
4640       IsMips16(false),
4641       IsMicromips(false),
4642       IsSingleFloat(false),
4643       FloatABI(HardFloat),
4644       DspRev(NoDSP),
4645       ABI(ABIStr)
4646   {}
4647 
4648   virtual const char *getABI() const { return ABI.c_str(); }
4649   virtual bool setABI(const std::string &Name) = 0;
4650   virtual bool setCPU(const std::string &Name) {
4651     CPU = Name;
4652     return true;
4653   }
4654   void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4655     Features[ABI] = true;
4656     Features[CPU] = true;
4657   }
4658 
4659   virtual void getTargetDefines(const LangOptions &Opts,
4660                                 MacroBuilder &Builder) const {
4661     DefineStd(Builder, "mips", Opts);
4662     Builder.defineMacro("_mips");
4663     Builder.defineMacro("__REGISTER_PREFIX__", "");
4664 
4665     switch (FloatABI) {
4666     case HardFloat:
4667       Builder.defineMacro("__mips_hard_float", Twine(1));
4668       break;
4669     case SoftFloat:
4670       Builder.defineMacro("__mips_soft_float", Twine(1));
4671       break;
4672     }
4673 
4674     if (IsSingleFloat)
4675       Builder.defineMacro("__mips_single_float", Twine(1));
4676 
4677     if (IsMips16)
4678       Builder.defineMacro("__mips16", Twine(1));
4679 
4680     if (IsMicromips)
4681       Builder.defineMacro("__mips_micromips", Twine(1));
4682 
4683     switch (DspRev) {
4684     default:
4685       break;
4686     case DSP1:
4687       Builder.defineMacro("__mips_dsp_rev", Twine(1));
4688       Builder.defineMacro("__mips_dsp", Twine(1));
4689       break;
4690     case DSP2:
4691       Builder.defineMacro("__mips_dsp_rev", Twine(2));
4692       Builder.defineMacro("__mips_dspr2", Twine(1));
4693       Builder.defineMacro("__mips_dsp", Twine(1));
4694       break;
4695     }
4696 
4697     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4698     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4699     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4700 
4701     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4702     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4703   }
4704 
4705   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4706                                  unsigned &NumRecords) const {
4707     Records = BuiltinInfo;
4708     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4709   }
4710   virtual bool hasFeature(StringRef Feature) const {
4711     return Feature == "mips";
4712   }
4713   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4714     return TargetInfo::VoidPtrBuiltinVaList;
4715   }
4716   virtual void getGCCRegNames(const char * const *&Names,
4717                               unsigned &NumNames) const {
4718     static const char * const GCCRegNames[] = {
4719       // CPU register names
4720       // Must match second column of GCCRegAliases
4721       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4722       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4723       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4724       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4725       // Floating point register names
4726       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4727       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4728       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4729       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4730       // Hi/lo and condition register names
4731       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4732       "$fcc5","$fcc6","$fcc7"
4733     };
4734     Names = GCCRegNames;
4735     NumNames = llvm::array_lengthof(GCCRegNames);
4736   }
4737   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4738                                 unsigned &NumAliases) const = 0;
4739   virtual bool validateAsmConstraint(const char *&Name,
4740                                      TargetInfo::ConstraintInfo &Info) const {
4741     switch (*Name) {
4742     default:
4743       return false;
4744 
4745     case 'r': // CPU registers.
4746     case 'd': // Equivalent to "r" unless generating MIPS16 code.
4747     case 'y': // Equivalent to "r", backwards compatibility only.
4748     case 'f': // floating-point registers.
4749     case 'c': // $25 for indirect jumps
4750     case 'l': // lo register
4751     case 'x': // hilo register pair
4752       Info.setAllowsRegister();
4753       return true;
4754     case 'R': // An address that can be used in a non-macro load or store
4755       Info.setAllowsMemory();
4756       return true;
4757     }
4758   }
4759 
4760   virtual const char *getClobbers() const {
4761     // FIXME: Implement!
4762     return "";
4763   }
4764 
4765   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4766                                  StringRef Name,
4767                                  bool Enabled) const {
4768     if (Name == "soft-float" || Name == "single-float" ||
4769         Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4770         Name == "mips32" || Name == "mips32r2" ||
4771         Name == "mips64" || Name == "mips64r2" ||
4772         Name == "mips16" || Name == "micromips" ||
4773         Name == "dsp" || Name == "dspr2") {
4774       Features[Name] = Enabled;
4775       return true;
4776     } else if (Name == "32") {
4777       Features["o32"] = Enabled;
4778       return true;
4779     } else if (Name == "64") {
4780       Features["n64"] = Enabled;
4781       return true;
4782     }
4783     return false;
4784   }
4785 
4786   virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4787     IsMips16 = false;
4788     IsMicromips = false;
4789     IsSingleFloat = false;
4790     FloatABI = HardFloat;
4791     DspRev = NoDSP;
4792 
4793     for (std::vector<std::string>::iterator it = Features.begin(),
4794          ie = Features.end(); it != ie; ++it) {
4795       if (*it == "+single-float")
4796         IsSingleFloat = true;
4797       else if (*it == "+soft-float")
4798         FloatABI = SoftFloat;
4799       else if (*it == "+mips16")
4800         IsMips16 = true;
4801       else if (*it == "+micromips")
4802         IsMicromips = true;
4803       else if (*it == "+dsp")
4804         DspRev = std::max(DspRev, DSP1);
4805       else if (*it == "+dspr2")
4806         DspRev = std::max(DspRev, DSP2);
4807     }
4808 
4809     // Remove front-end specific option.
4810     std::vector<std::string>::iterator it =
4811       std::find(Features.begin(), Features.end(), "+soft-float");
4812     if (it != Features.end())
4813       Features.erase(it);
4814   }
4815 
4816   virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4817     if (RegNo == 0) return 4;
4818     if (RegNo == 1) return 5;
4819     return -1;
4820   }
4821 };
4822 
4823 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4824 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4825 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4826                                               ALL_LANGUAGES },
4827 #include "clang/Basic/BuiltinsMips.def"
4828 };
4829 
4830 class Mips32TargetInfoBase : public MipsTargetInfoBase {
4831 public:
4832   Mips32TargetInfoBase(const std::string& triple) :
4833     MipsTargetInfoBase(triple, "o32", "mips32") {
4834     SizeType = UnsignedInt;
4835     PtrDiffType = SignedInt;
4836     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4837   }
4838   virtual bool setABI(const std::string &Name) {
4839     if ((Name == "o32") || (Name == "eabi")) {
4840       ABI = Name;
4841       return true;
4842     } else if (Name == "32") {
4843       ABI = "o32";
4844       return true;
4845     } else
4846       return false;
4847   }
4848   virtual void getTargetDefines(const LangOptions &Opts,
4849                                 MacroBuilder &Builder) const {
4850     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4851 
4852     if (ABI == "o32") {
4853       Builder.defineMacro("__mips_o32");
4854       Builder.defineMacro("_ABIO32", "1");
4855       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4856     }
4857     else if (ABI == "eabi")
4858       Builder.defineMacro("__mips_eabi");
4859     else
4860       llvm_unreachable("Invalid ABI for Mips32.");
4861   }
4862   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4863                                 unsigned &NumAliases) const {
4864     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4865       { { "at" },  "$1" },
4866       { { "v0" },  "$2" },
4867       { { "v1" },  "$3" },
4868       { { "a0" },  "$4" },
4869       { { "a1" },  "$5" },
4870       { { "a2" },  "$6" },
4871       { { "a3" },  "$7" },
4872       { { "t0" },  "$8" },
4873       { { "t1" },  "$9" },
4874       { { "t2" }, "$10" },
4875       { { "t3" }, "$11" },
4876       { { "t4" }, "$12" },
4877       { { "t5" }, "$13" },
4878       { { "t6" }, "$14" },
4879       { { "t7" }, "$15" },
4880       { { "s0" }, "$16" },
4881       { { "s1" }, "$17" },
4882       { { "s2" }, "$18" },
4883       { { "s3" }, "$19" },
4884       { { "s4" }, "$20" },
4885       { { "s5" }, "$21" },
4886       { { "s6" }, "$22" },
4887       { { "s7" }, "$23" },
4888       { { "t8" }, "$24" },
4889       { { "t9" }, "$25" },
4890       { { "k0" }, "$26" },
4891       { { "k1" }, "$27" },
4892       { { "gp" }, "$28" },
4893       { { "sp","$sp" }, "$29" },
4894       { { "fp","$fp" }, "$30" },
4895       { { "ra" }, "$31" }
4896     };
4897     Aliases = GCCRegAliases;
4898     NumAliases = llvm::array_lengthof(GCCRegAliases);
4899   }
4900 };
4901 
4902 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4903 public:
4904   Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4905     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4906                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4907   }
4908   virtual void getTargetDefines(const LangOptions &Opts,
4909                                 MacroBuilder &Builder) const {
4910     DefineStd(Builder, "MIPSEB", Opts);
4911     Builder.defineMacro("_MIPSEB");
4912     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4913   }
4914 };
4915 
4916 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4917 public:
4918   Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4919     BigEndian = false;
4920     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4921                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4922   }
4923   virtual void getTargetDefines(const LangOptions &Opts,
4924                                 MacroBuilder &Builder) const {
4925     DefineStd(Builder, "MIPSEL", Opts);
4926     Builder.defineMacro("_MIPSEL");
4927     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4928   }
4929 };
4930 
4931 class Mips64TargetInfoBase : public MipsTargetInfoBase {
4932   virtual void SetDescriptionString(const std::string &Name) = 0;
4933 public:
4934   Mips64TargetInfoBase(const std::string& triple) :
4935     MipsTargetInfoBase(triple, "n64", "mips64") {
4936     LongWidth = LongAlign = 64;
4937     PointerWidth = PointerAlign = 64;
4938     LongDoubleWidth = LongDoubleAlign = 128;
4939     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4940     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4941       LongDoubleWidth = LongDoubleAlign = 64;
4942       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4943     }
4944     SuitableAlign = 128;
4945     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4946   }
4947   virtual bool setABI(const std::string &Name) {
4948     SetDescriptionString(Name);
4949     if (Name == "n32") {
4950       LongWidth = LongAlign = 32;
4951       PointerWidth = PointerAlign = 32;
4952       ABI = Name;
4953       return true;
4954     } else if (Name == "n64") {
4955       ABI = Name;
4956       return true;
4957     } else if (Name == "64") {
4958       ABI = "n64";
4959       return true;
4960     } else
4961       return false;
4962   }
4963   virtual void getTargetDefines(const LangOptions &Opts,
4964                                 MacroBuilder &Builder) const {
4965     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4966 
4967     Builder.defineMacro("__mips64");
4968     Builder.defineMacro("__mips64__");
4969 
4970     if (ABI == "n32") {
4971       Builder.defineMacro("__mips_n32");
4972       Builder.defineMacro("_ABIN32", "2");
4973       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4974     }
4975     else if (ABI == "n64") {
4976       Builder.defineMacro("__mips_n64");
4977       Builder.defineMacro("_ABI64", "3");
4978       Builder.defineMacro("_MIPS_SIM", "_ABI64");
4979     }
4980     else
4981       llvm_unreachable("Invalid ABI for Mips64.");
4982   }
4983   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4984                                 unsigned &NumAliases) const {
4985     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4986       { { "at" },  "$1" },
4987       { { "v0" },  "$2" },
4988       { { "v1" },  "$3" },
4989       { { "a0" },  "$4" },
4990       { { "a1" },  "$5" },
4991       { { "a2" },  "$6" },
4992       { { "a3" },  "$7" },
4993       { { "a4" },  "$8" },
4994       { { "a5" },  "$9" },
4995       { { "a6" }, "$10" },
4996       { { "a7" }, "$11" },
4997       { { "t0" }, "$12" },
4998       { { "t1" }, "$13" },
4999       { { "t2" }, "$14" },
5000       { { "t3" }, "$15" },
5001       { { "s0" }, "$16" },
5002       { { "s1" }, "$17" },
5003       { { "s2" }, "$18" },
5004       { { "s3" }, "$19" },
5005       { { "s4" }, "$20" },
5006       { { "s5" }, "$21" },
5007       { { "s6" }, "$22" },
5008       { { "s7" }, "$23" },
5009       { { "t8" }, "$24" },
5010       { { "t9" }, "$25" },
5011       { { "k0" }, "$26" },
5012       { { "k1" }, "$27" },
5013       { { "gp" }, "$28" },
5014       { { "sp","$sp" }, "$29" },
5015       { { "fp","$fp" }, "$30" },
5016       { { "ra" }, "$31" }
5017     };
5018     Aliases = GCCRegAliases;
5019     NumAliases = llvm::array_lengthof(GCCRegAliases);
5020   }
5021 };
5022 
5023 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
5024   virtual void SetDescriptionString(const std::string &Name) {
5025     // Change DescriptionString only if ABI is n32.
5026     if (Name == "n32")
5027       DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5028                           "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5029                           "v64:64:64-n32:64-S128";
5030   }
5031 public:
5032   Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
5033     // Default ABI is n64.
5034     DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5035                         "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5036                         "v64:64:64-n32:64-S128";
5037   }
5038   virtual void getTargetDefines(const LangOptions &Opts,
5039                                 MacroBuilder &Builder) const {
5040     DefineStd(Builder, "MIPSEB", Opts);
5041     Builder.defineMacro("_MIPSEB");
5042     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5043   }
5044 };
5045 
5046 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5047   virtual void SetDescriptionString(const std::string &Name) {
5048     // Change DescriptionString only if ABI is n32.
5049     if (Name == "n32")
5050       DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5051                           "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
5052                           "-v64:64:64-n32:64-S128";
5053   }
5054 public:
5055   Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
5056     // Default ABI is n64.
5057     BigEndian = false;
5058     DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5059                         "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5060                         "v64:64:64-n32:64-S128";
5061   }
5062   virtual void getTargetDefines(const LangOptions &Opts,
5063                                 MacroBuilder &Builder) const {
5064     DefineStd(Builder, "MIPSEL", Opts);
5065     Builder.defineMacro("_MIPSEL");
5066     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5067   }
5068 };
5069 } // end anonymous namespace.
5070 
5071 namespace {
5072 class PNaClTargetInfo : public TargetInfo {
5073 public:
5074   PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) {
5075     BigEndian = false;
5076     this->UserLabelPrefix = "";
5077     this->LongAlign = 32;
5078     this->LongWidth = 32;
5079     this->PointerAlign = 32;
5080     this->PointerWidth = 32;
5081     this->IntMaxType = TargetInfo::SignedLongLong;
5082     this->UIntMaxType = TargetInfo::UnsignedLongLong;
5083     this->Int64Type = TargetInfo::SignedLongLong;
5084     this->DoubleAlign = 64;
5085     this->LongDoubleWidth = 64;
5086     this->LongDoubleAlign = 64;
5087     this->SizeType = TargetInfo::UnsignedInt;
5088     this->PtrDiffType = TargetInfo::SignedInt;
5089     this->IntPtrType = TargetInfo::SignedInt;
5090     this->RegParmMax = 0; // Disallow regparm
5091     DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5092                         "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
5093   }
5094 
5095   void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
5096   }
5097   virtual void getArchDefines(const LangOptions &Opts,
5098                               MacroBuilder &Builder) const {
5099     Builder.defineMacro("__le32__");
5100     Builder.defineMacro("__pnacl__");
5101   }
5102   virtual void getTargetDefines(const LangOptions &Opts,
5103                                 MacroBuilder &Builder) const {
5104     Builder.defineMacro("__LITTLE_ENDIAN__");
5105     getArchDefines(Opts, Builder);
5106   }
5107   virtual bool hasFeature(StringRef Feature) const {
5108     return Feature == "pnacl";
5109   }
5110   virtual void getTargetBuiltins(const Builtin::Info *&Records,
5111                                  unsigned &NumRecords) const {
5112   }
5113   virtual BuiltinVaListKind getBuiltinVaListKind() const {
5114     return TargetInfo::PNaClABIBuiltinVaList;
5115   }
5116   virtual void getGCCRegNames(const char * const *&Names,
5117                               unsigned &NumNames) const;
5118   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5119                                 unsigned &NumAliases) const;
5120   virtual bool validateAsmConstraint(const char *&Name,
5121                                      TargetInfo::ConstraintInfo &Info) const {
5122     return false;
5123   }
5124 
5125   virtual const char *getClobbers() const {
5126     return "";
5127   }
5128 };
5129 
5130 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
5131                                      unsigned &NumNames) const {
5132   Names = NULL;
5133   NumNames = 0;
5134 }
5135 
5136 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5137                                        unsigned &NumAliases) const {
5138   Aliases = NULL;
5139   NumAliases = 0;
5140 }
5141 } // end anonymous namespace.
5142 
5143 namespace {
5144   static const unsigned SPIRAddrSpaceMap[] = {
5145     1,    // opencl_global
5146     3,    // opencl_local
5147     2,    // opencl_constant
5148     0,    // cuda_device
5149     0,    // cuda_constant
5150     0     // cuda_shared
5151   };
5152   class SPIRTargetInfo : public TargetInfo {
5153     static const char * const GCCRegNames[];
5154     static const Builtin::Info BuiltinInfo[];
5155     std::vector<StringRef> AvailableFeatures;
5156   public:
5157     SPIRTargetInfo(const std::string& triple) : TargetInfo(triple) {
5158       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5159         "SPIR target must use unknown OS");
5160       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5161         "SPIR target must use unknown environment type");
5162       BigEndian = false;
5163       TLSSupported = false;
5164       LongWidth = LongAlign = 64;
5165       AddrSpaceMap = &SPIRAddrSpaceMap;
5166       // Define available target features
5167       // These must be defined in sorted order!
5168       NoAsmVariants = true;
5169     }
5170     virtual void getTargetDefines(const LangOptions &Opts,
5171                                   MacroBuilder &Builder) const {
5172       DefineStd(Builder, "SPIR", Opts);
5173     }
5174     virtual bool hasFeature(StringRef Feature) const {
5175       return Feature == "spir";
5176     }
5177 
5178     virtual void getTargetBuiltins(const Builtin::Info *&Records,
5179                                    unsigned &NumRecords) const {}
5180     virtual const char *getClobbers() const {
5181       return "";
5182     }
5183     virtual void getGCCRegNames(const char * const *&Names,
5184                                 unsigned &NumNames) const {}
5185     virtual bool validateAsmConstraint(const char *&Name,
5186                                        TargetInfo::ConstraintInfo &info) const {
5187       return true;
5188     }
5189     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5190                                   unsigned &NumAliases) const {}
5191     virtual BuiltinVaListKind getBuiltinVaListKind() const {
5192       return TargetInfo::VoidPtrBuiltinVaList;
5193     }
5194   };
5195 
5196 
5197   class SPIR32TargetInfo : public SPIRTargetInfo {
5198   public:
5199     SPIR32TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
5200       PointerWidth = PointerAlign = 32;
5201       SizeType     = TargetInfo::UnsignedInt;
5202       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5203       DescriptionString
5204         = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5205           "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5206           "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5207           "v512:512:512-v1024:1024:1024";
5208     }
5209     virtual void getTargetDefines(const LangOptions &Opts,
5210                                   MacroBuilder &Builder) const {
5211       DefineStd(Builder, "SPIR32", Opts);
5212     }
5213   };
5214 
5215   class SPIR64TargetInfo : public SPIRTargetInfo {
5216   public:
5217     SPIR64TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
5218       PointerWidth = PointerAlign = 64;
5219       SizeType     = TargetInfo::UnsignedLong;
5220       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5221       DescriptionString
5222         = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5223           "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5224           "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5225           "v512:512:512-v1024:1024:1024";
5226     }
5227     virtual void getTargetDefines(const LangOptions &Opts,
5228                                   MacroBuilder &Builder) const {
5229       DefineStd(Builder, "SPIR64", Opts);
5230     }
5231   };
5232 }
5233 
5234 
5235 //===----------------------------------------------------------------------===//
5236 // Driver code
5237 //===----------------------------------------------------------------------===//
5238 
5239 static TargetInfo *AllocateTarget(const std::string &T) {
5240   llvm::Triple Triple(T);
5241   llvm::Triple::OSType os = Triple.getOS();
5242 
5243   switch (Triple.getArch()) {
5244   default:
5245     return NULL;
5246 
5247   case llvm::Triple::hexagon:
5248     return new HexagonTargetInfo(T);
5249 
5250   case llvm::Triple::aarch64:
5251     switch (os) {
5252     case llvm::Triple::Linux:
5253       return new LinuxTargetInfo<AArch64TargetInfo>(T);
5254     default:
5255       return new AArch64TargetInfo(T);
5256     }
5257 
5258   case llvm::Triple::arm:
5259   case llvm::Triple::thumb:
5260     if (Triple.isOSDarwin())
5261       return new DarwinARMTargetInfo(T);
5262 
5263     switch (os) {
5264     case llvm::Triple::Linux:
5265       return new LinuxTargetInfo<ARMTargetInfo>(T);
5266     case llvm::Triple::FreeBSD:
5267       return new FreeBSDTargetInfo<ARMTargetInfo>(T);
5268     case llvm::Triple::NetBSD:
5269       return new NetBSDTargetInfo<ARMTargetInfo>(T);
5270     case llvm::Triple::OpenBSD:
5271       return new OpenBSDTargetInfo<ARMTargetInfo>(T);
5272     case llvm::Triple::Bitrig:
5273       return new BitrigTargetInfo<ARMTargetInfo>(T);
5274     case llvm::Triple::RTEMS:
5275       return new RTEMSTargetInfo<ARMTargetInfo>(T);
5276     case llvm::Triple::NaCl:
5277       return new NaClTargetInfo<ARMTargetInfo>(T);
5278     default:
5279       return new ARMTargetInfo(T);
5280     }
5281 
5282   case llvm::Triple::msp430:
5283     return new MSP430TargetInfo(T);
5284 
5285   case llvm::Triple::mips:
5286     switch (os) {
5287     case llvm::Triple::Linux:
5288       return new LinuxTargetInfo<Mips32EBTargetInfo>(T);
5289     case llvm::Triple::RTEMS:
5290       return new RTEMSTargetInfo<Mips32EBTargetInfo>(T);
5291     case llvm::Triple::FreeBSD:
5292       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T);
5293     case llvm::Triple::NetBSD:
5294       return new NetBSDTargetInfo<Mips32EBTargetInfo>(T);
5295     default:
5296       return new Mips32EBTargetInfo(T);
5297     }
5298 
5299   case llvm::Triple::mipsel:
5300     switch (os) {
5301     case llvm::Triple::Linux:
5302       return new LinuxTargetInfo<Mips32ELTargetInfo>(T);
5303     case llvm::Triple::RTEMS:
5304       return new RTEMSTargetInfo<Mips32ELTargetInfo>(T);
5305     case llvm::Triple::FreeBSD:
5306       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T);
5307     case llvm::Triple::NetBSD:
5308       return new NetBSDTargetInfo<Mips32ELTargetInfo>(T);
5309     default:
5310       return new Mips32ELTargetInfo(T);
5311     }
5312 
5313   case llvm::Triple::mips64:
5314     switch (os) {
5315     case llvm::Triple::Linux:
5316       return new LinuxTargetInfo<Mips64EBTargetInfo>(T);
5317     case llvm::Triple::RTEMS:
5318       return new RTEMSTargetInfo<Mips64EBTargetInfo>(T);
5319     case llvm::Triple::FreeBSD:
5320       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T);
5321     case llvm::Triple::NetBSD:
5322       return new NetBSDTargetInfo<Mips64EBTargetInfo>(T);
5323     case llvm::Triple::OpenBSD:
5324       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T);
5325     default:
5326       return new Mips64EBTargetInfo(T);
5327     }
5328 
5329   case llvm::Triple::mips64el:
5330     switch (os) {
5331     case llvm::Triple::Linux:
5332       return new LinuxTargetInfo<Mips64ELTargetInfo>(T);
5333     case llvm::Triple::RTEMS:
5334       return new RTEMSTargetInfo<Mips64ELTargetInfo>(T);
5335     case llvm::Triple::FreeBSD:
5336       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T);
5337     case llvm::Triple::NetBSD:
5338       return new NetBSDTargetInfo<Mips64ELTargetInfo>(T);
5339     case llvm::Triple::OpenBSD:
5340       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T);
5341     default:
5342       return new Mips64ELTargetInfo(T);
5343     }
5344 
5345   case llvm::Triple::le32:
5346     switch (os) {
5347       case llvm::Triple::NaCl:
5348         return new NaClTargetInfo<PNaClTargetInfo>(T);
5349       default:
5350         return NULL;
5351     }
5352 
5353   case llvm::Triple::ppc:
5354     if (Triple.isOSDarwin())
5355       return new DarwinPPC32TargetInfo(T);
5356     switch (os) {
5357     case llvm::Triple::Linux:
5358       return new LinuxTargetInfo<PPC32TargetInfo>(T);
5359     case llvm::Triple::FreeBSD:
5360       return new FreeBSDTargetInfo<PPC32TargetInfo>(T);
5361     case llvm::Triple::NetBSD:
5362       return new NetBSDTargetInfo<PPC32TargetInfo>(T);
5363     case llvm::Triple::OpenBSD:
5364       return new OpenBSDTargetInfo<PPC32TargetInfo>(T);
5365     case llvm::Triple::RTEMS:
5366       return new RTEMSTargetInfo<PPC32TargetInfo>(T);
5367     default:
5368       return new PPC32TargetInfo(T);
5369     }
5370 
5371   case llvm::Triple::ppc64:
5372     if (Triple.isOSDarwin())
5373       return new DarwinPPC64TargetInfo(T);
5374     switch (os) {
5375     case llvm::Triple::Linux:
5376       return new LinuxTargetInfo<PPC64TargetInfo>(T);
5377     case llvm::Triple::Lv2:
5378       return new PS3PPUTargetInfo<PPC64TargetInfo>(T);
5379     case llvm::Triple::FreeBSD:
5380       return new FreeBSDTargetInfo<PPC64TargetInfo>(T);
5381     case llvm::Triple::NetBSD:
5382       return new NetBSDTargetInfo<PPC64TargetInfo>(T);
5383     default:
5384       return new PPC64TargetInfo(T);
5385     }
5386 
5387   case llvm::Triple::nvptx:
5388     return new NVPTX32TargetInfo(T);
5389   case llvm::Triple::nvptx64:
5390     return new NVPTX64TargetInfo(T);
5391 
5392   case llvm::Triple::mblaze:
5393     return new MBlazeTargetInfo(T);
5394 
5395   case llvm::Triple::r600:
5396     return new R600TargetInfo(T);
5397 
5398   case llvm::Triple::sparc:
5399     switch (os) {
5400     case llvm::Triple::Linux:
5401       return new LinuxTargetInfo<SparcV8TargetInfo>(T);
5402     case llvm::Triple::AuroraUX:
5403       return new AuroraUXSparcV8TargetInfo(T);
5404     case llvm::Triple::Solaris:
5405       return new SolarisSparcV8TargetInfo(T);
5406     case llvm::Triple::NetBSD:
5407       return new NetBSDTargetInfo<SparcV8TargetInfo>(T);
5408     case llvm::Triple::OpenBSD:
5409       return new OpenBSDTargetInfo<SparcV8TargetInfo>(T);
5410     case llvm::Triple::RTEMS:
5411       return new RTEMSTargetInfo<SparcV8TargetInfo>(T);
5412     default:
5413       return new SparcV8TargetInfo(T);
5414     }
5415 
5416   case llvm::Triple::sparcv9:
5417     switch (os) {
5418     case llvm::Triple::Linux:
5419       return new LinuxTargetInfo<SparcV9TargetInfo>(T);
5420     case llvm::Triple::AuroraUX:
5421       return new AuroraUXTargetInfo<SparcV9TargetInfo>(T);
5422     case llvm::Triple::Solaris:
5423       return new SolarisTargetInfo<SparcV9TargetInfo>(T);
5424     case llvm::Triple::NetBSD:
5425       return new NetBSDTargetInfo<SparcV9TargetInfo>(T);
5426     case llvm::Triple::OpenBSD:
5427       return new OpenBSDTargetInfo<SparcV9TargetInfo>(T);
5428     case llvm::Triple::FreeBSD:
5429       return new FreeBSDTargetInfo<SparcV9TargetInfo>(T);
5430     default:
5431       return new SparcV9TargetInfo(T);
5432     }
5433 
5434   case llvm::Triple::systemz:
5435     switch (os) {
5436     case llvm::Triple::Linux:
5437       return new LinuxTargetInfo<SystemZTargetInfo>(T);
5438     default:
5439       return new SystemZTargetInfo(T);
5440     }
5441 
5442   case llvm::Triple::tce:
5443     return new TCETargetInfo(T);
5444 
5445   case llvm::Triple::x86:
5446     if (Triple.isOSDarwin())
5447       return new DarwinI386TargetInfo(T);
5448 
5449     switch (os) {
5450     case llvm::Triple::AuroraUX:
5451       return new AuroraUXTargetInfo<X86_32TargetInfo>(T);
5452     case llvm::Triple::Linux:
5453       return new LinuxTargetInfo<X86_32TargetInfo>(T);
5454     case llvm::Triple::DragonFly:
5455       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T);
5456     case llvm::Triple::NetBSD:
5457       return new NetBSDI386TargetInfo(T);
5458     case llvm::Triple::OpenBSD:
5459       return new OpenBSDI386TargetInfo(T);
5460     case llvm::Triple::Bitrig:
5461       return new BitrigI386TargetInfo(T);
5462     case llvm::Triple::FreeBSD:
5463       return new FreeBSDTargetInfo<X86_32TargetInfo>(T);
5464     case llvm::Triple::Minix:
5465       return new MinixTargetInfo<X86_32TargetInfo>(T);
5466     case llvm::Triple::Solaris:
5467       return new SolarisTargetInfo<X86_32TargetInfo>(T);
5468     case llvm::Triple::Cygwin:
5469       return new CygwinX86_32TargetInfo(T);
5470     case llvm::Triple::MinGW32:
5471       return new MinGWX86_32TargetInfo(T);
5472     case llvm::Triple::Win32:
5473       return new VisualStudioWindowsX86_32TargetInfo(T);
5474     case llvm::Triple::Haiku:
5475       return new HaikuX86_32TargetInfo(T);
5476     case llvm::Triple::RTEMS:
5477       return new RTEMSX86_32TargetInfo(T);
5478     case llvm::Triple::NaCl:
5479       return new NaClTargetInfo<X86_32TargetInfo>(T);
5480     default:
5481       return new X86_32TargetInfo(T);
5482     }
5483 
5484   case llvm::Triple::x86_64:
5485     if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5486       return new DarwinX86_64TargetInfo(T);
5487 
5488     switch (os) {
5489     case llvm::Triple::AuroraUX:
5490       return new AuroraUXTargetInfo<X86_64TargetInfo>(T);
5491     case llvm::Triple::Linux:
5492       return new LinuxTargetInfo<X86_64TargetInfo>(T);
5493     case llvm::Triple::DragonFly:
5494       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T);
5495     case llvm::Triple::NetBSD:
5496       return new NetBSDTargetInfo<X86_64TargetInfo>(T);
5497     case llvm::Triple::OpenBSD:
5498       return new OpenBSDX86_64TargetInfo(T);
5499     case llvm::Triple::Bitrig:
5500       return new BitrigX86_64TargetInfo(T);
5501     case llvm::Triple::FreeBSD:
5502       return new FreeBSDTargetInfo<X86_64TargetInfo>(T);
5503     case llvm::Triple::Solaris:
5504       return new SolarisTargetInfo<X86_64TargetInfo>(T);
5505     case llvm::Triple::MinGW32:
5506       return new MinGWX86_64TargetInfo(T);
5507     case llvm::Triple::Win32:   // This is what Triple.h supports now.
5508       return new VisualStudioWindowsX86_64TargetInfo(T);
5509     case llvm::Triple::NaCl:
5510       return new NaClTargetInfo<X86_64TargetInfo>(T);
5511     default:
5512       return new X86_64TargetInfo(T);
5513     }
5514 
5515     case llvm::Triple::spir: {
5516       llvm::Triple Triple(T);
5517       if (Triple.getOS() != llvm::Triple::UnknownOS ||
5518         Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5519         return NULL;
5520       return new SPIR32TargetInfo(T);
5521     }
5522     case llvm::Triple::spir64: {
5523       llvm::Triple Triple(T);
5524       if (Triple.getOS() != llvm::Triple::UnknownOS ||
5525         Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5526         return NULL;
5527       return new SPIR64TargetInfo(T);
5528     }
5529   }
5530 }
5531 
5532 /// CreateTargetInfo - Return the target info object for the specified target
5533 /// triple.
5534 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5535                                          TargetOptions *Opts) {
5536   llvm::Triple Triple(Opts->Triple);
5537 
5538   // Construct the target
5539   OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str()));
5540   if (!Target) {
5541     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5542     return 0;
5543   }
5544   Target->setTargetOpts(Opts);
5545 
5546   // Set the target CPU if specified.
5547   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5548     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5549     return 0;
5550   }
5551 
5552   // Set the target ABI if specified.
5553   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5554     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5555     return 0;
5556   }
5557 
5558   // Set the target C++ ABI.
5559   if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5560     Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5561     return 0;
5562   }
5563 
5564   // Compute the default target features, we need the target to handle this
5565   // because features may have dependencies on one another.
5566   llvm::StringMap<bool> Features;
5567   Target->getDefaultFeatures(Features);
5568 
5569   // Apply the user specified deltas.
5570   // First the enables.
5571   for (std::vector<std::string>::const_iterator
5572          it = Opts->FeaturesAsWritten.begin(),
5573          ie = Opts->FeaturesAsWritten.end();
5574        it != ie; ++it) {
5575     const char *Name = it->c_str();
5576 
5577     if (Name[0] != '+')
5578       continue;
5579 
5580     // Apply the feature via the target.
5581     if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5582       Diags.Report(diag::err_target_invalid_feature) << Name;
5583       return 0;
5584     }
5585   }
5586 
5587   // Then the disables.
5588   for (std::vector<std::string>::const_iterator
5589          it = Opts->FeaturesAsWritten.begin(),
5590          ie = Opts->FeaturesAsWritten.end();
5591        it != ie; ++it) {
5592     const char *Name = it->c_str();
5593 
5594     if (Name[0] == '+')
5595       continue;
5596 
5597     // Apply the feature via the target.
5598     if (Name[0] != '-' ||
5599         !Target->setFeatureEnabled(Features, Name + 1, false)) {
5600       Diags.Report(diag::err_target_invalid_feature) << Name;
5601       return 0;
5602     }
5603   }
5604 
5605   // Add the features to the compile options.
5606   //
5607   // FIXME: If we are completely confident that we have the right set, we only
5608   // need to pass the minuses.
5609   Opts->Features.clear();
5610   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5611          ie = Features.end(); it != ie; ++it)
5612     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5613   Target->HandleTargetFeatures(Opts->Features);
5614 
5615   return Target.take();
5616 }
5617